Stacked structure chip, display driving chip and touch and display integrated driving chip

Abstract

The utility model discloses a kind of stacked structure chip, display drive chip and touch and display integrated drive chip.The stacked structure chip, including first wafer, second wafer and third wafer that are sequentially stacked;The first wafer is equipped with driving module, the second wafer is equipped with logic module, the third wafer is equipped with storage module;The first wafer is bonded with the second wafer, and the second wafer is bonded with the third wafer.The process technology decoupling of the three wafers of this chip, can match different process technology according to the performance requirement of different functional modules, can reduce processing complexity, improve processing efficiency and reduce processing cost, and meet the performance requirement corresponding to different functional modules.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a stacked structure chip, a display driver chip, and a touch and display integrated driver chip. Background Technology

[0002] In the semiconductor chip design process, different functional modules are usually fabricated on the same wafer. To achieve performance compatibility between different functional modules, complex processing technology is required, which results in high processing costs and low efficiency. Furthermore, in order to integrate different functional modules on the same wafer, some performance is often sacrificed, making it difficult for chips that integrate different functional modules to balance low cost and high performance. Summary of the Invention

[0003] This utility model provides a stacked structure chip, a display driver chip, and a touch and display integrated driver chip to solve the problem of difficulty in balancing low cost and high performance in existing chip design processes.

[0004] A stacked chip structure includes a first wafer, a second wafer, and a third wafer stacked sequentially. The first wafer is provided with a driver module, the second wafer is provided with a logic module, and the third wafer is provided with a storage module; The first wafer is bonded to the second wafer, and the second wafer is bonded to the third wafer.

[0005] Preferably, the first wafer is provided with a first pad and a second pad, the first pad being electrically connected to the driving module and the logic module, and the second pad being electrically connected to the logic module and the storage module through a direct interconnect structure.

[0006] Preferably, the second wafer is provided with a transition dielectric layer; The direct interconnect structure includes a first TSV, a transition metal layer, and a second TSV. The transition metal layer is disposed within the transition dielectric layer; One end of the first TSV is connected to the second pad, and the other end of the first TSV is connected to the transition metal layer; One end of the second TSV is connected to the transition metal layer, and the other end of the second TSV is connected to the logic module and / or the storage module.

[0007] Preferably, the direct interconnection structure is a tungsten direct interconnection structure or a copper direct interconnection structure; Alternatively, a portion of the first TSV, the transition metal layer, and the second TSV may be filled with tungsten metal, while the other portion may be filled with copper metal.

[0008] Preferably, the first wafer includes a first substrate, a plurality of first dielectric layers, a plurality of first metal layers, a first metal bonding structure, a first pad, and a second pad; the plurality of first dielectric layers and the plurality of first metal layers are alternately disposed, the bottom first dielectric layer is in contact with the front side of the first substrate, and the top first metal layer is in contact with the first metal bonding structure; The second wafer includes a second substrate, a plurality of second dielectric layers, a plurality of second metal layers, a second metal bonding structure, and a third metal bonding structure; the plurality of second dielectric layers and the plurality of second metal layers are alternately arranged, the bottom second dielectric layer is in contact with the front side of the second substrate, the transition dielectric layer is in contact with the back side of the second substrate, the bottom second metal layer is in contact with the second metal bonding structure, the second metal bonding structure is disposed in the transition dielectric layer, and the top second metal layer is in contact with the third metal bonding structure; The third wafer includes a third substrate, multiple third dielectric layers, multiple third metal layers, and a fourth metal bonding structure; the multiple third dielectric layers and multiple third metal layers are alternately arranged, the bottom third dielectric layer is in contact with the front side of the third substrate, and the top third metal layer is in contact with the fourth metal bonding structure; The first dielectric layer at the top is bonded to the transition dielectric layer, and the first metal bonding structure is bonded to the second metal bonding structure; The second dielectric layer and the third dielectric layer of the top layer are bonded together, and the third metal bonding structure is bonded to the fourth metal bonding structure; The first pad is connected to the first metal layer of the underlying layer, and the second pad is connected to the second metal layer and / or the third metal layer through the direct interconnect structure.

[0009] Preferably, the first metal layer has three or more layers; the second metal layer has three or more layers; and the third metal layer has three or more layers.

[0010] Preferably, among the multiple metal layers corresponding to the same wafer, the bottom metal layer has the smallest thickness and the top metal layer has the largest thickness.

[0011] Preferably, all of the first metal layers are copper metal layers; Alternatively, all of the first metal layers may be aluminum metal layers; Alternatively, one portion of the plurality of the first metal layers may be an aluminum metal layer and another portion may be a copper metal layer.

[0012] Preferably, the plurality of second metal layers and the plurality of third metal layers are all copper metal layers.

[0013] Preferably, the first dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; and the transition dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer. The first metal bonding structure, the second metal bonding structure, the third metal bonding structure, and the fourth metal bonding structure are all copper bonding structures.

[0014] Preferably, the first wafer includes a first substrate and a multi-gate oxide device disposed on the front side of the first substrate, wherein the multi-gate oxide device includes at least two gate oxide devices with different gate oxide thicknesses; The second wafer includes a second substrate and a single gate oxide device disposed on the front side of the second substrate, wherein the single gate oxide device includes a plurality of gate oxide devices with the same gate oxide thickness; The gate oxide thickness of the multi-gate oxide device is greater than that of the single-gate oxide device.

[0015] Preferably, the multi-gate oxide device includes a first gate oxide thickness device, a second gate oxide thickness device, and a third gate oxide thickness device; The gate oxide thickness of the first gate oxide thickness device is 60nm-90nm; The gate oxide thickness of the second gate oxide thickness device is 12nm-20nm; The gate oxide thickness of the third gate oxide thickness device is 5nm-8nm.

[0016] Preferably, the gate oxide thickness of the single-gate oxide device is 1nm-3nm.

[0017] A display driver chip includes the above-described stacked chip structure; The drive module includes the medium- and high-voltage sections of the data driver, the medium- and high-voltage sections of the timing controller, the medium- and high-voltage sections of the I / O circuit, the medium- and high-voltage sections of the power management circuit, the medium- and high-voltage sections of the digital-to-analog converter circuit, and the ESD protection circuit. The logic module includes logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a clock management circuit, and a high-speed interface circuit.

[0018] A touch and display integrated driver chip, comprising the above-mentioned stacked structure chip; The drive module includes the medium-high voltage section of the data driver, the medium-high voltage section of the timing controller, the medium-high voltage section of the IO circuit, the medium-high voltage section of the power management circuit, the medium-high voltage section of the digital-to-analog conversion circuit, the ESD protection circuit, and the medium-high voltage section of the touch circuit. The logic module includes logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a clock management circuit, a high-speed interface circuit, and a low-voltage section of a touch circuit.

[0019] This utility model embodiment provides a stacked structure chip, a display driver chip, and a touch and display integrated driver chip. The driver module is separately mounted on the first wafer, the logic module on the second wafer, and the storage module 700 on the third wafer. This decouples the manufacturing processes of the three wafers, allowing different manufacturing processes to be matched according to the performance requirements of different functional modules. This ensures that the driver module meets the performance requirements of providing high voltage / high current driving capability, the logic module meets the performance requirements of high-speed computing capability, and the storage module meets the performance requirements of high-density, low-power storage. Furthermore, since different functional modules are mounted on different wafers, the fabrication process of each wafer does not need to consider the performance compatibility between different functional modules, which helps reduce processing complexity, improve processing efficiency, and reduce processing costs. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a stacked chip structure in one embodiment of the present invention; Figure 2 This is a schematic diagram of a display driver chip in one embodiment of the present invention; Figure 3 This is a schematic diagram of a touch and display integrated driver chip in one embodiment of the present invention.

[0022] In the figure: 100, first wafer; 110, first substrate; 120, multi-gate oxide device; 121, first gate oxide thickness device; 122, second gate oxide thickness device; 123, third gate oxide thickness device; 130, first dielectric layer; 140, first metal layer; 150, first metal bonding structure; 160, first pad; 170, second pad; 200, Second wafer; 210, Second substrate; 220, Single-gate oxide device; 221, Fourth-thickness gate oxide device; 230, Second dielectric layer; 240, Second metal layer; 250, Second metal bonding structure; 260, Third metal bonding structure; 270, Transition dielectric layer; 300, Third wafer; 310, Third substrate; 320, Third dielectric layer; 330, Third metal layer; 340, Fourth metal bonding structure; 400. Direct interconnect structure; 410. First TSV; 420. Transition metal layer; 430. Second TSV; 500. Driver module; 510. Medium and high voltage section of data driver; 520. Medium and high voltage section of timing controller; 530. Medium and high voltage section of I / O circuit; 540. Medium and high voltage section of power management circuit; 550. Medium and high voltage section of digital-to-analog converter circuit; 560. ESD protection circuit; 570. Medium and high voltage section of touch circuit; 600. Logic module; 610. Low-voltage section of data driver; 620. Low-voltage section of timing controller; 630. Low-voltage section of I / O circuit; 640. Low-voltage section of power management circuit; 650. Low-voltage section of digital-to-analog converter circuit; 660. Logic circuit; 670. Clock management circuit; 680. High-speed interface circuit; 690. Low-voltage section of touch circuit; 700. Storage module. Detailed Implementation

[0023] To make the technical problems solved, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0024] This utility model embodiment provides a stacked structure chip, such as Figure 1 , Figure 2 and Figure 3 As shown, the stacked structure chip includes a first wafer 100, a second wafer 200, and a third wafer 300 stacked sequentially; the first wafer 100 is provided with a driver module 500, the second wafer 200 is provided with a logic module 600, and the third wafer 300 is provided with a storage module 700; the first wafer 100 is bonded to the second wafer 200, and the second wafer 200 is bonded to the third wafer 300.

[0025] The first wafer 100, the second wafer 200, and the third wafer 300 are three independently configured wafers, which can be manufactured using different process technologies to achieve process decoupling. The driver module 500 is used to drive the hardware, which includes, but is not limited to, the display panel. The logic module 600 is used to implement logic processing. The storage module 700 is dedicated to storing data. The storage module 700 can be a high-density, high-capacity storage module, including but not limited to DRAM (Dynamic Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetoresistive Random Access Memory), and PCRAM (Phase Change Random Access Memory). The storage module 700 is separately located on the third wafer 300, which helps ensure the storage performance of the stacked chip structure.

[0026] As an example, the driver module 500 is separately located on the first wafer 100, the logic module 600 on the second wafer 200, and the storage module 700 on the third wafer 300. This decouples the manufacturing processes of the three wafers, allowing different manufacturing processes to be matched according to the performance requirements of different functional modules. This ensures that the driver module 500 meets the performance requirements of providing high voltage / high current driving capability, the logic module 600 meets the performance requirements of high-speed computing capability, and the storage module 700 meets the performance requirements of high-density, low-power storage. Furthermore, since different functional modules are located on different wafers, the fabrication process of each wafer does not need to consider the performance compatibility between different functional modules, which helps reduce processing complexity, improve processing efficiency, and reduce processing costs. The sequential stacking of the first wafer 100, second wafer 200, and third wafer 300 effectively saves area, reduces the overall size of the stacked chip structure, and improves its integration density. First wafer 100 and second wafer 200 are bonded together, and second wafer 200 and third wafer 300 are bonded together to enable high-density interconnection between adjacent wafers, which helps ensure the overall performance of the stacked chip structure. Positioning second wafer 200 between first wafer 100 and third wafer 300 brings the logic module 600 closer to the driver module 500 and memory module 700. This reduces signal transmission losses during communication between the logic module 600 and the driver module 500 and memory module 700, thus ensuring transmission performance. Furthermore, the drive module 500 generates a large current and magnetic field when it is working, and the storage module 700 is quite sensitive to external electromagnetic interference. By placing the second wafer 200 between the first wafer 100 and the third wafer 300, the distance between the first wafer 100 and the third wafer 300 can be increased, thereby achieving physical isolation between the drive module 500 and the storage module 700. This reduces the interference of the drive module 500 on the storage module 700 and ensures the storage performance of the storage module 700.

[0027] In one embodiment, the first wafer 100 is provided with a first pad 160 and a second pad 170. The first pad 160 is electrically connected to the driver module 500 and the logic module 600, and the second pad 170 is electrically connected to the logic module 600 and the storage module 700 through a direct interconnect structure 400.

[0028] The first pad 160 and the second pad 170 are two pads disposed on the back side of the first substrate 110 of the first wafer 100, and serve as the connection interface between the first wafer 100 and external packages (such as gold or copper wire bonding). In this example, both the first pad 160 and the second pad 170 are aluminum pads. The direct interconnect structure 400 is an architecture that enables signal or power transmission between wafers or modules through direct physical connection.

[0029] As an example, the first pad 160 connects to the driver module 500 of the first wafer 100 and the logic module 600 of the second wafer 200, and is connected to external circuitry. It is used to transmit drive signals output by the driver module 500, control signals, or feedback signals output by the logic module 600 to the driver module 500. These signals are typically high-current signals and are prone to electromagnetic interference. The second pad 170 connects to the logic module 600 and the storage module 700 via a direct interconnect structure 400. It is used to transmit signals generated during the operation of the logic module 600 and the storage module 700, such as read / write instructions, address signals, and clock signals generated during data storage. These signals are typically low-current signals and are sensitive to noise. In this example, the first pad 160 and the second pad 170 are used to transmit two types of signals respectively to avoid signal interference. Furthermore, the first pad 160 is directly connected to the driver module 500 and the logic module 600 to achieve drive control; the second pad 170 is connected to the logic module 600 and the storage module 700 through the direct interconnect structure 400 to achieve data storage or read operations. It can optimize the wiring design according to the signal flow direction, so that both signals are transmitted through the shortest path, which helps to reduce transmission delay and loss, and ensure the overall performance of the stacked structure chip.

[0030] In one embodiment, the second wafer 200 is provided with a transition dielectric layer 270; the direct interconnect structure 400 includes a first TSV 410, a transition metal layer 420, and a second TSV 430; the transition metal layer 420 is disposed within the transition dielectric layer 270; one end of the first TSV 410 is connected to the second pad 170, and the other end of the first TSV 410 is connected to the transition metal layer 420; one end of the second TSV 430 is connected to the transition metal layer 420, and the other end of the second TSV 430 is connected to the logic module 600 and / or the memory module 700.

[0031] The transition dielectric layer 270 is a dielectric layer disposed on the back side of the second substrate 210 of the second wafer 200. It can be a SiN dielectric layer or other dielectric layers. The transition metal layer 420 is a metal layer disposed within the transition dielectric layer 270 and is used to realize signal interconnection. The first TSV 410 and the second TSV 430 are two TSVs (Through Silicon Vias), which refer to vertical through-holes formed in silicon wafers or chips. By filling the holes with conductive material, vertical electrical connections are realized within the chip, between chips, and between the chip and the package.

[0032] As an example, a transition dielectric layer 270 is provided on the second wafer 200, and a transition metal layer 420 is provided within the transition dielectric layer 270. A first TSV 410 is disposed between the first wafer 100 and the transition dielectric layer 270 so that the first TSV 410 can connect the first pad 160 and the transition metal layer 420. A second TSV 430 is disposed within the second wafer 200 so that the second TSV 430 can be connected to the logic module 600. Alternatively, the second TSV 430 can be disposed between the second wafer 200 and the third wafer 300 so that the second TSV 430 can be connected to the memory module 700, or simultaneously connected to both the memory module 700 and the logic module 600, which can be configured according to actual needs. This segmented design eliminates the need for high-precision process technology to process deep TSVs, facilitating processing, avoiding excessively large or deep TSVs, reducing reliance on high-precision process technology, helping to reduce manufacturing costs, and shrinking chip area. It can also improve the yield of stacked structure chips to some extent.

[0033] In one embodiment, the direct interconnect structure 400 is a tungsten direct interconnect structure or a copper direct interconnect structure; or, a portion of the first TSV410, the transition metal layer 420, and the second TSV430 is filled with tungsten metal, and the other portion is filled with copper metal.

[0034] As an example, in the semiconductor packaging field, the fabrication of direct interconnect structures using tungsten (W) and copper (Cu) is a relatively mature process, convenient to process, and low in cost. Therefore, the direct interconnect structure 400 of the stacked chip can be fabricated using tungsten (W) and / or copper (Cu). In this example, the direct interconnect structure 400 can be a tungsten direct interconnect structure, that is, the first TSV410, the transition metal layer 420, and the second TSV430 are all direct interconnect structures formed of tungsten metal. Alternatively, the direct interconnect structure 400 can be a copper direct interconnect structure, that is, the first TSV410, the transition metal layer 420, and the second TSV430 are all direct interconnect structures formed of copper metal. Alternatively, a portion of the first TSV410, the transition metal layer 420, and the second TSV430 may be filled with tungsten metal, and another portion may be filled with copper metal. For example, the first TSV410 may be filled with tungsten metal, and the transition metal layer 420 and the second TSV430 may be filled with copper metal.

[0035] In one embodiment, a first wafer 100 includes a first substrate 110, a plurality of first dielectric layers 130, a plurality of first metal layers 140, a first metal bonding structure 150, a first pad 160, and a second pad 170; the plurality of first dielectric layers 130 and the plurality of first metal layers 140 are alternately disposed, with the bottom first dielectric layer 130 being in contact with the front side of the first substrate 110, and the top first metal layer 140 being in contact with the first metal bonding structure 150; a second wafer 200 includes a second substrate 210, a plurality of second dielectric layers 230, a plurality of second metal layers 240, a second metal bonding structure 250, and a third metal bonding structure 260; the plurality of second dielectric layers 230 and the plurality of second metal layers 240 are alternately disposed, with the bottom second dielectric layer 230 being in contact with the front side of the second substrate 210, a transition dielectric layer 270 being in contact with the back side of the second substrate 210, and the bottom second metal layer 240 being in contact with the second metal bonding structure 250, the second metal bonding structure 250 being disposed... Within the transition dielectric layer 270, the top second metal layer 240 is connected to the third metal bonding structure 260; the third wafer 300 includes a third substrate 310, a plurality of third dielectric layers 320, a plurality of third metal layers 330, and a fourth metal bonding structure 340; the plurality of third dielectric layers 320 and the plurality of third metal layers 330 are alternately arranged, the bottom third dielectric layer 320 is connected to the front side of the third substrate 310, and the top third metal layer 330 is connected to the fourth metal bonding structure 340; The first dielectric layer 130 of the top layer is bonded to the transition dielectric layer 270, and the first metal bonding structure 150 is bonded to the second metal bonding structure 250; the second dielectric layer 230 of the top layer and the third dielectric layer 320 of the top layer are bonded, and the third metal bonding structure 260 is bonded to the fourth metal bonding structure 340; the first pad 160 is connected to the first metal layer 140 of the bottom layer, and the second pad 170 is connected to the second metal layer 240 and / or the third metal layer 330 through the direct interconnect structure 400.

[0036] The first dielectric layer 130, the second dielectric layer 230, and the third dielectric layer 320 are the dielectric layers of the first wafer 100, the second wafer 200, and the third wafer 300, respectively, and are structures in which insulating material is filled between different metal layers. The first metal layer 140, the second metal layer 240, and the third metal layer 330 are the metal layers of the first wafer 100, the second wafer 200, and the third wafer 300, respectively, and are structures used to realize signal interconnection.

[0037] As an example, the first wafer 100, the second wafer 200, and the third wafer 300 can be fabricated using different process technologies to achieve process decoupling of the three wafers. In this example, the first wafer 100 includes a plurality of alternating first dielectric layers 130 and a plurality of first metal layers 140. The bottom first dielectric layer 130 is in contact with the front side of the first substrate 110, a portion of the bottom first metal layer 140 is in contact with the first pad 160, and a portion of the top first metal layer 140 is in contact with the first metal bonding structure 150, which is disposed within the top first dielectric layer 130. The second wafer 200 includes a plurality of alternately arranged second dielectric layers 230 and a plurality of second metal layers 240. The bottom second dielectric layer 230 is in contact with the front side of the second substrate 210, and the transition dielectric layer 270 is in contact with the back side of the second substrate 210. A portion of the bottom second metal layer 240 is in contact with a second metal bonding structure 250, which is disposed within the transition dielectric layer 270. A portion of the second metal layer 240 is in contact with a third metal bonding structure 260, which is disposed within the top second dielectric layer 230. The third wafer 300 includes a plurality of alternately arranged third dielectric layers 320 and a plurality of third metal layers 330. The bottom third dielectric layer 320 is in contact with the front side of the third substrate 310, and a portion of the top third metal layer 330 is in contact with a fourth metal bonding structure 340, which is disposed within the top third dielectric layer 320.

[0038] After fabricating the first wafer 100, the second wafer 200, and the third wafer 300, respectively, the first wafer 100 and the second wafer 200 can be bonded. Specifically, the first dielectric layer 130 of the top layer and the transition dielectric layer 270 are dielectrically bonded, allowing the insulating materials within the two dielectric layers to be initially fixed through atomic diffusion, ensuring structural stability. The first metal bonding structure 150 and the second metal bonding structure 250 are metallically bonded, forming ohmic contacts through atomic expansion under specific conditions to achieve high-density interconnection. The second wafer 200 and the third wafer 300 are also bonded. Specifically, the second dielectric layer 230 of the top layer and the third dielectric layer 320 of the top layer are dielectrically bonded, allowing the insulating materials within the two dielectric layers to be initially fixed through atomic diffusion, ensuring structural stability. The third metal bonding structure 260 and the fourth metal bonding structure 340 are metallically bonded, forming ohmic contacts through atomic expansion under specific conditions to achieve high-density interconnection.

[0039] In this example, the first pad 160 is connected to the bottom first metal layer 140, and multiple first metal layers 140 are interconnected. The top first metal layer 140 is connected to the bottom second metal layer 240 through a first metal bonding structure 150 and a second metal bonding structure 250, enabling the first pad 160 to connect the driver module 500 and the logic module 600. The first pad 160 enables signal interconnection between the driver module 500 and the logic module 600 and external circuits. The second pad 170 is connected to the second metal layer 240 and / or the third metal layer 330 through a direct interconnection structure 400. Since the second metal layer 240 and the third metal layer 330 are connected through a third metal bonding structure 260 and a fourth metal bonding structure 340, the second pad 170 enables the logic module 600 and the storage module 700 to connect, enabling signal interconnection between the logic module 600 and the driver module 500 and external circuits.

[0040] In one embodiment, the plurality of first metal layers 140 have three or more layers; the plurality of second metal layers 240 have three or more layers; and the plurality of third metal layers 330 have three or more layers.

[0041] In traditional processes, multi-layer stacked chips with a smaller number of nodes are directly fabricated using process technology, such as fabricating 7-8 metal layers. This approach has the following problems: First, process technology with a smaller number of nodes is inherently more expensive. The more metal layers there are, the finer the linewidth of the metal layers, and the higher the precision requirements, which also leads to a significant increase in cost. Second, the more metal layers there are, the higher the risk of failure due to interlayer alignment deviations, dielectric layer defects, or metal layer electromigration during the manufacturing process, resulting in lower cost and yield.

[0042] In this example, when fabricating the first wafer 100, the second wafer 200, and the third wafer 300 using different process technologies, the corresponding first metal layer 140, second metal layer 240, and third metal layer 330 must each have three or more layers to meet the requirements of driving display panels or other scenarios. This stacking design has the following advantages: three wafers can be fabricated using process technologies with different node numbers, which effectively reduces costs compared to using a single wafer with a smaller node number process technology; the number of metal layers required for each wafer is smaller, resulting in thicker linewidths and lower precision requirements, further reducing costs; and the decoupling of the process technologies for the three wafers, with fewer metal layers in each wafer, reduces the risk of failure due to inter-layer alignment deviations, dielectric layer defects, or metal layer electromigration, thereby improving cost and yield.

[0043] In one embodiment, among the multiple metal layers corresponding to the same wafer, the bottom metal layer has the smallest thickness and the top metal layer has the largest thickness.

[0044] As an example, among the multiple first metal layers 140 on the first wafer 100, when the chip is operating, the current flowing through the bottom first metal layer 140 is relatively small, so the thickness of the bottom first metal layer 140 is designed to be the smallest to meet performance requirements; while the current flowing through the top first metal layer 140 is relatively large, so the thickness of the top first metal layer 140 is designed to be the largest to reduce the resistance of the top first metal layer 140, enabling it to transmit large currents and meet signal transmission requirements. Similarly, in the design of the second wafer 200, the thickness of the bottom second metal layer 240 is the smallest, and the thickness of the top second metal layer 240 is the largest; and in the design of the third wafer 300, the thickness of the bottom third metal layer 330 is the smallest, and the thickness of the top third metal layer 330 is the largest.

[0045] In one embodiment, all of the plurality of first metal layers 140 are copper metal layers; or, all of the plurality of first metal layers 140 are aluminum metal layers; or, a portion of the plurality of first metal layers 140 are aluminum metal layers and another portion are copper metal layers.

[0046] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100. The plurality of first metal layers 140 are all copper metal layers. Since copper has a low resistivity, it can ensure its transmission efficiency, reduce signal delay and energy loss, and thus ensure its overall performance.

[0047] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100. The plurality of first metal layers 140 are all aluminum metal layers. Since the aluminum metal layers are usually processed on the wafer using mature semiconductor manufacturing processes (such as sputtering deposition and dry etching), they have strong adhesion to the substrate and are not prone to interface peeling. The material cost and processing cost are both low, which can effectively reduce the manufacturing cost.

[0048] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100, a portion of which are aluminum metal layers and another portion are copper metal layers, for example. Figure 1 The four first metal layers 140 closest to the first substrate 110 are aluminum metal layers, and the first metal layer 140 furthest from the first substrate 110 is a copper metal layer. This allows the aluminum metal layer to meet the low-cost requirement, while the copper metal layer can meet the high-voltage and high-current requirement, effectively reducing signal delay and loss, thereby ensuring overall performance and achieving a balance between cost and performance requirements.

[0049] In one embodiment, the plurality of second metal layers 240 and the plurality of third metal layers 330 are all copper metal layers.

[0050] As an example, the multiple second metal layers 240 on the second wafer 200 and the multiple third metal layers 330 on the third wafer 300 are both copper metal layers. Since copper has a low resistivity, it can ensure its transmission efficiency, reduce signal delay and energy loss, and thus ensure its overall performance.

[0051] In one embodiment, the first dielectric layer 130 is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer 230 is a SiN dielectric layer or a SiO2 dielectric layer; the transition dielectric layer 270 is a SiN dielectric layer or a SiO2 dielectric layer; and the first metal bonding structure 150, the second metal bonding structure 250, the third metal bonding structure 260 and the fourth metal bonding structure 340 are all copper bonding structures.

[0052] As an example, the first dielectric layer 130, the second dielectric layer 230, and the transition dielectric layer 270 are all SiN or SiO2 dielectric layers. This allows for high-precision grinding and etching to create a smooth bonding interface when the first dielectric layer 130 is bonded to the transition dielectric layer 270, and when the second dielectric layer 230 is bonded to the third dielectric layer 320. This prevents cracking and ensures the structural reliability of the final stacked chip. Furthermore, the bonding process is mature and cost-effective. Similarly, the first metal bonding structure 150, the second metal bonding structure 250, the third metal bonding structure 260, and the fourth metal bonding structure 340 are all copper bonding structures. This ensures tight connections after metal bonding, reduces interconnect losses and signal delays, and guarantees the overall performance of the final stacked chip. Moreover, the copper-copper bonding process is mature and cost-effective, balancing performance and cost requirements.

[0053] In one embodiment, the first wafer 100 includes a first substrate 110 and a multi-gate oxide device 120 disposed on the front side of the first substrate 110, the multi-gate oxide device 120 including at least two gate oxide devices with different gate oxide thicknesses; the second wafer 200 includes a second substrate 210 and a single gate oxide device 220 disposed on the front side of the second substrate 210, the single gate oxide device 220 including multiple gate oxide devices with the same gate oxide thickness; the gate oxide thickness of the multi-gate oxide device 120 is greater than the gate oxide thickness of the single gate oxide device 220.

[0054] The first substrate 110 and the second substrate 210 are the substrates of the first wafer 100 and the second wafer 200, respectively, serving as the substrate carriers for the wafers, typically Si substrates. The front side of the substrate is the side that supports the functional devices, while the back side is the side that assists in fixing or other functions. A multi-gate oxide device 120 is integrated on the first wafer 100, including at least two gate oxide devices with different gate oxide thicknesses. A single-gate oxide device 220 is integrated on the second wafer 200, including multiple gate oxide devices with the same gate oxide thickness. The gate oxide device includes gate oxide and polysilicon integrated on the gate oxide. The gate oxide is disposed on one surface of the substrate. The formation and disappearance of communication on the substrate surface are controlled by the electric field of the gate oxide device. In other words, the gate oxide, polysilicon, and substrate work together to form a complete switching structure, enabling voltage-controlled current switching.

[0055] As an example, the multi-gate oxide device 120 is connected to the front side of the first substrate 110, specifically disposed within the bottom first dielectric layer 130. The multi-gate oxide device 120 includes multiple gate oxide devices with different gate oxide thicknesses. For example, it integrates three gate oxide devices with different gate oxide thicknesses on the first substrate 110. It may include... Figure 1 The first gate oxide thickness device 121, the second gate oxide thickness device 122, and the third gate oxide thickness device 123 are shown. Each gate oxide thickness represents a functional device corresponding to a certain operating voltage, enabling the first gate oxide thickness device 121, the second gate oxide thickness device 122, and the third gate oxide thickness device 123 on the first wafer 100 to control the operation of at least three functional devices corresponding to different operating voltages. For example, they can control the operation of high-voltage devices, medium-voltage devices, and I / O devices. In this example, the first wafer 100 is provided with a drive module 500, and the multi-gate oxide device 120 is a part of the functional devices in the drive module 500 that implement drive control.

[0056] The single-gate oxide device 220 is in contact with the front side of the second substrate 210, specifically disposed within the bottom second dielectric layer 230. The single-gate oxide device 220 includes multiple gate oxide devices with the same gate oxide thickness, for example... Figure 1 The fourth gate oxide thickness device 221 shown has multiple gate oxide devices with the same gate oxide thickness, enabling multiple fourth gate oxide thickness devices 221 on the second wafer 200 to control the operation of a functional device corresponding to a certain operating voltage, for example, to control the operation of a low-voltage device. In this example, a logic module 600 is provided on the second wafer 200, and the single gate oxide device 220 is a functional device in the logic module 600 that implements logic control.

[0057] The gate oxide thickness of the multi-gate oxide device 120 is greater than that of the single-gate oxide device 220, indicating that the thicker gate oxide of the multi-gate oxide device 120 provides stronger load-bearing capacity. The fabrication process for the multi-gate oxide device 120 involves a larger number of nodes, is more mature, and has lower cost. Conversely, the single-gate oxide device 220 has a thinner gate oxide, resulting in weaker load-bearing capacity. The fabrication process for the single-gate oxide device 220 involves a smaller number of nodes, is more advanced, and has higher cost. However, the single-gate oxide device 220 has a larger on-state current, leading to faster switching speed and lower power consumption, thus ensuring overall performance. In this example, a first wafer 100 with multi-gate oxide devices 120 can be fabricated using a process with a larger number of nodes, while a second wafer 200 with single-gate oxide devices 220 can be fabricated using a process with a smaller number of nodes. This process decouples the fabrication processes of the first wafer 100 and the second wafer 200, achieving a balance between low cost and ensuring the overall performance of the stacked chip structure. The first wafer 100 and the second wafer 200 are stacked and bonded to enable high-density interconnection between the two wafers, which helps to save area and improve overall performance.

[0058] In this example, the manufacturing processes of the first wafer 100 and the second wafer 200 are decoupled. This means that the iteration speed of the stacked chip depends on the manufacturing processes of the two wafers. Since the first wafer 100 is manufactured using a process with a higher node count, the process is more mature, resulting in a slower iteration speed. Conversely, the second wafer 200 is manufactured using a process with a lower node count, the process is more advanced, and the iteration speed is faster. When the manufacturing process of the second wafer 200 is updated, the stacked chip is updated accordingly, thereby improving the iteration speed of the stacked chip and freeing it from the constraints of the manufacturing process update speed of the first wafer 100.

[0059] In one embodiment, the multi-gate oxide device 120 includes a first gate oxide thickness device 121, a second gate oxide thickness device 122, and a third gate oxide thickness device 123; the gate oxide thickness of the first gate oxide thickness device 121 is 60nm-90nm; the gate oxide thickness of the second gate oxide thickness device 122 is 12nm-20nm; and the gate oxide thickness of the third gate oxide thickness device 123 is 5nm-8nm.

[0060] As an example, the gate oxide thickness of the multi-gate oxide device 120 is relatively large, allowing it to be fabricated using a process with a high number of nodes. Specifically, a high-voltage process (i.e., HV process) with a node count of 110nm / 90nm can be used to fabricate at least two gate oxide devices with different gate oxide thicknesses. Each gate oxide thickness corresponds to a functional device with a specific operating voltage. For instance, when the stacked chip structure is used in DDIC or TDDI, the functional devices corresponding to different operating voltages are the devices that drive the display panel, and these can be high-voltage devices (HV devices), medium-voltage devices (MV devices), or I / O devices.

[0061] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a first gate oxide thickness device 121 with a gate oxide thickness of 60nm-90nm. For example, a first gate oxide thickness device 121 with a gate oxide thickness of 85nm can be fabricated, enabling the first gate oxide thickness device 121 to operate normally under a voltage of 20V-32V, thereby ensuring the voltage withstand performance of the first gate oxide thickness device 121. For example, when the stacked structure chip is used in DDIC or TDDI, the first gate oxide thickness device 121 with a gate oxide thickness of 60nm-90nm is a high-voltage device (HV device) used to process high-voltage signals.

[0062] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a second gate oxide thickness device 122 with a gate oxide thickness of 12nm-20nm. For example, a second gate oxide thickness device 122 with a gate oxide thickness of 18nm can be fabricated, enabling the second gate oxide thickness device 122 to operate normally under a voltage of 5V-10V, thereby ensuring the voltage withstand performance of the second gate oxide thickness device 122. For example, when the stacked chip structure is used in DDIC or TDDI, the second gate oxide thickness device 122 with a gate oxide thickness of 12nm-20nm is a medium-voltage device (MV device) used to process medium-voltage signals.

[0063] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a third gate oxide thickness device 123 with a gate oxide thickness of 5nm-8nm. For example, a third gate oxide thickness device 123 with a gate oxide thickness of 6nm can be fabricated, enabling the third gate oxide thickness device 123 to operate normally at 1.8V, 2.5V, or 3.3V to ensure its withstand voltage performance. For example, when the stacked chip structure is used in DDIC or TDDI, the third gate oxide thickness device 123 with a gate oxide thickness of 5nm-8nm serves as an I / O device for input or output signals.

[0064] In one embodiment, the gate oxide thickness of the single gate oxide device 220 is 1 nm to 3 nm.

[0065] As an example, the single-gate oxide device 220 has a relatively small gate oxide thickness, allowing it to be fabricated using a process with a smaller node count. Specifically, it can be fabricated using logic processes with node counts of 55nm / 40nm / 28nm / 22nm / 16nm, resulting in a gate oxide thickness of 1nm-3nm for the single-gate oxide device 220. This allows the single-gate oxide device 220 to be used with functional devices operating at lower voltages, meeting high-performance requirements. For instance, when the stacked chip structure is used in DDIC or TDDI, the functional devices operating at lower voltages are logic devices that control the operation of the display panel.

[0066] In this example, a logic process with a node count of 55nm / 40nm can be used to fabricate a fourth gate oxide thickness device 221 with a gate oxide thickness of 2nm-3nm. For example, a fourth gate oxide thickness device 221 with a gate oxide thickness of 2.5nm can be fabricated, enabling the fourth gate oxide thickness device 221 to operate normally at a voltage of 1.1V-1.2V. This ensures the voltage withstand capability of the fourth gate oxide thickness device 221 while meeting the performance requirements of high-speed operation and low power consumption. For example, when the stacked chip structure is used in DDIC or TDDI, the fourth gate oxide thickness device 221 with a gate oxide thickness of 2nm-3nm serves as a logic device for processing logic signals, capable of high-speed operation at a voltage of 1.1V-1.2V, and exhibiting good overall performance.

[0067] In this example, a logic process with node numbers of 28nm / 22nm / 16nm can be used to fabricate a fourth gate oxide thickness device 221 with a gate oxide thickness of 1nm-2nm. For example, a fourth gate oxide thickness device 221 with a gate oxide thickness of 1.5nm can be fabricated, enabling the fourth gate oxide thickness device 221 to operate normally at a voltage of 0.8V-0.9V. This ensures the voltage withstand capability of the fourth gate oxide thickness device 221 while meeting the performance requirements of high-speed operation and low power consumption. For example, when the stacked chip structure is used in DDIC or TDDI, the fourth gate oxide thickness device 221 with a gate oxide thickness of 1nm-2nm serves as a logic device for processing logic signals, enabling high-speed operation at a voltage of 0.8V-0.9V and resulting in better overall performance.

[0068] This utility model embodiment provides a display driver chip, including the stacked structure chip in the above embodiment; the driver module 500 includes a medium-high voltage section 510 of the data driver, a medium-high voltage section 520 of the timing controller, a medium-high voltage section 530 of the IO circuit, a medium-high voltage section 540 of the power management circuit, a medium-high voltage section 550 of the digital-to-analog converter circuit, and an ESD protection circuit 560; the logic module 600 includes a logic circuit 660, a low voltage section 610 of the data driver, a low voltage section 620 of the timing controller, a low voltage section 630 of the IO circuit, a low voltage section 640 of the power management circuit, a low voltage section 650 of the digital-to-analog converter circuit, a clock management circuit 670, and a high-speed interface circuit 680.

[0069] Among them, the display driver IC (hereinafter referred to as "DDIC") is a chip used to implement display driving.

[0070] The data driver is responsible for converting digital image signals into analog voltage signals that can directly drive the pixels of the display panel. The high-voltage section 510 of the data driver is the circuit unit responsible for processing high-voltage signals. In this embodiment, the high-voltage signal can be either a medium-voltage signal or a high-voltage signal. The low-voltage section 610 of the data driver is the circuit unit responsible for processing low-voltage signals.

[0071] The Timing Controller (TCON) is responsible for receiving external image data, parsing timing signals, and generating synchronization control signals required by the display panel (such as LCD and OLED) and driver chips. This ensures all modules operate at a unified pace, preventing image misalignment, tearing, or flickering. The high-voltage section 520 of the timing controller handles high-voltage signals. The low-voltage section 620 handles low-voltage signals.

[0072] An I / O circuit is responsible for data input and output. The high-voltage section 530 of the I / O circuit is the circuit unit responsible for processing high-voltage signals. The high-voltage section 530 of the I / O circuit is also the circuit unit responsible for processing low-voltage signals.

[0073] The power management circuit is used to convert and manage the power supply to the chip and display panel. The medium-high voltage section 540 of the power management circuit is the circuit unit used to process medium-high voltage signals. The low-voltage section 640 of the power management circuit is the circuit unit used to process low-voltage signals.

[0074] A digital-to-analog converter (DAC) is used to convert digital signals (such as grayscale data output by a TCON) into analog voltage signals. The high-voltage section 550 of the DAC is responsible for processing high-voltage signals. The low-voltage section 650 is responsible for processing low-voltage signals.

[0075] ESD (Electrostatic Discharge) protection circuits are primarily used to safely discharge instantaneous large currents / high voltages generated by static electricity to ground, preventing damage to sensitive components. Generally, the core components of the ESD protection circuit 560 (such as TVS diodes and ESD diode arrays) must be connected to the copper foil traces of the circuit board via pads to achieve effective discharge of electrostatic current. Since the pads of the stacked chip structure (i.e., the first pad 160) are all integrated on the first wafer 100, the ESD protection circuit 560 also needs to be integrated on the first wafer 100 to achieve a better protection effect.

[0076] Logic circuit 660 is a circuit that performs arithmetic and logical operations on digital quantities using digital signals; it is also known as a digital logic integrated circuit (IC). Clock management circuit 670 is the core unit responsible for generating, optimizing, and distributing clock signals. All digital logic relies on the "synchronous triggering" of the clock signal to ensure correct timing. High-speed interface circuit 680 is an interface for implementing high-speed data transmission, used to receive data transmitted from external circuits. In this example, logic circuit 660 interacts with clock management circuit 670 and high-speed interface circuit 680 via low-voltage signals. Therefore, these circuits need to be integrated into the second wafer 200 to ensure overall performance.

[0077] In this embodiment, the data driver, timing controller, I / O circuit, power management circuit, and digital-to-analog converter circuit all include medium-high voltage and low-voltage sections. The medium-high voltage sections of the above circuits and the ESD protection circuit 560 are integrated on a first wafer 100 capable of handling medium-high voltage signals. The above circuits include gate oxide devices 120 with different gate oxide thicknesses, allowing different gate oxide devices to be turned on or off based on medium-high voltage signals. The low-voltage section of the above circuits, as well as the logic circuit 660, clock management circuit 670, and high-speed interface circuit 680 communicating via low-voltage signals, are integrated on a second wafer 200. The above circuits include gate oxide devices 220 with the same gate oxide thickness, allowing them to be turned on or off based on low-voltage signals. In this example, since the pads of the stacked chip are all located on the first wafer 100, TSVs can be set on the first wafer 100 to enable direct interconnection and mutual trust between multiple wafers, so that the pads can communicate with the circuits of other wafers via the TSVs.

[0078] In this embodiment, the driving module 500 related to medium- and high-voltage signal processing is integrated on the first wafer 100, the logic module 600 related to low-voltage signal processing is integrated on the second wafer 200, and the storage module 700 is separately integrated on the third wafer 300. This allows the first wafer 100 to be fabricated using a process technology with a higher node count, while the second and third wafers 200 and 300 can be fabricated using a process technology with a lower node count. This decoupling of the process technologies of the three wafers allows different process technologies to be matched according to the performance requirements of different functional modules. The driving module 500 meets the performance requirements of providing high-voltage / high-current driving capability, the logic module 600 meets the performance requirements of high-speed computing capability, and the storage module 700 meets the performance requirements of high-density, low-power storage, thus achieving the goal of DDIC (Distributed Direct Component Integrated Circuit) that balances low cost and overall performance. Furthermore, since different functional modules are located on different wafers, the fabrication process of each wafer does not need to consider the performance compatibility between different functional modules, which also helps to reduce processing complexity, improve processing efficiency, and reduce processing costs.

[0079] This utility model embodiment provides a touch and display integrated driver chip, including the stacked structure chip in the above embodiment; the driver module 500 includes a medium-high voltage section 510 of the data driver, a medium-high voltage section 520 of the timing controller, a medium-high voltage section 530 of the IO circuit, a medium-high voltage section 540 of the power management circuit, a medium-high voltage section 550 of the digital-to-analog converter circuit, an ESD protection circuit 560, and a medium-high voltage section 570 of the touch circuit; the logic module 600 includes a logic circuit 660, a low voltage section 610 of the data driver, a low voltage section 620 of the timing controller, a low voltage section 630 of the IO circuit, a low voltage section 640 of the power management circuit, a low voltage section 650 of the digital-to-analog converter circuit, a clock management circuit 670, a high-speed interface circuit 680, and a low voltage section 690 of the touch circuit.

[0080] The Touch and Display Driver Integration (TDDI) chip is a chip that integrates display driving and touch control. It retains the display driving capability of DDIC and additionally integrates touch front-end circuitry to achieve integrated control of display and touch.

[0081] The touch circuit is the core circuit for realizing touch functionality. Its core function is to accurately acquire the physical touch signals from the touch panel (such as a capacitive touchscreen) and convert them into recognizable electrical signals. The high-voltage section 570 of the touch circuit is used to process high-voltage signals. The low-voltage section 690 of the touch circuit is used to process low-voltage signals.

[0082] In this embodiment, the data driver, timing controller, I / O circuit, power management circuit, digital-to-analog converter circuit, and touch circuit all include medium-high voltage and low-voltage sections. The medium-high voltage sections and ESD protection circuit 560 of the above circuits are integrated on a first wafer 100 capable of handling medium-high voltage signals. The above circuits include gate oxide devices 120 with different gate oxide thicknesses, allowing different gate oxide devices to be turned on or off based on medium-high voltage signals. The low-voltage section of the above circuits, as well as the logic circuit 660, clock management circuit 670, and high-speed interface circuit 680 communicating via low-voltage signals, are integrated on a second wafer 200. The above circuits include gate oxide devices 220 with the same gate oxide thickness, allowing them to be turned on or off based on low-voltage signals.

[0083] In this embodiment, the driving module 500 related to medium- and high-voltage signal processing is integrated on the first wafer 100, the logic module 600 related to low-voltage signal processing is integrated on the second wafer 200, and the storage module 700 is separately integrated on the third wafer 300. This allows the first wafer 100 to be fabricated using a process technology with a higher node count, while the second and third wafers 200 and 300 can be fabricated using a process technology with a lower node count. This decoupling of the process technologies of the three wafers allows different process technologies to be matched according to the performance requirements of different functional modules. The driving module 500 meets the performance requirements of providing high-voltage / high-current driving capability, the logic module 600 meets the performance requirements of high-speed computing capability, and the storage module 700 meets the performance requirements of high-density, low-power storage, thus achieving the goal of TDDI to balance low cost and overall performance. The separate placement of the storage module 700 on the third wafer 300 enables large storage capacity, supports richer data storage and retrieval functions, supports more image processing functions, and supports AI expansion. Furthermore, since different functional modules are set on different wafers, the fabrication process of each wafer does not need to consider the performance compatibility between different functional modules, which also helps to reduce processing complexity, improve processing efficiency, and reduce processing costs. Compared with DDIC, TDDI additionally sets up a touch circuit, integrating the high-voltage part 570 and the low-voltage part 690 of the touch circuit on the first wafer 100 and the second wafer 200 respectively. The process technology of the two wafers is decoupled, which allows the final touch circuit to meet the requirements of low cost and high performance.

[0084] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A stacked chip structure, characterized in that, This includes a first wafer, a second wafer, and a third wafer stacked sequentially. The first wafer is provided with a driver module, the second wafer is provided with a logic module, and the third wafer is provided with a storage module; The first wafer is bonded to the second wafer, and the second wafer is bonded to the third wafer.

2. The stacked structure chip according to claim 1, characterized in that, The first wafer is provided with a first pad and a second pad. The first pad is electrically connected to the driving module and the logic module, and the second pad is electrically connected to the logic module and the storage module through a direct interconnect structure.

3. The stacked structure chip according to claim 2, characterized in that, The second wafer is provided with a transition dielectric layer; The direct interconnect structure includes a first TSV, a transition metal layer, and a second TSV. The transition metal layer is disposed within the transition dielectric layer; One end of the first TSV is connected to the second pad, and the other end of the first TSV is connected to the transition metal layer; One end of the second TSV is connected to the transition metal layer, and the other end of the second TSV is connected to the logic module and / or the storage module.

4. The stacked structure chip according to claim 3, characterized in that, The direct interconnection structure is a tungsten direct interconnection structure or a copper direct interconnection structure; Alternatively, a portion of the first TSV, the transition metal layer, and the second TSV may be filled with tungsten metal, while the other portion may be filled with copper metal.

5. The stacked structure chip according to claim 3, characterized in that, The first wafer includes a first substrate, a plurality of first dielectric layers, a plurality of first metal layers, a first metal bonding structure, a first pad, and a second pad; the plurality of first dielectric layers and the plurality of first metal layers are alternately disposed, the bottom first dielectric layer is in contact with the front side of the first substrate, and the top first metal layer is in contact with the first metal bonding structure; The second wafer includes a second substrate, a plurality of second dielectric layers, a plurality of second metal layers, a second metal bonding structure, and a third metal bonding structure; Multiple second dielectric layers and multiple second metal layers are alternately disposed, the bottom second dielectric layer is in contact with the front side of the second substrate, the transition dielectric layer is in contact with the back side of the second substrate, the bottom second metal layer is in contact with the second metal bonding structure, the second metal bonding structure is disposed in the transition dielectric layer, and the top second metal layer is in contact with the third metal bonding structure. The third wafer includes a third substrate, multiple third dielectric layers, multiple third metal layers, and a fourth metal bonding structure; Multiple third dielectric layers and multiple third metal layers are alternately disposed, with the bottom third dielectric layer in contact with the front side of the third substrate and the top third metal layer in contact with the fourth metal bonding structure. The first dielectric layer at the top is bonded to the transition dielectric layer, and the first metal bonding structure is bonded to the second metal bonding structure; The second dielectric layer and the third dielectric layer of the top layer are bonded together, and the third metal bonding structure is bonded to the fourth metal bonding structure; The first pad is connected to the first metal layer of the underlying layer, and the second pad is connected to the second metal layer and / or the third metal layer through the direct interconnect structure.

6. The stacked structure chip according to claim 5, characterized in that, The number of the plurality of first metal layers is three or more; the number of the plurality of second metal layers is three or more; the number of the plurality of third metal layers is three or more.

7. The stacked structure chip according to claim 5, characterized in that, Among the multiple metal layers corresponding to the same wafer, the bottom metal layer has the smallest thickness, and the top metal layer has the largest thickness.

8. The stacked structure chip according to claim 5, characterized in that, All of the first metal layers are copper metal layers; Alternatively, all of the first metal layers may be aluminum metal layers; Alternatively, one portion of the plurality of the first metal layers may be an aluminum metal layer and another portion may be a copper metal layer.

9. The stacked structure chip according to claim 5, characterized in that, The plurality of second metal layers and the plurality of third metal layers are all copper metal layers.

10. The stacked structure chip according to claim 5, characterized in that, The first dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; the transition dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; The first metal bonding structure, the second metal bonding structure, the third metal bonding structure, and the fourth metal bonding structure are all copper bonding structures.

11. The stacked structure chip according to any one of claims 1-10, characterized in that, The first wafer includes a first substrate and a multi-gate oxide device disposed on the front side of the first substrate, the multi-gate oxide device including at least two gate oxide devices with different gate oxide thicknesses; The second wafer includes a second substrate and a single gate oxide device disposed on the front side of the second substrate, wherein the single gate oxide device includes a plurality of gate oxide devices with the same gate oxide thickness; The gate oxide thickness of the multi-gate oxide device is greater than that of the single-gate oxide device.

12. The stacked structure chip according to claim 11, characterized in that, The multi-gate oxide device includes a first gate oxide thickness device, a second gate oxide thickness device, and a third gate oxide thickness device; The gate oxide thickness of the first gate oxide thickness device is 60nm-90nm; The gate oxide thickness of the second gate oxide thickness device is 12nm-20nm; The gate oxide thickness of the third gate oxide thickness device is 5nm-8nm.

13. The stacked structure chip according to claim 11, characterized in that, The gate oxide thickness of the single-gate oxide device is 1nm-3nm.

14. A display driver chip, characterized in that, Includes the stacked structure chip as described in any one of claims 1-13; The drive module includes the medium- and high-voltage sections of the data driver, the medium- and high-voltage sections of the timing controller, the medium- and high-voltage sections of the I / O circuit, the medium- and high-voltage sections of the power management circuit, the medium- and high-voltage sections of the digital-to-analog converter circuit, and the ESD protection circuit. The logic module includes logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a clock management circuit, and a high-speed interface circuit.

15. A touch and display integrated driver chip, characterized in that, Includes the stacked structure chip as described in any one of claims 1-13; The drive module includes the medium-high voltage section of the data driver, the medium-high voltage section of the timing controller, the medium-high voltage section of the IO circuit, the medium-high voltage section of the power management circuit, the medium-high voltage section of the digital-to-analog conversion circuit, the ESD protection circuit, and the medium-high voltage section of the touch circuit. The logic module includes logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a clock management circuit, a high-speed interface circuit, and a low-voltage section of a touch circuit.

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