Chip frequency test circuit and chip frequency test device
Patent Information
- Application Number
- CN202522195231.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-10-16
AI Technical Summary
In existing technologies, ATE testing equipment has low accuracy in chip frequency testing, resulting in reduced test accuracy.
Design a chip frequency test circuit, including a path switching module, through which the frequency signal of the chip under test is output to ATE test equipment and/or frequency meter, and the test equipment is selected according to user needs to improve test accuracy and precision.
Using a frequency meter for testing when high precision is required, and using ATE testing equipment when precision requirements are reduced, or using both simultaneously, improves the accuracy and efficiency of chip frequency testing.
Smart Images
Figure CN224934066U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of chip technology, and in particular relates to a chip frequency testing circuit and a chip frequency testing device. Background Technology
[0002] With the continuous development of technology, many industries (such as communication technology, navigation technology, and industrial production technology) have increasingly higher requirements for the frequency testing accuracy of chips.
[0003] Currently, existing technologies typically use ATE (Automatic Test Equipment) to test the frequency of chips. However, although ATE equipment can test various performance parameters of chips, its frequency testing accuracy is low, which reduces the accuracy of chip frequency testing. Summary of the Invention
[0004] In view of this, embodiments of this application provide a chip frequency testing circuit and a chip frequency testing device to solve the technical problem of low accuracy in testing chip frequency in the prior art.
[0005] In a first aspect, embodiments of this application provide a chip frequency testing circuit, the circuit including a path switching module; the input terminal of the path switching module is connected to the frequency output terminal of the chip under test, the first output terminal of the path switching module is connected to the first input terminal of an ATE test device, and the first output terminal of the path switching module is connected to the first input terminal of a frequency meter; The path switching module is configured to output the frequency signal from the frequency output terminal of the chip under test to the ATE test equipment and / or the frequency meter.
[0006] Optionally, the path switching module includes a first relay, a second relay, a third relay, and a control signal input terminal; the common terminal of the first relay and the common terminal of the second relay are connected to the frequency output terminal of the chip under test; the normally open terminal of the first relay and the common terminal of the third relay are connected to the first input terminal of the ATE test equipment; the normally open terminal of the third relay and the normally closed terminal of the second relay are connected to the first input terminal of the frequency meter; and the controlled terminals of the first relay, the second relay, and the third relay are respectively connected to the control signal input terminal.
[0007] Optionally, the path switching module includes a first relay, a second relay, a third relay, and a control signal input terminal; the common terminal of the first relay and the common terminal of the second relay are connected to the frequency output terminal of the chip under test; the normally closed terminal of the first relay and the common terminal of the third relay are connected to the first input terminal of the ATE test equipment; the normally open terminal of the third relay and the normally open terminal of the second relay are connected to the first input terminal of the frequency meter; and the controlled terminals of the first relay, the second relay, and the third relay are respectively connected to the control signal input terminal.
[0008] Optionally, the circuit further includes a voltage output module; the first output terminal of the voltage output module is connected to the first input terminal of the chip under test, the second output terminal of the voltage output module is connected to the second input terminal of the chip under test, and the controlled terminal of the voltage output module is connected to the control terminal of the ATE test equipment. The ATE test equipment is configured to send a first control command and a second control command to the voltage output module; The voltage output module is configured to determine, according to the first control instruction, a target port for outputting voltage to the chip under test from the first output terminal and the second output terminal of the voltage output module, and to determine the target parameters for outputting voltage to the chip under test according to the second control instruction.
[0009] Optionally, the voltage output module includes a filtering unit; the filtering unit includes a fourth relay, a fifth relay, a first capacitor, and a second capacitor; the common terminal of the fourth relay, the first output terminal of the voltage output module, and the first controlled terminal of the voltage output module are all connected together; the normally closed terminal of the fourth relay is connected to the first terminal of the first capacitor; the second terminal of the first capacitor and the first terminal of the second capacitor are all connected to ground; the second terminal of the second capacitor is connected to the normally closed terminal of the fifth relay; and the common terminal of the fifth relay, the second output terminal of the voltage output module, and the second controlled terminal of the voltage output module are all connected together.
[0010] Optionally, the circuit further includes a first communication module; the first input terminal of the first communication module is connected to the first output terminal of the ATE test equipment, the second input terminal of the first communication module is connected to the second output terminal of the ATE test equipment, the first output terminal of the first communication module is connected to the third input terminal of the chip under test, and the second output terminal of the first communication module is connected to the fourth input terminal of the chip under test. The first communication module is configured to receive a clock signal sent by the ATE test equipment through a first input terminal of the first communication module, and send the clock signal to the chip under test through a first output terminal of the first communication module; and is also configured to receive a data signal sent by the ATE test equipment through a second input terminal of the first communication module, and send the data signal to the chip under test through a second output terminal of the first communication module.
[0011] Optionally, the first communication module includes a signal stabilization unit; the first output terminal of the signal stabilization unit, the first input terminal of the first communication module, and the first output terminal of the first communication module are all connected together, the second output terminal of the signal stabilization unit, the second input terminal of the first communication module, and the second output terminal of the first communication module are all connected together, and the input terminal of the signal stabilization unit is connected to the power supply terminal of the ATE test equipment. The signal stabilization unit is configured to send a high-level signal to the third input terminal of the chip under test through the first output terminal of the signal stabilization unit when the first input terminal of the first communication module does not receive the clock signal sent by the ATE test equipment; and is configured to send a high-level signal to the fourth input terminal of the chip under test through the second output terminal of the signal stabilization unit when the second input terminal of the first communication module does not receive the data signal sent by the ATE test equipment.
[0012] Optionally, the signal stabilization unit includes a first resistor, a second resistor, a sixth relay, and a seventh relay; the first end of the first resistor and the first end of the second resistor are connected together as the input terminal of the signal stabilization unit, the second end of the first resistor is connected to the normally open terminal of the sixth relay, the second end of the second resistor is connected to the normally open terminal of the seventh relay, the common terminal of the sixth relay serves as the first output terminal of the signal stabilization unit, and the common terminal of the seventh relay serves as the second output terminal of the signal stabilization unit.
[0013] Optionally, the circuit further includes a second communication module; The first input terminal of the second communication module is connected to the third output terminal of the ATE test equipment; the first output terminal of the second communication module is connected to the second input terminal of the frequency meter; the second input terminal of the second communication module is connected to the output terminal of the frequency meter; and the second output terminal of the second communication module is connected to the second input terminal of the ATE test equipment. The second communication module is configured to receive a frequency meter control command sent by the ATE test equipment and send the frequency meter control command to the frequency meter; and is also configured to receive a data signal sent by the frequency meter and send the data signal to the ATE test equipment.
[0014] Secondly, embodiments of this application provide a chip frequency testing device, which includes a plurality of chip frequency testing circuits as described in any of the first aspects.
[0015] The chip frequency testing circuit and chip frequency testing equipment provided in this application have the following beneficial effects: The chip frequency testing circuit provided in this application includes a path switching module. The input terminal of the path switching module is connected to the frequency output terminal of the chip under test (DUT), the first output terminal of the path switching module is connected to the first input terminal of an ATE testing device, and the first output terminal of the path switching module is connected to the first input terminal of a frequency meter. The path switching module is configured to output the frequency signal from the frequency output terminal of the DUT to the ATE testing device and / or the frequency meter. With the chip frequency testing circuit provided in this application, when the user has high requirements for the accuracy of chip frequency testing, a frequency meter specifically designed for testing chip frequencies can be used to test the chip frequency, improving the accuracy of chip frequency testing. When the user has lower requirements for the accuracy of chip frequency testing, an ATE testing device capable of testing various performance parameters of the chip can be used to test the chip frequency, improving the efficiency of chip frequency testing. Furthermore, the frequency of the DUT can be tested jointly by the ATE testing device and the frequency meter, further improving the accuracy of chip frequency testing. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the structure of a chip frequency testing circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a path switching module provided in an embodiment of this application; Figure 3 A schematic diagram of a path switching module provided in another embodiment of this application; Figure 4 A schematic diagram of a chip frequency testing circuit provided in another embodiment of this application; Figure 5 This is a schematic diagram of the structure of a voltage output module provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a chip frequency testing circuit provided in another embodiment of this application; Figure 7 This is a schematic diagram of the structure of a first communication module provided in an embodiment of this application; Figure 8 A schematic diagram of a chip frequency testing circuit is provided in another embodiment of this application; Figure 9 This is a schematic diagram of the structure of a chip frequency testing device provided in an embodiment of this application. Detailed Implementation
[0018] It should be noted that the terminology used in the embodiments of this application is only for explaining specific embodiments of this application and is not intended to limit this application. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, "at least one" or "one or more" means one, two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
[0019] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0020] In existing technologies, the frequency of a chip is usually tested using ATE (Automatic Test Equipment). ATE equipment can test various performance parameters of a chip, but compared to a frequency meter specifically designed for testing chip frequency, ATE equipment has lower accuracy in testing chip frequency, thus reducing the accuracy of chip frequency testing.
[0021] Based on this, embodiments of this application provide a chip frequency testing circuit to solve the technical problem of low accuracy in testing chip frequency in the prior art. Please refer to... Figure 1 , Figure 1This is a schematic diagram of a chip frequency testing circuit provided in an embodiment of this application.
[0022] like Figure 1 As shown, the chip frequency test circuit provided in this application embodiment includes a path switching module 11.
[0023] The input terminal of the path switching module 11 is connected to the frequency output terminal of the chip under test, the first output terminal of the path switching module 11 is connected to the first input terminal of the ATE test equipment, and the first output terminal of the path switching module 11 is connected to the first input terminal of the frequency meter.
[0024] The path switching module 11 can be configured to output the frequency signal of the frequency output terminal of the chip under test to the ATE test equipment and / or frequency meter.
[0025] Specifically, the path switching module 11 can output the frequency signal of the frequency output terminal of the chip under test to the ATE test equipment or frequency meter according to the control signal input by the user, so as to test the frequency of the chip under test through the ATE test equipment and / or frequency meter.
[0026] In practical applications, when users have high requirements for the frequency testing accuracy of chips, they can send a first control signal to the channel switching module 11 to instruct the channel switching module 11 to output the frequency signal of the frequency output terminal of the chip under test to the frequency meter, so as to test the frequency of the chip under test through the frequency meter and improve the accuracy of testing the chip frequency.
[0027] Similarly, when the user has low requirements for the frequency testing accuracy of the chip, a second control signal can be sent to the channel switching module 11 to instruct the channel switching module 11 to output the frequency signal of the frequency output terminal of the chip under test to the ATE test equipment, so as to test the frequency of the chip under test through the ATE test equipment and improve the efficiency of testing the chip frequency.
[0028] Optionally, when a user wants to test the frequency of the chip under test using both the ATE test equipment and the frequency meter, a third control signal can be sent to the path switching module 11 to instruct the path switching module 11 to simultaneously output the frequency signal of the chip under test's frequency output terminal to both the ATE test equipment and the frequency meter, thereby testing the frequency of the chip under test using both the ATE test equipment and the frequency meter, further improving the efficiency of testing the chip frequency.
[0029] As can be seen from the above, the chip frequency testing circuit provided in this application includes a path switching module; the input terminal of the path switching module is connected to the frequency output terminal of the chip under test, the first output terminal of the path switching module is connected to the first input terminal of the ATE test equipment, and the first output terminal of the path switching module is connected to the first input terminal of the frequency meter; the path switching module is configured to output the frequency signal of the frequency output terminal of the chip under test to the ATE test equipment and / or the frequency meter. With the chip frequency testing circuit provided in this application, when the user has high requirements for the frequency testing accuracy of the chip, a frequency meter specifically designed for testing chip frequencies can be used to test the chip frequency, improving the accuracy of chip frequency testing. When the user has lower requirements for the frequency testing accuracy of the chip, an ATE test equipment capable of testing various performance parameters of the chip can be used to test the chip frequency, improving the efficiency of chip frequency testing. Furthermore, the frequency of the chip under test can be tested jointly by the ATE test equipment and the frequency meter, further improving the accuracy of chip frequency testing.
[0030] In one possible implementation, the structural diagram of the path switching module provided in this application embodiment can be as follows: Figure 2 As shown.
[0031] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a path switching module provided in an embodiment of this application. Figure 2 As shown, the path switching module 11 may include a first relay K1, a second relay K2, a third relay K3, and a control signal input terminal IN.
[0032] The common terminal of the first relay K1 and the common terminal of the second relay K2 are connected to the frequency output terminal of the chip under test. The normally open terminal of the first relay K1 and the common terminal of the third relay K3 are connected to the first input terminal of the ATE test equipment. The normally open terminal of the third relay K3 and the normally closed terminal of the second relay K2 are connected to the first input terminal of the frequency meter. The controlled terminals of the first relay K1, the second relay K1, and the third relay K1 are respectively connected to the control signal input terminal IN.
[0033] It should be noted that, in Figure 2 In the first relay K1, the port pointed to by the switch is the normally closed terminal of the first relay K1, and the port not pointed to by the switch is the normally open terminal of the first relay K1; in the second relay K2, the port pointed to by the switch is the normally closed terminal of the second relay K2, and the port not pointed to by the switch is the normally open terminal of the second relay K2; in the third relay K3, the port pointed to by the switch is the normally closed terminal of the third relay K3, and the port not pointed to by the switch is the normally open terminal of the third relay K3.
[0034] Specifically, Figure 1 In the corresponding embodiment, the first control signal can control the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 to close and the normally open terminals to open. Combined with... Figure 2 It can be seen that when the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 are closed and their normally open terminals are open, the frequency signal output from the frequency output terminal of the chip under test is output to the frequency meter, thereby testing the frequency of the chip under test through the frequency meter.
[0035] Specifically, Figure 1 In the corresponding embodiment, the second control signal can control the normally closed terminals of the first relay K1 and the second relay K2 to open and the normally open terminals to close; and can control the normally closed terminal of the third relay K3 to close and the normally open terminal to open. Combined with... Figure 2 It can be seen that when the normally closed terminals of the first relay K1 and the second relay K2 are open and the normally open terminals are closed, and the normally closed terminal of the third relay K3 is closed and the normally open terminal is open, the frequency signal of the frequency output terminal of the chip under test is output to the ATE test equipment, thereby testing the frequency of the chip under test through the ATE test equipment.
[0036] Specifically, Figure 1 In the corresponding embodiment, the third control signal can control the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 to open and their normally open terminals to close. Combined with... Figure 2 It can be seen that when the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 are open and their normally open terminals are closed, the frequency signal of the frequency output terminal of the chip under test is simultaneously output to the ATE test equipment and the frequency meter, so that the frequency of the chip under test can be tested by the ATE test equipment and the frequency meter together.
[0037] In another possible implementation, the structural diagram of the path switching module provided in this application embodiment can be as follows: Figure 3 As shown.
[0038] Please see Figure 3 , Figure 3 This is a schematic diagram of a path switching module provided in another embodiment of this application. It should be noted that... Figure 3 The shown path switching module and Figure 2 Compared to the path switching module shown, the difference lies in Figure 3 The normally open terminals of the first relay K1 and the second relay K2 are respectively: Figure 2 The normally closed terminals of the first relay K1 and the second relay K2 in the circuit are respectively, and Figure 3The normally closed terminals of the first relay K1 and the second relay K2 are respectively: Figure 2 The normally open terminals of the first relay K1 and the second relay K2 are respectively.
[0039] like Figure 3 As shown, the path switching module 11 may include a first relay K1, a second relay K2, a third relay K3, and a control signal input terminal IN.
[0040] In this configuration, the common terminal of the first relay K1 and the common terminal of the second relay K2 are connected to the frequency output terminal of the chip under test. The normally closed terminal of the first relay K1 and the common terminal of the third relay K3 are connected to the first input terminal of the ATE test equipment. The normally open terminal of the third relay K3 and the normally open terminal of the second relay K2 are connected to the first input terminal of the frequency meter. The controlled terminals of the first relay K1, the second relay K2, and the third relay K3 are respectively connected to the control signal input terminal IN.
[0041] It should be noted that, in Figure 3 In the first relay K1, the port pointed to by the switch is the normally closed terminal of the first relay K1, and the port not pointed to by the switch is the normally open terminal of the first relay K1; in the second relay K2, the port pointed to by the switch is the normally closed terminal of the second relay K2, and the port not pointed to by the switch is the normally open terminal of the second relay K2; in the third relay K3, the port pointed to by the switch is the normally closed terminal of the third relay K3, and the port not pointed to by the switch is the normally open terminal of the third relay K3.
[0042] Specifically, Figure 1 In the corresponding embodiment, the first control signal can control the normally open terminals of the first relay K1 and the second relay K2 to close and the normally closed terminals to open, and control the normally closed terminal of the third relay K3 to close and the normally open terminal to open. Combined with... Figure 3 It can be seen that when the normally open terminals of the first relay K1 and the second relay K2 are closed and their normally closed terminals are open, and the normally closed terminal of the third relay K3 is closed and its normally open terminal is open, the frequency signal of the frequency output terminal of the chip under test is output to the frequency meter, thereby testing the frequency of the chip under test through the frequency meter.
[0043] Specifically, Figure 1 In the corresponding embodiment, the second control signal can control the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 to close and the normally open terminals to open. Combined with... Figure 3It can be seen that when the normally closed terminals of the first relay K1, the second relay K2, and the third relay K3 are closed and their normally open terminals are open, the frequency signal of the frequency output terminal of the chip under test is output to the ATE test equipment, thereby testing the frequency of the chip under test through the ATE test equipment.
[0044] Specifically, Figure 1 In the corresponding embodiment, the third control signal can control the normally closed terminal of the first relay K1 to close and the normally open terminal to open, and control the normally closed terminals of the second relay K2 and the third relay K3 to open and the normally open terminals to close, respectively. Combined with... Figure 3 It can be seen that when the normally closed terminal of the first relay K1 is closed and the normally open terminal is open, and when the normally closed terminals of the second relay K2 and the third relay K3 are opened and the normally open terminals are closed respectively, the frequency signal of the frequency output terminal of the chip under test is simultaneously output to the ATE test equipment and the frequency meter, so that the frequency of the chip under test can be tested by the ATE test equipment and the frequency meter together.
[0045] In one possible implementation, the chip frequency test circuit may also include a voltage output module. See also... Figure 4 , Figure 4 This is a schematic diagram of a chip frequency testing circuit provided in another embodiment of the application.
[0046] like Figure 4 As shown, the chip frequency test circuit provided in this application embodiment includes a voltage output module 12 in addition to the path switching module 11.
[0047] The first output terminal of the voltage output module 12 is connected to the first input terminal of the chip under test, the second output terminal of the voltage output module 12 is connected to the second input terminal of the chip under test, and the controlled terminal of the voltage output module 12 is connected to the control terminal of the ATE test equipment.
[0048] Based on this, the ATE test equipment can be configured to send a first control command and a second control command to the voltage output module 12.
[0049] The voltage output module 12 can be configured to determine the target port for outputting voltage to the chip under test from the first output terminal and the second output terminal of the voltage output module 12 according to the first control instruction, and to determine the target parameters for outputting voltage to the chip under test according to the second control instruction.
[0050] Specifically, the first output terminal of the voltage output module 12 can serve as the main power supply for the chip under test (DUT), and the second output terminal of the voltage output module 12 can serve as the backup power supply for the DUT. Based on this, the ATE test equipment can be configured to detect whether the first output terminal of the voltage output module 12 is working properly. If the first output terminal is working properly, a corresponding first control command is output to the voltage output module 12 to instruct the voltage output module 12 to designate the first output terminal as the target port for outputting voltage to the DUT. If the first output terminal is malfunctioning, a corresponding first control command is output to the voltage output module 12 to instruct the voltage output module 12 to designate the second output terminal as the target port for outputting voltage to the DUT.
[0051] In one possible implementation, the structural diagram of the voltage output module provided in this application embodiment can be as follows: Figure 5 As shown.
[0052] Please see Figure 5 , Figure 5 This is a schematic diagram of a voltage output module provided in an embodiment of this application. Figure 5 As shown, the voltage output module 12 includes a filtering unit.
[0053] The filtering unit includes a fourth relay K4, a fifth relay K5, a first capacitor C1, and a second capacitor C2. The common terminal of the fourth relay K4, the first output terminal of the voltage output module 12, and the first controlled terminal of the voltage output module 12 are all connected together. The normally closed terminal of the fourth relay K4 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are all connected to ground. The second terminal of the second capacitor C2 is connected to the normally closed terminal of the fifth relay K5. The common terminal of the fifth relay K5, the second output terminal of the voltage output module 12, and the second controlled terminal of the voltage output module 12 are all connected together.
[0054] By setting a filtering unit in the voltage output module 12, the output voltages of the first and second output terminals of the voltage output module 12 can be filtered to remove high-frequency noise and ripple, thereby reducing the impact of the output voltages of the first and second output terminals on the chip frequency output.
[0055] In one possible implementation, the chip frequency test circuit may also include a first communication module. See also... Figure 6 , Figure 6 This is a schematic diagram of a chip frequency testing circuit provided in another embodiment of this application.
[0056] like Figure 6 As shown, the chip frequency test circuit provided in this application embodiment includes a first communication module 13 in addition to the path switching module 11 and the voltage output module 12.
[0057] The first input terminal of the first communication module 13 is connected to the first output terminal of the ATE test equipment, the second input terminal of the first communication module 13 is connected to the second output terminal of the ATE test equipment, the first output terminal of the first communication module 13 is connected to the third input terminal of the chip under test, and the second output terminal of the first communication module 13 is connected to the fourth input terminal of the chip under test.
[0058] The first communication module 13 can be configured to receive a clock signal sent by the ATE test device through a first input terminal of the first communication module 13, and send the clock signal to the chip under test through a first output terminal of the first communication module 13; and can also be configured to receive a data signal sent by the ATE test device through a second input terminal of the first communication module 13, and send the data signal to the chip under test through a second output terminal of the first communication module 13.
[0059] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a first communication module provided in an embodiment of this application. Figure 7 As shown, the first communication module 13 includes a signal stabilization unit.
[0060] The first output terminal of the signal stabilization unit, the first input terminal of the first communication module 13, and the first output terminal of the first communication module 13 are all connected together. The second output terminal of the signal stabilization unit, the second input terminal of the first communication module 13, and the second output terminal of the first communication module 13 are all connected together. The input terminal of the signal stabilization unit is connected to the power supply terminal of the ATE test equipment. The signal stabilization unit can be configured to send a high-level signal to the third input terminal of the chip under test through the first output terminal of the signal stabilization unit when the first input terminal of the first communication module 13 does not receive a clock signal sent by the ATE test equipment; and can be configured to send a high-level signal to the fourth input terminal of the chip under test through the second output terminal of the signal stabilization unit when the second input terminal of the first communication module 13 does not receive a data signal sent by the ATE test equipment.
[0061] like Figure 7 As shown, the signal stabilization unit includes a first resistor R1, a second resistor R2, a sixth relay K6, and a seventh relay K7. The first terminal of the first resistor R1 and the first terminal of the second resistor R2 are connected together as the input terminal of the signal stabilization unit. The second terminal of the first resistor R1 is connected to the normally open terminal of the sixth relay K6, and the second terminal of the second resistor R2 is connected to the normally open terminal of the seventh relay K7. The common terminal of the sixth relay K6 serves as the first output terminal of the signal stabilization unit, and the common terminal of the seventh relay K7 serves as the second output terminal of the signal stabilization unit.
[0062] The following combination Figure 7 The working principle of the signal stabilization unit provided in the embodiments of this application will be explained.
[0063] When the first input terminal of the first communication module 13 does not receive the clock signal sent by the ATE test equipment, the normally closed terminal of the sixth relay K6 is opened and the normally open terminal is closed. Therefore, the signal stabilization unit can send a high-level signal to the third input terminal of the chip under test through the first output terminal of the signal stabilization unit.
[0064] When the second input terminal of the first communication module 13 does not receive the clock signal sent by the ATE test equipment, the normally closed terminal of the seventh relay K7 is opened and the normally open terminal is closed. Therefore, the signal stabilization unit can send a high-level signal to the fourth input terminal of the chip under test through the second output terminal of the signal stabilization unit.
[0065] In one possible implementation, the chip frequency test circuit may also include a second communication module. See also... Figure 8 , Figure 8 This application also provides a schematic diagram of the structure of a chip frequency testing circuit according to another embodiment.
[0066] like Figure 8 As shown, the chip frequency test circuit provided in this application embodiment includes a second communication module 14 in addition to the path switching module 11, the voltage output module 12 and the first communication module 13.
[0067] Specifically, the first input terminal of the second communication module 14 is connected to the third output terminal of the ATE test equipment, the first output terminal of the second communication module 14 is connected to the second input terminal of the frequency meter, the second input terminal of the second communication module 14 is connected to the output terminal of the frequency meter, and the second output terminal of the second communication module 14 is connected to the second input terminal of the ATE test equipment.
[0068] The second communication module 14 is configured to receive frequency meter control commands sent by the ATE test equipment and send the frequency meter control commands to the frequency meter; and is also configured to receive data signals sent by the frequency meter and send the data signals to the ATE test equipment.
[0069] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a chip frequency testing device provided in an embodiment of this application.
[0070] like Figure 9 As shown, the chip frequency testing equipment provided in this application embodiment may include several chip frequency testing circuits provided in this application embodiment. For the specific functions of the chip frequency testing circuits, please refer to... Figures 1 to 8 The corresponding implementation examples will not be described in detail here.
[0071] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0072] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0073] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A chip frequency testing circuit, characterized in that, The circuit includes a path switching module; the input terminal of the path switching module is connected to the frequency output terminal of the chip under test, the first output terminal of the path switching module is connected to the first input terminal of the ATE test equipment, and the first output terminal of the path switching module is connected to the first input terminal of the frequency meter. The path switching module is configured to output the frequency signal from the frequency output terminal of the chip under test to the ATE test equipment and / or the frequency meter.
2. The circuit according to claim 1, characterized in that, The path switching module includes a first relay, a second relay, a third relay, and a control signal input terminal. The common terminal of the first relay and the common terminal of the second relay are connected to the frequency output terminal of the chip under test. The normally open terminal of the first relay and the common terminal of the third relay are connected to the first input terminal of the ATE test equipment. The normally open terminal of the third relay and the normally closed terminal of the second relay are connected to the first input terminal of the frequency meter. The controlled terminals of the first relay, the second relay, and the third relay are respectively connected to the control signal input terminal.
3. The circuit according to claim 1, characterized in that, The path switching module includes a first relay, a second relay, a third relay, and a control signal input terminal. The common terminal of the first relay and the common terminal of the second relay are connected to the frequency output terminal of the chip under test. The normally closed terminal of the first relay and the common terminal of the third relay are connected to the first input terminal of the ATE test equipment. The normally open terminal of the third relay and the normally open terminal of the second relay are connected to the first input terminal of the frequency meter. The controlled terminals of the first relay, the second relay, and the third relay are respectively connected to the control signal input terminal.
4. The circuit according to claim 1, characterized in that, The circuit also includes a voltage output module; the first output terminal of the voltage output module is connected to the first input terminal of the chip under test, the second output terminal of the voltage output module is connected to the second input terminal of the chip under test, and the controlled terminal of the voltage output module is connected to the control terminal of the ATE test equipment. The ATE test equipment is configured to send a first control command and a second control command to the voltage output module; The voltage output module is configured to determine, according to the first control instruction, a target port for outputting voltage to the chip under test from the first output terminal and the second output terminal of the voltage output module, and to determine the target parameters for outputting voltage to the chip under test according to the second control instruction.
5. The circuit according to claim 4, characterized in that, The voltage output module includes a filtering unit; the filtering unit includes a fourth relay, a fifth relay, a first capacitor, and a second capacitor; the common terminal of the fourth relay, the first output terminal of the voltage output module, and the first controlled terminal of the voltage output module are all connected together; the normally closed terminal of the fourth relay is connected to the first terminal of the first capacitor; the second terminal of the first capacitor and the first terminal of the second capacitor are all connected to ground; the second terminal of the second capacitor is connected to the normally closed terminal of the fifth relay; the common terminal of the fifth relay, the second output terminal of the voltage output module, and the second controlled terminal of the voltage output module are all connected together.
6. The circuit according to claim 1, characterized in that, The circuit further includes a first communication module; the first input terminal of the first communication module is connected to the first output terminal of the ATE test equipment, the second input terminal of the first communication module is connected to the second output terminal of the ATE test equipment, the first output terminal of the first communication module is connected to the third input terminal of the chip under test, and the second output terminal of the first communication module is connected to the fourth input terminal of the chip under test. The first communication module is configured to receive a clock signal sent by the ATE test equipment through a first input terminal of the first communication module, and send the clock signal to the chip under test through a first output terminal of the first communication module; and is also configured to receive a data signal sent by the ATE test equipment through a second input terminal of the first communication module, and send the data signal to the chip under test through a second output terminal of the first communication module.
7. The circuit according to claim 6, characterized in that, The first communication module includes a signal stabilization unit; the first output terminal of the signal stabilization unit, the first input terminal of the first communication module, and the first output terminal of the first communication module are all connected together; the second output terminal of the signal stabilization unit, the second input terminal of the first communication module, and the second output terminal of the first communication module are all connected together; the input terminal of the signal stabilization unit is connected to the power supply terminal of the ATE test equipment. The signal stabilization unit is configured to send a high-level signal to the third input terminal of the chip under test through the first output terminal of the signal stabilization unit when the first input terminal of the first communication module does not receive the clock signal sent by the ATE test equipment; and is configured to send a high-level signal to the fourth input terminal of the chip under test through the second output terminal of the signal stabilization unit when the second input terminal of the first communication module does not receive the data signal sent by the ATE test equipment.
8. The circuit according to claim 7, characterized in that, The signal stabilization unit includes a first resistor, a second resistor, a sixth relay, and a seventh relay; the first end of the first resistor and the first end of the second resistor are connected together as the input terminal of the signal stabilization unit, the second end of the first resistor is connected to the normally open terminal of the sixth relay, the second end of the second resistor is connected to the normally open terminal of the seventh relay, the common terminal of the sixth relay serves as the first output terminal of the signal stabilization unit, and the common terminal of the seventh relay serves as the second output terminal of the signal stabilization unit.
9. The circuit according to claim 1, characterized in that, The circuit also includes a second communication module; The first input terminal of the second communication module is connected to the third output terminal of the ATE test equipment; the first output terminal of the second communication module is connected to the second input terminal of the frequency meter; the second input terminal of the second communication module is connected to the output terminal of the frequency meter; and the second output terminal of the second communication module is connected to the second input terminal of the ATE test equipment. The second communication module is configured to receive a frequency meter control command sent by the ATE test equipment and send the frequency meter control command to the frequency meter; and is also configured to receive a data signal sent by the frequency meter and send the data signal to the ATE test equipment.
10. A chip frequency testing device, characterized in that, The chip frequency testing equipment includes several chip frequency testing circuits as described in any one of claims 1 to 9.