Wireless headset and its delay reset circuit

Abstract

The utility model relates to a wireless headset and delay reset circuit thereof, delay reset circuit, including button circuit, delay circuit and diode D1, the non series connection node of resistance R5 and resistance R3 both is connected diode D1's anode, the non series connection node of resistance R1 and resistance R6 both is used for connecting battery voltage end, the series connection node of resistance R1 and resistance R2 connects the other end of first switch tube, the series connection node of resistance R2 and resistance R5 connects the control end of second switch tube, the control end of second switch tube connects one end of capacitor C1, the other end of capacitor C1 is grounded, the series connection node of resistance R4 and resistance R3 connects the control end of first switch tube, the series connection node of resistance R6 and resistance R4 connects the other end of second switch tube, the other end of second switch tube is used for with the reset end connection of earphone central controller, wherein, the reset end of earphone central controller is low level effective, and its hardware cost is lower, and the time of reset delay is shortened.

Description

Technical Field

[0001] This utility model relates to the field of extended reset circuit technology, and in particular to a wireless headset and its delayed reset circuit. Background Technology

[0002] With the development of the consumer electronics industry, various consumer electronic products are emerging in an endless stream. The application of various sensors in electronic products and devices has also led to a rapid increase in the technological content of these products. Wireless headphones, as a commonly used electronic product, are now increasingly moving towards high-end development. For example, with the increasing power of the headphone's MCU, the number of function buttons on the headphones is also increasing, gradually becoming the mainstream development direction for wireless headphones.

[0003] However, when the program in traditional wireless headphones freezes, it usually requires multiple button combinations to reset. This is not only complicated, but also has many possible combinations, which can easily lead to misoperation and make it inconvenient to operate.

[0004] Therefore, a method emerged where simply pressing and holding the mute switch for a specified time could reset the headphone's central control unit, eliminating the need for button combinations. Examples include the headphone delay reset circuit (CN216981879U, authorized on July 15, 2022) and wireless headphones. However, this reset circuit has the following drawbacks: it uses an inverter chip, resulting in high hardware costs; and the parameter design leads to an excessively long 12-second delay, resulting in a poor user experience. Furthermore, its anti-interference design is insufficient; for example, electrostatic interference may cause false resets.

[0005] Therefore, in this utility model patent application, the applicant has carefully researched a wireless headset and its delay reset circuit to solve the above problems. Utility Model Content

[0006] This utility model addresses the shortcomings of the existing technology mentioned above. Its main objective is to provide a wireless headset and its delayed reset circuit, which has low hardware cost and shortens the reset delay time.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A delayed reset circuit includes a button circuit and a delay circuit. The button circuit includes a mute switch, a resistor R7, and a capacitor C2. One end of the resistor R7 is connected to a reference power supply, and the other end of the resistor R7 is connected to the other end of the mute switch, with one end of the mute switch grounded. The other end of the resistor R7 is connected to one end of the capacitor C2, with the other end of the capacitor C2 grounded.

[0009] It also includes a diode D1, the negative terminal of which is connected to the other end of the mute switch;

[0010] The delay circuit includes resistors R1, R2, R3, R4, R5, and R6, capacitor C1, a first switching transistor, and a second switching transistor. Resistors R1, R2, and R5 are connected in series, and resistors R3, R4, and R6 are connected in series.

[0011] The non-series nodes of resistors R5 and R3 are both connected to the positive terminal of diode D1, and the non-series nodes of resistors R1 and R6 are both used to connect to the battery voltage terminal.

[0012] The series connection of resistors R1 and R2 is connected to the other end of the first switching transistor, and the series connection of resistors R2 and R5 is connected to the control terminal of the second switching transistor; the control terminal of the second switching transistor is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0013] The series connection of resistors R4 and R3 is connected to the control terminal of the first switching transistor, and the series connection of resistors R6 and R4 is connected to the other end of the second switching transistor. The other end of the second switching transistor is used to connect to the reset terminal of the headphone controller, wherein the reset terminal of the headphone controller is active low.

[0014] As a preferred embodiment, the button circuit further includes a first transient suppression diode TVS1, one end of which is connected to the other end of resistor R7, and the other end of the first transient suppression diode TVS1 is grounded.

[0015] As a preferred embodiment, the delay circuit further includes a second transient suppression diode TVS2, one end of which is connected to the other end of the second switching transistor, and the other end of which is grounded.

[0016] As a preferred embodiment, the first switch is an NMOS transistor or an NPN transistor, one end of the first switch is the emitter of the NPN transistor or the source of the MOS transistor, the other end of the first switch is the collector of the NPN transistor or the drain of the MOS transistor, and the control terminal of the first switch is the base of the NPN transistor Q1 or the gate of the MOS transistor.

[0017] As a preferred embodiment, the second switch is an NMOS transistor or an NPN transistor, one end of the second switch is the emitter of the NPN transistor or the source of the MOS transistor, the other end of the second switch is the collector of the NPN transistor or the drain of the MOS transistor, and the control terminal of the second switch is the base of the NPN transistor or the gate of the MOS transistor.

[0018] A wireless headset includes the aforementioned delayed reset circuit.

[0019] Compared with the prior art, this utility model has obvious advantages and beneficial effects. Specifically, it mainly achieves long-press reset by using a bistable circuit formed by the second transient suppression diode TVS2, resistors R1, R2, R3, R4, R5, R6, the first switch and the second switch, in conjunction with capacitor C1. The hardware cost is low and the reset delay time is shortened.

[0020] Secondly, by using the first transient suppression diode TVS1 and the second transient suppression diode TVS1, electrostatic discharge protection is added to ensure the stability and reliability of the delay reset circuit during use.

[0021] To more clearly illustrate the structural features and effects of this utility model, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the general circuit structure of an embodiment of this utility model.

[0023] Explanation of icon numbers:

[0024] 10. Button circuit

[0025] 20. Delay circuit. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0027] like Figure 1 As shown, a time-delayed reset circuit includes a button circuit 10, a diode D1, and a time-delay circuit 20.

[0028] The button circuit 10 includes a mute switch (for...). Figure 1 The components include button S1, resistor R7, capacitor C2, and first transient suppression diode TVS1.

[0029] One end of resistor R7 is used to connect to the reference power supply (for... Figure 1 The circuit consists of: one end connected to the VCC voltage terminal; the other end of resistor R7 connected to the other end of the mute switch; the cathode of diode D1 connected to the other end of the mute switch; one end of the mute switch grounded; the other end of resistor R7 connected to one end of capacitor C2; the other end of capacitor C2 grounded; one end of the first transient suppression diode TVS1 connected to the other end of resistor R7; and the other end of the first transient suppression diode TVS1 grounded. The first transient suppression diode TVS1 is used to prevent electrostatic interference at the reference power supply.

[0030] The delay circuit 20 includes a second transient suppression diode TVS2, resistors R1, R2, R3, R4, R5, and R6, capacitor C1, a first switching transistor, and a second switching transistor. Resistors R1, R2, and R5 are connected in series, and resistors R3, R4, and R6 are connected in series.

[0031] One end of the second transient suppression diode TVS2 is connected to the other end of the second switching transistor, and the other end of the second transient suppression diode TVS2 is grounded. The second transient suppression diode TVS2 is used at the reset terminal of the headphone central control to prevent electrostatic discharge.

[0032] The non-series nodes of resistors R5 and R3 are both connected to the positive terminal of diode D1, and the non-series nodes of resistors R1 and R6 are both used to connect to the battery voltage terminal (e.g., ...). Figure 1 (VBAT voltage terminal); the path from the battery voltage terminal to the second switch via resistors R1 and R2 is greater than the path from the battery voltage terminal to the first switch via resistors R6 and R4.

[0033] The series connection of resistors R1 and R2 is connected to the other end of the first switching transistor, and the series connection of resistors R2 and R5 is connected to the control terminal of the second switching transistor; the control terminal of the second switching transistor is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0034] The series connection of resistors R4 and R3 is connected to the control terminal of the first switching transistor, and the series connection of resistors R6 and R4 is connected to the other end of the second switching transistor. The other end of the second switching transistor is used to connect to the reset terminal of the headphone controller (e.g., ...). Figure 1 The connection is RESTful, wherein the reset terminal of the headphone controller is active low.

[0035] The first switch is an NMOS transistor or an NPN transistor. One end of the first switch is the emitter of the NPN transistor or the source of the MOS transistor, and the other end of the first switch is the collector of the NPN transistor or the drain of the MOS transistor. The control terminal of the first switch is the base of the NPN transistor Q1 or the gate of the MOS transistor.

[0036] The second switch is an NMOS transistor or an NPN transistor. One end of the second switch is the emitter of the NPN transistor or the source of the MOS transistor, and the other end is the collector of the NPN transistor or the drain of the MOS transistor. The control terminal of the second switch is the base of the NPN transistor or the gate of the MOS transistor. In this embodiment, both the first and second switches are NPN transistors, defined as transistor Q1 and transistor Q2, respectively.

[0037] A wireless headset includes the aforementioned delayed reset circuit.

[0038] The second transient suppression diode TVS2, resistors R1, R2, R3, R4, R5, and R6, along with the first and second switching transistors, together form a bistable circuit. The working principle will be briefly explained below:

[0039] At the moment of power-on, because the path between resistors R4 and R6 is short and capacitor C1 will charge, the base of transistor Q1 is triggered first. After the collector of transistor Q1 is turned on, transistor Q2 is in the off state.

[0040] When button S1 is pressed briefly, the VCC voltage is pulled down instantly, achieving the mute function; because the discharge time of capacitor C2 is short, the state of the bistable circuit remains unchanged, so it will not trigger a reset.

[0041] When button S1 is pressed and held, capacitor C2 discharges for 8 seconds and then continues to discharge to the base of transistor Q1, causing transistor Q1 to turn off. Because capacitor C1 discharges slowly, transistor Q2 will momentarily turn on, pulling REST low and resetting the circuit. When button S1 is released, capacitor C1 needs to recharge, so transistor Q1 turns on first, returning the circuit to its initial state.

[0042] The key design feature of this utility model is that it mainly uses a bistable circuit formed by the second transient suppression diode TVS2, resistors R1, R2, R3, R4, R5, R6, the first switch and the second switch, in conjunction with capacitor C1 to achieve long-press reset. This results in lower hardware costs and shorter reset delay time.

[0043] Secondly, by using the first transient suppression diode TVS1 and the second transient suppression diode TVS1, electrostatic discharge protection is added to ensure the stability and reliability of the delay reset circuit during use.

Claims

1. A delayed reset circuit, comprising a button circuit and a delay circuit, wherein the button circuit includes a mute switch, a resistor R7, and a capacitor C2, one end of the resistor R7 is connected to a reference power supply, the other end of the resistor R7 is connected to the other end of the mute switch, one end of the mute switch is grounded, and the other end of the resistor R7 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded, characterized in that: It also includes a diode D1, the negative terminal of which is connected to the other end of the mute switch; The delay circuit includes resistors R1, R2, R3, R4, R5, and R6, capacitor C1, a first switching transistor, and a second switching transistor. Resistors R1, R2, and R5 are connected in series, and resistors R3, R4, and R6 are connected in series. The non-series nodes of resistors R5 and R3 are both connected to the positive terminal of diode D1, and the non-series nodes of resistors R1 and R6 are both used to connect to the battery voltage terminal. The series connection of resistors R1 and R2 is connected to the other end of the first switching transistor, and the series connection of resistors R2 and R5 is connected to the control terminal of the second switching transistor; the control terminal of the second switching transistor is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded. The series connection of resistors R4 and R3 is connected to the control terminal of the first switching transistor, and the series connection of resistors R6 and R4 is connected to the other end of the second switching transistor. The other end of the second switching transistor is used to connect to the reset terminal of the headphone controller, wherein the reset terminal of the headphone controller is active low.

2. The delayed reset circuit according to claim 1, characterized in that: The button circuit also includes a first transient suppression diode TVS1, one end of which is connected to the other end of resistor R7, and the other end of the first transient suppression diode TVS1 is grounded.

3. The delayed reset circuit according to claim 1, characterized in that: The delay circuit also includes a second transient suppression diode TVS2, one end of which is connected to the other end of the second switching transistor, and the other end of which is grounded.

4. The delay reset circuit according to claim 1, characterized in that: The first switch is an NMOS transistor or an NPN transistor. One end of the first switch is the emitter of the NPN transistor or the source of the MOS transistor, and the other end of the first switch is the collector of the NPN transistor or the drain of the MOS transistor. The control terminal of the first switch is the base of the NPN transistor Q1 or the gate of the MOS transistor.

5. The delayed reset circuit according to claim 1, characterized in that: The second switch is an NMOS transistor or an NPN transistor. One end of the second switch is the emitter of the NPN transistor or the source of the MOS transistor, and the other end of the second switch is the collector of the NPN transistor or the drain of the MOS transistor. The control terminal of the second switch is the base of the NPN transistor or the gate of the MOS transistor.

6. A wireless headset, characterized in that: It includes a delayed reset circuit as described in any one of claims 1 to 5.

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