electronic device

Abstract

The present disclosure relates to electronic devices. An electronic device is provided, comprising: a semiconductor body of silicon carbide, having a surface and an edge region; and an edge structure extending over the edge region of the semiconductor body, the edge structure comprising: a metal layer extending over the surface of the semiconductor body; a first insulating layer of a first electrically insulating material extending partly over the metal layer and partly over the surface of the semiconductor body; an interface layer extending over the first insulating layer and partly over the metal layer, the interface layer being of a second electrically insulating material different from the first electrically insulating material; and a passivation layer extending partly over the surface, partly over the metal layer, and completely covering the interface layer, the passivation layer being of a third electrically insulating material different from the second electrically insulating material.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to Italian patent application No. 102024000014080 entitled “DISPOSITIVO ELETTRONICO BASATOSU SIC CON ROBUSTEZZA MIGLIORATA E METODO DI FABBRICAZIONE DEL DISPOSITIVO ELETTRONICO”, ​​filed on June 19, 2024, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to a SiC-based electronic device with enhanced robustness and a method for manufacturing the electronic device. Background Technology

[0004] Silicon carbide (SiC) is gaining considerable attention in the semiconductor industry, particularly for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0005] Electronic devices formed in silicon carbide substrates with their different polymorphs (e.g., 3C-SiC, 4H-SiC, 6H-SiC) have many advantages such as low output resistance during conduction, low leakage current, tolerance to high operating temperatures, and high operating frequency.

[0006] Generally, in these devices, the substrate is covered with one or more passivation layers made of a polymeric material (e.g., polyimide). This polymeric material provides protection against the external environment (particularly by preventing moisture from entering the device) and allows the device to withstand high operating temperatures. The polymeric material also has a high dielectric strength, for example, greater than 400 kV / mm. Specifically, the high dielectric strength of the polymeric material ensures that the passivation layer can withstand high electric fields and thus high potential differences across the passivation layer without cracking or perforation.

[0007] However, polymer materials have a high coefficient of thermal expansion (CTE) (for example, for polybenzobisoxazole materials or "PIX", CTE = 43e). -6 1 / K), and this results in a low coefficient of thermal expansion of the passivation layer (CTE = 3.8e). -6 The adhesion problem of SiC at 1 / K.

[0008] In particular, such adhesion problems between the passivation layer and SiC may occur, for example, during thermal cycling tests performed between about -50°C and about +150°C, or when using electronic devices, when the devices are subjected to high thermal displacement (e.g., an operating temperature difference equal to or greater than about 200°C). Due to the high difference in CTE between the passivation layer and SiC, this high thermal displacement may generate mechanical stress at the interface between the passivation layer and SiC, which may lead to at least partial delamination of the passivation layer relative to the SiC semiconductor body.

[0009] If this delamination expands (e.g., to the point that two metallizations of the electronic device located at different potentials are exposed to air), an electric discharge may occur at the interface, leading to damage to the electronic device. In particular, the risk of damage increases when the electronic device is used under reverse bias conditions due to the high voltage difference it must withstand (e.g., greater than 1000V).

[0010] Known solutions to this problem include forming a passivation multilayer using multiple dielectric layers of different materials (e.g., silicon nitride, silicon oxide, and polyimide layered sequentially) to limit mechanical stress at the interface with the SiC semiconductor body.

[0011] Figure 1 A cross-sectional view of a known type of electronic device (here exemplarily a JBS, "junction barrier Schottky" diode)1 is shown in a Cartesian (triaxial) reference frame with X, Y, and Z axes.

[0012] JBS device 1 includes an N-type SiC semiconductor body 3 having an upper surface 3a and a lower surface 3b. The semiconductor body 3 includes, for example, a substrate and one or more N-type regions epitaxially grown on the substrate and having corresponding doping concentration values.

[0013] The JBS device 1 also includes a plurality of junction barrier elements 9 (hereinafter also referred to as JB, junction barrier, element 9) and an ohmic contact (not shown) in the semiconductor body 3, the plurality of junction barrier elements 9 facing the upper surface 3a and each including a corresponding P-type region injected in the semiconductor body 3, the ohmic contact (not shown) being located on the upper surface 3a of the semiconductor body 3 at the injected region.

[0014] JBS device 1 also includes a first metallization 8 extending on the upper surface 3a and electrically contacting JB element 9 via a corresponding ohmic contact (not shown).

[0015] JBS device 1 also includes an edge termination region 10 (or guard ring), specifically a P-type injection region that completely surrounds JB element 9.

[0016] Schottky diode 12 is formed at the interface between the first metallization 8 and the semiconductor body 3, where a semiconductor-metal Schottky junction is formed. The region of JBS device 1 including JB element 9 and Schottky diode 12 (i.e., the region included within guard ring 10) is the active region 4 of JBS device 1.

[0017] JBS device 1 also includes a second metallization 6 extending on the lower surface 3b. The first metallization 8 and the second metallization 6 form an anode terminal and a cathode terminal, respectively, which can be biased during use of JBS device 1.

[0018] The passive electrical region 16 extends externally to the edge termination region 10.

[0019] An insulating layer 18, particularly silicon oxide (SiO2), extends partially above the edge termination region 10.

[0020] The first metallization 8 makes electrical contact with a portion of the edge termination region 10, where the portion of the edge termination region 10 is not covered by the insulating layer 18, and the first metallization 8 also extends partially over the insulating layer 18.

[0021] The interface layer 20 (here, silicon nitride (SiN)) extends over the first metallization 8 and the insulating layer 18.

[0022] Furthermore, the JBS device 1 includes a passivation layer 22, which is specifically polyimide, extending above the interface layer 20. In other words, the interface layer 20 serves as the interface between the passivation layer 22 and the underlying layers (here, the first metallization 8 and the insulating layer 18).

[0023] The protective layer 24 (a resin such as bakelite) extends over the passivation layer 22 to protect the JBS device 1 and form an encapsulation.

[0024] However, although the interface layer 20 improves the adhesion of the passivation layer 22 to the underlying layer, certain critical operating conditions or thermal or thermomechanical tests of the JBS device 1 may cause the passivation layer 22 to delaminate or partially detach from the interface layer 20 due to the resulting stress. This occurs particularly in the presence of high operating temperatures (e.g., above 150°C). This effect, in addition to making the JBS device 1 structurally vulnerable, may also promote unwanted discharges that prevent the JBS device 1 from operating normally or completely impair its operation. In fact, the applicant has demonstrated that under certain thermomechanical or mechanical stress conditions following the assembly process, the interface layer 20 exhibits one or more localized cracks throughout its thickness, which lead to discharges at the first metallization 8. This problem particularly occurs when the JBS device 1 is subjected to high thermal offset and high voltage differential under reverse bias conditions.

[0025] Therefore, it is necessary to overcome the above problems. Utility Model Content

[0026] According to this disclosure, a SiC-based electronic device and a method for manufacturing the same are provided, as defined in the appended claims.

[0027] According to some embodiments, an example electronic device is provided. The electronic device includes: a silicon carbide semiconductor body having a surface and an edge region; and an edge structure extending over the edge region of the semiconductor body, the edge structure including: a metal layer extending on the surface of the semiconductor body; a first insulating layer of a first electrically insulating material extending partially over the metal layer and partially over the surface of the semiconductor body; an interface layer extending over the first insulating layer and partially over the metal layer, the interface layer being a second electrically insulating material different from the first electrically insulating material; and a passivation layer extending partially on the surface, partially on the metal layer, and completely covering the interface layer, the passivation layer being a third electrically insulating material different from the second electrically insulating material.

[0028] In some embodiments, the interface layer has a first edge portion and a second edge portion, and the passivation layer completely covers and seals the first edge portion and the second edge portion of the interface layer, and directly contacts the surfaces of the metal layer and the semiconductor body next to the first edge portion and the second edge portion of the interface layer.

[0029] In some embodiments, the first insulating layer has a first end and a second end, and the interface layer completely covers and seals the first end and the second end of the first insulating layer, and directly contacts the surfaces of the metal layer and the semiconductor body next to the first end and the second end of the first insulating layer.

[0030] In some embodiments, the metal layer has an outer edge, and a first insulating layer covers and seals the outer edge of the metal layer.

[0031] In some embodiments, the second insulating layer extends partially beneath the first insulating layer and the metal layer on the surface of the semiconductor body, wherein a second end of the first insulating layer overlaps the outer lateral edge of the second insulating layer, and the interface layer also covers the outer lateral edge of the second insulating layer.

[0032] In some embodiments, the first electrical insulating material is silicon oxide or TEOS.

[0033] In some embodiments, the second electrical insulating material is silicon nitride.

[0034] In some embodiments, the third electrical insulating material is polyimide.

[0035] In some embodiments, the second insulating layer is silicon oxide or TEOS.

[0036] According to some embodiments, a method for manufacturing an electronic device is provided. An example method includes: forming an edge structure on a silicon carbide semiconductor having surface and edge regions, wherein forming the edge structure includes: forming a metal layer on a surface of the semiconductor body; forming a first insulating layer of a first electrically insulating material partially on the surface of the semiconductor body and partially on the metal layer; forming an interface layer of a second electrically insulating material different from the first electrically insulating material on the first insulating layer and partially on the metal layer; and forming a passivation layer of a third electrically insulating material different from the second electrically insulating material on the interface layer, partially on the metal layer, and partially on the first surface of the semiconductor body, the passivation layer completely covering the interface layer.

[0037] In some embodiments, forming an interface layer includes forming a first edge portion and a second edge portion, and forming a passivation layer includes completely covering and sealing the first edge portion and the second edge portion of the interface layer, with the surfaces of the metal layer and the semiconductor body directly contacting each other next to the first edge portion and the second edge portion of the interface layer.

[0038] In some embodiments, forming a first insulating layer includes forming a first end and a second end, and wherein forming an interface layer includes completely covering and sealing the first end and the second end of the first insulating layer, with the surfaces of the metal layer and the semiconductor body in direct contact next to the first end and the second end of the first insulating layer.

[0039] In some embodiments, forming a metal layer includes forming an outer edge, and wherein forming a first insulating layer includes covering and sealing the outer edge of the metal layer.

[0040] In some embodiments, a second insulating layer is formed on the surface of the semiconductor body, partially beneath the first insulating layer and the metal layer, and wherein the formation of the interface layer includes a lateral edge covering the second insulating layer.

[0041] In some embodiments, a second insulating layer defines an active region, and a metal layer is stacked at the active region and is in direct electrical contact with the surface of the semiconductor body. Attached Figure Description

[0042] To better understand this disclosure, embodiments will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0043] Figure 1 A cross-sectional view illustrates a known type of electronic device;

[0044] Figure 2 An electronic device according to one embodiment is illustrated in cross-sectional view;

[0045] Figures 3A-3D A cross-sectional view is shown according to the embodiment. Figure 2 The manufacturing steps of electronic devices;

[0046] Figure 4 An electronic device according to another embodiment is illustrated in cross-sectional view; and

[0047] Figures 5A-5D A cross-sectional view is shown according to the embodiment. Figure 4 The manufacturing steps of electronic devices. Detailed Implementation

[0048] Figure 2 Electronic device 50 is shown. In particular, device 50 is a JBS diode, but this specification is not limited to this device and can be applied to other types of electronic devices, especially power devices, such as MOSFETs, IGBTs, MPS, Schottky diodes, PN diodes, PiN diodes, etc.

[0049] In particular, Figure 2 An end of an electronic device 50 is shown, which is arranged around a semiconductor die 90 where the electronic device 50 is integrated.

[0050] Device 50 includes a semiconductor body 53 having a front surface 53a and a rear surface 53b. Specifically, in... Figure 2 In this embodiment, the semiconductor body 53 includes a substrate 53' and one or more epitaxial layers 53' optionally grown thereon and operating as a drift layer of the electronic device 50. In the following text, reference will be made to a single epitaxial layer 53', but the same applies to the case of multiple epitaxial layers.

[0051] The semiconductor substrate 53 is N-type or P-type silicon carbide (SiC) (N-type will be referred to only in a non-limiting manner hereinafter). Specifically, the semiconductor substrate 53 is 4H-SiC type, but other polytypes such as 2H-SiC, 3C-SiC, and 6H-SiC may also be used. For example, the substrate 53' has a 1.10 19 at / cm 3 and 1.10 22 at / cm 3 The epitaxial layer 53" has an N-type doping concentration between the substrate 53' and the substrate 53', and has a thickness (measured along the vertical axis Z of the Cartesian reference system XYZ) between surfaces 53a and 53b, which is included between 300 μm and 450 μm, specifically equal to about 360 μm. The epitaxial layer 53" has a corresponding doping concentration lower than that of the substrate 53', and is included in a thickness, for example, between 5 and 15 μm.

[0052] Metallization 57 extends on the rear surface 53b. In this example, metallization 57 is cathode metallization 57, such as Ti / NiV / Ag or Ti / NiV / Au. An ohmic contact layer (e.g., nickel silicide, not shown) may extend on the rear surface 53b between the substrate 53' and metallization 57.

[0053] One or more barrier-doped regions 59' (here, P-type) extend along the X-axis from the front surface 53a in the semiconductor body 53 (particularly in the epitaxial layer 53") at a certain distance from each other.

[0054] The barrier doped region 59' may have a width along the X-axis that is included, for example, between 0.5 and 10 μm.

[0055] In this embodiment, the electronic device 50 may optionally also include a corresponding ohmic contact region 59” for each barrier doped region 59’, which is accommodated in the barrier doped region 59’ at the front surface 53a.

[0056] Each barrier doped region 59' and the corresponding ohmic contact region 59" form a junction-barrier element 59, also referred to below as a JB (junction-barrier) element 59.

[0057] Electronic device 50 includes an edge structure 52 that extends relative to die 90 in both the circumferential and annular directions, and Figure 2 Only a portion of the edge structure 52 is shown in cross-section.

[0058] The edge structure 52 here includes a terminal anode region 51 that extends in the epitaxial layer 53” around the area that houses the JB element 59.

[0059] The edge structure 52 also includes an edge termination region or a protective ring 60.

[0060] The edge termination region 60 is formed by another doped region (here, P-type) extending in the epitaxial layer 53”, facing the positive surface 53a and completely surrounding the JB element 59 in a plan view, located on the XY plane defined by the horizontal axes X and Y of the Cartesian coordinate system XYZ. The edge termination region 60 defines the active region 54 and may be partially superimposed on the terminal anode region 51.

[0061] However, the edge termination region 60 is not required and can be omitted.

[0062] The edge structure 52 also includes a portion of a metallization 58 extending over a portion of the front surface 53a at the active region 54, which in this example is an anodic metallization 58, such as Ti / AlSiCu or Ni / AlSiCu.

[0063] One or more Schottky diodes 62 are formed laterally to and between the barrier doped regions 59' at the interface between the semiconductor body 53 and the anode metallization layer 58. Specifically, the Schottky diodes are formed from a semiconductor-metal junction, which is formed from the portion of the semiconductor layer 53 that is in direct contact with the anode metallization layer 58.

[0064] Furthermore, each ohmic contact region 59” located above the corresponding barrier doped region 59' forms an electrical connection region between the anode metallization 58 and the corresponding barrier doped region 59'; this electrical connection region has a lower resistivity value than the corresponding same barrier doped region 59'. Therefore, the JB element 59 is a PiN diode.

[0065] The edge structure 52 also includes an insulating layer 61, an interface layer 63, and a passivation layer 69.

[0066] The insulating layer 61 (particularly a dielectric or insulating material (such as, for example, silicon oxide or TEOS-tetraethyl orthosilicate)) extends partially over the anode metallization 58 (sealing its outer edge at the end of the electronic device 50) and partially over the front surface 53a.

[0067] For example, the insulating layer 61 has a thickness between 0.2 and 2 μm along the vertical axis Z.

[0068] The interface layer 63 (here, silicon nitride (SiN)) extends seamlessly next to the outer peripheral edge of the insulating layer 61, partially above the insulating layer 61 and partially on the anode metallization 58, and partially on the front surface 53a.

[0069] For example, the interface layer 63 has a thickness between 0.2 and 2 μm along the vertical axis Z.

[0070] The passivation layer 69 is an organic material, particularly a polymeric material such as polyimide (e.g., PIX), which completely covers the interface layer 63 and extends alongside the inner and outer edges of the interface layer 63, on the anodic metallization 58, and partially on the front surface 53a.

[0071] In practice, the interface layer 63 extends between the passivation layer 69 and the underlying layer (here, the insulating layer 61) and facilitates the adhesion of the upper passivation layer 69.

[0072] A protective layer 74 (a resin such as bakelite) extends over the passivation layer 69 for encapsulating the electronic device 50.

[0073] In this way, the edge structure 52 of the electronic device 50 includes three layers (insulating layer 61, interface layer 63, and passivation layer 69), which protects the electronic device 50 from the external environment, especially preventing moisture from reaching the high-voltage structure and metallization (e.g., anodic metallization 58).

[0074] Specifically, here, the insulating layer 61 surrounds and seals the periphery of the anode metallization 58; the interface layer 63 surrounds and seals the insulating layer 61 at the top and on the lateral edges of the insulating layer 61; and the passivation layer 69 surrounds and seals the interface layer 63 at the top and on the lateral edges of the interface layer 63.

[0075] Therefore, the edge structure 52 has an encapsulation construction in which each layer covers and seals the underlying layer, ensuring high robustness even under multiple thermal cycles and / or harsh environmental conditions.

[0076] The following text is for reference only. Figures 3A-3D describe Figure 2 The manufacturing steps of the electronic device 50 are described, and the description of these manufacturing steps is limited to those that help to understand the manufacturing steps of this disclosure. Figures 3A-3D With Figure 2 The same reference frame XYZ is used.

[0077] refer to Figure 3A First, the wafer 95 is processed to form the JB element 59, the terminal anode region 51, and the edge termination region 60 in the semiconductor body 53 of SiC in a manner known per se.

[0078] refer to Figure 3BThe anodic metallization 58 is formed, for example by evaporation or sputtering followed by photolithographic definition and etching of the deposited metal layer. The anodic metallization 58 may include one or more layers, such as titanium or nickel layers, and thick layers of aluminum-based alloys (such as AlSiCu, AlCu, Al).

[0079] Subsequently, an insulating or dielectric material is deposited to form an insulating layer 61. This step is performed, for example, by a CVD (chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition) process, in which the insulating or dielectric material is deposited on the entire upper surface of the wafer (again indicated by 53a), and then selectively removed by phototechnique and etching to completely cover the outer edge of the anodized metallization 58.

[0080] Then, Figure 3C An interface layer 63 is formed by, for example, CVD deposition of silicon nitride and by defining the deposited layer through photoelectric techniques and etching, such that the interface layer 63 surrounds and seals the insulating layer 61. The interface layer 63 also extends partially on both the surface of the anodic metallization 58 and the front surface 53a of the semiconductor body 53.

[0081] Then, Figure 3D A passivation layer 69 is formed. This step involves depositing an insulating material (e.g., polyimide) using a deposition process such as spinning, followed by defining and “curing” treatment.

[0082] Therefore, the passivation layer 69 completely covers the interface layer 63, thereby surrounding and sealing it relative to the outside, and the passivation layer 69 extends partially over the anodic metallization 58 and the front surface 53a.

[0083] In particular, the passivation layer 69 needs to be made so that areas accessible from the outside are not covered, such as the central area of ​​the anodic metallization 58, in order to allow for its electrical contact.

[0084] The manufacturing process then continues with known subsequent steps to form additional components of the electronic device 50, which are not described in detail here (e.g., to form an ohmic contact layer (if present) and a cathode metallization 57, and to cut the wafer 95 into individual dies.

[0085] Figure 4 An electronic device 100 according to another embodiment is illustrated. The electronic device 100 is compatible with... Figure 2 The same Cartesian (three-axis) reference frame XYZ is used in this context.

[0086] Specifically, electronic device 100 is a JBS diode, similar to the reference diode. Figure 1and Figure 2 As described; however, even in this case, the present disclosure is not limited to JBS devices, but can also be applied to other types of electronic devices, especially power devices, such as, for example, MOSFETs, IGBTs, MPS, Schottky diodes, PN diodes, PiN diodes, etc.

[0087] Electronic Components 100 and Figure 2 The common elements of the electronic devices 50 are indicated by the same reference numerals and will not be described further.

[0088] Edge structure 52 includes an additional insulating layer 64 of dielectric or insulating material (such as, for example, silicon oxide or TEOS-tetraethyl orthosilicate).

[0089] The additional insulating layer 64 extends partially beneath the insulating layer 61 (and is therefore also referred to herein as the first insulating layer 61) and the anode metallization 58, on the front surface 53a of the semiconductor body 53.

[0090] Since the additional insulating layer 64 can be made of the same material as the first insulating layer 61, it may not be distinguishable from the first insulating layer 61 in the overlapping area; therefore, in Figure 4 The boundary between the two insulating layers 61 and 64 is indicated by a dashed line.

[0091] Here, the interface layer 63 also covers the outer lateral edge of the additional insulating layer 64.

[0092] The anodic metallization 58 extends along the inner edge of the additional insulating layer 64.

[0093] Therefore, the interface layer 63 (also silicon nitride (SiN)) extends alongside and seals the outer peripheral edges of the first insulating layer 61 and the other insulating layer 64.

[0094] For example, the additional insulating layer 64 has a thickness of 0.5 to 2 μm along the vertical axis Z.

[0095] A passivation layer 69 of polymeric material (such as polyimide (e.g., PIX)) completely covers the interface layer 63 and extends further beside the inner and outer edges of the interface layer 63, on the anodic metallization 58, and partially on the front surface 53a.

[0096] The following text is for reference only. Figures 5A-5D describe Figure 4 The manufacturing steps of the electronic device 100, and for Figure 4 The description of the manufacturing steps of the electronic device 100 is limited to those steps that are helpful in understanding the manufacturing steps of this disclosure.

[0097] refer to Figure 5AThe wafer 195 has been pre-processed to form JB element 59, terminal anode region 51 and edge termination region 60 in the semiconductor body 53 of SiC and in a manner known per se.

[0098] Here, an insulating or dielectric material is deposited on the front surface 53a to form an additional insulating layer 64, thereby forming an active region 54 in the semiconductor body 53 of SiC in a manner known per se.

[0099] The step of forming an additional insulating layer 64 is performed, for example, by a CVD (chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition) process, wherein an insulating or dielectric material is deposited on the entire upper surface 53a of the wafer 195 and then selectively removed by photonics and etching to completely cover the edge termination region 60 and partially cover the terminal anode region 51.

[0100] refer to Figure 5B Next, an anode metallization 58 is formed, for example by sputtering and subsequent photolithography defining and etching of the deposited metal layer. Subsequently, an insulating or dielectric material is deposited using the above process to form a first insulating layer 61, thereby completely covering and sealing the outer edge of the anode metallization 58.

[0101] Then, Figure 5C An interface layer 63 is formed, for example, by the process described above, such that the interface layer 63 surrounds and seals the insulating layer 61 and the additional insulating layer 64, and also extends partially on both the surface of the anode metallization 58 and the front surface 53a of the semiconductor body 53.

[0102] Then, Figure 5D A passivation layer 69 is formed. This step includes, for example, depositing an insulating material (such as polyimide) by spin coating, followed by defining and curing.

[0103] Therefore, the passivation layer 69 completely covers the interface layer 63, surrounds and seals it from the outside, and extends partially over the anodic metallization 58 and the front surface 53a.

[0104] Furthermore, here the passivation layer 69 needs to be made so that areas accessible from the outside are not covered, such as the central area of ​​the anodic metallization 58.

[0105] The manufacturing process then proceeds to subsequent steps to form additional components of the electronic device 100 (e.g., to form an ohmic contact layer—not shown—if present, and cathode metallization 57) and to cleave the wafer 195 to form the electronic device 100.

[0106] The described electronic device and its manufacturing process have many advantages.

[0107] First, the edge structure 52 includes three layers (a first insulating layer 61, an interface layer 63, and a passivation layer 69) which protect the electronic devices 50 and 100 from the influence of the external environment and, in particular, prevent moisture from reaching the high-voltage structure and metallization.

[0108] Furthermore, the passivation layer 69 extends over the interface layer 63 and the front surface 53a, thereby protecting the edge structure; therefore, it is particularly robust and durable during thermal stress testing of the electronic devices 50, 100. In addition, the passivation layer 69 reduces the propagation of stress that could lead to fracture of the interface layer 63.

[0109] In other words, the edge structure 52 ensures high electrical performance of the electronic devices 50 and 100 while eliminating structural problems associated with possible breakage of the interface layer 63 after thermal cycling or use of the electronic devices 50 and 100.

[0110] Finally, it is apparent that modifications and variations may be made to the electronic devices and their manufacturing processes described and illustrated herein without departing from the scope of this disclosure as defined in the appended claims.

Claims

1. An electronic device, characterized in that, include: The semiconductor body of silicon carbide has surface and edge regions; as well as An edge structure extends above an edge region of the semiconductor body, the edge structure comprising: A metal layer extending on the surface of a semiconductor substrate; The first insulating layer of the first electrical insulating material extends partially over the metal layer and partially over the surface of the semiconductor body; An interface layer extends above the first insulating layer and partially above the metal layer, the interface layer being a second electrically insulating material different from the first electrically insulating material; and A passivation layer extends partly on the surface and partly on the metal layer, and completely covers the interface layer. The passivation layer is a third electrical insulating material that is different from the second electrical insulating material.

2. The electronic device as described in claim 1, characterized in that, The interface layer has a first edge portion and a second edge portion, and the passivation layer completely covers and seals the first edge portion and the second edge portion of the interface layer, and the surfaces of the metal layer and the semiconductor body are in direct contact with the first edge portion and the second edge portion of the interface layer.

3. The electronic device as described in claim 1, characterized in that, The first insulating layer has a first end and a second end, and the interface layer completely covers and seals the first end and the second end of the first insulating layer, and directly contacts the surfaces of the metal layer and the semiconductor body next to the first end and the second end of the first insulating layer.

4. The electronic device as described in claim 1, characterized in that, The metal layer has an outer edge, and a first insulating layer covers and seals the outer edge of the metal layer.

5. The electronic device as described in claim 3, characterized in that, It also includes a second insulating layer that extends partially beneath the first insulating layer and the metal layer on the surface of the semiconductor body, wherein a second end of the first insulating layer overlaps the outer lateral edge of the second insulating layer, and the interface layer also covers the outer lateral edge of the second insulating layer.

6. The electronic device as claimed in claim 1, characterized in that, The first electrical insulating material is silicon dioxide or TEOS.

7. The electronic device as claimed in claim 1, characterized in that, The second electrical insulating material is silicon nitride.

8. The electronic device as claimed in claim 1, characterized in that, The third electrical insulating material is polyimide.

9. The electronic device as described in claim 5, characterized in that, The second insulating layer is made of silicon oxide or TEOS.

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