Shielded gate trench field effect transistor

Abstract

The application relates to the field of power semiconductor devices, and particularly provides a shield gate trench field effect transistor, aiming to solve the problem that the gate oxide layer at the corner between the trench sidewall and the bottom of an SGT MOSFET is thin and poor in quality, causing the gate withstand voltage to be limited. The shield gate trench field effect transistor comprises a substrate and an epitaxial layer, and a plurality of first trenches are arranged in the active region of the epitaxial layer; a shield gate, a control gate and a dielectric layer are arranged in the first trench; the dielectric layer comprises a first dielectric layer to a third dielectric layer and a connecting portion, the connecting portion is between the first dielectric layer and the third dielectric layer, and along the direction from the top to the bottom of the first trench, the thickness of the connecting portion increases to form a protrusion away from the sidewall of the first trench. By arranging the connecting portion between the first dielectric layer and the third dielectric layer, the protrusion structure away from the first trench is formed, so that the oxide layer at the corner between the sidewall and the bottom of the sub-trench is thick, the reverse withstand voltage capacity of the device is improved, and the reliability risk of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, specifically to a shielded gate trench field-effect transistor. Background Technology

[0002] In the field of semiconductor devices, traditional trench gate metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit a contradictory relationship between on-resistance and breakdown voltage: the on-resistance is proportional to the 2.5th power of the breakdown voltage. This results in a higher device resistance while simultaneously achieving a higher breakdown voltage. In contrast, shielded gate trench (SGT) MOSFETs possess a field plate connected to the source potential, enabling lateral depletion of carriers in the drift region. This allows for increased doping concentration in the drift region while maintaining the same breakdown voltage. Furthermore, it shields the parasitic capacitance between the control gate and drain, significantly improving the device's operating frequency, reducing power consumption in the system, and enhancing overall system efficiency.

[0003] However, in existing SGT MOSFET fabrication processes, after forming the shielding gate and the control gate inter-polyoxide (IPO), the gate oxide layer is often directly formed on the trench sidewalls via an oxidation process. The gate oxide layer formed using this process is significantly thinner at the bottom corners of the trench than on the sidewalls, and the quality of the insulating layer at these corners is also relatively poor. Since the gate breakdown voltage is positively correlated with the thickness of the gate oxide layer on the trench sidewalls and at the corners, SGT MOSFETs cannot effectively resist the electric field under high voltage, thus limiting the device's breakdown voltage capability.

[0004] Therefore, a new technical solution is needed to address the above problems. Utility Model Content

[0005] In order to overcome the above-mentioned defects, this application is made to provide a solution or at least a partial solution to the technical problem that the gate oxide layer at the trench sidewalls and bottom corners of existing SGTMOSFETs is thin and of poor quality, which causes the gate withstand voltage to be limited.

[0006] To achieve the above objectives, this application provides a shielded gate trench field-effect transistor, comprising:

[0007] A substrate of a first conductivity type and an epitaxial layer, wherein the epitaxial layer includes an active region and a terminal region, and a plurality of first trenches are disposed in the active region;

[0008] A shielding grid located within the first trench and a control grid disposed above the shielding grid;

[0009] A dielectric layer located within the first trench, the dielectric layer comprising a first dielectric layer to a third dielectric layer and a connecting portion, wherein the first dielectric layer covers the bottom of the sidewall and the bottom wall of the first trench, and encloses the shielding grid from the side and the bottom; a second dielectric layer is located between the shielding grid and the control grid; a third dielectric layer covers the top of the sidewall of the first trench, and encloses the control grid from the side; the connecting portion connects the first dielectric layer and the third dielectric layer, and along the direction from the top to the bottom of the first trench, the thickness of the connecting portion increases to form a protrusion away from the sidewall of the first trench, and is connected to the second dielectric layer.

[0010] In one technical solution of the above-mentioned shielded gate trench field-effect transistor, the connection portion is located obliquely above the second dielectric layer; the bottom width of the control gate is smaller than the top width, and it has a convex structure.

[0011] In one technical solution of the aforementioned shielded gate trench field-effect transistor, the protrusion of the connection portion has a smooth curved surface.

[0012] In one technical solution of the shielded gate trench field-effect transistor described above, the thickness of the first dielectric layer is greater than the thickness of the third dielectric layer.

[0013] One technical solution for the aforementioned shielded gate trench field-effect transistor also includes:

[0014] The second trench is located within the terminal area;

[0015] A fourth dielectric layer covering the inner wall of the second trench, and a terminal conductor located within the second trench, the terminal conductor being at the same potential as the shielding grid.

[0016] In one technical solution of the above-mentioned shielded gate trench field-effect transistor, the terminal conductor is electrically connected to the shielded gate.

[0017] One technical solution for the aforementioned shielded gate trench field-effect transistor also includes:

[0018] The second type of conductivity well region is located in the epitaxial layer spaced apart from adjacent first trenches;

[0019] A source region of the first conductivity type is located within the epitaxial layer and above the well region;

[0020] The fifth dielectric layer covers the epitaxial layer;

[0021] A first electrode and a second electrode, wherein the first electrode is electrically connected to the control gate, and the second electrode is electrically connected to the well region through the source region.

[0022] In one technical solution of the aforementioned shielded gate trench field-effect transistor,

[0023] The first electrode includes a first plug penetrating the fifth dielectric layer, a first metal wiring layer disposed on the fifth dielectric layer, and a first pad;

[0024] The second electrode includes a second plug penetrating the fifth dielectric layer, a second metal wiring layer disposed on the fifth dielectric layer, and a second pad, wherein the second plug is electrically connected to the well region through the source region.

[0025] The above-described technical solutions of this application have at least one or more of the following beneficial effects:

[0026] The SGT MOSFET provided in this application has a connection portion between the first dielectric layer and the third dielectric layer, which has a protruding structure away from the first trench. This results in a thicker oxide layer at the sidewall and bottom corner of the sub-trench, thus solving the problem of thin and poor-quality gate oxide layer at the sidewall and bottom corner of the sub-trench in traditional manufacturing processes. This improves the reverse voltage withstand capability of the SGT MOSFET, reduces the gate-source capacitance of the device, and enhances the overall reliability of the device. Attached Figure Description

[0027] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Wherein:

[0028] Figure 1 This is a schematic diagram of the structure of an SGT MOSFET manufactured using existing processes;

[0029] Figure 2 This is a schematic diagram of the structure of an SGT MOSFET according to an embodiment of this application;

[0030] Figures 3a to 3g This is a schematic diagram of some key steps in the fabrication method of an SGT MOSFET according to an embodiment of this application.

[0031] List of reference numerals in the attached diagram:

[0032] 1: Substrate; 2: Epitaxial layer; 3: First trench; 4: Shielding gate; 5: Control gate; 6: First dielectric layer; 7: Second dielectric layer; 8: Third dielectric layer; 9: Second trench; 10: Terminating conductor; 11: Fourth dielectric layer; 12: Well region; 13: Source region; 14: Fifth dielectric layer; 15: First electrode; 16: Second electrode; 17: Third electrode; 18: Mask layer; 19: First dielectric material layer; 20: Second dielectric material layer; 21: First groove; 22: Third groove; 23: Second groove; 24: Silicon nitride protective layer; 25: Connector. Detailed Implementation

[0033] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0034] In the description of this application, the terms "first," "second," and other ordinal numbers are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, in this application, unless otherwise expressly specified and limited, the terms "connected," "linked," and other such terms should be interpreted broadly; for example, they may refer to a direct connection or an indirect connection through an intermediate medium, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] As described in the background section, in existing SGT MOSFET manufacturing processes, after the initial IPO (Initial Gate Activation), the gate oxide layer is often formed directly on the trench sidewalls via an oxidation process. It should be noted that the trench here refers to the new trench formed in the remaining space within the deep trench after the shielding gate and IPO are formed, or a sub-trench. Correspondingly, the trench corner refers to the corners on both sides of the bottom of the new trench (or sub-trench).

[0036] Figure 1 This is a schematic diagram of an SGT MOSFET manufactured using existing processes. (Example:) Figure 1The area indicated by the middle circle is characterized by a thinner gate oxide layer at the bottom corner of the sub-trench due to current film deposition technology limitations and the difference in oxide layer thickness between the shielding gate and the control gate. This thinner layer is compared to the gate oxide layer covering the sidewall of the sub-trench. Furthermore, the quality of the oxide layer at the corner is relatively poor, which directly affects the voltage withstand capability of the SGT MOSFET. Consequently, it cannot effectively resist the electric field effect under high voltage, thus limiting its application.

[0037] To address the aforementioned issues, this application provides a shielded gate trench field-effect transistor.

[0038] Figure 2 This is a schematic diagram of the structure of an SGT MOSFET according to an embodiment of this application. Figure 2 As shown, the SGT MOSFET provided in this application embodiment mainly includes a semiconductor substrate, a first trench 3, a shielding gate 4, a control gate 5, a first dielectric layer 6, a second dielectric layer 7, a third dielectric layer 8, a second trench 9, a terminal conductor 10, a fourth dielectric layer 11, a well region 12, a source region 13, a fifth dielectric layer 14, a first electrode 15, a second electrode 16, and a third electrode 17.

[0039] The semiconductor substrate can specifically be an epitaxial wafer, comprising a substrate 1 and an epitaxial layer 2 stacked together, but is not limited thereto. The substrate 1 can be a single-crystal silicon substrate of a first conductivity type (e.g., N+ type), serving as the base support layer for the SGT MOSFET and providing mechanical support for the entire device. The substrate 1 has opposing first and second surfaces, where the first surface is commonly referred to in the industry as the "front side" and the second surface as the "back side." The epitaxial layer 2 is disposed on the first surface of the substrate 1. The epitaxial layer 2 can be a silicon-based epitaxial layer of a first conductivity type (e.g., N- type), with a lower doping concentration than that of the substrate 1.

[0040] Functionally, the semiconductor substrate includes an active region and a termination region. The active region contains multiple spaced-apart first trenches 3, and the termination region contains second trenches 9. Both the first trenches 3 and the second trenches 9 are located within the epitaxial layer 2; that is, their bottoms are both within the epitaxial layer 2. The trench depth can range from 1 micrometer to 10 micrometers. In practice, the first trenches 3 and the second trenches 9 are often formed simultaneously, and the spacing between adjacent first trenches can be the same.

[0041] The first trench 3 contains a dielectric layer, a shielding gate 4, and a control gate 5. The shielding gate 4 is located below the control gate 5; as an electrode between the control gate 5 and the channel, the shielding gate 4 improves the electric field distribution and reduces stress on the gate oxide layer. Furthermore, the shielding gate 4 helps maintain charge balance below the gate, thereby maintaining stable conductivity of the channel; the shielding gate 4 can be made of doped polysilicon. The control gate 5, as the control electrode for the device's switching function, can precisely turn the device on and off by receiving external voltage signals; the control gate 5 can also be made of doped polysilicon.

[0042] The dielectric layer within the first trench 3 serves to isolate the shielding gate 4 from the control gate 5, and to isolate the shielding gate 4 and the control gate 5 from the epitaxial layer 2 outside the first trench 3. Specifically, the dielectric layer within the first trench 3 includes a first dielectric layer to a third dielectric layer and a connecting portion, wherein the first dielectric layer 6 covers the bottom region of the sidewalls and the bottom wall of the first trench 3, covering the shielding gate 4 from the sides and bottom. The material of the first dielectric layer 6 can be silicon oxide, and its thickness (i.e., the lateral dimension in the figure) ranges from 1000 angstroms to 10000 angstroms. To a certain extent, a thicker design can improve the breakdown voltage of the device.

[0043] The second dielectric layer 7 is equivalent to the IPO and is located between the shielding gate 4 and the control gate 5. Together with the first dielectric layer 6, it electrically isolates the shielding gate 4 from the control gate 5 and the epitaxial layer 2. The thickness ranges from 2000 angstroms to 5000 angstroms.

[0044] The third dielectric layer 8 is disposed in the upper part of the sidewall of the first trench 3, covering the side of the control gate 6. The material of the third dielectric layer 8 can be silicon oxide, and the thickness of the third dielectric layer 8 is less than the thickness of the first dielectric layer 6, specifically 400 angstroms to 1000 angstroms. The longitudinal depth of the third dielectric layer 8 depends on the control gate 5, and can be determined according to the actual device performance requirements, generally 0.7 micrometers to 1.2 micrometers.

[0045] like Figure 2 As shown in the middle circle, a connecting portion 25 is provided between the first dielectric layer 6 and the third dielectric layer 8. The thickness of the connecting portion 25 gradually decreases from the first dielectric layer 6 to the third dielectric layer 8, or in other words, the thickness of the connecting portion 25 increases along the direction from the top to the bottom of the first trench 3, forming a protrusion away from the sidewall of the first trench 3, and connecting to the second dielectric layer 7. The connecting portion 25 is located diagonally above the second dielectric layer 7, and its upper and lower ends smoothly transition with the first dielectric layer 6 and the third dielectric layer 8, with a convex surface on the side away from the sidewall of the first trench 3.

[0046] In trench-gate type semiconductor devices, the gate withstand voltage is positively correlated with the thickness of the gate oxide layer, in particular positively correlated with the thickness of the gate oxide layer at the trench corner. Adopting the technical solution of the embodiments of the present application, the third dielectric layer 8, the connecting portion 25 and the second dielectric layer 7 collectively serve as the gate oxide layer of the control gate 5, wherein the connecting portion 25 is located at the corner of the trench (specifically, the sub-trench), and since the connecting portion 25 protrudes toward the sidewall of the sub-trench, its thickness is greater than the thickness of the third dielectric layer 8 covered on the sidewall of the sub-trench, so that on the premise of not changing the threshold voltage, the gate withstand voltage capability of the device can be improved, the gate-source capacitance can be optimized, and the reliability risk can be reduced. With further reference to Figure 2 , since the connecting portion 25 protrudes away from the sidewall of the first trench 3, the control gate 5 is approximately in an inverted "convex" shape, that is, the bottom width of the control gate 5 is smaller than the top width; on this basis, the protruding surface of the connecting portion 25 is a smooth surface, which avoids the problems caused by sharp corners at the bottom of the control gate 5.

[0047] The second trench 9 is a terminal trench disposed in the epitaxial layer 2, the inner wall of the trench is covered with a fourth dielectric layer 11, the material of the fourth dielectric layer 11 may be the same as that of the first dielectric layer 6, for example, both are silicon dioxide, with a thickness ranging from 1000 angstroms to 10000 angstroms. In practice, a dielectric material layer may be first formed in the first trench 3 and the second trench 9 by deposition or thermal oxidation, wherein the dielectric material layer covering the inner wall of the second trench 9 is the fourth dielectric layer 11; then, while protecting the second trench 9, part of the dielectric material layer located in the first trench 3 is removed to obtain the first dielectric layer 6.

[0048] A terminal conductor 10 is disposed in the second trench 9, and is covered by the fourth dielectric layer 11 from the side surface and the bottom surface. The terminal conductor 10 achieves uniform electric field intensity by assisting in depleting drift region charges and optimizing the electric field distribution, so as to reduce the potential risk caused by excessively high local voltage gradient. The terminal conductor 10 has the same potential as the shield gate 4 in the active region. In practice, the terminal conductor 10 and the shield gate 4 may be directly connected, or may be electrically connected through metal wiring to ensure that the two have the same potential.

[0049] The well region 12 is located in the epitaxial layer 2 that spaces adjacent first trenches 3 apart, and is a semiconductor region of the second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is N-type, the second conductivity type is P-type. The doping concentration of the well region 12 is higher than the doping concentration of the epitaxial layer 2, and the bottom of the well region 12 is higher than the bottom of the third dielectric layer 8.

[0050] The source region 13 is located within the epitaxial layer 2, above the well region 12, and is a semiconductor region of the first conductivity type (such as N+ type), with a higher doping concentration than the epitaxial layer 2. As the body region of the device, the well region 12, together with the source region 13 and the epitaxial layer 2, forms the channel region of the MOS structure. By electrically shorting the well region 12 and the source region 13, the parasitic transistor effect can be effectively eliminated, avoiding problems such as increased drain-source leakage current and reduced device breakdown voltage.

[0051] The fifth dielectric layer 14 covers the epitaxial layer 2, the first trench 3, and the second trench 9. The fifth dielectric layer 14 can be an insulating material such as silicon oxide or silicon nitride, and it has multiple conductive windows inside for accommodating metal plugs. These conductive windows include a first opening, a second opening, and a third opening corresponding to the first electrode 15, the second electrode 16, and the third electrode 17, respectively. As an interlayer dielectric (ILD) layer, the fifth dielectric layer 14 effectively prevents external impurities from contaminating the device and provides insulation between the metal electrodes and between the metal electrodes and the structures in the epitaxial layer 2, preventing short circuits.

[0052] The first electrode 15, the second electrode 16, and the third electrode 17 are metal electrodes, enabling electrical connection between the internal structure of the device and the external circuit. The materials of the metal electrodes can be Ti, TiN, W, AlCu, AlSiCu, etc. Specifically, the metal electrodes may include metal plugs, metal wiring layers, and pads. The metal plugs are located within the conductive windows of the dielectric layer, with their bottoms directly contacting the internal functional structure of the device and their tops extending to the surface of the dielectric layer. The tops of the metal plugs are electrically connected to the corresponding metal wiring layers. The dispersed metal plugs are led out and interconnected through planar metal wiring to realize the aggregation and transmission of internal signals. The pads are the terminal interface areas extending from the metal wiring layers. They are usually formed into larger, regular areas at specific locations (such as the edge of the device) and serve as the connection interface between the device and the external circuit.

[0053] like Figure 2 As shown, the first electrode 15 is electrically connected to the control gate 5 inside the corresponding first trench 3. The first electrode 15 includes a first plug disposed in the fifth dielectric layer 14, a first metal wiring layer disposed on the fifth dielectric layer 14, and a corresponding first pad. As an electrical lead-out structure of the control gate 5, the first electrode 15 can transmit external control voltage signals to the control gate 5 to control the switching state of the device.

[0054] The second electrode 16 includes a second plug disposed within the fifth dielectric layer 14, a second metal wiring layer disposed on the fifth dielectric layer 14, and a corresponding second pad. The second plug of the second electrode 16 is electrically connected to the source region 13 and the well region 12 through a second opening, thereby short-circuiting the well region 12 and the source region 13 to prevent increased leakage current between the drain and source caused by parasitic transistors and a decrease in device withstand voltage. Simultaneously, the second electrode 16 serves as an electrical lead-out structure for the source region 13, enabling conduction between external circuitry and the source region 13.

[0055] The third electrode 17 is electrically connected to the terminal conductor 10 inside the second trench 9. The third electrode 17 includes a third plug disposed in the fifth dielectric layer 14, a third metal wiring layer disposed on the fifth dielectric layer 14, and a corresponding third pad. As an electrical lead-out structure of the terminal conductor 10, the third electrode 17 can transmit external signals or current to the terminal conductor 10, ensuring the stable realization of the auxiliary electrical functions of the terminal conductor 10.

[0056] The SGT MOSFET provided in this embodiment has a connection portion 25 between the first dielectric layer 6 and the third dielectric layer 8. By utilizing the thickness difference of the connection portion 25, a thicker oxide layer is formed at the sidewall and bottom corner of the sub-trench. This solves a series of problems caused by the thin gate oxide thickness and poor quality at the sidewall and bottom corner of the sub-trench in traditional manufacturing processes, improves the gate oxide withstand voltage capability of the shielded gate trench device, optimizes the gate-source capacitance, and improves the overall reliability of the shielded gate trench field-effect transistor device.

[0057] Furthermore, the above Figure 2 The shielded gate trench field-effect transistor shown can be fabricated through the following process steps.

[0058] Step 1: Form an epitaxial layer 2 of the first conductivity type on a semiconductor substrate 1 of the first conductivity type.

[0059] The semiconductor substrate 1 of the first conductivity type can specifically be an N+ single-crystal silicon substrate, and the epitaxial layer 2 can be an N- silicon epitaxial layer. Specifically, the epitaxial layer 2 can be grown on the first surface of the substrate 1 through an epitaxial growth process.

[0060] Step 2: Form multiple first trenches 3 and second trenches 9 within the epitaxial layer 2.

[0061] refer to Figure 2 In some embodiments, step S2 may specifically include: forming a mask layer 18 on the epitaxial layer 2; wherein the mask layer 18 is a stacked structure consisting of two silicon oxide layers and a silicon nitride layer located between them, that is, the mask layer 18 has a "Oxide-Nitride-Oxide (ONO)" sandwich structure to ensure that the bird beak effect is minimized in the subsequent oxidation process.

[0062] When preparing the above-mentioned mask layer 18, a bottom silicon dioxide layer can be grown on the surface of the epitaxial layer 2 by thermal oxidation process, followed by the deposition of a silicon nitride layer by processes such as low-pressure chemical vapor deposition (LPCVD), and finally the top silicon dioxide layer is deposited on the surface of the silicon nitride layer by processes such as plasma-enhanced chemical vapor deposition (PECVD) to form an ONO layered mask layer.

[0063] Subsequently, photoresist PR is coated on the surface of mask layer 18, and the pattern of the trench, i.e. the area to be etched away, is defined by exposure and development processes, so that the ONO mask layer in this area is exposed; then, using the photoresist layer as a mask, the exposed ONO layer is dry etched until the underlying epitaxial layer 2 is exposed, and then the photoresist layer is removed; then, using the remaining ONO layer as a mask, the epitaxial layer 2 is etched to form a trench with a depth of 1 micrometer to 10 micrometers.

[0064] Step 3: A first dielectric material layer 19 and a second dielectric material layer 20 are formed in the first trench 3 and the second trench 9, respectively.

[0065] Specifically, the first dielectric material layer 19 and the second dielectric material layer 20 can be made of silicon oxide, formed by chemical vapor deposition (CVD), thermal oxidation, or thermal oxidation combined with CVD and then etching. CVD includes sub-atmospheric pressure chemical vapor deposition (SACVD), plasma-enhanced chemical vapor deposition (PECVD), etc.; thermal oxidation includes wet oxidation, dry oxidation, etc. Considering factors such as time and quality, this application chooses the wet oxidation combined with SACVD process to ensure better quality and uniformity of the dielectric material layers.

[0066] like Figure 3a As shown, the first dielectric material layer 19 covers the sidewalls and bottom wall of the first trench 3, and the second dielectric material layer 20 covers the sidewalls and bottom wall of the second trench 9, thereby forming a first groove 21 in the first trench 3 and a third groove 22 in the second trench 9.

[0067] Step 4: Fill the first groove 21 and the third groove 22 with doped polysilicon, and remove the doped polysilicon located on the surface of the hard mask and remove part of the doped polysilicon located in the first groove 21 to obtain the shielding gate 4 located in the first groove 21 and the terminal conductor 10 located in the third groove 22; wherein, the top surface of the shielding gate 4 is lower than the surface of the epitaxial layer 2, and the second dielectric material layer covering the terminal conductor 10 on the inner wall of the third groove 22 is the fourth dielectric layer 11.

[0068] refer to Figure 3bWhen removing the doped polysilicon located in the first trench 21, a photoresist PR mask layer can be formed first to protect the terminal conductor 10 and the fourth dielectric layer 11 in the second trench 9. Then, the doped polysilicon in the first trench 21 is etched back so that the doped polysilicon is lower than the surface of the epitaxial layer 2. Generally, the longitudinal depth between the doped polysilicon and the trench opening of the first trench 3 can be determined comprehensively based on factors such as the IPO thickness and well depth of the device.

[0069] Step 5: Remove the first dielectric material layer 19 of the upper half of the first trench 3 with a preset thickness to obtain the second groove 23; then remove the photoresist mask layer.

[0070] Specifically, wet etching can be used to partially remove the upper half of the first dielectric material layer 19 in the first trench 3, making the thickness of the first dielectric material layer 19 in the upper half of the sidewall of the first trench 3 less than the thickness of the lower half. During this process, the outermost silicon oxide layer of the mask layer 18 is also removed simultaneously.

[0071] like Figure 3c As shown, the thickness of the first dielectric material layer 19 retained at the top of the sidewall of the first trench 3 is less than the thickness of the first dielectric material layer 19 at the bottom of the sidewall, exposing the top of the doped polysilicon. Specifically, with the top of the shielding gate 4 as the boundary, the first dielectric material layer 19 located on its side is relatively thick, ranging from 1000 angstroms to 10000 angstroms, while the first dielectric material layer 19 located diagonally above the shielding gate 4 is relatively thin, ranging from 400 angstroms to 1000 angstroms, thus forming a region of thin-thickness boundary near the top of the shielding gate 4. The relatively thick part located on the side of the shielding gate 4 is the first dielectric layer 6, and the uniform and thinner part located diagonally above the shielding gate 4 is the third dielectric layer 8.

[0072] Step 6: Form a silicon nitride protective layer 24 in the second groove 23.

[0073] Specifically, a silicon nitride protective layer 24 of a certain thickness (e.g., 500 angstroms to 1500 angstroms) can be deposited on the sidewalls, bottom walls, and top of the shielding gate 4 of the second groove 23 by PECVD (temperature 300 to 450°C) or LPCVD (temperature 700 to 900°C) processes.

[0074] like Figure 3d As shown, since the mask layer 18 covering the surface of the epitaxial layer 2 includes a silicon nitride layer and the outermost silicon oxide layer in the mask layer 18 has been removed, the thickness of the silicon nitride protective layer 24 covering the inner wall of the first trench 3 is less than the overall thickness of the silicon nitride layer on the surface of the epitaxial layer 2.

[0075] Step 7: Remove the silicon nitride protective layer 24 and the shielding grid of the preset depth from the bottom wall of the second groove 23 and the top of the shielding grid 4, so that the remaining shielding grid 4 is lower than the area where the thickness of the first dielectric material layer 19 meets, that is, the remaining shielding grid 4 is lower than the first dielectric layer 6, the third dielectric layer 8 is covered by the silicon nitride protective layer, and the area where the thickness of the first dielectric layer 6 and the third dielectric layer 8 meets is exposed.

[0076] Specifically, dry etching can be used to remove the silicon nitride protective layer 24 from the bottom wall of the second groove 23 and the top of the shielding gate 4, exposing the underlying first dielectric layer 6 and the shielding gate 4. Then, the shielding gate at a predetermined depth is removed using another etching process. The remaining silicon nitride protective layer 24 covers the third dielectric layer 8, such as... Figure 3e As shown.

[0077] Step 8: Oxidation is performed under the protection of silicon nitride protective layer 24 to form the connection part.

[0078] Specifically, oxidation can be performed in a humid oxygen oxidation environment. The polysilicon at the top of the shielding gate 4 is oxidized and undergoes volume expansion to form the second dielectric layer 7. Since some silicon oxide layers inside the second groove 23 are not covered by the silicon nitride protective layer and are exposed, and the exposed silicon oxide layers have different thicknesses, the number of oxygen molecules entering the epitaxial layer during oxidation varies, resulting in different oxidation rates. The epitaxial layer covered by the thinner oxide layer has a relatively faster oxidation rate. At this time, the thickness of the thickness-thin interface region also increases to varying degrees, thereby forming a protrusion away from the sidewall of the first trench 3 and directly contacting the second dielectric layer 7. This causes the thickness of the silicon oxide layer formed in the thickness-thin interface region to increase from the top to the bottom of the first trench 3. In particular, through humid oxygen oxidation, the surface of the protrusion is a smooth curved surface, approximately an arc-shaped structure. Specifically, during oxidation, the sidewall of the second groove 23 is protected by the silicon nitride protective layer 24, which can block oxygen from entering. Therefore, the thickness of the dielectric material layer here remains basically unchanged.

[0079] After oxidation, the raised structure becomes the connecting part 25, which connects the second dielectric layer 7 and the third dielectric layer 8, as shown below. Figure 3f Figure 3g As shown.

[0080] Step 9: Remove the silicon nitride protective layer 24.

[0081] Specifically, wet etching can be used to remove the silicon nitride protective layer 24 on the sidewall of the second groove 23 and the silicon nitride layer on top of the epitaxial layer 2, exposing the third dielectric layer 8.

[0082] Step 10: Continue to fill the second groove 23 with doped polysilicon material and etch it back to form the control gate 5.

[0083] In some embodiments, doped polysilicon can be filled into the second groove 23 using an LPCVD process. After filling, the control gate 5 can be formed by chemical mechanical polishing, dry etching, etc. At this time, the shielding gate 4 and the control gate 5 are electrically isolated through the first dielectric layer 6, the second dielectric layer 7, and the third dielectric layer 8, and the sidewall of the control gate 5 is insulated from the epitaxial layer 2 through the third dielectric layer 8 to ensure the switching control function of the gate.

[0084] Step 11: Form a well region 12 of the second conductivity type within the epitaxial layer 2.

[0085] Specifically, an ion implantation process can be used to implant a second type of conductivity (such as P-type) impurity into the epitaxial layer 2. After implantation, high-temperature annealing is performed to allow the impurity to diffuse and activate, forming a P-type well region 12. The bottom of the well region 12 does not exceed the bottom of the third dielectric layer 8.

[0086] Step 12: Form a source region 13 of the first conductivity type in the epitaxial layer 2, located on the well region 12.

[0087] In some implementations, the source region can be defined by photolithography, and then a first conductivity type (such as N+) impurity can be introduced into the epitaxial layer 2 on top of the well region 12 by high-concentration ion implantation. After implantation, thermal annealing is performed to form an N+ source region 13 located on the well region 12.

[0088] Step 13: Form a fifth dielectric layer 14 covering the epitaxial layer 2, the first trench 3, and the second trench 9.

[0089] Specifically, a CVD process can be used to deposit insulating materials such as silicon oxide or silicon nitride on the epitaxial layer 2, the first trench 3, and the second trench 9 to form a fifth dielectric layer 14. Subsequently, the fifth dielectric layer 14 is patterned to form conductive windows that penetrate the fifth dielectric layer 14.

[0090] Step 14: Form the first electrode 15, the second electrode 16 and the third electrode 17.

[0091] The first electrode 15 is electrically connected to the control gate 5, the second electrode 16 is electrically connected to the source region 13, and the third electrode 17 is electrically connected to the terminal conductor 10.

[0092] The first electrode 15, the second electrode 16, and the third electrode 17 are metal electrodes, enabling electrical connection between the internal structure of the device and the external circuit. The metal electrodes are made of materials such as Ti, TiN, W, AlCu, and AlSiCu, and can be deposited using processes such as CVD and PVD to form a metal electrode material layer that fills the aforementioned conductive window and covers the fifth dielectric layer 14. Subsequently, the metal electrode material layer is patterned to obtain the aforementioned metal electrodes, wherein the metal electrode material layer filling the conductive window serves as a conductive plug.

[0093] Furthermore, subsequent thinning and back-side metallization can be performed as needed, and this is not limited here. Additionally, the above process route is not the only one; other methods or adjustments can be made. For example, step 1 can be omitted, and a commercially available epitaxial wafer meeting the product's process requirements can be directly purchased.

[0094] The fabrication method provided in this application can form a raised structure opposite to the first trench between the first dielectric layer and the third dielectric layer. The raised structure has a relatively smooth arc surface, which makes the oxide layer at the sidewall and bottom corner of the sub-trench thicker, thereby improving the gate oxide withstand voltage capability of the shielded gate trench device, optimizing the gate source capacitance, and improving the overall reliability of the device.

[0095] The technical solution of this application has been described above with reference to one embodiment shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A shielded gate trench field-effect transistor, characterized in that, include: A substrate of a first conductivity type and an epitaxial layer, the epitaxial layer including an active region and a terminal region, wherein a plurality of first trenches are provided in the active region; A shielding grid located within the first trench and a control grid disposed above the shielding grid; A dielectric layer located within the first trench, the dielectric layer comprising a first dielectric layer to a third dielectric layer and a connecting portion, wherein the first dielectric layer covers the bottom of the sidewall and the bottom wall of the first trench, and encloses the shielding grid from the side and the bottom; a second dielectric layer is located between the shielding grid and the control grid; a third dielectric layer covers the top of the sidewall of the first trench, and encloses the control grid from the side; the connecting portion connects the first dielectric layer and the third dielectric layer, and along the direction from the top to the bottom of the first trench, the thickness of the connecting portion increases to form a protrusion away from the sidewall of the first trench, and is connected to the second dielectric layer.

2. The shielded gate trench field-effect transistor according to claim 1, characterized in that, The connecting portion is located diagonally above the second dielectric layer; the bottom width of the control gate is smaller than the top width, and it has a convex structure.

3. The shielded gate trench field-effect transistor according to claim 1, characterized in that, The protrusions of the connecting part have smooth curved surfaces.

4. The shielded gate trench field-effect transistor according to any one of claims 1 to 3, characterized in that, The thickness of the first dielectric layer is greater than the thickness of the third dielectric layer.

5. The shielded gate trench field-effect transistor according to any one of claims 1 to 3, characterized in that, Also includes: The second trench is located within the terminal area; A fourth dielectric layer covering the inner wall of the second trench, and a terminal conductor located within the second trench, the terminal conductor being at the same potential as the shielding grid.

6. The shielded gate trench field-effect transistor according to claim 5, characterized in that, The terminal conductor is electrically connected to the shielding grid.

7. The shielded gate trench field-effect transistor according to any one of claims 1 to 3, characterized in that, Also includes: The second type of conductivity well region is located in the epitaxial layer spaced apart from adjacent first trenches; A source region of the first conductivity type is located within the epitaxial layer and above the well region; The fifth dielectric layer covers the epitaxial layer; A first electrode and a second electrode, wherein the first electrode is electrically connected to the control gate, and the second electrode is electrically connected to the well region through the source region.

8. The shielded gate trench field-effect transistor according to claim 7, characterized in that, The first electrode includes a first plug penetrating the fifth dielectric layer, a first metal wiring layer disposed on the fifth dielectric layer, and a first pad; The second electrode includes a second plug penetrating the fifth dielectric layer, a second metal wiring layer disposed on the fifth dielectric layer, and a second pad, wherein the second plug is electrically connected to the well region through the source region.

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