Semiconductor test structure

Abstract

The application relates to a semiconductor test structure, comprising a first test unit and a second test unit, the first test unit comprising a first capacitor, and the second test unit comprising a second capacitor; the first capacitor comprising a first active region, a first gate dielectric layer and a first gate structure, one of the first active region and the first gate structure being a first upper plate and the other being a first lower plate; the second capacitor comprising a second active region, a second gate dielectric layer and a second gate structure, one of the second active region and the second gate structure being a second upper plate and the other being a second lower plate; a projection of the first upper plate extending from inside to outside of a projection edge of the first lower plate, and a projection of the second upper plate extending from inside to outside of a projection edge of the second lower plate; the first upper plate and the second upper plate being spaced apart; a direction from inside to outside of the projection edge of the first lower plate being a first direction, and a direction from inside to outside of the projection edge of the second lower plate being a second direction, the first direction and the second direction being non-collinear.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor test structure. Background Technology

[0002] In semiconductor manufacturing processes, multiple photolithography overlays are required to transfer patterns and form device structure layers. The alignment accuracy between different structure layers affects the performance of the device. For example, the misalignment between the active region and the gate structure can directly lead to fluctuations and degradation of electrical parameters such as the threshold voltage and leakage current of the device.

[0003] Currently, in-line measurement technology is widely used in this field to evaluate the degree of misalignment between different structural layers by optically measuring the morphology of overlay marks. However, the measurement results of in-line measurement are easily affected by factors such as pattern defects of the overlay marks themselves, the accuracy of the measurement equipment, optical magnification, and alignment errors caused by human operation, resulting in uncertainty in the measurement results and inconsistency with the final tested electrical parameters of the device.

[0004] Therefore, how to accurately reflect the overlay offset between different structural layers of a device and its impact on electrical performance has become a technical problem that urgently needs to be solved in this field. Utility Model Content

[0005] In view of this, embodiments of this application provide a semiconductor testing structure to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a semiconductor test structure, including: a first test unit and a second test unit. The first test unit includes a first capacitor, and the second test unit includes a second capacitor. The measured values ​​of the first capacitor and the second capacitor are used to characterize the positional deviation between the first structure and the second structure in the product structure. The first structure, the first upper electrode of the first capacitor, and the second upper electrode of the second capacitor are formed in the same process. The second structure, the first lower electrode of the first capacitor, and the second lower electrode of the second capacitor are formed in the same process. The first capacitor includes a first active region, a first gate dielectric layer, and a first gate structure stacked along a third direction, wherein one of the first active region and the first gate structure is the first upper plate and the other is the first lower plate. The second capacitor includes a second active region, a second gate dielectric layer, and a second gate structure stacked along the third direction, wherein one of the second active region and the second gate structure is the second upper electrode plate, and the other is the second lower electrode plate; In a plane perpendicular to the third direction, the projection of the first upper electrode extends from the inside of the edge of the projection of the first lower electrode to the outside, and the projection of the second upper electrode extends from the inside of the edge of the projection of the second lower electrode to the outside; the first upper electrode and the second upper electrode are spaced apart; the direction extending from the inside of the edge of the projection of the first lower electrode to the outside is the first direction, and the direction extending from the inside of the edge of the projection of the second lower electrode to the outside is the second direction, and the first direction and the second direction are not collinear.

[0007] In conjunction with the first aspect of this application, in an alternative embodiment, the first direction is perpendicular to the second direction.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, in a plane perpendicular to the third direction, the projection of the first upper electrode plate crosses a first side of the projection of the first lower electrode plate and is spaced apart from the remaining sides of the projection of the first lower electrode plate, wherein the extension direction of the first side is perpendicular to the first direction. In a plane perpendicular to the third direction, the projection of the second upper electrode plate extends along the second direction across the second side of the projection of the second lower electrode plate and is spaced apart from the remaining sides of the projection of the second lower electrode plate, and the extension direction of the second side is perpendicular to the second direction.

[0009] In conjunction with the first aspect of this application, in an alternative embodiment, the first lower electrode plate and the second lower electrode plate are two portions of a material layer having continuous edges.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the projected shape of the material layer in a plane perpendicular to the third direction is rectangular, and the first upper electrode plate and the second upper electrode plate respectively cross any two adjacent sides of the rectangle along the first direction and the second direction.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, it further includes: a third testing unit and a fourth testing unit; the third testing unit includes a third capacitor, the fourth testing unit includes a fourth capacitor, and the measured values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are used together to characterize the positional deviation between the first structure and the second structure; the third upper electrode of the third capacitor, the fourth upper electrode of the fourth capacitor, and the first structure are formed in the same process; the third lower electrode of the third capacitor, the fourth lower electrode of the fourth capacitor, and the second structure are formed in the same process; wherein, The third capacitor includes a third active region, a third gate dielectric layer, and a third gate structure stacked along the third direction, wherein one of the third active region and the third gate structure is the third upper plate and the other is the third lower plate. The fourth test unit includes a fourth active region, a fourth gate dielectric layer, and a fourth gate structure stacked along the third direction, wherein one of the fourth active region and the fourth gate structure is the fourth upper electrode plate, and the other is the fourth lower electrode plate. In a plane perpendicular to the third direction, the projection of the third upper electrode extends from the inside of the edge of the projection of the third lower electrode to the outside, and the projection of the fourth upper electrode extends from the inside of the edge of the projection of the fourth lower electrode to the outside; the first upper electrode, the second upper electrode, the third upper electrode, and the fourth upper electrode are distributed at intervals; the direction extending from the inside of the edge of the projection of the third lower electrode to the outside is the opposite direction of the first direction, and the direction extending from the inside of the edge of the projection of the fourth lower electrode to the outside is the opposite direction of the second direction.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, in a plane perpendicular to the third direction, the projections of the first test unit and the third test unit are centrally symmetrically arranged, and the projections of the second test unit and the fourth test unit are centrally symmetrically arranged.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, the first test unit further includes a first source-doped region and a first drain-doped region located within the first active region; the first test unit is also configured to output a first threshold voltage; The second test unit further includes a second source doped region and a second drain doped region located within the second active region; the second test unit is also used to output a second threshold voltage.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, the first gate structure, the first active region, the second gate structure, and the second active region are respectively a first upper electrode plate, a first lower electrode plate, a second upper electrode plate, and a second lower electrode plate; On a plane perpendicular to the third direction, the projections of the first source doped region and the first drain doped region are located on opposite sides of the projection of the first gate structure, and the projections of the second source doped region and the second drain doped region are located on opposite sides of the projection of the second gate structure. The first source doped region, the second source doped region, the first drain doped region, and the second drain doped region are formed by doping in the same doping process along the same ion implantation direction; the first source doped region and the first drain doped region are formed by doping with the first gate structure as a mask; and the second source doped region and the second drain doped region are formed by doping with the second gate structure as a mask.

[0015] In conjunction with the first aspect of this application, in an optional embodiment, the first upper electrode plate includes a first main body portion and a plurality of first interdigitated portions disposed parallel to each other and connected to the first main body portion. On a plane perpendicular to the third direction, the projections of the first interdigitated portions extend from the inside to the outside of the edge of the projection of the first lower electrode plate along the first direction. The projection of the first connecting portion is located outside the edge of the projection of the first lower electrode plate; and / or, The second upper electrode plate includes a second main body and a plurality of second interdigitated portions arranged parallel to each other connected to the second main body. On a plane perpendicular to the third direction, the projection of the second interdigitated portions extends from the inside to the outside of the projection edge of the second lower electrode plate along the second direction. The projection of the second connecting portion is located outside the projection edge of the second lower electrode plate.

[0016] The semiconductor test structure provided in this application utilizes the principle that the overlap area between the gate structure and the active region changes due to positional offset. Each test unit's gate structure and active region form the two plates of a capacitor. The change in overlap area leads to a change in the measured capacitance value, thus characterizing the offset. Compared to optical measurement, capacitance measurement is more sensitive to structural changes and less affected by factors such as pattern defects, measurement equipment, and human alignment errors, resulting in higher accuracy. Furthermore, this semiconductor test structure can obtain the capacitance parameter during the electrical testing phase, making the offset evaluation highly correlated with the device's electrical parameters. In a plane perpendicular to the third direction, the projection of the upper plate of the capacitor extends from the inside to the outside of the projection of the lower plate, ensuring that the overlap area of ​​the two plates changes in real time with the overlay offset, avoiding blind spots in capacitance measurement caused by unchanged overlap area in some offset directions. The first and second directions are not collinear, resulting in different sensitivities of the two test units to the offset direction. The direction and magnitude of the offset can be determined by the measured values ​​of the first and second capacitors, enabling the evaluation of the offset.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A graphic illustration of overlay markings in related technologies; Figure 2 A schematic diagram of optical measurement for overlay markings in related technologies; Figure 3 A layout of a semiconductor test structure is provided as an optional example. Figure 4 for Figure 3 The layout of the semiconductor test structure shown is after a negative X-axis offset. Figure 5 for Figure 3 The layout of the semiconductor test structure shown is after a negative Y-axis offset. Figure 6 A layout of a semiconductor test structure is provided as another optional example; Figure 7 A layout of a semiconductor test structure is provided as yet another optional example; Figure 8 A layout of a semiconductor test structure is provided as another optional example; Figure 9 Layout of semiconductor test structures provided for other optional examples; Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure of the first test unit during ion implantation. Detailed Implementation

[0019] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0021] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] In related technologies, overlay misalignment is typically assessed by optically measuring the morphology of the overlay mark. Specifically, in the previous photolithography-etching process, a front-layer mark is formed at a specific location. The machine tool is positioned based on the front-layer mark and performs the next photolithography-etching process, forming a back-layer mark at the same specific location. The front-layer mark and the back-layer mark are combined to form the overlay mark. Figure 1 Figures (a), (b), and (c) show three different overlay marks.

[0027] When performing optical measurements on overlay marks, the alignment between two photolithography steps can be determined by the positional relationship between the preceding and following marks. However, the measurement results are easily affected by factors such as pattern defects in the overlay marks themselves, the precision of the measuring instrument, the optical magnification, and human error in alignment. Please refer to [reference needed]. Figure 2 In the figure, (a) shows a normal overlay mark; (b) shows a case where the overlay mark itself has graphic defects, which will cause the machine to feed back incorrect values; and (c) shows a case where the overlay mark is unclear, which will cause the machine to be unable to capture the signal. As a result, the measurement results themselves are uncertain, making it inconsistent with the final tested electrical parameters of the device, and making it difficult to assess the impact of overlay misalignment on device performance.

[0028] Based on this, this application provides a semiconductor testing structure, please refer to... Figures 3 to 8 The semiconductor testing structure includes a first testing unit 10 and a second testing unit 20. The first testing unit 10 includes a first capacitor 100, and the second testing unit 20 includes a second capacitor 200. The measured values ​​of the first capacitor 100 and the second capacitor 200 are used to characterize the positional deviation between the first structure and the second structure in the product structure. The first structure, the first upper electrode of the first capacitor 100, and the second upper electrode of the second capacitor 200 are formed in the same process. The second structure, the first lower electrode of the first capacitor 100, and the second lower electrode of the second capacitor 200 are formed in the same process. The first capacitor 100 includes a first active region 110, a first gate dielectric layer 120, and a first gate structure 130 stacked along a third direction. One of the first active region 110 and the first gate structure 130 is a first upper plate, and the other is a first lower plate. The second capacitor 200 includes a second active region 210, a second gate dielectric layer 220, and a second gate structure 230 stacked along a third direction. One of the second active region 210 and the second gate structure 230 is a second upper plate, and the other is a second lower plate. In a plane perpendicular to a third direction, the projection of the first upper plate extends from the inside of the edge of the projection of the first lower plate to the outside, and the projection of the second upper plate extends from the inside of the edge of the projection of the second lower plate to the outside; the first upper plate and the second upper plate are distributed alternately; the direction extending from the inside of the edge of the projection of the first lower plate to the outside is the first direction, and the direction extending from the inside of the edge of the projection of the second lower plate to the outside is the second direction, and the first direction and the second direction are not collinear.

[0029] This application embodiment utilizes the principle that the overlap area changes due to the offset of the gate structure and active region. Each test unit's gate structure and active region form the two plates of a capacitor. The change in overlap area leads to a change in the measured capacitance value, thus characterizing the offset. Compared to optical measurement, capacitance measurement is more sensitive to structural changes and less affected by factors such as pattern defects, measurement equipment, and human alignment errors, resulting in higher accuracy. Furthermore, this semiconductor test structure can obtain the capacitance parameter during the electrical testing phase, making the offset evaluation highly correlated with the device's electrical parameters. In a plane perpendicular to the third direction, the projection of the upper plate of the capacitor extends from the inside to the outside of the projection of the lower plate, ensuring that the overlap area of ​​the two plates changes in real time with the overlay offset, avoiding capacitance measurement blind spots caused by the overlap area remaining unchanged in some offset directions. By setting the first and second directions to be non-collinear, the two test units have different sensitivities to the offset direction. The direction and magnitude of the offset can be determined by the measured values ​​of the first capacitor 100 and the second capacitor 200, enabling the evaluation of the offset.

[0030] Furthermore, the upper and lower plates of the capacitor in the semiconductor test structure are formed in the same process as the first and second structures of the product structure, respectively. The fabrication of the semiconductor test structure is consistent with the fabrication of the product structure, ensuring that capacitance variations originate directly from deviations introduced by the process itself, accurately reflecting the positional deviations between different structures within the product structure. When the first active region 110, the second active region 210, the first gate structure 130, and the second gate structure 230 are respectively the first upper plate, the second upper plate, the first lower plate, and the second lower plate, the first structure is the product active region, and the second structure is the product gate structure; conversely, the opposite is also true. This allows for the measurement of the overlay deviation between the gate structure and the active region in the product structure.

[0031] Understandably, the semiconductor test structure provided in this application is essentially an electrical semiconductor test structure, used to measure various electrical parameters of a chip in WAT (Wafer Acceptance Test) to verify the process window, monitor process stability, and predict yield. Therefore, the electrical parameters measured by the electrical semiconductor test structure in this application can characterize overlay misalignment, effectively solving various problems caused by optical measurement.

[0032] Each individual test unit is sensitive to overlay offsets in a specific direction. For example, the first test unit 10 is sensitive to overlay offsets in a first direction. When the offset direction is exactly parallel to the first direction, the overlap area of ​​the two plates changes significantly, resulting in a large change in the capacitance measurement. If the overlay offset occurs in a direction perpendicular to the first direction, the overlap area of ​​the first capacitor 100 changes less, and the capacitance measurement does not change significantly. The actual overlay offset is a vector occurring in any direction within a 360-degree plane. Therefore, to fully capture this unknown two-dimensional vector, it can be decomposed into two measurable components. Thus, by setting non-collinear first and second directions, a measurement system capable of resolving overlay offsets in any direction within a two-dimensional plane is constructed.

[0033] Specifically, by comparing the changes in the measured values ​​of two capacitors relative to their preset values ​​(i.e., the ideal capacitance value without offset, which can be pre-obtained using capacitance calculation formulas based on parameters such as plate size and gate dielectric layer thickness), it can be determined whether the main direction of the overlay offset is more biased towards the first or second direction, thus making a qualitative or even semi-quantitative judgment on the offset direction. The change in each capacitor is proportional to the magnitude of the component of the overlay offset vector in its sensitive direction. After determining the angular relationship between the offset direction and the two measurement directions, quantitative calculations can be performed to determine the amplitude of the offset vector. This enables the measurement of the direction and magnitude of the overlay offset.

[0034] In some embodiments, in a plane perpendicular to a third direction, the projection of the first upper electrode plate crosses a first side of the projection of the first lower electrode plate and is spaced apart from the remaining sides of the projection of the first lower electrode plate, the extension direction of the first side being perpendicular to the first direction; in a plane perpendicular to a third direction, the projection of the second upper electrode plate crosses a second side of the projection of the second lower electrode plate along a second direction and is spaced apart from the remaining sides of the projection of the second lower electrode plate, the extension direction of the second side being perpendicular to the second direction.

[0035] This ensures that the change in capacitance is almost uniquely determined by the overlay offset in the direction of the upper plate's extension (or its opposite direction), effectively improving measurement sensitivity. For example, if an offset occurs in the first direction, the overlapping area of ​​the two plates of the first capacitor 100 changes, and the measured value changes. If an offset occurs in a direction perpendicular to the first direction, the overlapping area of ​​the two plates does not change due to the gap, and the measured value remains unchanged. Since the upper plate only crosses over one side of the lower plate, and the extension direction of the side is perpendicular to the extension direction of the upper plate (either the first or second direction), the geometric design of "single-sided crossing, multi-sided isolation" makes the change in overlapping area linear with the overlay offset. Consequently, the change in capacitance is also approximately linear with the offset, simplifying the calculation model for deducing the overlay offset from the capacitance measurement value and improving calculation accuracy and efficiency.

[0036] In some embodiments, the first direction is perpendicular to the second direction. A Cartesian coordinate system is constructed, avoiding calculation errors introduced by directional coupling, making the measurement results more direct and reliable, and reducing the complexity of data processing. In a non-perpendicular layout, there may be offset components in a certain direction that have a very weak impact on both capacitors, resulting in low measurement sensitivity in that direction, forming a "sensitivity depression." The perpendicular layout uniformly decomposes the entire plane onto two orthogonal axes, ensuring that overlay offsets in any direction can be efficiently captured and decomposed by these two axes, avoiding measurement weakness zones.

[0037] In this embodiment, the first direction is specifically the positive X-axis, the second direction is specifically the positive Y-axis, and the third direction is specifically the positive Z-axis.

[0038] like Figure 3 and Figure 6 As shown, the first test unit 10 may further include a first active region contact structure 111 and a first gate contact structure 131, which are electrically connected to the first active region 110 and the first gate structure 130, respectively; the second test unit 20 may further include a second active region contact structure 211 and a second gate contact structure 231, which are electrically connected to the second active region 210 and the second gate structure 230, respectively. Thus, a low-resistance conductive path is established between the capacitor plates and the external test equipment through the contact structures. When measuring the capacitance, different voltages are applied to the first active region contact structure 111 and the first gate contact structure 131, creating a potential difference between the two plates of the first capacitor 100; and different voltages are applied to the second active region contact structure 211 and the second gate contact structure 231, creating a potential difference between the two plates of the second capacitor 200.

[0039] The number of the first active region contact structure 111, the first gate contact structure 131, the second active region contact structure 211, and the second gate contact structure 231 can be multiple. Understandably, if there is only one contact structure, the circuit flows from a single point through the entire electrode plate. The resistance of the electrode plate itself will cause inconsistent potentials at different locations on the plate, making the effective area of ​​the capacitor uncertain and introducing measurement errors. Therefore, by setting multiple contact structures, potentials can be provided to the electrode plate from different points, greatly reducing the influence of the electrode plate resistance and ensuring the uniformity of the potential across the entire electrode plate area. This allows the capacitance measurement value to truly and accurately reflect the overlap area between the two electrodes.

[0040] It should be noted that the specific number of contact structures can be set according to the magnitude of the current, and this application embodiment does not limit this.

[0041] In some embodiments, the first lower electrode and the second lower electrode are two parts of a material layer with continuous edges. This avoids introducing additional defects that could affect measurement accuracy when forming two separate structures.

[0042] Please refer to Figure 3 In an optional example, the first lower electrode plate and the second lower electrode plate are respectively the first active region 110 and the second active region 210. The first active region 110 and the second active region 210 are two parts of an active region with continuous edges. In this case, the first active region contact structure 111 and the second active region contact structure 211 can be the same contact structure. Please refer to [reference needed]. Figure 6 In another alternative example, the first lower electrode plate and the second lower electrode plate are respectively the first gate structure 130 and the second gate structure 230. The first gate structure 130 and the second gate structure 230 are two parts of a gate structure with continuous edges. In this case, the first gate contact structure 131 and the second gate contact structure 231 can be the same contact structure.

[0043] like Figure 3 and Figure 6 As shown, in a plane perpendicular to the third direction, the projected shape of the material layer is rectangular, with the first and second upper electrodes spanning any two adjacent sides of the rectangle along the first and second directions, respectively. Compared to irregular shapes, rectangular shapes offer higher integration density and are more advantageous for calculating offsets based on capacitance measurements.

[0044] The first direction and the second direction are perpendicular to the extension direction of the side they cross, thus fixing the first direction and the second direction as two mutually perpendicular directions.

[0045] In some embodiments, the semiconductor test structure may further include: a third test unit 30 and a fourth test unit 40; the third test unit 30 includes a third capacitor 300, and the fourth test unit 40 includes a fourth capacitor 400; the measured values ​​of the first capacitor 100, the second capacitor 200, the third capacitor 300, and the fourth capacitor 400 are used together to characterize the positional deviation between the first structure and the second structure; the third upper electrode of the third capacitor 300, the fourth upper electrode of the fourth capacitor 400, and the first structure are formed in the same process; the third lower electrode of the third capacitor 300, the fourth lower electrode of the fourth capacitor 400, and the second structure are formed in the same process; wherein, The third capacitor 300 includes a third active region 310, a third gate dielectric layer 320 and a third gate structure 330 stacked along the third direction. One of the third active region 310 and the third gate structure 330 is the third upper plate and the other is the third lower plate. The fourth test unit 40 includes a fourth active region 410, a fourth gate dielectric layer 420 and a fourth gate structure 430 stacked along the third direction. One of the fourth active region 410 and the fourth gate structure 430 is the fourth upper plate and the other is the fourth lower plate. In a plane perpendicular to the third direction, the projection of the third upper plate extends from the inside of the edge of the projection of the third lower plate to the outside, and the projection of the fourth upper plate extends from the inside of the edge of the projection of the fourth lower plate to the outside; the first upper plate, the second upper plate, the third upper plate, and the fourth upper plate are distributed alternately; the direction extending from the inside of the edge of the projection of the third lower plate to the outside is the opposite direction of the first direction, and the direction extending from the inside of the edge of the projection of the fourth lower plate to the outside is the opposite direction of the second direction.

[0046] Therefore, the corresponding two test units (first test unit 10 and third test unit 30, second test unit 20 and fourth test unit 40) are sensitive to two opposite directions. When an overlay misalignment occurs, the capacitance changes of the two test units are the same in magnitude but opposite in sign. On the axis corresponding to the extension direction (first direction or second direction) of the test unit, the capacitance change is doubled. This makes the capacitance change more significant and constitutes a differential measurement, which can eliminate deviations and improve test accuracy.

[0047] It should be noted that, in the embodiments of this application, the structures within the third test unit 30 and the fourth test unit 40, except for the extension direction of the upper electrode plate, can all refer to the above description of the structures within the first test unit 10 and the second test unit 20, and will not be repeated here.

[0048] In some embodiments, in a plane perpendicular to the third direction, the projections of the first test unit 10 and the third test unit 30 are centrally symmetrically arranged, and the projections of the second test unit 20 and the fourth test unit 40 are centrally symmetrically arranged.

[0049] Therefore, the measured values ​​of the first capacitor 100 of the first test unit 10 and the third capacitor 300 of the third test unit 30 are the same, and the same is true for the second test unit 20 and the fourth test unit 40, which can further eliminate common-mode error and improve test accuracy.

[0050] Furthermore, in a plane perpendicular to the third direction, the projections of the first test unit 10 and the third test unit 30 are arranged axially symmetrically, and the projections of the second test unit 20 and the fourth test unit 40 are arranged axially symmetrically.

[0051] Next, we will explain in detail the capacitance change of the semiconductor test structure when overlay misalignment occurs, using a specific example. For this specific example, please refer to... Figure 3 The first active region 110, the second active region 210, the third active region 310, and the fourth active region 410 are four parts of a material layer. The projection of this material layer onto a plane perpendicular to the third direction is rectangular. The first gate structure 130, the second gate structure 230, the third gate structure 330, and the fourth gate structure 430 are respectively along the first direction (see details). Figure 3 (Positive X-axis direction) and second direction (see details) Figure 3 The positive Y-axis direction, the opposite direction of the first direction, and the opposite direction of the second direction cross two adjacent sides of the rectangle. The first direction and the second direction are perpendicular to the extension direction of the side they cross. The first test unit 10 and the third test unit 30 are centrally symmetrical, and the second test unit 20 and the fourth test unit 40 are centrally symmetrical.

[0052] During electrical testing, different voltages are applied to the two plates of each capacitor to create a potential difference. Specifically, a first voltage is applied to the first gate contact structure 131, the second gate contact structure 231, the third gate contact structure 331, and the fourth gate contact structure 431. The first active region contact structure 111, the second active region contact structure 211, the third active region contact structure 311, and the fourth active region contact structure 411 are the same contact structure, and a second voltage is applied to it. Either the first voltage or the second voltage is 0V.

[0053] Please refer to Figure 4When the overlay offset direction is negative along the X-axis, the overlapping area of ​​the two plates of the first capacitor 100 in the first test unit 10 decreases, and the capacitance decreases; the overlapping area of ​​the two plates of the third capacitor 300 in the third test unit 30 increases, and the capacitance increases; the overlapping area of ​​the two plates of the second capacitor 200 in the second test unit 20 and the fourth capacitor 400 in the fourth test unit 40 remains unchanged, and the capacitance remains unchanged. Therefore, if the capacitance values ​​of the four test units show the above changes during the electrical testing phase, it can be inferred that an overlay offset has occurred along the negative X-axis. If the first capacitor 100 increases and the third capacitor 300 decreases, it can be inferred that an overlay offset has occurred along the positive X-axis.

[0054] Please refer to Figure 5 When the overlay offset direction is negative Y-axis, the overlapping area of ​​the two plates of the second capacitor 200 in the second test unit 20 decreases, and the capacitance decreases; the overlapping area of ​​the two plates of the fourth capacitor 400 in the fourth test unit 40 increases, and the capacitance increases; the overlapping area of ​​the two plates of the first capacitor 100 in the first test unit 10 and the third capacitor 300 in the third test unit 30 remains unchanged, and the capacitance remains unchanged. Therefore, if the capacitance values ​​of the four test units show the above changes during the electrical testing phase, it can be inferred that an overlay offset has occurred along the negative Y-axis. If the second capacitor 200 increases and the fourth capacitor 400 decreases, it can be inferred that an overlay offset has occurred along the positive Y-axis.

[0055] Therefore, through four test units, the direction of overlay offset can be characterized based on the measured values ​​of each capacitor during the electrical testing phase.

[0056] The capacitance C of each test unit is calculated using the formula C = εWL / t; where ε is the dielectric constant of the gate dielectric layer, W is the width of the overlap between the upper and lower plates, L is the length of the overlap between the upper and lower plates, and t is the thickness of the gate dielectric layer. In this specific example, the width W of the overlap between the upper and lower plates is specifically the width of the gate structure, and the length L of the overlap is specifically the length of the overlap in its corresponding extension direction (first direction or second direction). For each capacitor, the width of the gate structure is a fixed value, while L changes with the offset. Therefore, after obtaining the measured values ​​of each capacitor, the displacement in the first and second directions can be directly calculated to assess the degree of overlay offset.

[0057] In some embodiments, please refer to Figure 9The first test unit 10 further includes a first source-doped region 140 and a first drain-doped region 150 located within the first active region 110; the first test unit 10 is also used to output a first threshold voltage; the second test unit 20 further includes a second source-doped region 240 and a second drain-doped region 250 located within the second active region 210; the second test unit 20 is also used to output a second threshold voltage. Thus, electrical parameters such as threshold voltage can be measured, comprehensively reflecting the impact of overlay offset on the electrical performance of the product structure.

[0058] In some embodiments, the first test unit 10 may further include a first source contact structure 141 and a first drain contact structure 151, which are electrically connected to the first source doped region 140 and the first drain doped region 150, respectively; the second test unit 20 may further include a second source contact structure 241 and a second drain contact structure 251, which are electrically connected to the second source doped region 240 and the second drain doped region 250, respectively. Thus, a low-resistance conductive path is established between each doped region and the external test equipment through the contact structures.

[0059] In some embodiments, the first test unit 10 may further include a first gate lead-out structure 132, a first source lead-out structure 142, and a first drain lead-out structure 152, which are electrically connected to the first gate contact structure 131, the first source contact structure 141, and the first drain contact structure 151, respectively; the second test unit 20 may further include a second gate lead-out structure 232, a second source lead-out structure 242, and a second drain lead-out structure 252, which are electrically connected to the second gate contact structure 231, the second source contact structure 241, and the second drain contact structure 251, respectively.

[0060] In this embodiment, the material of each lead-out structure (first gate lead-out structure 132, first source lead-out structure 142, etc.) is a metallic material.

[0061] In embodiments where the semiconductor test structure further includes a third test unit 30 and a fourth test unit 40, the third test unit 30 may include a third source doped region 340, a third drain doped region 350, a third source contact structure 341, a third drain contact structure 351, a third gate lead-out structure 332, a third source lead-out structure 342, and a third drain lead-out structure 352; the fourth test unit 40 may include a fourth source doped region 440, a fourth drain doped region 450, a fourth source contact structure 441, a fourth drain contact structure 451, a fourth gate lead-out structure 432, a fourth source lead-out structure 442, and a fourth drain lead-out structure 452. For details, please refer to the relevant descriptions in the first test unit 10 and the second test unit 20; further details will not be elaborated here.

[0062] Please refer to Figure 3 and Figure 6 The first upper electrode plate includes a first main body and a plurality of first interdigitated portions connected to the first main body and arranged parallel to each other. On a plane perpendicular to a third direction, the projection of the first interdigitated portions extends from the inside to the outside of the edge of the projection of the first lower electrode plate along a first direction, and the projection of the first connecting portion is located outside the edge of the projection of the first lower electrode plate; and / or, the second upper electrode plate includes a second main body and a plurality of second interdigitated portions connected to the second main body and arranged parallel to each other. On a plane perpendicular to a third direction, the projection of the second interdigitated portions extends from the inside to the outside of the edge of the projection of the second lower electrode plate along a second direction, and the projection of the second connecting portion is located outside the edge of the projection of the second lower electrode plate.

[0063] Each test unit is also used to output the breakdown voltage value and the leakage current value. Specifically, the first test unit is also used to output the first breakdown voltage value and the first leakage current value; the second test unit is also used to output the second breakdown voltage value and the second leakage current value.

[0064] During the etching process to form the gate structure, the morphology of the exposed gate dielectric layer is damaged, leading to localized thinning or the formation of defect states. Electrical testing will then reveal distortions in the capacitance-voltage characteristics, a decrease in gate oxide breakdown voltage, and an increase in gate leakage current. Therefore, capacitance, breakdown voltage, and leakage current tests can be used to assess the extent of damage to the gate dielectric layer caused by the etching process. Please refer to [reference needed]. Figure 3 In another alternative example, the upper electrode is a gate structure. By setting the gate structure to include multiple interdigitated portions, the exposed area of ​​the gate dielectric layer is increased, which exacerbates etching damage, improves measurement sensitivity, and helps to improve measurement accuracy.

[0065] At the sharp corners of the active region, the electric field is abnormally concentrated, resulting in a local electric field strength much higher than in other flat regions. This makes the region more prone to reaching the critical breakdown electric field, leading to breakdown at a relatively low global voltage. Furthermore, the high electric field at the sharp corners encourages more carriers to tunnel through the gate dielectric layer, increasing leakage current and exhibiting subthreshold leakage. Please refer to [reference needed]. Figure 6 In another alternative example, the upper electrode plate is the active region. By including multiple interdigitated portions in the active region, the sharp corner defects in the active region are enhanced, and the impact of sharp corner parasitics can be assessed more effectively. If the breakdown voltage is too low and / or the leakage current is abnormally high, it directly reflects a problem with the active region morphology control process, which needs to be optimized.

[0066] It should be noted that the embodiments of this application do not limit the number of each interdigitated part.

[0067] In this embodiment, the gate dielectric layer is made of an oxide material. The semiconductor test structure can be used for GOI (Gate Oxide Integrity) integrity testing.

[0068] Please refer to Figure 7 and Figure 8 On a plane perpendicular to the third direction, the overlapping area of ​​the projections of the first upper plate and the first lower plate accounts for 70% to 90% of the projected area of ​​the first lower plate; the overlapping area of ​​the projections of the second upper plate and the second lower plate accounts for 70% to 90% of the projected area of ​​the second lower plate.

[0069] During the growth of the gate dielectric layer, growth defects may occur within it. Since the gate dielectric layer serves as the dielectric between the two plates of a capacitor, its crystal quality affects the measured capacitance value. Therefore, setting the projected area of ​​the overlapping portion of the upper and lower plates to 70%–90% of the projected area of ​​the lower plate achieves a large-area overlap between the two plates and a large-area coverage of the gate dielectric layer. This increases the probability of defects appearing within the gate dielectric layer and is more conducive to monitoring the defect density during the gate dielectric layer growth process through leakage current and breakdown voltage tests.

[0070] In some examples, without any offset, the percentage of overlapping area between the projections of the first upper plate and the first lower plate, the percentage of overlapping area between the projections of the second upper plate and the second lower plate, the percentage of overlapping area between the projections of the third upper plate and the third lower plate, and the percentage of overlapping area between the projections of the fourth upper plate and the fourth lower plate are consistent. The percentage of overlapping area between the projections of the upper and lower plates refers to the ratio of the overlapping area of ​​the upper and lower plate projections to the total projected area of ​​the lower plate.

[0071] Please refer to Figure 9 The first gate structure 130, the first active region 110, the second gate structure 230, and the second active region 210 are respectively the first upper electrode plate, the first lower electrode plate, the second upper electrode plate, and the second lower electrode plate. On a plane perpendicular to the third direction, the projections of the first source doped region 140 and the first drain doped region 150 are located on opposite sides of the projection of the first gate structure 130, and the projections of the second source doped region 240 and the second drain doped region 250 are located on opposite sides of the projection of the second gate structure 230. The first source doped region 140, the second source doped region 240, the first drain doped region 150, and the second drain doped region 250 are formed by doping in the same doping process along the same ion implantation direction. The first source doped region 140 and the first drain doped region 150 are formed by doping with the first gate structure 130 as a mask. The second source doped region 240 and the second drain doped region 250 are formed by doping with the second gate structure 230 as a mask.

[0072] like Figure 10As shown, during the doping process, if the ion implantation direction is not perfectly perpendicular, the gate structure will act like a wall, casting a shadow on the side facing away from the ion source (e.g., Figure 10 (As shown in the shaded area with a diagonal line), this results in insufficient or uneven doping concentration on that side. In this embodiment, the gate structures of the first test unit 10 and the second test unit 20 are arranged in different directions, ensuring that their source and drain doped regions are formed in the same ion implantation process. Since the implantation direction is fixed, gates with different orientations will produce varying degrees of shading on their respective source and drain doped regions. Figure 10 Taking the ion implantation direction as an example, the doping concentration of the first source doped region 140 is lower than the doping concentration of the first drain doped region 150; corresponding to Figure 9 In the XY plane, the component of the ion implantation direction is in the positive Y-axis direction, and the doping concentration of the second source doped region 240 is the same as that of the second drain doped region 250. The doping concentrations of the source and drain doped regions affect the device's threshold voltage. Therefore, the impact of the device placement orientation during ion implantation on device performance can be evaluated by comparing the effect of the shadow effect on the threshold voltage Vth.

[0073] In the example where the first gate structure 130 includes a plurality of first interdigitated regions and the second gate structure 230 includes a second interdigitated region, the first source doped region 140 and the first drain doped region 150 can be formed on both sides of any first interdigitated region, and the second source doped region 240 and the second drain doped region 250 can be formed on both sides of any second interdigitated region.

[0074] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A semiconductor testing structure, characterized in that, include: A first testing unit and a second testing unit, the first testing unit including a first capacitor, and the second testing unit including a second capacitor, wherein the measured values ​​of the first capacitor and the second capacitor are used to characterize the positional deviation between the first structure and the second structure in the product structure, the first structure, the first upper electrode of the first capacitor, and the second upper electrode of the second capacitor are formed in the same process, and the second structure, the first lower electrode of the first capacitor, and the second lower electrode of the second capacitor are formed in the same process; wherein. The first capacitor includes a first active region, a first gate dielectric layer, and a first gate structure stacked along a third direction, wherein one of the first active region and the first gate structure is the first upper electrode plate, and the other is the first lower electrode plate. The second capacitor includes a second active region, a second gate dielectric layer, and a second gate structure stacked along the third direction, wherein one of the second active region and the second gate structure is the second upper electrode plate, and the other is the second lower electrode plate; In a plane perpendicular to the third direction, the projection of the first upper electrode extends from the inside of the edge of the projection of the first lower electrode to the outside, and the projection of the second upper electrode extends from the inside of the edge of the projection of the second lower electrode to the outside; the first upper electrode and the second upper electrode are spaced apart; the direction extending from the inside of the edge of the projection of the first lower electrode to the outside is the first direction, and the direction extending from the inside of the edge of the projection of the second lower electrode to the outside is the second direction, and the first direction and the second direction are not collinear.

2. The semiconductor test structure according to claim 1, characterized in that, The first direction is perpendicular to the second direction.

3. The semiconductor test structure according to claim 1, characterized in that, In a plane perpendicular to the third direction, the projection of the first upper electrode plate crosses the first side of the projection of the first lower electrode plate and is spaced apart from the other sides of the projection of the first lower electrode plate, and the extension direction of the first side is perpendicular to the first direction. In a plane perpendicular to the third direction, the projection of the second upper electrode plate extends along the second direction across the second side of the projection of the second lower electrode plate and is spaced apart from the remaining sides of the projection of the second lower electrode plate, wherein the extension direction of the second side is perpendicular to the second direction.

4. The semiconductor test structure according to claim 1, characterized in that, The first lower electrode plate and the second lower electrode plate are two parts of a material layer with continuous edges.

5. The semiconductor test structure according to claim 4, characterized in that, In a plane perpendicular to the third direction, the projected shape of the material layer is rectangular, and the first upper electrode plate and the second upper electrode plate cross any two adjacent sides of the rectangle along the first direction and the second direction, respectively.

6. The semiconductor test structure according to claim 1, characterized in that, Also includes: The third and fourth test units; The third test unit includes a third capacitor, and the fourth test unit includes a fourth capacitor. The measured values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are used together to characterize the positional deviation between the first structure and the second structure. The third upper electrode of the third capacitor, the fourth upper electrode of the fourth capacitor, and the first structure are formed in the same process. The third lower electrode of the third capacitor, the fourth lower electrode of the fourth capacitor, and the second structure are formed in the same process. The third capacitor includes a third active region, a third gate dielectric layer, and a third gate structure stacked along the third direction, wherein one of the third active region and the third gate structure is the third upper plate and the other is the third lower plate. The fourth test unit includes a fourth active region, a fourth gate dielectric layer, and a fourth gate structure stacked along the third direction, wherein one of the fourth active region and the fourth gate structure is the fourth upper electrode plate, and the other is the fourth lower electrode plate. In a plane perpendicular to the third direction, the projection of the third upper electrode extends from the inside of the edge of the projection of the third lower electrode to the outside, and the projection of the fourth upper electrode extends from the inside of the edge of the projection of the fourth lower electrode to the outside; the first upper electrode, the second upper electrode, the third upper electrode, and the fourth upper electrode are distributed at intervals; the direction extending from the inside of the edge of the projection of the third lower electrode to the outside is the opposite direction of the first direction, and the direction extending from the inside of the edge of the projection of the fourth lower electrode to the outside is the opposite direction of the second direction.

7. The semiconductor test structure according to claim 6, characterized in that, In a plane perpendicular to the third direction, the projections of the first test unit and the third test unit are centrally symmetrically arranged, and the projections of the second test unit and the fourth test unit are centrally symmetrically arranged.

8. The semiconductor test structure according to claim 1, characterized in that, The first test unit further includes a first source doped region and a first drain doped region located within the first active region; the first test unit is also used to output a first threshold voltage; The second test unit further includes a second source doped region and a second drain doped region located within the second active region; the second test unit is also used to output a second threshold voltage.

9. The semiconductor test structure according to claim 8, characterized in that, The first gate structure, the first active region, the second gate structure, and the second active region are respectively the first upper electrode plate, the first lower electrode plate, the second upper electrode plate, and the second lower electrode plate; On a plane perpendicular to the third direction, the projections of the first source doped region and the first drain doped region are located on opposite sides of the projection of the first gate structure, and the projections of the second source doped region and the second drain doped region are located on opposite sides of the projection of the second gate structure. The first source doped region, the second source doped region, the first drain doped region, and the second drain doped region are formed by doping in the same doping process along the same ion implantation direction; the first source doped region and the first drain doped region are formed by doping with the first gate structure as a mask; and the second source doped region and the second drain doped region are formed by doping with the second gate structure as a mask.

10. The semiconductor test structure according to claim 1 or 8, characterized in that, The first upper electrode plate includes a first main body and a plurality of first interdigitated portions arranged parallel to each other connected to the first main body. On a plane perpendicular to the third direction, the projection of the first interdigitated portions extends from the inside to the outside of the projection edge of the first lower electrode plate along the first direction. The projection of the first connecting portion is located outside the projection edge of the first lower electrode plate. And / or, The second upper electrode plate includes a second main body and a plurality of second interdigitated portions arranged parallel to each other connected to the second main body. On a plane perpendicular to the third direction, the projection of the second interdigitated portions extends from the inside to the outside of the projection edge of the second lower electrode plate along the second direction. The projection of the second connecting portion is located outside the projection edge of the second lower electrode plate.

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