Solid-state relay for switching alternating current to a reactive load and method of operating the relay

Abstract

Solid-state relay for switching power from buses of an AC power source having a first phase (A) and a second phase (B) to a load (R L ) having a reactive component, the solid-state relay comprising: a first and a second power semiconductor switch (K1, K2) connected in series and for switching power from the two-phase buses to the load (R L ) can be coupled to the two-phase buses, wherein each of the first and second power semiconductor switches (K1, K2) can be controlled into the conductive and the non-conductive state; a first and a second power diode (D1, D2), each connected in parallel with the first and the second power semiconductor switch (K1, K2); and a control circuit for monitoring the voltage on the two-phase buses and the load current, wherein the control circuit is configured, upon activation, to sequentially bring the first and second switches (K1, K2) into the conducting state based on the monitored voltage, and, upon deactivation, to sequentially bring the first and second switches (K1, K2) into the non-conducting state based on the monitored load current.

Description

The present invention relates generally to solid state switching of AC power, and more particularly to a solid state relay for switching AC power to a load having a reactive component with reduced electromagnetic interference (EMI) or reduced noise, and a method of operating the relay.As electronic / computerized control, measurement and regulation systems on board aircraft and spacecraft are increasingly used, it becomes more and more important to minimize electromagnetic interference (EMI) or noise that is / is generated when switching AC power to electrical loads. Such EMI can have a negative influence on the aircraft electronics, in particular if they are generated in the course of the AC lines. Solid state switches connected in antiparallel, such as field effect transistors (FETs), are used in solid state relays in a variety of applications for AC switching. Hitherto, in these applications, attempts have been made to switch the solid state switches or FETs of the solid state relays simultaneously at zero voltage across the FET switches and / or at zero current in the switches. Due to inaccuracies in timing, there is no exact switching at zero voltage and / or zero current, which results in EMI being inherently generated by the AC switching. These inaccuracies in timing are further enhanced when the line frequency fluctuates or is unknown.US 4 680 490 A shows a solid state relay with two switches. Each of the two switches includes a switch and a diode in parallel.JP H02-230814 A shows a solid state relay with two diodes and with two transistors, the transistors being controlled by a control circuit.It is therefore an object of the present invention to provide a solid state relay which eliminates the disadvantages of the prior art solid state relay by permitting AC switching with minimal generation of EMI. Providing a solid state relay that is not dependent on the accuracy in switching timing or constant or known line frequencies is highly desirable.This object is achieved according to the invention with the features of claims 1 and 11 respectively.Exemplary embodiments of the invention are explained in more detail below with reference to the drawings. The following are shown: FIG. 1 is a schematic diagram of a conceptual embodiment of the present invention; FIGS. 2-5 illustrate various circuit configurations of the embodiment shown in FIG. 1 for describing an exemplary operation; FIGS. 6 and 7 are more detailed circuit diagrams of the embodiment shown in FIG. 1; FIGS. 8A-8G are timing waveforms for describing an exemplary operation of the circuits shown in FIGS. 6 and 7 ; FIG. 9 is a schematic diagram of an alternative embodiment of the present invention.Fig. 1 is a schematic diagram of a conceptual embodiment of the present invention. Referring to FIG. 1, two switches K1 and K2 are connected in series in parallel with an AC power source having a load R in L fashion. The switches K1 and K2 are representative of solid state switches which are electronically controlled as will be seen from the description below. In the present embodiment, the AC power source is generated via phase φ A and neutral N, resulting in an RMS AC voltage of, for example, about 115 volts. It should be noted, however, that the AC power source may also be generated via two phases of a three-phase or multi-phase power source, and in this case the AC voltage may be on the order of, for example, 200 volts RMS or more. When used in an aircraft, the frequency of the AC power source may be about 400 hertz, but may vary between 300 and 800 hertz, for example. The present embodiment may operate at frequencies of thousands of hertz.Further, in the present embodiment, one power diode D 1 is connected in parallel to the switch K 1 in a configuration in which the current flow is blocked when the Φ A- voltage potential relative to the N voltage potential is positive, and another power diode D 2 is connected in parallel to the switch K 2 in a configuration in which the current flow is blocked when the Φ A- voltage potential relative to the N voltage potential is negative. In the embodiment shown in FIG. 1, a solid state relay includes the switches K 1 and K 2 and the power diodes D 1 and D 2. Accordingly, the embodiment of the circuit shown in FIG. 1 enables the switches K1 and K2 to be operated to conduct and block the flow of current from the AC source through the load R L with minimal generation of EMI using the parallel connected diodes D1 and D2.FIGS. 1-5 show various circuit configurations illustrating operation of the present embodiment in accordance with the broad principles of the present invention. In the circuit configuration shown in FIG. 1, it is assumed that the solid state relay is turned off or deactivated, both switches K 1 and K 2 are non-conductive, and the diodes D 1 and D 2 block the current flow through the load. In the circuit configuration shown in FIG. 2, the solid state relay is activated or turned on, and when Φ A becomes positive relative to N, one of the switches, for example, K2, is controlled to a closed or conductive state. In this state, however, diode D1 continues to block current flow through the load from φ A to N. In the circuit configuration shown in FIG. 3, when the solid state relay is activated or turned on, as the voltage polarity of φ A relative to N changes from positive to negative, a gradual current flow via switch K2 that has been closed and conductive diode D1 through the load begins. In this state, the other switch K1 is controlled to a closed or conductive state. In the period in which the switch K 1 closes, the load current gradually transitions from the diode D 1 to the switch K 1. In the circuit configuration shown in FIG. 4, the switch K 1 finally closes. Thus, the parallel connected diode D 1 allows for an initial load current flow until the switch K 1 is able to conduct the full load current when Φ A changes from positive to negative relative to N. It should be noted that when K1 begins to conduct, a smooth transition of the load current from D1 to K1 occurs. Consequently, when the alternating current is switched from on to off by the load, little or no EMI is generated.In the circuit configuration shown in FIG. 4, when Φ A becomes positive relative to N, when the solid state relay is turned off, one of the switches K 2 is controlled to the open state while the other switch K 1 remains closed as shown in FIG. 5, but the load current continues to flow through the diode D 2 connected in parallel. That is, when the switch K 2 opens, the load current gradually transitions from the switch K 2 to the diode D 2. Then, the diode D2 blocks the flow of load current when Φ A becomes negative relative to N. While Φ A is negative relative to N, switch K1 may be opened without affecting the current flow already blocked by diode D2. Consequently, when the AC power is switched from on to off by the load, little or no EMI is generated. Further, by using the parallel-connected diodes D1 and D2, the critical timing of the zero crossing required so far for turning on and off the alternating current to the load is substantially eliminated. The parallel connected diodes inherently commute between on and off to conduct and block the load current when the respective switch is turned on and off at any frequency of the AC power source.Fig. 6 is a detailed schematic diagram of the embodiment of the present invention. Referring to FIG. 6, a floating DC power supply 10 is disposed between the voltage buses.phi.A and.phi.B of the AC power source. Phase Φ B may be the zero bus N or another phase of a polyphase power source. In the present embodiment, solid state switches K1 and K2 are implemented as power N-metal oxide semiconductor (MOS) FETs FET-1 and FET-2, respectively, as described in connection with FIG. 1, for example, of the type manufactured by Advanced Power Technology under the type number APT5015. Each APT1555 package includes a power diode that is anode-to-source (S) and cathode-to-drain (D) coupled to the FET. That is, diode D1 is coupled to FET-1 and diode D2 is coupled to FET-2. The switches FET-1 and FET-2 are connected in series at their source terminals and connected in series between the buses.phi.A and.phi.B with the load R L14, which is a heating element in the present embodiment, for example.The floating power supply 10 includes a resistor R 1 having one end coupled to the Φ B- ( phase B) power bus and the other end coupled to the anode of a diode D 3. The cathode of diode D3 is coupled to the cathode of a zener diode D4, which may be, for example, a 12V zener diode, and to one side of a capacitor C1 connected in parallel with zener diode D4. The anode of D4 is coupled to the source of FET-1 and the anode of D1. The drain of FET-1 and the cathode of D1 are coupled to the Φ A- ( phase A) bus. Accordingly, each time the phase A bus becomes positive relative to the phase B bus, current flows through the series connection of components R1, D3, D4 and D1 (half-wave rectification) and is limited by the resistance of R1, which in the present embodiment may be on the order of, for example, 20 kOhm, and the voltage generated across it. This current charges the capacitor C1, which may be on the order of 10 microfarads for example, to the voltage of the zener diode, which may be 12 volts. Diodes D1 and D3 prevent C1 from discharging back into the phase B bus when it becomes negative relative to the phase A bus. The voltage at C1 is the voltage of the floating power supply 10. DC power supply lines V cc and V ss of the floating supply 10 are coupled to the positive and negative sides of C1, respectively.A logic circuit 12 for controlling switching of the switches FET-1 and FET-2 is coupled to the supply lines V cc and V ss of the floating power supply 10. In the present embodiment, the collectors of the separate phototransistors PT1, PT2, and PT3 are coupled to the V cc- bus. The emitter of PT1 is connected in series with a constant current sinking diode D5 with the V ss- bus, and the emitter of PT2 is connected in series with another constant current sinking diode D6 with the V ss- bus. The constant current bypass diodes D5 and D6 may be, for example, 1N5297 diodes and carry a predetermined current, which is, for example, on the order of 1 milliampere. Each diode D5 and D6 functions as a switch which turns on to generate a voltage with a very steep rising edge across the diode when the line current reaches the predetermined level. Before the line current reaches the predetermined level, the voltage across each diode D5 and D6 remains substantially zero. Respective photodiodes PD1 and PD2 are connected in parallel with each other, and the parallel circuit is connected in series with a current limiting resistor R5 via the phase A bus and the phase B bus. Photodiodes PD1 and PD2 may be embedded with their respective phototransistors PT1 and PT2 in a common dual optocoupler package, which may be, for example, a package of the type manufactured by Fairchild under the type designation MCT 62.During the half-wave cycles of the AC power supply, where the phase A bus is positive relative to the phase B bus, current flows through PD1, which in response generates light referred to as "POS". The POS light signal is optically coupled to the corresponding transistor PT1 to cause PT1 to conduct current through diode D5. Similarly, during the half-wave cycles of the AC power supply where the phase A bus is negative relative to the phase B bus, current flows through PD2 which, in response, generates light referred to as "NEG". The NEG light signal is optically coupled to the corresponding transistor PT2 to cause PT2 to conduct current through diode D6.Referring to FIG. 7, a photodiode PD3 corresponding to PT3 may be connected in series between a voltage source V+ and ground with a switch S1 and a current limiting resistor R6. The switch S 1 may be a solid state switch or an electromechanical switch operated by a controller such as a temperature controller for turning on and off the solid state relay to control the temperature of the heating element. The switch S 1 may further be a manually operated mechanical switch. When the switch S1 is switched to the conductive state, current flows through PD3 and PD3 generates light, referred to as "ON", in response thereto. The PD3 and the corresponding PT3 may further be arranged in a common optocoupler component, such as MCT 62. As shown in FIG. 6, the emitter of the PT3 is connected in series with a resistor R2 and coupled to the V ss- bus. Accordingly, the light "ON" is optically coupled to PT3 and causes PT3 to conduct current from bus V cc through resistor R2 to bus V ss and thus causes the development of a positive voltage relative to V ss across R2. In this manner, the logic 12 powered by the floating power supply 10 is completely isolated from the source of the control signals POS, NEG and ON by the optical coupling of the control signals POS, NEG and ON.Further, in the embodiment shown in FIG. 6, the anode of D5 is coupled to a clock input, referred to as CLK, of a D flip-flop FF1, and the connection node between the emitter of PT3 and the resistor R2 is coupled to a data input, referred to as D, of FF1. An output Q1 of FF1 is coupled via a resistor R3 to the gate terminal of FET-2 and to a D input of another D flip-flop FF2. Further, the anode of D6 is coupled to a CLK input of FF2 and an output Q2 of FF2 is coupled through a resistor R4 to the gate terminal of FET-1. Each flip-flop FF1 and FF2 is powered from the floating power supply via buses V cc and V ss and is for transferring the status of the signal at the D input of the flip-flops to the output Q upon the occurrence of a rising edge pulse at the CLK input and thereafter maintains the output Q until the occurrence of the next rising edge pulse at the CLK input.The operation of the embodiment described in connection with FIGS. 6 and 7 will now be explained using the example time waveforms shown in FIGS. 8A-8G. In operation, the solid state relay switches FET-1 and FET-2 are controlled by the logic circuit 12 to switch the AC power supply (see FIG. 8A) to the load or heating element 14. To this end, opto-coupler PD1 / PT1 generates a pulse, referred to as POS, at the CLK input of FF1 at times when the phase A bus is positive relative to the phase B bus, as shown in FIGS. 8A and 8B. Similarly, opto-coupler PD2 / PT2 generates a pulse, referred to as NEG, at the CLK input of FF2 at times when the phase A bus is negative relative to the phase B bus, as shown in FIGS. 8A and 8C. It should be noted that until the solid state relay is activated, the outputs Q1 and Q2 of the flip-flops FF1 and FF2 remain in the L or non-positive state in response to the POS and NEG pulses. In these states of Q1 and Q2, switches FET-1 and FET-2 remain open or non-conductive.The solid state relay may be activated to couple the AC supply to the load via the control of switches FET-1 and FET-2 by closing switch S1 which controls opto-coupler PD3 / PT3 to generate an H or positive pulse at the D input of FF1, referred to as ON. Referring to FIG. 8D, the pulse ON remains effective until the switch S1 is opened. After activation of the solid state relay, FF1 generates the H or positive state at Q1 at the rising edge of the next POS pulse representative of a positive half wave of the phase A bus, as shown in Figure 8E. The positive state on Q1 drives the switch FET-2 to begin closing and is fed to the D input of FF2. It may take a time period t1 within the positive half-wave cycle of the phase A bus until FET-2 becomes fully conductive. In the present embodiment, the time period t 1 may be, for example, about 300 microseconds. It should be noted that this closure of FET-2 is a preparation for conducting current to load 14, but does not allow this conduction of current to load 14 because FET-1 remains open and diode D1 is in a blocking state.However, once the phase A bus becomes negative relative to the phase B bus, diode D1 begins to conduct current through previously closed switch FET-2 to load 14, as shown in FIG. 8G. At the rising edge of the subsequent NEG pulse, representative of a negative half wave of the phase A BUS, FF2 generates the H or positive state at Q2 (since the D input is in the positive state), as shown in Figure 8F. The positive state on Q2 drives the switch FET-1 to begin closing. It may take a time period t2 within the negative half-wave cycle of the phase A bus until FET-2 becomes fully conductive. In the present embodiment, the time period t 2 may be, for example, about 300 microseconds. As FET- 1 closes, the load current gradually transitions from D 1 to FET- 1. Thus, when FET-1 is fully closed at the end of t2, it conducts the entire load current.The solid state relay may be disabled to decouple the AC power supply from the load via the control of switches FET- 1 and FET- 2 by opening switch S 1 that controls opto-coupler PD3 / PT3 to sink the ON pulse at the D input of FF1, as shown in FIG. 8D. The ON pulse thereafter remains in the L state until the switch S1 is again closed. At the rising edge of the next POS pulse after the deactivation of the solid state relay, FF1 generates the L or non-positive state at Q1 as shown in FIGS. 8B and 8E. The low state on Q1 drives the switch FET-2 to begin opening and is fed to the D input of FF2. It may take time for FET-2 to become fully open or non-conductive. It should be noted that this opening of FET-2 is a preparation for conduction but not blocking conduction of current to load 14 (see FIG. 8G ) because FET-1 remains closed and the load current transitions to diode D 2 which is in the conducting state. However, as soon as the phase A bus becomes negative relative to the phase B bus, the diode D2 becomes non-conductive. When D2 is non-conductive and FET-2 is open, current flow to load 14 is blocked, as shown in FIG. 8G. Further, when the phase A bus becomes negative, the NEG pulse is generated (see FIG. 8C) which triggers the output Q2 of FF2 to an L or non-positive state, thereby driving FET-1 to an open or blocking state.Although the solid state relay embodiment described above is suitable for controlling the AC current to a resistive load at low EMI emissions, it should be appreciated that, in minor modifications, it may control the AC current to loads other than resistive loads. To minimize EMI emissions in loads having a significant reactive component, such as an inductive load - where the load current is out of phase with respect to the supply voltage, it is desirable to turn on the load current at the zero crossing of the supply voltage and turn off the load current at the zero crossing of the load current. A suitable modified embodiment of the solid state relay described with reference to FIG. 6 is shown in the schematic diagram of FIG. 9. In FIG. 9, those circuit elements which are the same as those in the embodiment of the solid state relay shown in FIG. 6 are denoted by the same reference numerals.Referring to FIG. 9, the modified embodiment includes four NAND gates NG1-NG4 which may be included in a single integrated circuit (IC) package and four operational amplifiers A1-A4 which may also be included in a single IC package. Both the gate and operational amplifier packets are powered by the V cc- and V ss- buses. Shunt resistors R10 and R11 interposed between the switches FET-1 and FET-2 are connected in series with a reactive load L1. For example, resistor R10 may be disposed between the V ss- bus and FET-2, and resistor R11 may be disposed between the V ss- bus and FET-1. An inverting (-) input of amplifiers A1 and A3 is coupled to the V ss- bus side of resistors R10 and R11, respectively. The other side of resistors R10 and R11 is coupled to the noninverting (+) inputs of amplifiers A1 and A2, respectively.The outputs of A1 and A3 are coupled to the inverting (-) inputs of amplifiers A2 and A4, respectively. A voltage divider network comprising resistors R12 and R13 is coupled to busses V cc and V ss to generate a reference voltage at the node between R12 and R13 which is coupled to the noninverting (+) inputs of amplifiers A2 and A4. The output of A2 is coupled to one of the inputs of gates NG1 and NG4 and serves as an enable signal for that input, and the output of A4 is coupled to one of the inputs of gates NG2 and NG3 and serves as an enable signal for that input. The V pos- and V neg- signals are coupled to the other input of the gates NG1 and NG3, respectively, and the outputs of NG1 and NG3 are coupled to the other input of the gates NG2 and NG4, respectively. The outputs of NG2 and NG4 are coupled to the clk1 and clk2 inputs of flip-flops FF1 and FF2, respectively. Further, a power-on reset circuit comprising a series circuit of capacitor C3 and resistor R14 is coupled to buses V cc and V ss respectively. The node between C3 and R14 is coupled to a reset input of the flip-flop circuits FF1 and FF2 to ensure that the start state of the outputs Q1 and Q2 of the flip-flop circuits FF1 and FF2 is reset to zero upon power-on.In the alternative embodiment, amplifiers A1 and A3 function as differential amplifiers, generating signals INEG and IPOS at their outputs, which are representative of the load currents of resistors R10 and R11, respectively. Amplifiers A2 and A4 function as comparator circuits which compare current representative signals INEG and IPOS of A1 and A3 with the voltage at the node of resistors R12 and R13, which may be representative of, for example, a zero current level. Similarly, comparators A2 and A4 generate logic signals INEG (bar) and IPOS (bar) representative of the negative and positive zero load currents, respectively. Thus, gate NG1 is disabled by the output signal of A2 at a negative load current other than zero and gate N3 is disabled by the output signal of A4 at a positive load current other than zero. Note that all the gates NG1-NG4 are activated when the load current is zero.The alternative embodiment shown in FIG. 9 operates as follows: When the ON pulse generated by PD3 / PT3 is started, no load current flows (i.e., all of the gates NG1-NG4 are activated) and the circuit operates in substantially the same manner as described in connection with the embodiment of the circuit shown in FIG. 6, i.e., the gates NG1-NG2 are transmissive, and the signals V pos and V neg directly drive the clock inputs of FF1 and FF2. Accordingly, the load current from the switch / diode configurations FET 1 / D 1 and FET 2 / D 2 is turned on at or very close to the zero crossing of the supply voltage. When the load current is turned on, the amplifiers A1 and A2 generate their load current representative signals INEG and IPOS through the resistors R10 and R11, and then the amplifiers A2 and A4 generate the logic signals INEG (bar) and IPOS (bar), respectively.In this state, the gates NG1 and NG3 are deactivated by the logic signals INEG (bar) and IPOS (bar), respectively, and do not respond to the logic signals V pos and V neg respectively. When gates NG1 and NG3 are disabled, gates NG2 and NG4 are responsive to logic signals INEG (bar) and IPOS (bar), respectively, representative of the phase states of the load current. Therefore, when the load current is on, the logic signals from the supply voltage device are ignored and the phase states of the load current control the clock inputs in FF1 and FF2. Thus, when the logic signal ON is switched to the L state to turn off the current to the load L 1, the load current logic signals IPOS (bar) and INEG (bar) (via NG2 / FF1 and NG4 / FF2, respectively) control the turning off of the switches FET- 2 and FET- 1 at or near the load current zero junction or crossing rather than the supply voltage zero crossing.Further, if desired, a capacitor C4 and a varactor V1 may be added to the solid state relay embodiment. In the present embodiment, the capacitor C4 and a varactor V1 are connected in parallel across the series arrangement of the switches FET-1 and FET-2 between the load L1 and phase A of the AC power supply. Varactor V1 serves to protect the circuit from voltage spikes and the function of capacitor C4 is to perform filtering of the current waveform.Thus, the circuit modifications in the alternative embodiment ensure that the load current is turned on at the zero crossing of the supply voltage and turned off at the zero crossing of the load current, thereby minimizing EMI emissions for loads with reactive components. Further, since the load current signals depend on the value of the load current in the alternative embodiment, the shunt resistors R 10 and R 11 may be configured in a manner suitable for multiple load current ranges. Further, in the alternative embodiment, if the load current is insufficient for the modified circuit, a default setting to the operating mode of the embodiment shown in FIG. 6 is automatically made.It should be noted that in the solid state relay of the present invention, no sharp load current transitions occur upon switching of the power supply to and from the load 14. Thus, when the solid state relay is in operation, little or substantially no EMI is generated by the switching operation. Further, since the solid state relay of the present invention is not sensitive to zero switching timing, the solid state relay can operate at different frequencies of the AC power supply. Further, while the solid state switches are embodied as MOSFETs in the present example, it should be appreciated that other types of solid state switches may be used, such as power bipolar transistors, insulated gate bipolar transistors (IGBTs), and the like, without departing from the broad principles of the present invention.

Claims

A solid state relay for switching power from buses of an AC power source having a first phase (A) and a second phase (B) to a load (R L), having a reactive component, the solid state relay comprising: first and second power semiconductor switches (K1, K2) connected in series and couplable to the two phase buses for switching power from the two phase buses to the load (R L) wherein each of the first and second power semiconductor switches (K1, K2) is controllable to the conductive and non-conductive states; first and second power diodes (D1, D2) connected in parallel with the first and second power semiconductor switches (K1, K2), respectively; and a control circuit for monitoring the voltage across the biphasic buses and the load current, wherein the control circuit, after activation, is configured to sequentially bring the first and second switches (K1, K2) into the conductive state based on the monitored voltage, and after deactivation, sequentially bring the first and second switches (K1, K2) into the non-conductive state based on the monitored load current.The relay of claim 1, wherein the first and second power diodes (D1,D2)jeweils are arranged in parallel with the first and second power semiconductor switches (K1, K2) in a circuit configuration in which current flow to the load (R L) is blocked when both the first and second power semiconductor switches (K1, K2) are in the non-conductive state.The relay of claim 2, wherein the series connection of first and second power semiconductor switches (K1, K2) is connected in series with the load (R L) ; and wherein the series connection of load (R L) and first and second power semiconductor switches (K1, K2) is coupled to the buses having a first phase (A) and a second phase (B).The relay of claim 1, wherein the control circuit is controlled to control the first semiconductor switch (K1) based on the transition of the monitored voltage from the first polarity to the second polarity to the conductive state, and to control the second semiconductor switch (K2) based on the transition of the monitored voltage from the second polarity to the first polarity to the conductive state from an enable signal.The relay of claim 1, wherein the control circuit is controlled by a disable signal to control the first semiconductor switch (K1) based on the transition of the monitored load current from the first polarity to the second polarity to the non-conductive state, and to control the second semiconductor switch (K2) based on the transition of the monitored load current from the second polarity to the first polarity to the non-conductive state.The relay of claim 1, wherein the control circuit comprises: a first circuit for monitoring the voltage across the buses having a first phase (A) and a second phase (B) and generating logic voltage signals representative of the first and second polarities of the voltage; a second circuit for monitoring the load current and generating logic current signals representative of the first and second polarities of the load current; and a third circuit for controlling the first and second switches based on the logic voltage signals and the logic current signals.A relay as claimed in claim 6, wherein the second circuit is arranged to generate the logic current signals when the monitored load current exceeds a predetermined level.The relay of claim 7, wherein the third circuit is configured to respond to the Iogian voltage signals when the monitored load current falls below the predetermined level.A relay as claimed in claim 7, wherein the third circuit is arranged to respond to the logic current signals when the monitored load current exceeds the predetermined level.The relay of claim 6, wherein the second circuit comprises at least one resistor connected in series with the load (R L).A method of switching power from bus lines of an AC power source having a first phase (A) and a second phase (B) to a load (R L), having a reactive component, the method comprising the steps of: arranging first and second power semiconductor switches (K1, K2) in a series connection and connecting the series connection to the two-phase buses to switch power from the two-phase buses to the load (R L); coupling the first and second power diodes (D1, D2) via the first and second power semiconductor switches (K1, K2), respectively; monitoring a voltage on the two-phase buses and a load current; activating the solid state relay to provide power from the two-phase buses to the load (R L) ; deactivating a power output of the solid state relay from the two-phase buses to the load (R L); upon activating the solid state relay, sequentially controlling the first and second switches (K1, K2) to the conductive state based on the monitored voltage; and upon deactivating the solid state relay, sequentially controlling the first and second switches (K1, K2) to the non-conductive state based on the monitored load current.The method of claim 11, wherein the first and second power diodes (D1, D2) are connected in parallel with the first and second power semiconductor switches (K1, K2) in a circuit configuration to block current flow to the load element when both the first and second power semiconductor switches (K1, K2) are in the non-conductive state.Method according to claim 12, comprising the following steps: connecting the series circuit of first and second power semiconductor switches (K1, K2) in series with the load (R L); and connecting the series circuit of load (R L) and first and second power semiconductor switches (K1, K2) to the buses having a first phase (A) and a second phase (B).The method of claim 11 comprising the step of: in the activated state, controlling the first semiconductor switch (K1) based on the transition of the monitored voltage from the first polarity to the second polarity to the conductive state, and thereafter controlling the second semiconductor switch (K2) based on the transition of the monitored voltage from the second polarity to the first polarity to the conductive state.The method of claim 11 comprising the step of: in the deactivated state, controlling the first semiconductor switch (K1) based on the transition of the monitored load current from the first polarity to the second polarity to the non-conductive state, and thereafter controlling the second semiconductor switch (K2) based on the transition of the monitored load current from the second polarity to the first polarity to the non-conductive state.The method of claim 11 comprising the steps of: monitoring the voltage across the buses having a first phase (A) and a second phase (B) and generating logic voltage signals representative of the first and second polarities of the voltage; monitoring the load current and generating logic current signals representative of the first and second polarities of the current; and controlling the first and second switches based on the logic voltage signals and the logic current signals.The method of claim 16, including the step of generating said logic current signals when said monitored load current exceeds a predetermined level.The method of claim 17, comprising the step of responding to said logic voltage signals to control said first and second switches (K1, K2) when said monitored load current falls below said predetermined level.The method of claim 17, comprising the step of responding to said logic current signals to control said first and second switches (K1, K2) when said monitored load current exceeds said predetermined level.The method of claim 16, wherein the step of monitoring the load current comprises monitoring the voltage across at least one resistor in series with the load (RL).

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