Semiconductor device

Abstract

Semiconductor device (1, 2) comprising: a semiconductor substrate (11) with a component formation area (12); Element or component insulation regions or areas (13) that are buried in the semiconductor substrate (11), wherein the element or component insulation regions or areas (13) have top surfaces; a gate electrode (22) formed on the component formation area (12), wherein the gate electrode extends in a first direction; a gate insulation layer (21) formed between the gate electrode (22) and the component formation area (12); Source-drain regions (27, 28) formed in the device formation area (12), wherein the source-drain regions (27, 28) are formed on both sides of the gate electrode (22) in a second direction and are formed below the top of the element or device insulation regions or areas (13); and a channel area (14) which is formed in the component formation area (12) below the gate electrode (22), wherein the element or component insulation areas or regions (13) have recesses (15) in the top surfaces, and the recesses (15) are formed below the gate electrode (22) and are bounded along the second direction.

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

[0001] The present invention relates to a semiconductor device in which a voltage or mechanical stress is applied to a channel region, and to a manufacturing method for a semiconductor device. 2. Description of the state of the art

[0002] Recently, many reports have been published regarding techniques for improving operation or operational capabilities without relying on a scaling law. These known techniques improve operational capabilities by imposing or applying a voltage or mechanical stress to a silicon region or area (e.g., a silicon substrate) in which a channel region or area is formed, thereby increasing the mobility or movement of electrons or holes.One such technique that has been adopted into practical use is a process in which a drain-source part is introduced by silicon etching, or is driven into or buried at depth, and in which a silicon compound with a lattice constant different from that of silicon (Si) is grown by an epitaxial growth process, thereby imparting or exerting stress on the channel part (see, e.g., JP 2000 - 315 789 A). Reference is also made to the disclosures in JP 2006 - 12 924 A, US 2006 / 0 223 290 A1, US 2006 / 0157 797 A1, DE 10 2005 022 306 A1, and US 2006 / 0 278 952 A1.

[0003] In addition, various attempts have been made, for example using so-called stress liners, which distort or deform the channel by forming a lining, cover or top layer of a silicon nitride layer which exerts a stress or mechanical strain after forming a transistor, and techniques which distort or deform the channel by using a layer which exerts a stress or mechanical strain as part of a hidden or buried material, e.g. for an STI (Shallow Trench Isolation) structure, and the like.

[0004] The mechanism is explained with reference to a schematic diagram. Fig. 10A and Fig. Figure 10B shows the three-dimensional directions of stress under mechanical strain, which are most effective when applied to the respective transistors of a pMOSFET, as used in Fig. 10A is shown, and an nMOSFET, as shown in Fig. As shown in Figure 10B, an effective stress or strain is applied to deform or distort the channel. This stress, common to both the NMOS and the PMOS, is applied in a direction of stretching or extending the active area or region in an x-direction.

[0005] A section in the direction of the width or extent of the gate (a direction orthogonal to the direction of the source drain region) of a (planar) two-dimensional MOS transistor from the prior art is described with reference to Fig. 11 describes, which shows a cross-sectional view of the structure or configuration. It is known that, as described in Fig. As shown in Figure 11, an insulating layer (a high-density plasma; HDP or the like) possesses or generates a compression stress when it is concealed or buried in a trench 115 formed in a semiconductor substrate 111 to construct element insulation regions or areas 113 of an STI structure. The stress applied to the channel region or channel area 114 of the transistor acts in a direction that impairs mobility (the direction of the arrows).

[0006] On the other hand, with the development of transistor generations, many researchers have focused on developing transistors with a three-dimensional structure or design, instead of the two-dimensional (planar) transistors of the prior art. A typical transistor is called a fin-gate transistor, in which a gate electrode is arranged on a silicon substrate, a gate dielectric is provided between the gate electrode and the silicon substrate, and the gate dielectric covers part of the channel area of ​​a fin part or fin section, protruding, projecting, or extending beyond the fin in the manner or shape of a fin (see, e.g.,JP 2006 - 12 924 A In addition, a so-called tri-gate transistor was provided, which uses as a channel not only a top surface of a semiconductor substrate in which a trench is formed, but also a side wall area of ​​a top surface of the trench (see e.g. JP 2002 - 198 532 A).

[0007] Fig. Figure 12 is a schematic three-dimensional diagram of an ordinary MOS transistor. Fig. 13 is a vertical cross-sectional view with one or along a line AA' from Fig. 12. If the silicide layers 131 and 132 are formed to reduce the resistance on the surfaces of the source drain regions 127 and 128 in a transistor 101 with a structure in which the channel region 114 and the source drain regions 127 and 128 protrude from or out of the surface of the semiconductor substrate 111, as shown in the Fig. 12 and Fig. As shown in Figure 13, a leak or leakage current arises as a result of the silicide layers 131 and 132, because these are near or in contact with the PN junction of the source drain regions 127 and 128, which are formed by means of ion implantation and protrude from or from the surface of the semiconductor substrate 111. SUMMARY OF THE INVENTION

[0008] The problems to be solved are to prevent stress or mechanical strain imposed in a width direction of the gate (hereinafter, the width direction of the gate refers to a direction perpendicular to the direction of the source drain region) of the channel region of the transistor from acting in a direction of deteriorating or weakening mobility when the STI structure is used as an element isolation region, and to prevent leakage or leakage current from occurring when the source drain regions are formed in a state in which they protrude from the silicon substrate, and the silicide layers are formed in such a way as to reduce the resistance of the source drain regions.

[0009] The problems underlying the invention are solved according to the invention in a semiconductor device by the features of independent claim 1. Preferred embodiments are the subject of the respective dependent claims.

[0010] It is desirable to form and impose the stress or mechanical tension in such a way that it acts in a direction of the width or extent of the gate of the channel area or channel region in a direction which improves mobility or movement, preventing leakage or leakage current, which occur when the silicide layers are formed, in order to reduce the resistance on the surfaces of the source drain areas by improving the structure of the channel area or channel region and the element insulation area or element insulation area.

[0011] According to a first example, a semiconductor device is created comprising: element isolating / isolation regions formed in a state where they are hidden or buried in a semiconductor substrate, e.g., such that an element forming / formation region of the semiconductor substrate is arranged between the element isolating / isolation regions; a gate electrode arranged on the element forming / formation region with a gate insulating layer arranged between the gate electrode and the element forming / formation region, the gate electrode being configured to intersect the element forming / formation region;and source drain regions or areas formed in the element or component formation region or area on both sides of the gate electrode, wherein a channel region or area of ​​the element or component formation region or area is formed below the gate electrode to protrude from the element or component insulation regions or areas, and wherein the source drain regions are formed at a location or position deeper than the surfaces of the component or element insulation regions or areas.

[0012] In the first example described above, the channel region is formed from an element or component formation region or area beneath the gate electrode, projecting from or rising above the element or component insulation regions or areas. Consequently, the compressive stress caused by the mechanical stress imposed on the channel region or area directly beneath the gate electrode is released or discharged within the channel region or area by the element or component insulation regions or areas in a direction corresponding to the width or extent of the gate of the lower portion of the channel region or area. Therefore, a strong tensile stress acts in the direction corresponding to the width or extent of the gate of the channel region or area.Additionally, the source drain regions are located at a position that is lower than the surfaces of the element or device insulation regions. Therefore, the junction positions of the source drain regions are also located at a lower depth than the surfaces of the element or device insulation regions. Even if low-resistance silicide layers are applied to the surfaces of the source drain regions, these layers do not approach or come into contact with the semiconductor substrate in the lower regions of the source drain regions, thus preventing leakage or leakage currents.

[0013] According to a second example, a manufacturing process for a semiconductor device is created comprising the steps of: forming element or component isolation regions or areas in a semiconductor substrate such that an element or component formation region or area is formed between the element or component isolation regions or areas and the element or component isolation regions or areas are hidden or buried in the semiconductor substrate; forming a dummy gate or sacrificial gate on the element or component formation region or area such that the dummy gate intersects or crosses the element or component formation region or the corresponding area; forming source drain regions or areas in the element or component formation region or area on both sides of the dummy gate such thatthat locations or positions of transitions of the source drain regions are lower than faces or surfaces of the element or device insulation regions or areas, forming a first insulating layer on the semiconductor substrate, wherein a face or surface of the dummy gate remains or is exposed, forming a recess by removing the dummy gate, removing the upper or topmost parts or sections of the element or device insulation regions or areas within the recess, and forming a gate electrode on the semiconductor substrate within the recess, wherein a gate insulating layer is arranged between the gate electrode and the semiconductor substrate.

[0014] In the second example described above, the channel region is formed from the element or component formation area or region below the gate electrode such that it extends from or protrudes from the element or component insulation areas or regions. Consequently, a compressive stress, caused by the mechanical stress imposed on the channel region or region directly below the gate electrode by the element or component insulation areas or regions in a direction corresponding to the width or extent of the gate of the lower region or part of the channel region or region, is released or discharged within the channel region or region. Therefore, a strong tensile stress acts in a direction corresponding to the width or extent of the gate of the channel region.Additionally, the transitions of the source drain regions are located deeper than the surfaces of the element or component insulation regions. Even if silicide layers for low resistance are formed on the surfaces of the source drain regions, these silicide layers do not come close to or into contact with the semiconductor substrate in the deeper part of the source drain regions, thus preventing leakage points or leakage currents.

[0015] The first example described above has the advantage that it allows for the generation of mechanical stress in the channel region directly below the gate electrode in a longitudinal direction, which is beneficial for the transistor characteristics (carrier or charge carrier mobility). This consequently improves the transistor's on-current ion, thus enhancing its performance. Additionally, leakage current between the silicide layers and the semiconductor substrate can be avoided because the junction positions of the source drain regions are located lower than the surfaces of the element or component insulation regions, even when a low-resistance silicide is applied to the source drain regions. These measures improve the transistor's reliability.The effects described above are increased by reducing the gate width of the transistor.

[0016] The second example described above has the advantage that it allows for the generation of mechanical stress in the channel region directly below the gate electrode in a longitudinal direction, which is beneficial for the transistor characteristics (carrier or charge carrier mobility). This consequently improves the transistor's on-current ion, thus enhancing its performance. Additionally, leakage current between the silicide layers and the semiconductor substrate can be avoided because the junction positions of the source drain regions are located lower than the surfaces of the element or component insulation regions, even when a low-resistance silicide is applied to the source drain regions. These measures improve the transistor's reliability.The effects described above are increased by reducing the gate width of the transistor. BRIEF DESCRIPTION OF THE FIGURES Fig. Figure 1 is a schematic perspective view which schematically shows an embodiment (first embodiment) of a semiconductor device according to the present invention. Fig. 2 is a vertical cross-sectional view along line AA' from Fig. 1. Fig. Figure 3 is a vertical cross-sectional view along line BB'. Fig. 1. Fig. Figure 4 is a vertical cross-sectional view along line CC'. Fig. 1. Fig. 5 is a vertical cross-sectional view along line DD' from Fig. 1. Fig. Figures 6A-P are cross-sectional views for a manufacturing process of an embodiment (first embodiment) of a semiconductor device according to the present invention. Fig. Figures 7A and B are schematic and sectioned views of a structure of an embodiment (second embodiment) of a semiconductor device according to the present invention. Fig. Figures 8A and 8B are schematic and sectional views of a structure of an embodiment (third embodiment) of a semiconductor device according to the present invention. Fig. Figures 9A-O are cross-sectional views relating to a manufacturing process of an embodiment (second embodiment), specifically relating to a manufacturing process for a semiconductor device according to the present invention. Fig. Figures 10A and 10B are schematic top-down diagrams relating to the structure to assist in explaining the mechanical stresses imposed on an active region or active area of ​​a transistor. Fig. Figure 11 is a schematic cross-sectional view of a structure showing a cross-section in a width direction of a gate of a two-dimensional (planar) type MOS transistor from the prior art; Fig. Figure 12 is a schematic and perspective view which schematically shows a three-dimensional structure of an ordinary MOS transistor. Fig. 13 is a vertical section view along line AA' from Fig. 12. DETAILED DESCRIPTION OF PREFERRED EXECUTION FORMS

[0017] A preferred embodiment (first embodiment) of a semiconductor device according to the present invention is described with reference to the schematic and perspective view of the Fig. 1, a vertical cross-sectional view along line AA' of the Fig. 1 in Fig. 2, a vertical cross-sectional view along line BB' from Fig. 1 in Fig. 3, a vertical cross-sectional view along a line CC' from Fig. 1 in Fig. 4 and a vertical cross-sectional view along a line DD' from Fig. 1 in Fig. 5 explained. At the same time, Fig. 1. A diagram explaining the basic structure, although some of the components forming the structure are not shown in this diagram. In the Fig. 3 and Fig. Figure 5 shows an insulating intermediate layer.

[0018] With main reference to the Fig. 1 and Fig. 2 The structure of a semiconductor device 1 is described below.

[0019] In a semiconductor substrate 11, element or component isolation regions or areas 13 are formed for electrically isolating an element or component formation region or area 12 in which a transistor is formed. For example, a silicon substrate is used as the semiconductor substrate 11. For example, a conventional STI structure (STI: Shallow Trench Isolation) can be used in conjunction with the element or component isolation regions or areas 13. Consequently, a portion of the semiconductor substrate 11 located between the element or component isolation regions or areas 13 forms the element or component formation region 12 or the corresponding area.

[0020] Recesses or depressions 15 are provided in the upper parts or areas of the element or component insulation regions or areas on both sides of a channel region 14 in the element or component formation area or region 12 such that the channel region 14 rises from or protrudes from the surfaces of the element or component insulation regions or areas 13 (see also the vertical cross-sectional view from Fig. 3 along line BB' from Fig. 1 and the vertical cross-sectional view from Fig. 4 along line CC' from Fig. 1) Consequently, the recesses or depressions 15 in the element or component insulation areas or regions 13 on both sides of the channel area 14 are designed such that only the channel area 14 protrudes from or is raised from the element or component insulation areas or regions 13. In this case, the degree or value of the protrusion or elevation of the channel area 14 from the surfaces of the element or component insulation areas or regions 13 at the bottom of the recesses or depressions 15 is, for example, selected or set in the range of approximately 3 nm to approximately 30 nm. (The channel width is set to a value of 0.5 µm or less.) An effective stress or mechanical strain is thereby imposed in one direction of the gate width of the channel area 14 (X-direction).If the protrusion or elevation is less than 3 nm, the channel area 14 is otherwise influenced by the stress or mechanical strain in the element or component insulation areas 13. Consequently, the formation of a raised or protruding channel area 14 cannot be achieved by forming depressions or recesses 15. If the channel area 14 protrudes or rises by more than 30 nm, the induction or release of the stress or mechanical strain in the element or component insulation areas 13 may saturate, with the mechanical strain acting on a lower part of the channel area 14; consequently, the stress or mechanical strain does not occur in the channel area 14.

[0021] As in the vertical section view of the Fig. 3 along line BB' from Fig. As shown in Figure 1, the effect and influence of the direct mechanical stress from the element or component isolation areas or regions 13 are suppressed in the channel area or region 14. This means that in the channel area or region 14, the stress or mechanical stress (indicated by arrows B) in a direction of stress or mechanical stress transmission (indicated by arrows A) in a part or region of the semiconductor substrate 11 occurs as the lower part or region of the channel area 14, with this part or region being directly influenced by the stress or mechanical stress from the element or component isolation areas or regions 13. The value or degree of protrusion or elevation of the channel area or region 14 can be adjusted by controlling the depth of the recesses or depressions 15.Furthermore, the area or surface of the source drain regions 27 and 28 is formed at the same level as the area or surface of the semiconductor substrate 11 in another region, as described above in the channel region 14. However, this is only one example.

[0022] It is known that an insulating layer (e.g., a high-density plasma silicon oxide or the like) which is formed hidden or buried to form the element or component insulation regions or areas 13 of the STI structure generally exhibits mechanical compression stress. The mechanical stress imposed in the direction of the gate width or width of the channel region 14 acts in a direction of weakening or deteriorating mobility or flexibility. With the construction of the embodiment of the present invention described above, the effect of the direct mechanical compression stress of the element or component insulation regions or areas 13 on the channel region 14 is suppressed.A mechanical tensile stress occurs in the channel region 14 in a direction of the release or induction of the mechanical compression stress in the part of the semiconductor substrate 11 that acts as the lower region of the channel region 14, this region being directly influenced by the mechanical compression stress of the element or component insulation regions 13. Consequently, in the direction of the gate width of the channel region 14, the mechanical tensile stress acts in a direction to improve the mobility of the transistor or the charge carriers of the transistor.

[0023] A gate electrode 22 is formed on the semiconductor substrate 11, with a gate insulating layer 21 provided between the gate electrode 22 and the semiconductor substrate 11. The gate electrode 22 is or is formed in such a way that it extends, for example, over the channel region 14 or the channel area 14 and the recesses or depressions 15. A layer with a high dielectric constant (high-k) can be used, for example, as the gate insulating layer 21. The layer made of a material with a high dielectric constant can be, for example, a nitrided hafnium silicate (HfSiON), a hafnium nitride or oxide or oxynitride, an aluminum nitride or oxide or oxynitride. Alternatively, an ordinary silicon oxide layer can also be used as the gate insulating layer 21. A single-layer structure of a metal or a metallic compound can be used, for example, as the gate electrode 22 for a metallic gate.A laminated structure is also conceivable. Furthermore, polysilicon can also be used as the material for the gate electrode 22. A silicon nitride layer, for example, can be used as the hard mask 53.

[0024] Offset spacers 23 are formed on the side walls of the gate electrode 22 (with the gate insulation layer 21). The offset spacers 23 are formed by means of a thin insulating layer of, for example, approximately 1 nm to approximately 10 nm. For example, an insulating layer with etch selectivity with respect to the element-device insulation regions or areas 13 can be used as the thin insulating layer. The thin insulating layer can, for example, be a silicon nitride (SiN) layer.

[0025] Extension regions 24 and 25 are formed in the semiconductor substrate 11 on both sides of the gate electrode 22, with offset spacers 23 positioned between the extension regions 24 and 25 and the gate electrode 22. The extension regions 24 and 25 may contain an n-type impurity, e.g., arsenic (As₂). + ), Phosphorus (P + ) or the like, when forming an NMOS transistor. However, a foreign material component or a p-type impurity can also be used, e.g., boron (B₂). + ), Indium (In + ) or the like, when a PMOS transistor is formed. The extension regions 24 and 25 are formed with a shallow junction.

[0026] Furthermore, the side wall spacers 26 are formed on both sides of the gate electrode 22 with offset spacers 23 between the side wall spacers 26 and the gate electrode 22. The source drain regions 27 and 28 are formed in the semiconductor substrate 11 on both sides of the gate electrode 22, with the extension regions 24 and 25 being provided between the source drain regions 27 and 28 and the gate electrode 22. Layers 31 and 32 for reducing the resistance are formed on the source drain regions 27 and 28. The resistance-reducing layers 31 and 32 are formed, for example, from cobalt (Co), nickel (Ni), platinum (Pt), or a compound of these elements. The compound can also, for example, include metal silicides of these metals. As in the vertical cross-sectional view of the Fig. 5 based on the in Fig. As shown in line DD in Figure 1, the source drain regions 27 and 28 are formed at a location that is lower than the area or surface of the portions of the element or component isolation regions 13 that are formed on both sides (direction of the gate width) of the source drain regions 27, 28. Consequently, the resistance-reducing layers 31 and 32 do not approach or come into contact with the semiconductor substrate 11, even when the resistance-reducing layers 31 and 32 (in Fig. 5 is the resistance-reducing layer 32 (not shown) formed by a salicidal or silicidal process, e.g. on the surfaces of the source drain areas 27 and 28 (in Fig. (5 is the source drain area 28 not shown). This prevents leakage current from the resistance-reducing layers 31 and 32 to the semiconductor substrate 11.

[0027] Furthermore, an insulating layer 41 is formed over the semiconductor substrate 11 such that it covers the semiconductor device 1 of the above-described assembly, which is formed on the semiconductor substrate 11. Moreover, although not shown in the figures, contact parts connected to the gate electrode 22 and to the source drain regions 27 and 28, as well as wiring connected to the respective contact regions, and the like, can be formed in the insulating layer 41.

[0028] The semiconductor device 1 with the above-described structure is advantageous in that it is possible to generate the stress or mechanical strain in the channel region 14 directly below the gate electrode 22 in a direction of the gate width or gate width in an advantageous manner with regard to the transistor characteristics (carrier or charge carrier mobility or mobility) and thus to improve the inrush current (ion) of the transistor in such a way that the performance and behavior of the transistor are improved.Additionally, no leakage current occurs between the resistance-reducing layers 31 and 32 and the semiconductor substrate 11 because the junction positions of the source drain regions 27 and 28 are located lower than the surfaces of the element or component insulation regions, even when the resistance-reducing layers 31 and 32 are formed from a silicide layer to achieve low resistance on the surfaces of the source drain regions 27 and 28. This improves the reliability of the semiconductor device 1 (transistor). The effects described above are further enhanced when the semiconductor device 1 (transistor) is designed with a reduced gate width.

[0029] As in the Fig. 10A and Fig. As shown in Figure 10B and described above, the improvement in the ion inrush current is greater the more stress or mechanical strain is initially applied to the channel region in the y-direction. A stronger effect can be achieved by applying mechanical strain or stress in the y-direction by forming the source drain regions as silicon germanium epitaxial layers or by providing a liner for compression stress in the case of a pMOSFET, or by applying stress or mechanical strain in the y-direction by forming the source drain regions as epitaxial silicon carbide layers or by providing a liner for tensile stress in the case of an nMOSFET.These structures and relationships will be described later in connection with a second embodiment and a third embodiment for a semiconductor device according to the present invention.

[0030] One embodiment (first embodiment) of a manufacturing process for a semiconductor device according to the present invention is described below with reference to the cross-sectional views for a manufacturing process according to the Fig. Sections 6A to 6P are described. This manufacturing process is cited as an example of a manufacturing process for the construction of a semiconductor device 1. Furthermore, the Fig. 6A, Fig. 6K, Fig. 6L and Fig. 6P cross-sections in the so-called gate width direction (cross-sections at a point that is aligned with the vertical section along line BB' in Fig. 1, as described above (corresponds). In the Fig. Sections 6B to 6J and 6M to 6O show sections in a so-called longitudinal direction of the gate (sections at a point that corresponds to the vertical section along line AA' in Fig. 1, as described above (corresponds).

[0031] As in Fig. As shown in Figure 6A, element or component isolation areas 13 are formed in a semiconductor substrate 11 for electrically isolating an element or component formation area or region 12 in which a transistor is formed. A silicon substrate can, for example, be provided as the semiconductor substrate 11. For the element or component isolation areas 13, for example, a conventional STI (Shallow Trench Isolation) structure can be provided.

[0032] The following section will explain how this is done in Fig. Figure 6B shows a protective layer (not shown) formed on the semiconductor substrate 11 to prevent channeling during ion implantation for the insertion of an impurity or foreign substance. This protective layer is formed, for example, by silicon dioxide (SiO2). A method for forming the protective layer can be based on an oxidation process with respect to the surface of the semiconductor substrate 11.

[0033] The contaminant or foreign material is then injected to perform transistor element isolation and threshold adjustment. This is done by ion implantation. After ion implantation, the previously formed silicon oxide layer (SiO2), which served as a protective layer for the ion implantation, is removed to expose the surface of the semiconductor substrate 11.

[0034] Subsequently, an insulating layer 51 for a dummy gate, a dummy gate 52 itself and a hard mask 53 are formed in this order on the semiconductor substrate 11.

[0035] The insulating layer 51 for the dummy gate is, for example, an oxide layer and is initially formed on the semiconductor substrate 11 with a thickness of approximately 1 nm to 3 nm. Then, for example, a layer for forming the dummy gate is subsequently formed on the insulating layer 51. This dummy gate layer can be formed, for example, by depositing a polycrystalline silicon layer (polysilicon), with a thickness of approximately 100 nm to 200 nm. A chemical vapor deposition (CVD) process can be used, for example, to form the dummy gate layer. Furthermore, a hard mask layer can be provided on the dummy gate layer by means of a silicon nitride layer. This silicon nitride layer can be, for example,with a layer thickness of approximately 30 nm to approximately 100 nm using, for example, a chemical vapor deposition (CVD) process.

[0036] For the lithography process, a resist layer (not shown) can be formed on the hard mask layer. A resist suitable for use with a specific exposure source is used for the resist layer. The resist layer is then exposed to light to form a dummy gate array (not shown). Subsequently, the dummy gate array is used as the etch mask. The hard mask layer is etched to form the hard mask 53. Optical lithography using, for example, KrF, ArF, F2, or the like as a light source, or electron beam lithography, is used for exposure in the lithography process described above. When etching the hard mask layer, the hard mask layer can be used with a line thickness smaller than that of the resist array (e.g., by slimming and trimming) to reduce the gate length.The dummy gate arrangement or template formed by the resist layer is then removed. Using the hard mask 53, formed by the etching process, as a hard mask, the layer is dry-etched to form the dummy gate 52. The line width or thickness of the dummy gate 52 is set at this point to a value in the range of a few nm to several tens of nm. During this etching process, the insulating layer 51 for the dummy gate is also etched.

[0037] The following will then explain how this is done in Fig. As shown in Figure 6C, offset spacers 23 are formed on the side walls of the dummy gate 52 (the portion formed by the dummy gate's insulating layer 51, the dummy gate 52 itself, and the hard mask 53 is hereinafter referred to as the dummy gate). The offset spacers 23 are formed, for example, by forming a thin insulating layer of approximately 1 nm to approximately 10 nm to cover the dummy gate 52 and subsequently etching back this thin insulating layer so that it remains only on the side walls of the dummy gate 52. The thin insulating layer forming the offset spacers 23 is made, for example, of silicon dioxide (SiO2) or silicon nitride (SiN). The thin insulating layer on the semiconductor substrate 11 is removed by the etching process described above.The extension regions 24 and 25 are subsequently formed in the semiconductor substrate 11 on both sides of the dummy gate 52, with offset spacers 23 being provided and formed between the extension regions 24 and 25 and the dummy gate 52. The extension regions 24 and 25 can be formed, for example, by ion implantation. An impurity or foreign substance of the n-type, e.g., arsenic (As. + ), Phosphorus (P + ) or the like when forming an NMOS transistor. On the other hand, p-type impurities or foreign matter such as boron (B) can be used. + ), Indium (In + ) or the like are used when a PMOS transistor is exposed to energy (100 eV to 300 eV) and a dose of 5 × 10 14 ( / cm 2 ) to 2 × 10 15 ( / cm 2) are carried out, whereby the extension areas 24 and 25 are formed with a flat or near-surface transition. Subsequently, as described in Fig. As shown in Figure 6D, wall spacers 26 are formed on both sides of the dummy gate 52, with offset spacers 23 being formed between the side wall spacers 26 and the dummy gate 52. At the time of back-etching to form the side wall spacers 26, the etching process is carried out in such a way that the hard mask 53 remains.

[0038] The following will then explain how this is done in Fig. As shown in Figure 6E, the source drain regions 27 and 28 are formed in the semiconductor substrate 11 on both sides of the dummy gate 52, with the expansion regions 24 and 25 being formed between the source drain regions 27 and 28 and the dummy gate 52. Subsequently, an activation process is carried out by rapid thermal annealing (RTA) at a temperature of, for example, 1000°C.

[0039] When a PMOS transistor and an NMOS transistor are formed on the semiconductor substrate 11, the foreign substance injection to adjust the transistor threshold, the ion implantation to form the expansion or extension regions 24 and 25, and the ion implantation to form the source drain regions 27 and 28 are performed separately for the NMOS region and for the PMOS region. For example, a first mask is formed in the NMOS region. Ion implantation is performed in the PMOS region. Then the first mask is removed. Then the second mask is formed in the PMOS region, and ion implantation is performed with respect to the NMOS region. The second mask is then subsequently removed.

[0040] The following explains how this is done in Fig. As shown in Figure 6F, multiple layers 31 and 32 are formed on the source drain regions 27 and 28 to reduce resistance. These layers are selectively formed on the surfaces of the source drain regions 27 and 28 by means of a salicidal or silicidal process. The layers can be formed, for example, from cobalt (Co), nickel (Ni), platinum (Pt), or a compound of these elements. The compound indicates metal silicides of these metals.

[0041] As in Fig. As shown in 6G, a first insulating intermediate layer 42 is formed, which covers or covers the dummy gate 52 and the like.

[0042] As in Fig. As shown in Figure 6H, an upper portion of the first insulating intermediate layer 42 is subsequently removed to expose the surface of the hard mask 53. For example, a chemical-mechanical polishing (CMP) process is used to remove the upper portion of the first insulating intermediate layer 52. Alternatively, any other polishing process can be used. The upper portion of the first insulating intermediate layer 42 can also be removed by a back-etching process. Furthermore, chemical-mechanical polishing can also help to planarize the polished surface.

[0043] Subsequently, the hard mask 53 and the dummy gate 52 are removed. Damage to the semiconductor substrate 11 during dry etching can be prevented by retaining the insulating layer 51 for the dummy gate during steam dry etching. The insulating layer 51 for the dummy gate is then removed. A wet etching process can also be used for the removal process. Etching damage to the semiconductor substrate 11 is prevented by performing the removal process using a wet etching process. As a result, as shown in Fig. As shown in Figure 6I, a recess 59 is formed, which is enclosed by the offset spacers 23. As shown in the cross-sectional view of the Fig. Since 6K is shown in one direction of the gate width or gate width, the channel region 14, which is formed in the semiconductor substrate 11 directly below the region in which the dummy gate 52 is provided, is formed at substantially the same height as the area or surface of the element or component insulation regions or areas 13. The stress or mechanical strain of the element or component insulation regions or areas 13 is imposed on the channel region 14. Consequently, the channel region 14 is directly influenced by the stress or mechanical strain of the element or component insulation regions or areas 13.

[0044] As shown in the cross-sectional view of the Fig. If the 6L is shown in one direction of the gate width or gate width, the wet etching process described above can lower the faces or surfaces of the element or device isolation regions or areas 13 below the region or area where the dummy gate 52 was formed by creating the recesses or depressions 15. This allows the height of the element or device isolation regions or areas 13 below the area where the dummy gate 52 was formed to be lower than the surface of the semiconductor substrate 11 (channel region or channel area 14). The height of the element or device isolation regions or areas 13 can be controlled by the thickness or degree of wet etching. The degree of protrusion or raising of the channel region or channel area 14 from the faces or surfaces of the element or device isolation regions or areas 13 corresponds to a height of, for example, about 3 nm to about 30 nm.The wet-setting process described above does not reduce the height of the element or component isolation regions or areas 13 on either side of the source drain regions or areas 27 or 28 (in one direction of the gate width or gate width) on either side. Additionally, the source drain regions or areas 27 and 28 can be kept at substantially the same height as the semiconductor substrate 11 by means of the channel region or channel area 14 described above, e.g., in a different region thereof.

[0045] The following describes how it is in Fig. As shown in Figure 6J, a gate insulation layer 21 is formed on the semiconductor substrate 11 within the recess 29. The gate insulation layer 21 is actually formed on the inner surfaces of the recesses 20 and the surface of the first insulating intermediate layer 42. The gate insulation layer can be formed, for example, from an insulating layer consisting of a high-k dielectric constant or a silicon oxide layer. In this case, the gate insulation layer 21 is formed, for example, from a high-k dielectric constant. In this case, a heat treatment (annealing treatment) is performed to modify the gate insulation layer 21.

[0046] Then, as is done in Fig. Figure 6M shows a layer 61 for forming the gate electrode on the gate insulation layer 21 such that the interior of the recess 29 is filled. The layer 61 for forming the gate electrode can be formed, for example, by laminating metals or metallic compounds to produce a metal gate or a single-layer structure.

[0047] As in Fig. As shown in Figure 6N, an excess portion of layer 61 is subsequently removed to form the gate electrode. The gate electrode 22 is thus formed from layer 61 on the semiconductor substrate 11 within the recess 29, with the gate insulation layer 21 positioned between the gate electrode 22 and the semiconductor substrate 11. The removal process is carried out, for example, by chemical-mechanical polishing (CMP).

[0048] In Fig. Figure 6O shows that a second insulating layer 42 is formed on the first insulating layer 42 such that the gate electrode 22 is covered or obscured. The first insulating layer 42 and the second insulating layer 43 form an insulating layer 41. In the sectional view of the Fig. Figure 6P shows that at this time in one direction of the gate width or gate span, a stress or mechanical strain is maintained or becomes in a stress state in the channel area or channel region 14, which occurs when the upper regions of the element or component insulation regions or regions 13 are below the region where the dummy gate 52 is located in the manner described above with reference to the Fig. 6L was produced, removed, or were removed.

[0049] Although not shown, contact areas are subsequently electrically connected to the respective source drain areas 27 and 28, metallic connections which are routed to the contact parts, and the like, within the insulating intermediate layer 41. This completes the semiconductor device.

[0050] The method for manufacturing a semiconductor device according to this first embodiment is advantageous insofar as it makes it possible to generate a stress or mechanical strain in the channel region 14 directly below the gate electrode 22 in a direction of the gate width or gate width, advantageously influencing the transistor properties (carrier or charge carrier mobility or mobility) and thereby improving the inrush current Ion of the transistor, so that the performance and behavior of the transistor are improved.Since the junction positions of the source drain regions 27 and 28 are lower than the surfaces of the element or component insulation regions 13, even when resistance-reducing layers 31 and 32, formed by a resistance-reducing silicide layer, are present or are formed on the surfaces of the source drain regions 27 and 28, no leakage current occurs between the resistance-reducing layers 31 and 32 and the semiconductor substrate 11. This improves the reliability of the semiconductor device 1 (transistor). The effects and influences described above are enhanced if the gate width of the semiconductor device 1 (transistor) is reduced.

[0051] An embodiment (second embodiment) of a semiconductor device according to the present invention is described below with reference to the schematic sectional views regarding the structures in relation to the Fig. 7A and Fig. 7B described. Fig. 7A shows a section in the direction of the gate length. Fig. 7B shows a section in the direction of the gate width or gate width. The in the Fig. 7A and Fig. The semiconductor device 2 shown in Figure 7B is designed using a stress imprinting layer to impose a mechanical stress or strain on the channel area 14, as in the source drain areas 27 and 28 of the semiconductor device 1 from the first embodiment.

[0052] As in the Fig. 7A and Fig. As shown in Figure 7B, element or component isolation regions or areas 13 are formed in a semiconductor substrate 11 for electrical isolation of an element or component formation region or area 12 in which a transistor is or is formed. For example, a silicon substrate is used as the semiconductor substrate 11. For example, a conventional STI (Shallow Trench Isolation) structure is used as the element or component isolation regions 13. Consequently, a portion of the semiconductor substrate 11, namely the portion formed between the element or component isolation regions or areas (not shown), constitutes the element or component formation region 12.

[0053] In upper areas or parts of the element or component insulation areas or regions 13, which are formed on both sides of a channel area 14, which in turn is formed in the element or component formation area or region 12, recesses or depressions 15 are formed such that the channel area 14 rises from or projects from the surfaces of the element or component insulation areas or regions 13. Thus, the recesses or depressions 15 in the element or component insulation areas or regions 13 on both sides of the channel area 14 are formed such that only the channel area 14 projects from the element or component insulation areas or regions 13.In this case, as in the first embodiment, the degree of protrusion or elevation of the channel area 14 from the surfaces of the element or component insulation areas 13 at the bottom of the recesses or depressions 15 is set to a value in the range of approximately 3 nm to approximately 30 nm. This suppresses the effects of direct stress or mechanical strain from the element or component insulation areas 13 in the channel area 14.This means that in the channel region 14 a stress or mechanical strain (indicated by arrows B) occurs in a direction of the transfer or induction of the stress or mechanical strain (indicated by arrows A) in a part or area of ​​the semiconductor substrate 11 as the lower part of the channel region or channel area 14, wherein this part or area is directly influenced by the stress or mechanical strain of the element or device insulation areas or regions 13. The degree of protrusion of the channel region 14 can be adjusted by controlling the depth of the recesses or depressions 15.

[0054] A gate electrode 22 is formed on the semiconductor substrate 11, with a gate insulating layer 21 provided between the gate electrode 22 and the semiconductor substrate 11. The gate electrode 22 is configured to extend over the channel region 14 and the recesses or depressions 15. This is just one example. For instance, a layer with a high dielectric constant (high-k) can be used as the gate insulating layer 21. However, an ordinary silicon oxide layer can also be used. For example, a single-layer structure of a metal or metallic compound can be used as the gate electrode 22. However, a laminated structure can also be used. Furthermore, polysilicon can also be used as the material for the gate electrode 22. For example, a silicon nitride layer can be used as the hard mask 53.

[0055] So-called offset spacers 23 are provided on the side walls of the gate electrode 22 (with the gate insulating layer 21). The offset spacers 23 can be formed, for example, in a thin insulating layer with a thickness in the range of approximately 1 nm to approximately 10 nm. For example, an insulating layer with etch selectivity with respect to the element-device insulation regions or areas 13 can be used as the thin insulating layer. For example, a silicon nitride (SiN) layer can be used as the thin insulating layer.

[0056] Expansion regions or extension regions 24 and 25 are provided in the semiconductor substrate 11 on both sides of the gate electrode 22, with offset spacers 23 arranged between the expansion regions 24 and 25 and the gate electrode 22. For the expansion regions 24 and 25, for example, an impurity or foreign substance of the n-type, e.g., in the form of arsenic (As₂), can be provided. + ), Phosphorus (P +) or the like may be provided when forming an NMOS transistor. On the other hand, an impurity or foreign substance of the p-type, e.g. in the form of boron (B), may be present. + ), Indium (In + ) or the like may be provided when a PMOS transistor is formed. The extension regions 24 and 25 may be configured with a shallow junction.

[0057] Furthermore, sidewall spacers or sidewall spacing elements 26 are formed on both sides of the gate electrode 22, with offset spacers 23 being arranged between the sidewall spacers 26 and the gate electrode 22. Source drain regions 27 and 28 are formed in the semiconductor substrate 11 on both sides of the gate electrode 22, with extension regions 24 and 25 arranged between the source drain regions 27 and 28 and the gate electrode 22. The source drain regions 27 and 28 are formed by forming a stress-applying layer to impose a stress or mechanical stress on the channel region 14 between the source drain regions 27 and 28. For example, if...If the semiconductor device 2 is a p-type FET (field-effect transistor), the source drain regions 27 and 28 are formed by a silicon germanium layer that is or is grown epitaxially, imposing a compression stress on the channel region or channel area 14. If the semiconductor device 2 is, for example, an n-type FET (field-effect transistor), the source drain regions 27 and 28 can be formed by a silicon carbide layer grown epitaxially, which imposes a tensile stress on the channel region or channel area 14. In either case, it is effective to form the source drain regions 27 and 28 in an embedded source-drain structure that is raised from the area or surface of the semiconductor substrate 11. The layers 31 and 32 for lowering the resistance are or are formed on the source drain regions 27 and 28.Layers 31 and 32, used to reduce resistance, can consist of, for example, cobalt (Co), nickel (Ni), platinum (Pt), or their compounds. The compound can also be a metal silicide of these metals.

[0058] The source drain regions 27 and 28 are formed at a location lower than the surface area of ​​the element or component isolation regions 13 on both sides (in the direction of the gate width) of the source drain regions 27 and 28. Even when the resistance-reducing layers 31 and 32 are formed during a salicidal or silicidal process on the surfaces of the source drain regions 27 and 28, the resistance-reducing layers 21, 31, and 32 do not come close to or into contact with the semiconductor substrate 11. This prevents leakage currents from the resistance-reducing layers 31 and 32 to the semiconductor substrate 11.

[0059] Furthermore, an intermediate insulating layer 41 is formed over the semiconductor substrate 11 such that the semiconductor device 2 with the structure described above, which is formed in the semiconductor substrate, is covered or concealed. Moreover, although not explicitly shown in the figures, contact areas connected to the gate electrode 22 and to the source drain areas 27 and 28, wiring connections to each of the contact areas, and the like are formed in the intermediate insulating layer 41.

[0060] Semiconductor device 2 has similar properties and effects to semiconductor device 1. In a similar manner, a stress or mechanical strain is imposed from the source drain regions 27 and 28 onto the channel region 14 to improve mobility or movement. Semiconductor device 2 can therefore exhibit a greater degree of mobility or movement compared to semiconductor device 1.

[0061] An embodiment (third embodiment) of a semiconductor device according to the present invention is described below with reference to the schematic cross-sectional views relating to the structure. Fig. 8A and Fig. 8B described. Fig. Figure 8A shows a section in one direction of the gate length. Fig. Figure 8B shows a section in the direction of the gate width or gate width. The semiconductor device 3, which is located in the Fig. 8A and Fig. 8B is obtained by forming a stress liner layer to impose a stress or mechanical tension on the channel area or channel region 14 of the semiconductor device 1 according to the first embodiment.

[0062] This means, in particular, as shown in the Fig. 8A and Fig. Figure 8B shows that the element or component isolation regions or areas 13 are formed in a semiconductor substrate 11 for electrically isolating an element or component formation region or area 12 in which a transistor is formed. For example, a silicon substrate can be used as the semiconductor substrate 11. For example, a conventional STI (Shallow Trench Isolation) structure can be used for the element or component isolation regions or areas 13. Consequently, a portion of the semiconductor substrate provided between the element or component isolation regions or areas (not shown) forms the element or component formation region 12.

[0063] Recesses or depressions 15 are provided in the upper areas or parts of the element or component insulation areas or regions 13 on both sides of a channel area or channel section 14, which is formed in the element or component formation area or region 12, such that the channel area 14 projects beyond the surfaces of the element or component insulation areas or regions 13. Thus, the recesses or depressions 15 in the element or component insulation areas or regions 13 on both sides of the channel area or channel section 14 are designed such that only the channel area 14 rises above the element or component insulation areas or regions 13.In this case, as in the first embodiment, the degree of elevation of the channel area 14 from the surfaces of the element or component insulation areas 13 at the bottom of the recesses or depressions 15 is set to a value in the range of, for example, approximately 3 nm to approximately 30 nm. This allows the effects of direct stress or direct mechanical strain from the element or component insulation areas 13 in the channel area 14 to be suppressed.This means that in the channel region or channel area 14, a stress or mechanical strain (indicated by arrows B) occurs in a direction of the release or induction of the stress or mechanical strain (indicated by arrows A) in a part or area of ​​the semiconductor substrate 11 as the lower area or part of the channel region or channel area 14, which is directly influenced by the stress or mechanical strain of the element or device insulation areas or areas 13. The degree of elevation of the channel region 14 can be adjusted by controlling the depth of the recesses or depressions 15.

[0064] A gate electrode 22 is provided on the semiconductor substrate 11, with a gate insulating layer 21 positioned between the gate electrode 22 and the semiconductor substrate 11. The gate electrode 22 is configured, for example, to extend over the channel region 14 and the recesses or depressions 15. A layer with a high dielectric constant (high-k) can be used as the gate insulating layer 21. The use of an ordinary silicon oxide layer is also conceivable. A single-layer structure of a metal or metallic compound can be used for a metallic gate, or a laminated structure can be used as the gate electrode 22. Polysilicon can also be used as the material for the gate electrode 22. A silicon nitride layer can be used as the hard mask 53, for example.

[0065] Offset spacers 23 are formed on the side walls of the gate electrode 22 (with the gate insulation layer 21). The offset spacers 23 are formed, for example, by a thin insulating layer with a thickness in the range of approximately 1 nm to approximately 10 nm. For example, an insulating layer that possesses etch selectivity with respect to the element or component insulation regions 13 can be used as the thin insulating layer. For instance, it is conceivable to use a layer of silicon nitride (SiN) as the thin insulating layer.

[0066] Expansion or extension regions 24 and 25 are formed in the semiconductor substrate 11 on both sides of the gate electrode 22, wherein the offset spacers 23 are arranged between the expansion regions 24 and 25 and the gate electrode 22. An impurity or foreign substance of n-type, e.g., in the form of arsenic (As₂), can be present in the expansion regions 24 and 25. + ), Phosphorus (P + ) or the like when forming an NMOS transistor. On the other hand, for example, an impurity or foreign substance of the p-type, e.g. in the form of boron (B) can be used. + ), Indium (In + ) or the like are used when forming a PMOS transistor. The extension regions 24 and 25 are formed with a shallow junction.

[0067] Furthermore, sidewall spacers 26 are formed on both sides of the gate electrode 22, with offset spacers 23 being or being arranged between the sidewall spacers 26 and the gate electrode 22. Source drain regions 27 and 28 are formed in the semiconductor substrate 11 on both sides of the gate electrode 22, with extension regions 24 and 25 being or being arranged between the source drain regions 27 and 28 and the gate electrode 22. The resistance-reducing layers 31 and 32 can be formed, for example, of cobalt (Co), nickel (Ni), platinum (Pt), or their compounds. The compounds can also be metal silicides of these metals.

[0068] The source drain regions 27 and 28 are formed at a location lower than the surface area of ​​the parts or regions of the element or component isolation areas 13 that are formed on both sides (in one direction of the gate width) of the source drain regions 27 and 28. Even if the resistance-reducing layers 31 and 32 are formed on the surfaces of the source drain regions 27 and 28, for example by means of a salicide or silicide process, the resistance-reducing layers 31 and 32 do not come close to or into contact with the semiconductor substrate 11. This prevents leakage currents from the resistance-reducing layers 31 and 32 to the substrate 11.

[0069] Furthermore, a stress liner film 71 is formed to impose a stress or mechanical stress on the channel region 14 such that it covers or overlies the semiconductor device 3 with the structure described above, which is formed in the semiconductor substrate 11. This stress liner film 71 is formed, for example, by a silicon nitride layer and can be produced, for example, using a plasma-CVD process. By changing the conditions during the formation of the layer, it is possible to produce a silicon nitride layer that has a tensile stress or a silicon nitride layer that replaces a compressive stress. If the semiconductor device 3, for example,If the semiconductor device 3 is a p-type FET (field-effect transistor), a compression stress liner layer is used as the stress liner layer 71 to apply a compression stress to the channel region 14. If the semiconductor device 3 is a p-type FET (field-effect transistor), a tension stress liner layer is used as the stress liner layer 71 to apply a tension stress to the channel region 14.

[0070] Furthermore, an insulating intermediate layer 41 is formed. Moreover, although not explicitly shown in the figures, contact areas or regions connected to the gate electrode 22 and the source drain regions 27 and 28, wiring connected to each of the contact areas or regions, and the like are formed in the insulating intermediate layer 41.

[0071] To manufacture the semiconductor device 3, in the manufacturing process according to the first embodiment, the gate electrode 22 is formed on the gate insulation layer 21 within the recesses 29. The first intermediate insulation layer 42 is then removed. Next, the stress-suppressing or stress-lining layer 71 is formed to cover the gate electrode 22 and the sidewall spacers 26. The first intermediate insulation layer 42 is then formed again. Finally, the second intermediate insulation layer 43 is formed. It is desirable to planarize the surface of the first intermediate insulation layer 42 formed in this way.

[0072] Semiconductor device 3 has the same properties and effects as semiconductor device 1, wherein the stress or mechanical strain is effectively applied to improve mobility or movement, likewise from the stress or strain lining layer or liner layer 71 to the channel region or channel area 14. Therefore, in semiconductor device 3, the mobility or movement is even more improved than in semiconductor device 1.

[0073] Additionally, a stress-discharge lining layer or liner layer 71, similar to the stress-discharge lining layer or liner layer 71 in connection with the semiconductor device 3 according to the third embodiment, is used to further develop the semiconductor device 2 according to the second embodiment. In other words, this means that the source drain regions 27 and 28, formed by the stress-discharge layer similar to the stress-discharge layer in connection with the semiconductor device 2 according to the second embodiment, can be used in the semiconductor device 3 according to the third embodiment.

[0074] An embodiment (second embodiment) of a manufacturing process for a semiconductor device according to the present invention is now described with reference to the sectional views of a manufacturing process according to the Fig. Sections 9A to 9O describe this manufacturing process. This process is described as a method for manufacturing the assembly of semiconductor device 2.

[0075] As above with reference to Fig. As described in Section 6A, element or component isolation regions or areas (not shown) are formed in a semiconductor substrate 11 for electrical isolation of an element or component formation region or area 12 in which a transistor is formed. For example, a silicon substrate is used as the semiconductor substrate 11. For example, a conventional STI (Shallow Trench Isolation) structure can be used for the element or component isolation regions or areas 13.

[0076] As in Fig. As shown in Figure 9A, a protective layer (not shown) is formed on the semiconductor substrate 11 to prevent channeling when ion implantation is performed to introduce an impurity or foreign substance into the semiconductor substrate 11. This protective layer can be formed, for example, by a silicon oxide layer (SiO2). An oxidation process of the surface of the semiconductor substrate 11 can also be cited as an example of a method for forming the protective layer.

[0077] Subsequently, an impurity or foreign substance is injected to isolate the transistor element and adjust the threshold value via ion implantation. After ion implantation, the silicon oxide layer (SiO2) previously formed as an ion implantation protection layer is removed to expose the surface of the semiconductor substrate 11.

[0078] Subsequently, an insulation layer 51 for a dummy gate, a dummy gate 52 itself, and a hard mask 53 are formed in this order on the semiconductor substrate 11.

[0079] For example, the insulating layer 51 for the dummy gate can first be formed on the semiconductor substrate 11 in the form of an oxide layer with a thickness of approximately 1 nm to 3 nm. Then, a layer for forming the dummy gate is subsequently formed on the insulating layer 51. This dummy gate layer can be formed, for example, by depositing a polycrystalline silicon layer (polysilicon) with a thickness of approximately 100 nm to 200 nm. A chemical vapor deposition (CVD) process can be used, for example, to form the dummy gate layer. Furthermore, a hard mask layer, for example, in the form of a silicon nitride layer, can be formed on the dummy gate layer. This silicon nitride layer can be, for example,with a layer thickness in the range of approximately 30 nm to approximately 100 nm, for example using a chemical vapor deposition (CVD) process.

[0080] Subsequently, a resist layer (not shown) is formed on the hard mask layer for a lithography process. A resist suitable for exposure to an exposure source is used for the resist layer. The resist layer is then exposed to light to form a dummy gate structure (not shown). The dummy gate structure is then used as the etching mask. The hard mask layer is then etched to form the hard mask 53. Optical lithography techniques using, for example, KrF, ArF, F2, or the like for light source or electron beam lithography are employed for the exposure of the lithography processes described above. During the etching of the hard mask, the hard mask layer can be processed or treated with a line thickness or line width that is less than that of the resist arrangement (e.g.,The length of the gate is reduced by thinning and trimming. Subsequently, the dummy gate structure formed by the resist layer is removed. This is done by using the hard mask 53, formed by the etching process, as an etching mask. The layer forming the dummy gate is processed by a dry etching operation to create the dummy gate 52. The line width or thickness of the dummy gate 52 is set at this point, for example, in the range of a few nm to several tens of nm. During this etching process, the insulating layer 51 for the dummy gate is also etched.

[0081] Then, as is done in the Fig. As shown in Figure 9B, so-called offset spacers 53 are formed on the side walls of the dummy gate 52 (a part or area formed by the insulating layer 51 for the dummy gate, the dummy gate 52 itself, and the hard mask 53 is hereinafter referred to as the dummy gate). The offset spacers 23 can, for example, be formed from a thin insulating layer with a thickness, for example, in the range of about 1 nm to about 10 nm, to cover or enclose the dummy gate 52. Subsequent etching of the thin insulating layer then takes place, such that the thin insulating layer remains only on the side walls of the dummy gate 52. The thin insulating layer forming the offset spacers 53 is, for example, made of silicon oxide (SiO2) or silicon nitride (SiN). The thin insulating layer on the semiconductor substrate 11 is removed by means of the etching process described above.

[0082] As in Fig. As shown in Figure 9C, the dummy sidewalls 55 are formed on both sides of the dummy gate 52, with offset spacers provided between the dummy sidewalls 55 and the dummy gate 52. At the time of back-etching to form the dummy sidewalls 55, an etching process is carried out such that the hard mask 53 remains.

[0083] As in Fig. As shown in Figure 9D, the recesses or depressions 33 and 34 for the source drain areas 27 and 28 are subsequently formed in the semiconductor substrate 11 on both sides of the dummy gate 52. Then an activation process takes place, namely a rapid thermal annealing process (RTA), e.g., at a temperature of approximately 1000°C.

[0084] How that in Fig. As shown in Figure 9E, the source drain regions 27 and 28 are formed by growing a stress or strain imprint layer in the recesses or depressions 33 and 34 using an epitaxial growth process. If the semiconductor device 2 is, for example, a p-type FET (field-effect transistor), the source drain regions 27 and 28 are formed by a silicon-germanium layer grown using an epitaxial growth process, which then imposes a compression stress on the channel region or channel area 14. As an example of the conditions for forming the layer, a processing temperature (substrate temperature) in the range of approximately 650°C to approximately 750°C at a growth atmosphere pressure in the range of approximately 6.7 kPa to approximately 13.3 kPa is mentioned. For example,Dichlorosilane (SiCl₂H; DCS) is used as the silicon raw material gas, and germanium hydride (GeH₄, germane) is used as the germanium raw material gas. If the semiconductor device 2 is an n-type field-effect transistor (FET), the source drain regions 27 and 28 are formed by a silicon carbide layer grown by an epitaxial growth process, imposing a mechanical tensile stress on the channel region 14. In either case, it is effective to form the source drain regions 27 and 28 in an embedded source drain structure raised from the surface of the semiconductor substrate 11.

[0085] Then the dummy sidewalls 55 are removed to expose the semiconductor substrate 11 between the dummy gate 52 and the source drain areas 27 and 28, as shown in the Fig. 9F is shown.

[0086] As in Fig. As shown in Figure 9G, the expansion regions 24 and 25 are formed in the semiconductor substrate 11 on both sides of the dummy gate 52, with offset spacers 53 forming between the expansion regions 24 and 25 and the dummy gate 52. The expansion regions 24 and 25 can be formed, for example, by ion implantation. An impurity or foreign substance of the n-type, e.g., in the form of arsenic (As*) or phosphorus (P), can be implanted. + ) or the like, can be used when forming an NMOS transistor. On the other hand, an impurity or foreign substance of the p-type, e.g. boron (B₂), can be used. + ), Indium (In + ) or the like, can be used when forming a PMOS transistor. For example, implantation can be performed with a low acceleration energy (100 eV to 300 eV) and with a dose, e.g., in the range of 5 × 10 14 ( / cm 2 ) to 2 × 10 15 ( / cm2 ), wherein the extension regions 24 and 25 are formed with a shallow junction. Thus, the source drain regions 27 and 28 are formed in the semiconductor substrate 11 on both sides of the dummy gate 52, with the extension regions 24 and 25 being formed between the dummy gate 52 and the source drain regions 27 and 28.

[0087] As in Fig. As shown in Figure 9H, the side wall spacers or side wall spacing elements 26 are then formed on both sides of the dummy gate 52, with the offset spacers 23 being formed between the side wall spacers 26 and the dummy gate 52. At this point, the side wall spacers 26 cover the areas or surfaces of the extension regions 24 and 25. When back-etching to form the side wall spacers 26, the etching is carried out in such a way that the hard mask 53 remains.

[0088] Layers 31 and 32 are then formed on source drain areas 27 and 28 to reduce resistance. These resistance-reducing layers are selectively formed on the surfaces of source drain areas 27 and 28 using a salicidal or silicidal process. The resistance-reducing layers 31 and 32 can be formed, for example, from cobalt (Co), nickel (Ni), platinum (Pt), or their compounds. Metal salicids of these compounds can also be used.

[0089] With reference to the Fig. Figure 9I shows that a first insulating intermediate layer 42 is subsequently formed, which covers or covers the dummy gate 52, the side wall spacers 56, the layers 31 and 32 for lowering the resistance and the like.

[0090] The Fig. Figure 9J shows that an upper portion of the first insulating layer 42 is subsequently removed to expose the surface of the hard mask 53. For example, a chemical-mechanical polishing (CMP) process can be used to remove the upper portion or part of the first insulating layer 42. Alternatively, any other polishing method can be used. The upper portion or area of ​​the first insulating layer 42 can also be removed by a back-etching process. Furthermore, the polished surface can also be planarized by chemical-mechanical polishing.

[0091] Then the hard mask 53 and the dummy gate 52 are removed. A dry etching process can be used for this removal. Damage to the semiconductor substrate 11 caused by dry etching can be prevented by leaving the insulating layer 51 for the dummy gate in place during dry etching. The insulating layer 51 for the dummy gate is then removed. A wet etching process can also be used to perform the removal. Damage to the semiconductor substrate 11 caused by etching can be prevented by performing the removal operations using wet etching. As a result of these operations, as shown in Fig. As shown in the 9K section, a recess 29 is formed, which is enclosed by offset spacers 23. As shown in the cross-sectional view of the Fig. As 6K is shown in the direction of the gate width, the channel region 14 in the semiconductor substrate 11 is formed directly below the region in which the dummy gate 52 is provided, essentially at the same level as the surfaces of the element or component insulation regions 13. The stress or mechanical strain of the element or component insulation regions 13 is imposed on the channel region 14. Thus, the channel region 14 is directly influenced by the stress or mechanical strain of the element or component insulation regions 13.

[0092] As shown in the cross-sectional view of the Fig. As 6L is shown in the direction of the gate width, the wet-setting process described above can lower the areas or surfaces of the element or device isolation regions or areas 13 below the region in which the dummy gate 52 was formed by creating recesses 15. This makes the height of the element or device isolation regions 13 below the region in which the dummy gate is formed lower than that of the area or surface of the semiconductor substrate 11 (channel region or channel area 14). The height of the element or device isolation regions or areas 13 can be controlled by the degree or intensity of the wet-setting. The degree of protrusion of the channel region or channel area 14 with respect to the areas or surfaces of the element or device isolation regions or areas 13 is, for example, a value of approximately 3 nm to approximately 30 nm.The wet setting process described above does not lower the height of the element or component isolation regions or areas 13 on either side (in one direction of the gate width or gate width) of the source drain regions 27 and 28. Additionally, the source drain regions 27 and 28 can be kept at essentially the same height as the semiconductor substrate 11 in another region by means of the channel region or channel area 14 described above.

[0093] As in the Fig. As shown in Figure 9L, a gate insulation layer 21 is then formed on the semiconductor substrate 11 in the recess 29. The gate insulation layer 21 is actually formed on the inner surfaces of the recess 29 and on the surface of the first insulating intermediate layer 42. The gate insulation layer 21 can be formed, for example, by an insulating layer, such as a layer with a high dielectric constant (high-k) or, for example, by a silicon oxide layer. In this case, the gate insulation layer 21 is formed by a layer with a high dielectric constant as an example. In this case, a heat treatment (annealing treatment) is performed to modify the gate insulation layer 21.

[0094] As in Fig. As shown in Figure 9M, a layer 61 for forming the gate electrode is then formed on the gate insulation layer 21 such that the interior of the recess 29 is filled. This layer 61 for forming the gate electrode is formed by laminating metals or metallic compounds for a metallic gate or by means of a single-layer structure.

[0095] As in connection with the Fig. As shown in Figure 9N, the superfluous part or portion of layer 61 is removed to form the gate electrode. This creates an electrode 22 within the recess 29 from layer 61, forming the gate electrode on the semiconductor substrate 11, with the gate insulation layer 21 positioned between the gate electrode 22 and the semiconductor substrate 11. The removal process can be carried out, for example, using a chemical-mechanical polishing (CMP) method.

[0096] As in connection with the Fig. As shown in Figure 9O, a second insulating layer 43 is formed on top of the first insulating layer 42 such that the gate electrode 22 is covered or concealed. The first insulating layer 42 and the second insulating layer 43 form an insulating layer 41. The stress or mechanical tension in the channel region 14 is maintained at this time in a stress or tension state that occurs when the upper regions or portions of the element or component insulation regions 13 are located below the area where the dummy gate 52 has been formed (see Figure 9O). Fig. 9J and the above description) will be removed.

[0097] Although not shown, contact areas electrically connected to the respective source drain areas 27 and 28, metallic wiring connected to the contact areas, and the like are subsequently formed in the insulating intermediate layer 41. This completes the semiconductor device.

[0098] The manufacturing process for a semiconductor device described above achieves similar results and effects to those of the first embodiment for a semiconductor device manufacturing process. A stress or mechanical strain is effectively imposed on the channel area 14 from the source drain regions 27 and 28 to improve mobility or movement. Semiconductor device 2 therefore improves mobility or movement more than a semiconductor device manufactured using a semiconductor device manufacturing process according to the first embodiment.

[0099] It is further noted that in each of the embodiments described above, a layer exhibiting stress or mechanical tension can be used as the gate electrode 22. For example, in the case of an n-type MOSFET (field-effect transistor), hafnium, hafnium silicides, tantalum, tantalum silicides, or the like can be used to impart a tensile stress in a longitudinal direction to the channel region 14. In the case of a p-type MOSFET (field-effect transistor), titanium, titanium nitride, ruthenium, tungsten, or the like can be used to impart a compression stress to the channel region 14. The use of such layers can further improve mobility or flexibility.

Claims

[1] Semiconductor device (1, 2) comprising: a semiconductor substrate (11) with a component formation area (12); Element or component insulation regions or areas (13) that are buried in the semiconductor substrate (11), wherein the element or component insulation regions or areas (13) have top surfaces; a gate electrode (22) formed on the component formation area (12), wherein the gate electrode extends in a first direction; a gate insulation layer (21) formed between the gate electrode (22) and the component formation area (12); Source-drain regions (27, 28) formed in the device formation area (12), wherein the source-drain regions (27, 28) are formed on both sides of the gate electrode (22) in a second direction and are formed below the top of the element or device insulation regions or areas (13); and a channel area (14) which is formed in the component formation area (12) below the gate electrode (22), wherein the element or component insulation areas or regions (13) have recesses (15) in the top surfaces, and the recesses (15) are formed below the gate electrode (22) and are bounded along the second direction. [2] Semiconductor device according to claim 1, wherein the source-drain regions (27, 28) have first epitaxial regions having a lattice constant other than Si. [3] Semiconductor device according to claim 2, wherein the first epitaxial regions are SiGe regions. [4] Semiconductor device according to claim 3, wherein the channel region (14) below the gate electrode (22) is flanked in the second direction by the SiGe regions, and the channel region (14) is flanked in the first direction by the recesses (15). [5] Semiconductor device according to claim 1 or 4, which further comprises a silicon nitride layer flanking the gate electrode (22) in the second direction. [6] Semiconductor device according to claim 5, wherein the silicon nitride layer is a stress-seal layer (71). [7] Semiconductor device according to claim 4 or 6, wherein the channel region (14) is subject to a compressive strain in the second direction if the semiconductor device is a pMOSFET. [8] Semiconductor device according to claim 4, wherein the recesses (15) are configured to at least partially eliminate the compressive stress of the channel area (14) in the first direction, and the SiGe areas are configured to impose a compressive stress on the channel area (14) in the second direction. [9] Semiconductor device according to claim 5 or 8, wherein the silicon nitride layer is a stress-seal layer (71) which is under compressive stress if the semiconductor device is a pMOSFET. [10] Semiconductor device according to claim 9, wherein the stress-suppression layer (71) is configured to impose a compressive stress on the channel region (14) in the second direction if the semiconductor device is a pMOSFET. [11] Semiconductor device according to claim 1 or 7, which further comprises a silicon nitride layer flanking the gate electrode (22) in the second direction. [12] Semiconductor device according to claim 11, wherein the silicon nitride layer is a stress-seal layer (71). [13] Semiconductor device according to claim 1 or 12, wherein the source-drain regions (27, 28) have second epitaxial regions having a lattice constant other than Si. [14] Semiconductor device according to claim 13, wherein the channel region (14) below the gate electrode (22) is flanked in the second direction by the second epitaxial regions, and the channel region (14) is flanked in the first direction by the recesses (15). [15] Semiconductor device according to claim 12 or 14, wherein the channel region (14) is subject to tensile stress in the second direction if the semiconductor device is an nMOSFET. [16] Semiconductor device according to claim 5, wherein the silicon nitride layer is a stress-strain lining layer (71) if the semiconductor device is an nMOSFET. [17] Semiconductor device according to claim 16, wherein the recesses (15) are configured to at least partially eliminate the compressive stress of the channel region (14) in the first direction, and the stress-relieving lining layer (71) is configured to impose a tensile stress on the channel region (14) in the second direction. [18] Semiconductor device according to claim 1 or 17, wherein the source-drain regions (27, 28) have second epitaxial regions having a lattice constant other than Si. [19] Semiconductor device according to claim 18, wherein the channel region (14) below the gate electrode (22) is flanked in the second direction by the second epitaxial regions, and the channel region (14) is flanked in the first direction by the recesses (15). [20] Semiconductor device according to claim 19, wherein the second epitaxial regions are configured to subject the channel region (14) to tensile stress in the second direction if the semiconductor device is an nMOSFET. [21] Semiconductor device according to claim 1, 7, or 10, wherein the difference between a part of a top surface of the channel region (14) and a part of a bottom surface of the recesses (15) is 3 nm to 30 nm. [22] Semiconductor device according to claim 1, 7, or 10, wherein the difference between a top surface of the channel region (14) and a bottom surface of the recesses (15) is 3 nm to 30 nm. [23] Semiconductor device according to claim 1, 7, or 10, wherein the semiconductor substrate (11) has a protruding section, and the protruding size of the protruding section from a base of the recesses (15) is 3nm to 30nm. [24] Semiconductor device according to claim 1, 7, 10, 21, 22 or 23, wherein the recesses (15) extend in the first direction. [25] Semiconductor device according to claim 1 or 24, wherein the positions of the transitions of the source-drain regions (27, 28) are formed below the top surfaces of the element or component insulation regions or areas (13). [26] Semiconductor device according to claim 25, wherein silicide layers (31, 32) on a top surface of the source-drain regions are formed from at least one of cobalt, nickel, platinum. [27] Semiconductor device according to claim 1, 7, or 10, wherein the gate insulation layer (21) has side surfaces and a bottom surface, and the side surfaces of the gate insulation layer (21) are connected to the bottom surface of the gate insulation layer (21) to define a third area (29). [28] Semiconductor device according to claim 1 or 27, wherein the gate insulation layer (21) has a layer with a high dielectric constant. [29] Semiconductor device according to claim 1 or 28, wherein the gate electrode (22) comprises a metallic material. [30] Semiconductor device according to claim 1 or 29, wherein the gate electrode (22) has a layered structure. [31] Semiconductor device according to claim 1, 7, 10 or 24, wherein the channel region (14) has a top surface and side surfaces along the second direction. [32] Semiconductor device according to claim 31, wherein a width of the top of the channel region (14) is longer than a height of the side surfaces of the channel region (14) in the second direction.

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