Circuits for determining the capacitance value of capacitors

Abstract

Circuit (102) to determine the value of a capacitor, with: a first circuit (554) to generate a first indication when a variable voltage across the variable capacitor crosses a limit voltage; a second circuit (556) to generate a second indication when a reference voltage is present across a reference capacitor (C ref ) intersects with the limit voltage; a control logic (530) that responds to the first and second indications to generate a control signal indicating whether at least one of the first or second indications has occurred before the other of the first or second indications has occurred; a successive approximation machine (510) for generating an N-bit control value based on the control signal; a variable current source (546) that responds to the N-bit control value to generate a variable current for the first circuit (554); a reference current source (548) to generate a reference current for the second circuit (556); and wherein the value of the capacitor can be determined by an associated processing circuit, based on a value of the reference capacitor, the reference current and the variable current supplied by the variable current source, when the variable voltage is substantially equal to the reference voltage.

Description

REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over U.S. preliminary patent application No. 61 / 152,071, filed on February 12, 2009, entitled SYSTEM AND METHOD FOR DETERMINING CAPACITANCE VALUE, and this application is related to U.S. patent application No. 12 / 146,349, filed on June 25, 2008, entitled LCD CONTROLLER CHIP. TECHNICAL AREA

[0002] The present invention relates to determining a capacitance value for a capacitor associated with a touch-sensitive capacitive switch, which may be a stand-alone switch or may be integrated into a capacitive sensor array, and in particular to a system and a method for determining a capacitance value using successive approximation techniques. BACKGROUND

[0003] The design of electronic circuits often requires the use of various interface circuits, such as capacitive sensor arrays, which allow the user to interact with or receive information from an electronic circuit. Typically, specific measurement circuits can be used to detect the activation of various capacitive switches within a capacitive sensor array, enabling the user to input specific information into the circuit.

[0004] A capacitive sensor array requires the ability to detect changes in the capacitance value of a capacitive switch in response to a user's finger touching it. In addition to detecting the touch and the corresponding change in capacitance caused by the finger, it is essential to make the measuring circuit insensitive to external interference within the capacitive sensor array. Examples of external interference include mobile phones, whose emissions can cause an unintended detection of an increase in the switch's capacitance. Furthermore, mains electrical circuits, such as those associated with air conditioners or other high-power devices, can also cause interference in capacitive sensor arrays.Other types of interference and inaccuracies within the capacitive measurement circuits themselves can also lead to errors in the detection of certain capacitance values ​​in capacitive sensor array circuits. Therefore, there is a requirement to provide a capacitive touch sensor circuit that enables the detection of a finger on a capacitive sensor array while simultaneously limiting the extent of detections based on external interference and inaccuracies, as well as interference inherent in the detection circuits.

[0005] US 2007 / 0 170 931 A1 relates to a capacitance measurement circuit comprising a current source, a switch, and a comparator. The current source is coupled to conduct a current through a circuit node. The switch is coupled to the circuit node to switch the current into a capacitor of a device under test (DUT). The comparator comprises a first and a second input terminal. The comparator is coupled to compare a first voltage received at the first input terminal with a reference voltage received at the second input terminal. The first voltage is related to the current flowing through the circuit node, the frequency at which the switch is operated, and the capacitance of the DUT capacitor.

[0006] US Patent 4,860,232 A discloses a circuit for measuring the capacitive differences of small capacitors. The circuit consists of a reference capacitor and a sensor capacitor. A switch is connected to one plate of each capacitor, connecting the capacitors to one of two reference voltages. The other plate of the capacitor is connected to an input terminal of a voltage comparator. The comparator compares the input voltage to a third reference voltage. Voltage differences detected by the comparator are applied to a feedback loop to generate an offset voltage at the input terminal. The offset voltage applied at the input terminal is proportional to the capacitive difference between the reference capacitor and the sensor capacitor.The feedback loop comprises a successive approximation register for digitizing the offset voltages and a digital-to-analog converter for converting the digitized voltages into analog voltages applied to the input terminal. The digitized offset voltages can be measured at the output of the successive approximation register. SUMMARY

[0007] The present invention, as disclosed and described herein with reference to one aspect thereof, comprises a circuit for determining the value of a variable capacitor. A first circuit generates a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. A second circuit generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responds to the first and second indications to generate a control signal indicating whether the first or second indication occurs first. A successive approximation machine generates an N-bit control value in response to the control signal. A variable current source, dependent on the N-bit control value, generates a variable current for the first circuit. A reference current source generates a reference current for the second circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more detailed understanding, please refer to the following description in conjunction with the accompanying drawings, which show: Fig. 1 is a higher-level block diagram of an integrated circuit with capacitive measurement capabilities; Fig. 2a is a functional block diagram of the capacitive touch measurement circuit; Fig. 2b shows a block diagram of the analog front-end circuit; Fig. 3. A time diagram is shown, which illustrates the function of the circuit. Fig. 2b represents; and Fig. Figure 4 shows a flowchart for the SAR algorithm for capturing the value of a capacitor on an external pin. DETAILED DESCRIPTION

[0009] Reference is now made to the drawings, in which the same reference numerals are used to denote identical elements throughout, and in which the various views and embodiments of a capacitive touch sensor are shown and described, as well as other possible embodiments. The figures are not necessarily drawn to scale, and in some cases the drawings have been enlarged and / or simplified in places to improve clarity. It is obvious to those skilled in the art that possible applications and modifications can be based on the following examples of possible embodiments.

[0010] It will now be on Fig. Figure 1 is referenced, which shows an overall block diagram of an integrated circuit (IC) 102 coupled to a plurality of capacitor touch fields 106, each coupled to the IC 102 via associated external pins 108. Each of the capacitor touch fields 106 includes some type of external capacitor, the capacitance of which can be varied by touching the capacitor with a finger or by positioning the finger close to it, thus influencing its capacitance value. It should also be understood that any type of capacitive element can be used, and not just a capacitive touch field. The capacitor touch fields 106 can be stand-alone elements, or they can be part of a capacitive sensor array.

[0011] The IC 102 features a multiplexer 544, which can be operated to select one of the external pins 108 and a plate from an associated capacitor touch field 106 to provide an input to a capacitive measuring block 252. The capacitive measuring block 252 can be operated to determine the value of the capacitance associated with the selected pin 108. This then allows a determination of the capacitance associated with pin 108, referred to as the capacitance associated with an "external capacitance switch," where this value is the sum of the value of the associated capacitor touch field 106 and a parasitic capacitance, this parasitic capacitance being the result of a finger touch, external interference, etc.The information regarding the capacitance value of the external capacitance switch is then sent to a processor 110 to determine changes in the capacitance value, etc., using a proprietary algorithm. An example of such an application is described in US patent application No. 12 / 146,349, filed on June 25, 2008, entitled "LCD CONTROLLER CHIP". It should be understood that the multiplexer 544 can be implemented with a switch.

[0012] In general, an application would either individually measure the static value of each of the external capacitance switches on each of the pins 108 at a given time, or continuously sample these external capacitance switches to determine whether a change in capacitance has occurred, i.e., whether the capacitance value has changed by more than a certain delta. If so, a proprietary algorithm can be used to determine whether this indicates a touch by a finger or external interference. However, the capacitive sensing block 252 can primarily be operated to determine the value of the external capacitance switch and then potentially perform hardware control to accumulate the determined values ​​and compare them with previous values ​​to generate a break for the processor 110.The first task of the capacitive measuring block 252 is to determine the value of the external capacitance switch connected to a specific pin 108, which is sampled at a specific time.

[0013] It will now be on Fig. 2a and Fig. Reference is made to Figure 2b, which shows a functional block diagram of the capacitive touch measuring block 252. The analog front-end circuit 502, which is shown in Fig. As shown in Figure 2a, the circuit responds to an attached external capacitance switch to determine the capacitance value. The analog front-end circuit 502 receives a 16-bit current control value, fed to the IDAC_DATA input via input 504, to control a variable current source. This current is controlled by a digital-to-analog current converter (IDAC), which is not shown. The analog front-end circuit also receives an enable signal at the ENLOG input 506 from a control circuit 508. The analog front-end circuit 502 additionally provides a clock signal. A successive 16-bit approximation register machine 510 controls a first variable current source in the analog front-end circuit 502, which controls the external capacitance switch. The 16-bit SAR machine 510 modifies a control value that is the current value of a variable current I. A defined, which includes an external capacitor C EXT (as in Fig. (2b) controls a selected path of the output paths 541. This selection is made by the multiplexer 544, and the capacitor C EXT This corresponds to a capacitor contact field of 106 in combination with a parasitic capacitance of the external capacitance switch. The current source that supplies the current I A generated, which generates the selected external capacitor C EXT Controlled by the power source 546, this causes a voltage to be applied to this external capacitance switch C. EXT is generated by the voltage across an internal reference capacitor C REF is compared (as in Fig. 2b shown). This capacitor C REF is an internal capacitor, and the current supplied to it from an internal current source is a constant current. Both capacitors, the selected capacitor C EXT and the reference capacitor C REF, are initialized at a predetermined point, and the currents supplied to them make it possible for the voltages across the capacitors C to EXT and C REF The ramp voltages and ramp rates increase at a rate determined by the respective capacitance value and the current supplied by the respective current sources that feed these control currents. By comparing the ramp voltages and ramp rates, a relative value of the two currents can be determined. This is simplified by setting a digital value for the IDAC and determining whether the ramp rates are essentially equal. If the capacitors C EXT and C REF If the current control capacitors C are identical, then the two ramp rates would be essentially identical. EXT and C REF are essentially identical. If the capacitor C EXTIf it is larger, this would require more current to derive a ramp rate that is essentially identical to that of capacitor C. REF This is described in greater detail below. When the SAR algorithm is complete, the 16-bit value "represents" the capacitance value of the external capacitance switch at the external node.

[0014] The current source control value for the variable current source 546 is further supplied to an adder block 512. The control value, which generates the required controlled current, is stored in a special function data register (SFR) 514, which represents the capacitive value of the external capacitive switch. This SFR 514 is a register that provides a data interface to the processor 110. Secondly, an input can be supplied to an accumulation register 516 to determine whether a touch has been detected on the currently monitored external capacitive switch of the capacitive sensor array. Several accumulations are used to confirm a touch of the switch, depending on the specific algorithm used. The output of the accumulation register 516 is supplied to the positive input of a comparator 518, which compares the supplied value with a value from a limit SFR register 520.When a selected number of repeated detections of activations, i.e., changes, of the associated external capacitive switch in the capacitive sensor array have been detected, the comparator 518 generates an interrupt for the processor 110. The output of the accumulation register 516 is also fed to the adder block 512.

[0015] It will now focus specifically on Fig. Reference is made to Figure 2b, which shows a more detailed representation of the 502 analog front-end circuit. The 502 analog front-end circuit contains control logic that produces an output d out , which is fed to the successive approximation register machine 510, and provides the output clock "clk_out". D OUT indicates a state that shows that the ramp voltage at C EXT was faster than the ramp voltage across C REF, which indicates that the tested SAR bit must be reset to "zero". The Logic 530 receives an input clock signal "clkn" and provides an output clock signal "clk" as well as an output clock signal "clkb" (clock bar) to a series of transistors.

[0016] The output clock signal "clk" is fed to a first n-channel transistor 532. The drain / source path of transistor 532 is connected between node 534 and ground. The gate of transistor 532 is connected to receive the "clk" signal. The gates of transistors 536 and 538 are coupled to the clock bar signal "clkb". The drain / source path of transistor 536 is connected between node 540 and ground, and node 540 is connected to an output surface 541 via multiplexer 544. The drain / source path of transistor 538 is connected between node 542 and ground.

[0017] Transistors 536, 538 and 532 act as discharge switches for capacitors C EXT , C REF or C P2 The capacitor C EXT is connected between the corresponding output of the multiplexer 544 and ground. The capacitor C REF is connected between internal node 542 and ground. The capacitor C P2 is connected between internal node 534 and ground. The capacitor C EXT This represents the external capacitive switch for the selected capacitor contact area 106 of the capacitive sensor array and its value is variable. The capacitive value can change depending on whether the associated capacitor contact area 106 has been actuated by the user's finger. The multiplexer 544 or other switching circuits are used to connect other external capacitive switches in the capacitive sensor array to node 540 to determine their capacitive values.

[0018] The variable current source 546 provides a current input to node 540. The variable current source 546 (an IDAC) is controlled by a 16-bit data control value supplied by the successive approximation register machine 510. The current source 546 is used to control the capacitor C EXT to charge when transistor 536 is switched off, creating a "ramp voltage" because the current source 546 supplies a constant current I A delivers. When transistor 536 is conducting, then the charging current and the voltage across capacitor C are EXT short-circuited to earth, causing C EXT is unloaded.

[0019] The power source 548 supplies a constant charging current I B at node 542. This charging current corresponds to a charging source for capacitor C. REF , when transistor 538 is switched off to generate a "ramp voltage", and the current I Bis lowered to ground when transistor 538 is conducting, thus discharging capacitor C REF is discharged. Similarly, the 550 power source supplies a constant charging current I. C to node 534. This power source 550 is used to power the capacitor C P2 to charge in order to generate a "ramp voltage" when transistor 532 is switched off, and I C is lowered to ground when transistor 532 is conducting, thus discharging capacitor C P2 is unloaded.

[0020] A low-pass filter 552 is connected to node 540. The low-pass filter 552 is used to filter out high-frequency interference generated at the external capacitor switch in the capacitive sensor array. The output of the low-pass filter 552 is connected to the input of a comparator 554. The comparator 554 compares the ramp voltage at node 540, which is the charging voltage across capacitor C. EXTrepresents, with a limit reference voltage V REF (not shown) and generates a negative pulse when the ramp voltage at node 540 exceeds the reference voltage V REF This crosses. It is routed to the control logic 530 as the signal "doutb". Similarly, a comparator 556 compares the ramp voltage of the fixed capacitor C. REF at node 542 with the limit reference voltage V REF and generates a negative output pulse “refb” when the voltage at node 542 exceeds the limit reference voltage V REF The comparator 558 then compares the ramp voltage at node 534, which is the charging voltage at capacitor C. P2 includes, with the limit reference voltage V REF and generates an output based on this as a signal “p2b” when the ramp voltage at node 534 exceeds the limit reference voltage.

[0021] The circuit in Fig. 2b works by initially resetting the voltage across capacitors C EXT and C REF to zero by switching on transistors 536 and 538. This causes the voltage across capacitors C to drop to zero. EXT and C REF The current is discharged to ground. Transistors 536 and 538 are then switched off, and the voltage across capacitors C EXT and C REF begins upwards towards the reference voltage V REF to increase, depending on the current output of the respective current sources 546 and 548. When the voltage across capacitor C EXT the limit voltage V REF reached before the voltage across capacitor C REF When the limit voltage is reached, the output of the comparator 554 is triggered to deliver a negative pulse, and this information is used by the control logic 530 as output D. OUTsupplied to the successive approximation register machine 510 to allow the tested SAR bit to remain at a "one", and a next value of the 16-bit control value for the current source 546 is selected for testing when C REF with the limit reference voltage level V REF Crosses. If comparator 554 "triggers" before comparator 556, this indicates that less current is required for the next bit being tested.

[0022] The control logic 530 generates the d OUT-Signal that controls the function of setting bits of the 16-bit SAR control value by the successive approximation register machine 510 in response to the output from the comparator 554. The successive approximation register machine 510 initially sets one most significant bit of the 16-bit control value to "one" and the rest to "zero" to control the variable current source 546 to operate at half a value. If the output of the comparator 554 goes "low" before the output of the comparator 556 goes "low", then d OUTThe signal D provides an indication to the successive approximation register machine 510 to reset this bit to "zero" and to set the next most significant bit to "one" for the next test of the 16-bit SAR control value. However, if the output of comparator 556 goes "low" before the output of comparator 554 goes "low", then the tested bit remains set to "one", and subsequently, the next most significant bit is tested. This process is repeated for each of the 16 bits of the 16-bit control value by the successive approximation register machine 510 in response to signal D. OUT from the control logic 530, until the final value of the 16-bit control value is determined for the variable current source 546.

[0023] The “clkb” issue highlights the tensions over C EXT and C REFback, by turning on transistors 536 and 538 to discharge the voltages across these capacitors, and turning off transistors 536 and 538 to allow capacitors C to recharge. EXT and C REF to enable the use of the supplied variable current or the respective reference current. The voltages across the capacitors C EXT and C REF are again measured by comparators 554 and 556 with the limit reference voltage V REFcompared. If the output of comparator 556 provides a negative output pulse prior to the output of comparator 554, this provides an indication to set a corresponding bit in the 16-bit control value to "one", as described above. The 16-bit control value, supplied to the variable current source 546, is stored when the SAR algorithm is complete, at which point both voltages rise at substantially the same rate. The current I A , which is supplied by the variable current source 546, which is related to the generated 16-bit value, the fixed current I B the power source 548 and the fixed capacitance value C REF can be used to determine the value of the capacity C EXT according to equation I A / I B × C REF to determine using the associated processing circuitry of the array controller. Although the current value of C EXTWhile this equation can be used to determine whether the value of the external capacitive switch has changed, it is not necessary to do so. For capacitive touch measurement, it is only necessary to determine a "delta" between a previously known value of the external capacitive switch and a current value. By repeatedly sampling all external capacitive switches in the capacitive sensor array and comparing a corresponding current value with the previous corresponding value, it can be determined whether a change has occurred. Therefore, it is only necessary to store a "normalized" value and then compare this previously stored normalized value with a new normalized value. The current value is not important; only the delta value is relevant.

[0024] By using similar circuits to generate the ramp voltages and to compare the voltages at nodes 540 and 542, essentially all common-mode errors in the circuits are avoided. Only filter 552 disturbs the common-mode balance between the circuits, but this is necessary to prevent high-frequency interference from external sources, such as mobile phones. The circuit for measuring the voltages at the nodes provides a proportional balance between the internal reference voltage and the external capacitance voltage. Therefore, errors in the comparators or reference voltage V are negligible. REF Not critical, as they are the same in every circuit.

[0025] It will now be on Fig. 3 Referenced, in which a timing diagram is shown that illustrates the function of the analog front-end circuit 502 from Fig. 2b describes this. In the analog front-end circuit 502, nothing can happen until time T1 when the activation signal goes logic "high". In response to the activation signal going "high" at time T1, the "clk" signal goes "low". Shortly after time T1, at point 670, the voltage CP2 across capacitor C begins to rise. P2(It should be noted that the ramp rate for the initial ramp is smaller due to start-up delays up to a point 671.) When the voltage reaches a set reference voltage level at time T2, the end of the first phase of a two-phase clock from comparator 558 produces a "low" clock pulse as the second phase of the two-phase clock, because the P2B signal and the CLK signal (and the CLKOUT signal) go "high". This causes the clock for the analog front-end circuit 502. The CLKB (clock bar) signal also goes "low" at the same time. The CLKB signal going "low" turns off transistors 536 and 538, causing the rise of the respective voltages across C EXT and C REF begins. If either of the voltages CREF or CEXT exceeds a reference voltage V REF reached (in this case the voltage CREF reaches the limiting voltage V) REF(First occurring at time T3), the output of comparator 556 generates a "low" pulse as the REFB signal. This causes the CLKOUT and CLK signals to go "low" and the CLKB signal to go "high". When the CLKB signal goes "high", transistors 536 and 538 are switched on, causing the CREF and CEXT voltages to discharge. The switching off of transistor 532 by CLK, which goes "low" at time T3, causes a rise in voltage CP2 across capacitor C. P2 This voltage continues to rise until it reaches a reference voltage at time T4, causing the output of comparator 558 to send a "low" pulse P2B. This causes the clock signals CLK and CLKOUT to go "high" and the clock signal CLKB to go "low". This increases the voltage across capacitor C. P2 discharge, and a rise in voltages across capacitors C begins. EXT and C REF .

[0026] At time T5, the voltage CEXT across capacitor C reaches EXT the reference voltage, specifically before the CREF voltage reaches the reference voltage. This causes the output of comparator 554 to go "low", where D OUT is generated. When the voltage CREF reaches the reference voltage at time T6, a "low" pulse is generated on REFB, and the CLKOUT and CLK signals go "low," while the CLKB signal goes "high." This discharges the voltages CREF and CEXT, and the charging of capacitor C P2 The process begins with voltage CP2. This process is repeated, if necessary, for each of the 16 bits of the SAR algorithm.

[0027] With further reference to the time diagram from Fig. 3 and on the representations from Fig. 2a and Fig. Section 2b describes the function in greater detail. As noted above, the base clock is provided by CP2 and CREF. CP2 provides one phase of the clock, i.e., the range when the clock is "low," and CREF provides the second phase of the clock, i.e., the range when the clock is "high." Therefore, CREF controls the second phase, and CEXT does not. Referring to the two ramp voltages for CREF and CEXT, this is essentially a race to the limit voltage. It should be noted that the two comparators, 554 and 556, are manufactured with the same circuitry on the same chip, and therefore temperature drifts, delays, etc., are essentially identical, thus avoiding any variations on a common-mode basis. It is only important that V REFThe comparators 554 and 556 are essentially identical, and their comparator delays are also essentially identical. To achieve further insensitivity to high-frequency noise, above and above that related to filter 552, these comparators 554 and 556 are designed to be somewhat "sluggish" and can therefore be incorporated into the SAR algorithm. This provides additional noise insensitivity. The key to low-frequency noise insensitivity is that while the low-frequency noise runs on the ramp voltage, the ramp voltage is reset after each bit of the 16-bit SAR cycle has been tested, so the low-frequency noise is present for only one cycle of the 1 kHz SAR cycle. This means that the low-frequency noise is a factor for only one microsecond period.This avoids low-frequency noise.

[0028] It will now be on Fig. 4 Referenced in which a flowchart is shown representing the function of the SAR machine 510, the connection with the function of the time diagram from Fig. 3 is described. The program starts at block 902 and then proceeds to a function block 904. At function block 904, the multiplexer 544 can be operated to select one of the pins. It should be noted that with reference to Fig. 2b Each external capacitance switch is connected to a separate input of the 544 multiplexer. It should be noted that each external capacitance switch is related to a 16-bit register to store the value of that external capacitance switch after it has been determined.

[0029] Upon activation, the program proceeds to block 906 to activate the SAR machine. The first step is to select the MSB, as indicated by block 908. This essentially sets the current source 546 to ½ for testing. Referring to the timing diagram, this occurs on the rising edge of signal EN. At this point, the voltages across capacitors C EXT and C REFThe voltages discharge to ground and rise to a voltage dependent on the current supplied by the respective current sources 546 and 548. As noted above, current source 546 is equipped with a current DAC, so its value is a function of the 16-bit value, which for the first cycle is "10000000000000000". The program then proceeds to a function block 910, which is a test for the specified bit. This test involves measuring the rise of the two voltages to determine which voltage reaches the reference voltage first. Essentially, this is a race between these two voltages to reach the reference voltage.

[0030] Basically, for each tested bit, a determination is made as to whether the capacitor C EXTMore or less current should be supplied. If, at the end of CREF, it was determined that CEXT crossed the limit voltage before CREF crossed the limit voltage, then this indicates that too much current was supplied, i.e., the tested bit must be reset to "0". This indicates that the current supplied by the current source 546 is sufficient to charge the capacitor C. EXT has been charged at too fast a rate. By resetting this bit to "0" and then, for the next bit to be tested, setting this bit to "1", the value at C is reset. EXT The delivered current is reduced. However, if at the end of CREF it was determined that CEXT did not cross the limit voltage, then this indicates that the capacitor C EXTInsufficient current was supplied, and therefore the tested bit would remain at "1". It is important to note that each SAR cycle ends at the end of CREF, at which point CLKB goes "high". Therefore, it is not necessary for CEXT to be allowed to go all the way up to the limit voltage. This can be seen particularly at time T3, where the clock signal CLKB goes "high" at the end of CREF, i.e., there is a reset, and transistors 536 and 538 are turned on to power C. EXT and C REF to discharge, thereby increasing C EXTThe process is terminated. At the end of CREF, a specific SAR bit is therefore assumed to be tested. At this point, a decision is made whether the bit should remain at "1" or be reset to "0". This is indicated by generating a "hit" in decision block 612 if CEXT crossed the threshold before the end of CREF, thus indicating the point at which the voltage across C REF has exceeded the limit. If CEXT has exceeded the limit before CREF has exceeded the limit, this is displayed as a "hit", indicating that C EXTIf too much current was supplied, meaning current source 546 won the race to the limit voltage, the program then follows the "YES" path to block 914 to set the tested SAR bit to "0," indicating that the 16-bit value must be lower. However, if the CEXT signal does not exceed the limit before CREF does, this indicates that there is no "hit," meaning current source 546 did not win the race, and the tested SAR bit is set to "1," as indicated by function block 916. After the SAR bit is tested, the program proceeds from either function block 914 or 916 to decision block 918.

[0031] At decision block 918, a determination is made as to whether all 16 bits have been tested. If not, the program follows a "NO" path to function block 920 to select the next MSB and then returns to the input of block 910 to test that bit. This continues until all 16 bits have been tested, at which point the program proceeds from decision block 918 along the "YES" path to function block 924 to store that value in the corresponding register. As noted above, this specific value represents the normalized value of the external capacitance switch. When the absolute values ​​of both currents in current sources 546 and 548, and the absolute value of capacitor C, are REFIf the value of the external capacitance switch is known, then it is possible to calculate its absolute value. However, calculating this value is not essential; rather, it is more important to have a 16-bit value available for later determination if the value of this external capacitance switch has changed. If the value has changed, a comparison is made with the previously stored 16-bit value in the register to determine whether the contents need to be updated, and this occurs upon such a change. This change is communicated to a program that executes an algorithm to determine if a "touch" is detected. Any type of algorithm can be used for this purpose. The primary purpose of the SAR machine 510 is to determine a 16-bit value for this external capacitance circuit for use by the algorithm.This value can then be used for comparison with a previously stored value, etc., to determine whether the change in capacitive value is of such a nature as to indicate whether a contact has occurred.

[0032] It is obvious to a person skilled in the art, and follows from this disclosure, that this capacitive measuring circuit provides a flexible solution for providing capacitive measurement functions for a capacitive sensor array on a single integrated chip, enabling the measurement of a capacitor for monitoring this value in order to determine whether a change has occurred. It should be understood that the drawings and detailed description presented here are for illustrative purposes only and are not intended to be limited to the specific embodiments and examples disclosed.On the contrary, further modifications, alterations, rearrangements, substitutions, alternatives, design choices, and embodiments are possible, which are obvious to the person skilled in the art, without deviating from the fundamental concept and the scope of protection defined by the following claims. It is therefore intended that the following claims be interpreted to encompass all such further modifications, alterations, rearrangements, substitutions, alternatives, design choices, and embodiments.

Claims

[1] Circuit (102) to determine the value of a capacitor, with: a first circuit (554) to generate a first indication when a variable voltage across the variable capacitor crosses a limit voltage; a second circuit (556) to generate a second indication when a reference voltage is present across a reference capacitor (C ref ) intersects with the limit voltage; a control logic (530) that responds to the first and second indications to generate a control signal indicating whether at least one of the first or second indications has occurred before the other of the first or second indications has occurred; a successive approximation machine (510) for generating an N-bit control value based on the control signal; a variable current source (546) that responds to the N-bit control value to generate a variable current for the first circuit (554); a reference current source (548) to generate a reference current for the second circuit (556); and wherein the value of the capacitor can be determined by an associated processing circuit, based on a value of the reference capacitor, the reference current and the variable current supplied by the variable current source, when the variable voltage is substantially equal to the reference voltage. [2] Circuit (102) according to claim 1, wherein the first circuit (554) further comprises a first comparator with a first input which is switched to monitor the variable voltage across the capacitor and a second input which is switched to monitor the limit voltage in order to generate the first indication. [3] Circuit (102) according to claim 2, wherein the second circuit (556) further comprises a second comparator with a first input which is switched to monitor the reference voltage across the reference capacitor and a second input which is switched to monitor the limit voltage to generate the second indication. [4] Circuit (102) according to claim 1, further comprising a low-pass filter (552) to filter out interference from the variable voltage across the capacitor. [5] Circuit (102 according to claim 1, further comprising a switching circuit (536, 538) for discharging the capacitor and for discharging the reference capacitor in response to the second indication that the reference voltage has exceeded the limit voltage. [6] Circuit (102) according to claim 1, further comprising: a third circuit (558) for generating a third indication when a second reference voltage across a second reference capacitor has exceeded the limit voltage; and a control logic (530) for generating a clock signal with a first clock edge in response to the third indication and a second clock edge in response to the second indication. [7] Circuit (102) according to claim 6, wherein the third circuit (558) further comprises a third comparator with a first input which is switched to monitor the second reference voltage across the second reference capacitor and a second input which is switched to monitor the limit voltage to generate the third indication. [8] Circuit (102) according to claim 6, further comprising a switching circuit (532) for discharging the second reference voltage across the second reference capacitor in response to the third indication that the second reference voltage has exceeded the limit voltage. [9] Circuit (102) to determine the value of a capacitor, with: a first connection to a capacitor switch array; a reference capacitor (C ref ); a processing core; a first comparator (554) with a first input switched to monitor a charging ramp voltage across a capacitor related to the capacitor switch array, and a second input switched to monitor a threshold voltage to generate a first indication when the charging ramp voltage across the capacitance exceeds the threshold voltage; a second comparator (556) with a first input switched to monitor a charging ramp voltage across the reference capacitor and a second input switched to monitor the limit voltage in order to generate a second indication when the charging ramp voltage across the reference capacitor crosses the limit voltage; a control logic (530) that responds to the first and second indications to generate a control signal indicating when at least one of the first indications or the second indication occurs first; a successive approximation machine (510) for generating an N-bit control value based on the control signal; a variable current source (546) that responds to the N-bit control value to generate a variable current to charge the capacitor in order to generate a charging ramp voltage across the capacitor; a reference current source (548) for generating a reference current to charge the reference capacitor in order to generate the charging ramp voltage across the reference capacitor; and where the value of the capacitor can be determined by the processing core based on a value of the reference capacitor, the reference current and the variable current supplied by the variable current source, when the charging ramp voltage across the capacitor is substantially equal to the charging ramp voltage across the reference capacitor. [10] Circuit (102) according to claim 9, further comprising a low-pass filter (552) to filter out interference from the charging ramp voltage across the capacitor. [11] Circuit (102) according to claim 9, further comprising a switching circuit (536, 538) for discharging the capacitor and for discharging the reference capacitor in response to the second indication that the charging ramp voltage across the reference capacitor has exceeded the limit voltage. [12] Circuit (102) according to claim 9, further comprising: a third circuit (558) to generate a third indication when a charging ramp voltage across a second reference capacitor has exceeded the limit voltage; wherein the control logic (530) also generates a clock signal with a first clock edge in response to the third indication and a second clock edge in response to the second indication. [13] Circuit (102) according to claim 9, wherein the third circuit (558) further comprises a third comparator with a first input which is switched to monitor the charging ramp voltage across the second reference capacitor and a second input which is switched to monitor the limit voltage to generate the third indication. [14] Circuit (102) according to claim 9, further comprising a switching circuit (532) for discharging the second reference capacitor in response to the third indication that the second reference voltage has exceeded the limit voltage. [15] Circuit (102) to determine the value of a capacitor, with: a first comparator (554) with a first input that is switched to monitor a charging ramp voltage across a capacitor and a second input that is switched to monitor a limit voltage in order to generate a first indication when the charging ramp voltage across the capacitor exceeds the limit voltage; a second comparator (556) with a first input switched to monitor a charging ramp voltage across the reference capacitor and a second input switched to monitor the limit voltage in order to generate a second indication when the charging ramp voltage across the reference capacitor crosses the limit voltage; a third comparator (558) with a first input switched to monitor a charging ramp voltage across a second reference capacitor and a second input switched to monitor the limit voltage to generate a third indication when the charging ramp voltage across the second reference capacitor crosses the limit voltage; a control logic (530) that responds to the first and second indications to generate a control signal indicating when at least one of the first indication or the second indication occurs first, wherein the control logic also generates a clock signal with a first clock edge in response to the third indication and a second clock edge in response to the second indication; a successive approximation machine (510) for generating an N-bit control value based on the control signal; a variable current source (546) that responds to the N-bit control value to generate a variable current for the associated capacitor to generate a charging ramp voltage; a reference current source (548) for generating a reference current for the reference capacitor in order to generate the associated charging ramp voltage; and wherein the value of the capacitor can be determined by an associated processing circuit, based on a value of the reference capacitor, the reference current and the variable current supplied by the variable current source, when the charging ramp voltage across the capacitor is substantially equal to the charging ramp voltage across the reference capacitor. [16] Circuit (102) according to claim 15, further comprising a low-pass filter (552) to filter out interference from the charging voltage across the capacitor. [17] Circuit (102) according to claim 15, further comprising a switching circuit (536, 538) for discharging the capacitor and for discharging the reference capacitor in response to the second indication that the charging ramp voltage across the reference capacitor crosses the limit voltage. [18] Circuit (102) according to claim 17, further comprising a second switching circuit (532) for discharging the second reference capacitor in response to the third indication that the associated charging ramp voltage crosses the limit voltage. [19] Capacitor value determination circuit (102) to determine the value of a capacitor, comprising: a charging circuit which is switched to charge the capacitor with a defined charging pattern from an initial voltage, wherein the defined charging pattern is variable; a reference circuit with a reference charging pattern; a controller for controlling the charging circuit to vary the defined charging pattern supplied to the capacitor over a range of discrete defined charging patterns, each defined charging pattern having a related control value; a comparison circuit for comparing the defined charging pattern with the reference pattern to determine whether they satisfy a defined relationship between themselves for a given control value; wherein the controller changes the control value in discrete steps to apply each discrete charge control value to the capacitor in order to supply it with a charge from the initial voltage until a determination is made that the defined relationship essentially exists, and correlates the capacitor value with the given control value. [20] Circuit (102) according to claim 19, wherein the charging circuit generates a ramp with an associated defined slope when the defined charging pattern by which the capacitor is charged from the initial voltage and the reference circuit generates a reference ramp with a reference slope, and the defined relationship is a ratio of the reference slope to the defined slope. [21] Circuit (102) according to claim 20, wherein the ramp is varied with a variable current source (546) to define a plurality of discrete slopes. [22] Circuit (102) according to claim 20, wherein the ratio is substantially uniform. [23] Circuit (102) according to claim 19, wherein the control includes a successive approximation algorithm to vary the control value. [24] Circuit (102) according to claim 19, wherein the capacitor is an external capacitor to an integrated circuit which includes the capacitor value determination circuit. [25] Circuit (102) according to claim 19, wherein the capacitor is part of a capacitor array containing a plurality of capacitors. [26] Circuit (102) according to claim 25, further comprising a multiplexer circuit (544) for scanning the capacitors in the capacitor array to determine the value of selected capacitors therein. [27] Circuit (102) according to claim 20, further comprising a storage element for storing the determined current value as a reference control value, wherein the control initiates a further capacitor value determination at a later time and compares the determined current control value with the stored control value to determine whether a change in the capacitance value has taken place. [28] Circuit (102) for successive approximation (SAR) to determine the value of an external capacitor, with: a primary drive source to drive the external capacitor with a discrete current that can be varied in discrete steps; a reference capacitor; a reference drive source for driving the reference capacitor with a fixed current; a controller for controlling the primary drive source and the reference drive source in order to drive the respective external capacitor and the reference capacitor from an initial voltage; a comparator to compare the charging curves of the primary capacitor and the reference capacitor to determine if they have a predetermined relationship; a SAR control circuit for varying the value of the discrete current according to a SAR algorithm until the charging curves of the primary capacitor and the reference capacitor essentially have the predetermined relationship, wherein the value of a control value for the SAR control circuit at a given time corresponds to the value of the external capacitor.

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