Non-volatile memory device, method for operating the same and electronic device with the same

Abstract

A method of operating a non-volatile memory device, comprising: receiving an operation command; detecting a noise level of a common source line (S20); adjusting the frequency that an operation is to be performed on a memory cell based on the detected noise level in response to the operation command, wherein the step of adjusting adjusts the frequency that a program verify operation of each of program loops is to be performed on the memory cell based on the detected noise level when the operation command is a programming command, and wherein the adjusting comprises: first, performing a first number of program verify operations on the memory cell when the detected noise level exceeds a threshold noise level and the operation command is a program command (S30); second, performing a second number of program verify operations on the memory cell if the detected noise level does not exceed a threshold noise level and the operation command is a program command, the second number being less than the first number (S50).

Description

BACKGROUND

[0001] US 2010 / 0124111 A1 discloses a non-volatile semiconductor memory device comprising: a memory cell array having a plurality of memory cell units, each comprising memory cells, a plurality of bit lines, and a common source line; a sense amplifier that reads data from a selected memory cell; a control circuit that controls a read operation of the sense amplifier; and a cell source monitor circuit that detects a voltage of the common source line, compares the detected voltage of the common source line with a reference voltage, and outputs a read control signal. The sense amplifier is configured to read data from the selected memory cell over at least two cycles.The control circuit is configured to perform a control to determine, based on the read control signal, whether the data reading should be terminated after a first read cycle or a second read cycle should be performed.

[0002] The object of the invention is to improve a known non-volatile memory device. This object is achieved by the invention defined in the appended independent claims. Further developments of the invention are specified in the dependent claims.

[0003] Embodiments of the present inventive concepts relate to a non-volatile memory device, and more particularly to a non-volatile memory device capable of adjusting a frequency of a read operation or a program verify operation in accordance with a noise level of a common source line, a method of operating the same, and an electronic device having the same.

[0004] A semiconductor memory device is divided into a volatile memory device and a non-volatile memory device. The volatile memory device includes dynamic random access memory (DRAM) and static random access memory (SRAM), and the non-volatile memory device includes flash memory, electrically erasable programmable read-only memory (EEPROM), and resistive memory.

[0005] The flash memory includes a memory cell array for storing data. The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells.

[0006] The majority of memory cells are separated into an on-cell and an off-cell according to a threshold voltage distribution. The on-cell is an erased cell, and the off-cell is a programmed cell.

[0007] A flash memory performs an erase operation on a memory block basis and performs a program operation or a read operation on a page basis.

[0008] A flash memory has a cell string structure. A cell string comprises a plurality of transistors connected in series between a string selection transistor connected to a string selection line (SSL) and a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to a bit line, and the ground selection transistor is connected to a common source line (CSL).

[0009] Each of a plurality of memory cells can be implemented as a single-level cell (SLC) for storing one bit or a multi-level cell (MLC) for storing a plurality of bits. The MLC has an erase state and a plurality of programming states, according to threshold voltages.

[0010] It is important that the MLC secures a span of each of a plurality of programming states by narrowing the distribution range of a threshold voltage in a programming state. Noise in the CSL causes the distribution range of each of the plurality of programming states to expand. CSL noise means that the voltage of the CSL increases due to current flowing in and within cells during a read operation or a program verify operation. With an identical word line voltage or an identical bit line voltage, if the voltage level of a source node of a ground select transistor increases due to noise in the CSL, the current flowing in and within cells decreases.This causes the threshold voltage of an on-cell to increase so that an on-cell can be determined to be an off-cell and causes an error during a read operation or a program verify operation. SUMMARY

[0011] The present invention relates to a method for operating a non-volatile memory device.

[0012] In one embodiment, the method comprises receiving an operation command, detecting a noise level of a common source line, and adjusting the frequency to adjust an operation on a memory cell in response to the operation command based on the detected noise level.

[0013] For example, the adjusting step may adjust the frequency of performing a program verify operation on the memory cell based on the detected noise level when the operation command is a programming command. In one embodiment, the adjusting first comprises performing a first number of program verify operations on the memory cell when the detected noise level exceeds a threshold noise level and the operation command is a programming command. Here, the first number is greater than 1. This embodiment further comprises secondly performing a second number of program verify operations on the memory cell when the detected noise level does not exceed a threshold noise level and the operation command is a programming command. Here, the second number is less than the first number.

[0014] As another example, adjusting adjusts the number of times a read operation is performed on the memory cell based on the detected noise level when the operation command is a read command. In one embodiment, adjusting first comprises performing a first number of read operations on the memory cell when the detected noise level exceeds a threshold noise level and the operation command is a read command. Here, the first number is greater than 1. The embodiment further comprises secondly performing a second number of read operations on the memory cell when the detected noise level does not exceed a threshold noise level and the operation command is a read command. Here, the second number is less than the first number.

[0015] Another embodiment of the method includes detecting a noise level of a common source line and adjusting a frequency of program verify operations on a memory cell during a program loop based on the detected noise level.

[0016] Yet another embodiment of the method includes detecting a noise level of a common source line and adjusting a frequency of read operations performed on a memory cell in response to a read command based on the detected noise level.

[0017] The present invention also relates to a non-volatile memory device.

[0018] In one embodiment, the device comprises a memory cell array comprising a plurality of memory cells connected in series between a bit line and a common source line, a detection circuit configured to detect a noise level of a common source line, and a control circuit configured to adjust the frequency of performing an operation on a memory cell in response to an operation command based on the detected noise level.

[0019] Embodiments are also directed to an electronic device, a memory card, a data storage device, etc., and a method of operation associated therewith, which incorporate embodiments of the storage device or method of reading according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] These and other aspects and advantages of the present general inventive concepts will be apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which: Fig. 1 shows a block diagram of a non-volatile memory device according to an exemplary embodiment of the present invention; Fig. 2 shows an exemplary embodiment of a memory cell arrangement which in Fig. 1 is illustrated; Fig. 3 shows another exemplary embodiment of the memory cell arrangement shown in Fig. 1 is illustrated; Fig. 4 is a block diagram showing an exemplary embodiment of a common source line level detection circuit used in Fig. 1 is illustrated; Fig. 5A is a block diagram showing an exemplary embodiment of control logic used in Fig. 1 is illustrated; Fig. 5B is a block diagram showing another exemplary embodiment of control logic used in Fig. 1 is illustrated; Fig. 6 shows a distribution of a threshold voltage of a plurality of non-volatile memory cells used in the memory cell array of the Fig. 1 are included, voltages during a read operation and voltages during a program verify operation. Fig. 7A to 7C are conceptual drawings for explaining a method of frequency adjusting a program verify operation based on a result of comparing a noise level of a common source line with a reference level according to an exemplary embodiment of the present invention; Fig. 8A and Fig. 8B are conceptual drawings for explaining a method of frequency adjusting a read operation based on a result of comparing a noise level of a common source line with a reference level according to another exemplary embodiment of the present invention. Fig. 9 is a flowchart for explaining a method of frequency adjusting a program verify operation based on a result of comparing a noise level of a common source line with a reference level according to an exemplary embodiment of the present invention; Fig. 10 is a flowchart for explaining a method of frequency adjusting a read operation based on a result of comparing a noise level of the common source line with a reference level according to another exemplary embodiment of the present invention; Fig. 11 shows an exemplary embodiment of an electronic device having a non-volatile memory device incorporated in Fig. 1 is illustrated; Fig. 12 shows another exemplary embodiment of an electronic device having the non-volatile memory device shown in Fig. 1 is illustrated; Fig. 13 shows yet another exemplary embodiment of an electronic device having the non-volatile memory device shown in Fig. 1 is illustrated; Fig. 14 shows yet another exemplary embodiment of an electronic device having the non-volatile memory device shown in Fig. 1 is illustrated; Fig. 15 shows yet another exemplary embodiment of an electronic device having the non-volatile memory device shown in Fig. 1 is illustrated; Fig. 16 shows yet another exemplary embodiment of an electronic device having the non-volatile memory device shown in Fig. 1 is illustrated; and Fig. 17 shows an exemplary embodiment of a data processing device comprising the electronic device shown in Fig. 16 is illustrated. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0021] Reference will now be made in detail to embodiments of the present general inventive concepts, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below to explain the present general inventive concepts by reference to the figures.

[0022] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items and may be abbreviated as " / ".

[0023] It will be understood that although the terms "first," "second," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first signal could be referred to as a second signal, and similarly, a second signal could be referred to as a first signal without departing from the teachings of the disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a" and "an" are intended to include the plural forms unless the context clearly indicates otherwise. It will further be understood that the phrases "comprises," "having," "includes," and / or "including," when used herein, specify the presence of named features, ranges, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more features, ranges, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms such as these, which are defined in commonly used dictionaries, should be interpreted to have the meaning consistent with their meaning in the context of the relevant field, and they will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0026] Fig. 1 shows a block diagram of a non-volatile memory device according to an exemplary embodiment of the present invention. Fig. 2 shows an exemplary embodiment of a memory cell arrangement which in Fig. 1 is illustrated, and Fig. 3 shows another exemplary embodiment of the memory cell arrangement shown in Fig. 1 is illustrated.

[0027] With reference to the Fig. 1 and Fig. 2, a non-volatile memory device 10 includes a memory cell array 20 for storing data; an access circuit 28 for performing a data access operation on the memory cell array 20 (e.g., a program operation), a read operation, or an erase operation; and a control circuit 48 for controlling the data access operation of the access circuit 29.

[0028] As shown, access circuit 28 includes a voltage generator 30, a row decoder 40, a page buffer and sense amplifier (S / A) circuit block 70, a column decoder 80, a Y-gating or clocking circuit 90, and an input / output (I / O) buffer and latch circuit block 95. Control circuit 48 includes control logic 50 and a common source line (CSL) level detection circuit 60. The above-mentioned elements of access circuit 28 and control circuit 48 will be described in more detail below.

[0029] The memory cell array includes a plurality of cell strings 20-1, 20-2, ..., 20-m, where m is a natural number. Each of the plurality of cell strings 20-1, 20-2, ..., 20-m includes a plurality of non-volatile memory cells connected in series.

[0030] As in Fig. 2, each cell string 20-1, 20-2, ..., 20-m may be arranged (or executed) on a plane or layer which is two-dimensionally identical.

[0031] Fig. Figure 2 illustrates the memory cell array 20 arranged two-dimensionally, the CSL level detection circuit 60 connected to a common source line (CSL), and the page buffer and sense amplifier block 70.

[0032] The cell string 20-1 includes a plurality of non-volatile memory cells connected in series between a first selection transistor (or string selection transistor) ST1 and a second selection transistor (or ground selection transistor) ST2. The first string selection transistor ST1 is connected to a bit line BL1, and the second string selection transistor ST2 is connected to the CSL. Each of the other cell strings 20-2 to 20-m has the same structure as the first cell string 20-1, and the description thereof will not be repeated for the sake of brevity. Each of the memory cells 21 has a control gate of the programmable / erasable transistor connected to a word line WL. The gates of the first and second selection transistors ST1 and ST2 are connected to selection lines SSL and GSL.

[0033] Each of a plurality of non-volatile memory cells 21 included in each cell string 20-1 to 20-m may be implemented in a flash electrically erasable programmable read-only memory (EEPROM) capable of storing one or more bits.

[0034] According to an exemplary embodiment, each of the plurality of non-volatile memory cells may be implemented in a NAND flash memory, such as a single-level cell (SLC) or a multi-level cell (MLC) capable of storing one or more bits. Accordingly, each cell string 20-1 to 20-m may be referred to as a NAND cell string.

[0035] The CSL level detection circuit 60 detects a noise level of the CSL, compares a detected noise level with a reference level, and generates a detection signal DET according to a comparison result.

[0036] The noise level is determined based on a parasitic resistance of a common source line connected to one of a plurality of memory cells.

[0037] The page register and sense amplifier 70 includes a plurality of page buffers 71-1 to 71-m. Each of the plurality of page buffers 71-1 to 71-m is connected to a corresponding one of the plurality of bit lines BL1 to BLm.

[0038] Each of the plurality of page buffers 71-1 to 71-m operates as a driver for programming data in the memory cell array 20 during a programming operation according to the control of a control logic 50. Furthermore, each of the plurality of page buffers 71-1 to 71-m may operate as a sense amplifier that sense-amplifies a voltage level of a corresponding one of the plurality of bit lines BL1 to BLm during a read operation or a verify operation according to the control of the control logic 50.

[0039] The verify operation includes a program verify operation and an erase verify operation.

[0040] For example, during a program operation, each of a plurality of page buffers 71-1 to 71-m performs two program verify operations at each program loop according to control of the control logic 50 when a noise level of the CSL is higher than a reference level, and performs only one program verify operation at each program loop when the noise level is lower than the reference level.

[0041] In addition, during a read operation, each of the plurality of page buffers 71-1 to 71-m may perform two read operations under the control of the control logic 50 when a noise level of the CSL is higher than a reference level and may perform only one read operation under the control of the control logic 50 when the CSL noise level is lower than the reference level.

[0042] Accordingly, the control circuit 48 tracks a noise level of the CSL and adjusts the number of a program verification operation or a read operation according to a tracking result, and an access circuit 28 can perform the program verification operation or the read operation as many times as the number is adjusted by the control circuit 48. Consequently, the nonvolatile memory device 10 can have better performance because it does not need to perform an unnecessary program verification operation or a read operation.

[0043] Fig. 3 illustrates an alternative embodiment for the memory cell array 20. Referring to Fig. 3, each cell string 20'-1, 20'-2, ... 20'-k, where k is a natural number, can be arranged three-dimensionally on a different level.

[0044] As in Fig. 3, a first cell string 20'-1 may be arranged on a first layer 21-1, a second cell string 20'-2 may be arranged on a second layer 21-2 which is different from the first layer 21-1, and a k-th string may be arranged three-dimensionally on a layer 21-k which is different from the second layer 21-2.

[0045] A plurality of layers 21-1 to 21-k may be formed by a wafer stack, a chip stack, or a cell stack. Each of the plurality of layers 21-1 to 21-k includes a plurality of cell strings.

[0046] A first cell string 20'-1, which is implemented on a first layer 21-1, comprises a plurality of non-volatile memory cells, for example NAND flash memory cells, which are connected in series between a plurality of selection transistors ST11 and ST21.

[0047] A second cell string 20'-2, which is implemented on a second layer 21-2, comprises a plurality of non-volatile memory cells, for example NAND flash memory cells, which are connected in series between a plurality of selection transistors ST12 and ST22.

[0048] A k-th cell string 20'-k, which is implemented on a k-th layer 21-k, comprises a plurality of non-volatile memory cells, for example NAND flash memory cells, which are connected in series between a plurality of selection transistors ST1k and ST2k.

[0049] This structure can be repeated for each bit line BL1 to BLm, with the repeated structures sharing the same word line WL; select line SSL, GSL, etc.

[0050] In this embodiment, a row decoder 40' replaces the row decoder 40 of the Fig. 1. The row decoder 40 is described in more detail below.

[0051] The row decoder 40' can provide any selection signal, such as a read voltage Vread during a read operation, a power voltage Vcc during a program operation, or 0 volts during an erase operation, to each string selection line SSL1 to SSLk connected to each gate of each first selection transistor ST11 to ST1k implemented on each layer 21-1 to 21-k. Accordingly, each first selection transistor ST11, ST12, ..., ST1k can be selectively turned on or off.

[0052] Row decoder 40' can provide any selection signal, for example, a read voltage Vread during a read operation, 0 volts during a program operation, or 0 volts during an erase operation, to each ground selection line GSL1, GSL2, ..., GSLk connected to each gate of each second selection transistor ST21, ST22, ..., ST2k implemented on each layer 21-1 to 21-k. Accordingly, each second selection transistor ST21, ST22, ..., ST2k can be selectively turned on or off.

[0053] As in Fig. As illustrated in Figure 3, each cell string 20'-1, 20'-2, ..., 20'-k may share a plurality of word lines WL1 to WLn, CSL, and a bit line BL1. That is, each cell string, implemented in a corresponding location on each layer 21-1 or 21-k, may be connected to each page buffer 71-1 to 71-m implemented in a page register and sense amplifier block 70.

[0054] The following explains an operation of a non-volatile semiconductor device 10 assuming that a cell string 20'-1 formed on one of a plurality of layers 21-1 to 21-k, for example, a first layer 21-1 in the three-dimensional memory cell array 20', is selected by a row decoder 40'.

[0055] Accordingly, a memory cell array 20 used in the present invention generally shows a two-dimensional memory cell array 20 arranged in Fig. 2 and a three-dimensional memory cell arrangement 20', which in Fig. 3 and generally shows a row decoder 40 which is Fig. 2 and a row decoder 40', which in Fig. 3 is illustrated.

[0056] In addition, a data access operation used in the present invention means a read operation and a verify operation, and the verify operation means a program verify operation and an erase verify operation.

[0057] Here, the program verify operation refers to an operation for determining whether a threshold voltage of a selected memory cell reaches a required threshold voltage after a program operation. The erase verify operation refers to an operation for determining whether a threshold voltage of a selected memory cell reaches a required threshold voltage after an erase operation.

[0058] Returning to Fig. 1, the control circuit 48 detects a noise level of the CSL and adjusts a frequency of a data access operation on each of a plurality of memory cells of a memory cell array 20 according to a result of comparing a detected noise level with a reference level.

[0059] The control circuit 48 includes a CSL level detection circuit 60 and the control logic 50.

[0060] The CSL level detection circuit 60 detects a noise level of the CSL, compares a detected noise level with a reference level, and outputs a detection signal DET according to a comparison result.

[0061] Fig. 4 is a block diagram showing an exemplary embodiment of a common source line level detection circuit used in Fig. 1 is illustrated.

[0062] Referring to Fig. 4, the CSL level detection circuit 60 comprises a CSL level detector 60-1, an analog / digital converter (ADC=Analog Digital Converter) 60-2, a reference level register 60-3 and a comparator 60-4.

[0063] The CSL level detector 60-1 detects a noise level of the CSL in response to an activated enable signal EN and outputs a detected noise level V CSL When an enable signal EN is deactivated, the CSL level detector 60-1 is deactivated.

[0064] The ADC 60-2 converts a detected noise level V CSL into a digital code Vd CSL around.

[0065] The reference level register 60-3 stores a reference code V dref corresponding to a reference level.

[0066] The comparator 60-4 compares the digital code Vd CSL with the reference code V drefand outputs a detection signal DET corresponding to a comparison result. For example, when a noise level of the CSL is higher than the reference level, the comparator 60-4 outputs a detection signal DET having a first level, such as a low level, or a data of 0. However, when a noise level of the CSL is lower than or equal to the reference level, the comparator 60-4 outputs a detection signal DET having a second level, such as a high level or a data of 1.

[0067] According to a level and a data value of a detection signal DET, the control logic 50 adjusts the frequency of the data access operation on each of a plurality of memory cells where a read operation or a program operation is performed.

[0068] For example, if the data access operation is a program operation, control logic 50 may control operation of access circuit 28 such that two program verify operations are performed sequentially at each program loop of a current program operation in response to a detect signal DET having a first level or a data 0. Control logic 50 may also control operation of access circuit 28 such that a single program verify operation can be performed at each program loop of the current program operation in response to a detect signal DET having a second level or a data 1.

[0069] Additionally, when the data access operation is a read operation, the control logic 50 may control an operation of the access circuit 28 such that, during a current read operation, two read operations may be performed consecutively in response to a sense signal having a first level or a data 0. The control logic 50 may also control an operation of the access circuit 28 such that, during the read operation, a single read operation may be performed in response to a sense signal DET having a second level or a data 1.

[0070] Fig. 5A is a block diagram showing an exemplary embodiment of the control logic used in Fig. 1 is illustrated.

[0071] Referring to Fig. 5A, the control logic 50 includes a scheduler 52, a plurality of state machines 54 and 56, and page buffer control logic 58. For ease of explanation, Fig. 5A, a voltage generator 30 and a page buffer and sense amplifier block 70 together with the control logic 50. The control logic 50 can control a data access operation of a non-volatile memory device 10 according to a command CMD input from the outside.

[0072] The scheduler 52 may control an operation of each of a plurality of state machines 54 and 56 according to a level of the detection signal DET.

[0073] For example, when the detection signal DET is a second level or a data 1, the scheduler or control program may enable or enable all of a plurality of state machines 54 and 56.

[0074] In addition, when the detection signal DET is a second level or a data 1, the scheduler 52 may enable or enable one of the plurality of state machines 54 and 56, for example, the state machine 56.

[0075] A read / verify level generator 30-1 of the voltage generator 30 generates a word line voltage V WL according to a level selection code output from at least one of the plurality of state machines 54 and 56. This will be described in detail with reference to the Fig. 6, Fig. 8A and Fig. 8B are described below.

[0076] Here the word line voltage V WLa program voltage Vpgm provided to a selected word line among a plurality of word lines during a program operation, or a program verify voltage Vvfy provided to a selected word line during a program verify operation.

[0077] In addition, the word line voltage V WL a selected word line voltage Vrd provided to a selected word line among a plurality of word lines, or a non-selected word line voltage Vread provided to the non-selected word lines not selected among the plurality of word lines during a read operation corresponding to a single read command.

[0078] Scheduler 52 may control an operation of page buffer control logic 48 according to a level of a detect signal DET. For example, when detect signal DET is a first level or a data 0, scheduler 52 may control an operation of page buffer control logic 58 so that two program verify operations or two read operations can be performed.

[0079] In addition, when the detection signal DET is a second level or a data 1, the scheduler 52 may control an operation of the page buffer control logic 58 so that a single program verify operation or a single read operation may be performed.

[0080] A page buffer control driver 70-1 of the page buffer and sense amplifier block 70 can drive a control signal output from the page buffer control logic 58 to each page buffer 71-1 through 71-m under the control of the control logic 50.

[0081] Accordingly, when two program verify operations or two read operations are performed consecutively, each of the page buffers 71-1 to 71-m can sense and amplify a signal of each bit line BL1 to BLm twice consecutively according to a control of the buffer control driver 70-1.

[0082] In addition, when a single program verify operation or a single read operation is performed, each page buffer 71-1 to 71-m can sense amplify a signal of each bit line BL1 to BLm once according to a control of the buffer control driver 70-1.

[0083] The scheduler 52, a plurality of state machines 54 and 56, and the page buffer control logic 58 may be implemented in hardware or software to control an operation of the hardware.

[0084] Fig. 5B is a block diagram showing another exemplary embodiment of the control logic used in Fig. 1 is illustrated.

[0085] Referring to Fig. 5B, the control logic 50' includes a scheduler 52', a state machine 53', and a page buffer control logic 58'. For better explanation, Fig. 5B, a voltage generator 30 and a page buffer and sense amplifier block 70. The control logic 50 can control a data access operation of a non-volatile memory device 10 according to a command CMD input from the outside.

[0086] The scheduler 52' may control an operation of the state machine 53' according to a level of a detection signal DET.

[0087] For example, when a detection signal DET is a first level or data 0, the scheduler 52' analyzes the detection signal DET having the first level or data 0 and outputs a result of the analysis to the state machine 53'. The state machine 53' controls an operation of the read / verify level generator 30-1 of the voltage generator 30 to perform two program verification operations per program loop or two read operations per single read command based on the result of the analysis.

[0088] Additionally, when a detection signal DET is a second level or data 1, the scheduler 52' analyzes the detection signal DET having the second level or data 1 and outputs a result of the analysis to the state machine 53'. The state machine 53' controls an operation of the read / verify level generator 30-1 of the voltage generator 30 to perform a single program verification operation per program loop or a single read operation per single read command based on the result of the analysis.

[0089] Returning to Fig. 1, the access circuit 28 can access each of a plurality of memory cells of the memory cell array 20 as many times as a frequency of a data access operation is adjusted by the control circuit 48.

[0090] For example, when the data access operation is a program verify operation of a programming operation, the access circuit 28 may perform the program verify operation on data programmed in each of the plurality of memory cells as many times as the frequency is adjusted by the control circuit 28.

[0091] For example, the control circuit 48 adjusts the frequency so that two program verify operations are performed sequentially at each program loop on each of the plurality of memory cells when a noise level of the CSL is higher than a reference level.

[0092] In addition, the control circuit 48 adjusts the frequency so that a single program verify operation can be performed on each of the plurality of memory cells at each program loop when a noise level of the CSL is not greater than a reference level.

[0093] When the data access operation is a read operation, the control circuit 48 adjusts the frequency so that two read operations can be performed consecutively on each of the plurality of memory cells when the noise level is higher than the reference level, and adjusts the frequency so that only one read operation can be performed on each of the plurality of memory cells when the noise level is lower than or equal to a reference level.

[0094] The voltage generator 30 generates a plurality of voltages including a program voltage Vpgm necessary for performing a program operation, a plurality of voltages including read voltages necessary for performing a read operation, or a plurality of voltages including an erase voltage Vera necessary for performing an erase operation, and outputs voltages necessary for performing each operation to a row decoder 40.

[0095] During a program operation, row decoder 40 provides a programming voltage Vpgm to a word line selected from among the plurality of word lines WL1 to WLn, for example, WL3, in response to a row address XADD, and provides a pass voltage to the remaining or unselected word lines. An incremental-stage pulse program (ISPP) can be used as the program operation. It is assumed that a non-volatile memory cell 21 connected to a word line WL3 is a selected memory cell.

[0096] During a program verify operation, a row decoder 40 may provide a program verify voltage Vvfy to a selected word line, for example, WL3.

[0097] During a read operation, the row decoder 40 provides a selected read voltage Vrd to a selected word line, for example, WL3, among a plurality of word lines WL1 to WLn and provides a non-selected voltage Vread to the remaining or non-selected word lines in response to a row address XADD.

[0098] The column decoder 80 decodes a column address YADD under the control of the control logic 50 and outputs decode signals to the Y control circuit 90.

[0099] The Y control circuit 90 may control data transfer between the second register and sense amplifier block 70 and an input / output buffer and latch register block 95 in response to decode signals output from the column decoder 80.

[0100] The input / output buffer and latch register block 95 can transmit data input from the outside to the Y control circuit 80, and can transmit data output from the Y control circuit 90 to the outside through a plurality of input / output pads.

[0101] Fig. Fig. 6 shows a distribution of threshold voltages of a plurality of non-volatile memory cells included in the memory cell array shown in Fig. 1, voltages during a read operation and voltages during a program verify operation are included.

[0102] Referring to Fig. 6, after a first program verify voltage Vvfy1', Vvfy2' or Vvfy3' is provided to a selected word line to perform a first of two program verify operations at each program loop of a programming operation, a second program verify voltage Vvfy1, Vvfy2 or Vvfy3 is provided to the selected word line if the detected noise level of the CSL is greater than a reference level.

[0103] In addition, the second program verify voltage Vvfy1, Vvfy2 or Vvfy3 is provided to a selected word line to perform a single program verify operation at each program loop of the operation when the detected noise level of the CSL is not greater than the reference level.

[0104] According to an exemplary embodiment, which is described in Fig. 7B, Vvfy1 may be selected higher than Vvfy1', Vvfy2 may be selected higher than Vvfy2', and Vvfy3 may be selected higher than Vvfy3'. According to another exemplary embodiment, shown in Fig. As shown in Figure 7C, Vvfy1 may be selected to be equal to Vvfy1', Vvfy2 may be selected to be equal to Vvfy2', and Vvfy3 may be selected to be equal to Vvfy3'.

[0105] In addition, during a read operation, after a first read voltage Vrd1', Vrd2', or Vrd3' is provided to a selected word line to perform a first of two read operations, a second read voltage Vrd1, Vrd2, or Vrd3 is provided to the selected word line if the detected noise level of the CSL is greater than a reference level.

[0106] In addition, during the read operation, the second read voltage Vrd1, Vrd2 or Vrd3 is provided to a selected word line to perform a single read operation when the detected noise level of the CSL is not greater than the reference level.

[0107] According to one exemplary embodiment, Vrd1 may be selected higher than Vrd1', Vrd2 may be selected higher than Vrd2', and Vrd3 may be selected higher than Vrd3'. According to another exemplary embodiment, Vrd1 and Vrd1' may be set equal, Vrd2 and Vrd2' may be selected equal, and Vrd3 and Vrd3' may be selected equal.

[0108] The Fig. 7A to 7C are conceptual diagrams for explaining a method of adjusting the frequency of a program verify operation based on a result of comparing a noise level of a common source line with a reference level according to an exemplary embodiment of the present invention, and Fig. 9 is a flowchart for explaining the method of adjusting the frequency of the program verification operation based on the result of comparing the noise level of the common source line with the reference level according to an exemplary embodiment. In the example of Fig. 7A to 7C, it is assumed that the detected noise on the CSL exceeds the reference level for the first to fifth program loops PL1 to PL5, but does not exceed the reference level for a sixth to eighth program loop PL6 to PL8.

[0109] With reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 6, Fig. 7A, Fig. 7B, Fig. 7C and Fig. 9, a programming operation is performed on a non-volatile memory device 10 (S10). The non-volatile memory device 10 receives a serial data input command, addresses, data, and a program command output from an external source, such as a memory controller or host, and programs the data to one page of the memory cell array 20 according to the addresses and the program command.

[0110] The program operation performs a program execution operation and a program verification operation at each of program loops PL1 to PL8 at each of states E, P1, P2, and P3. During the program execution operation, a program voltage (or a program pulse) according to ISPP is provided to a selected word line, and at least one program verification voltage Vvfy1', Vvfy1, Vvfy2', Vvfy2, Vvfy3', or Vvfy3 is provided during the program verification operation.

[0111] During the programming operation, a CSL level detection circuit detects a noise level of the CSL (S20).

[0112] The CSL level detection circuit 60 compares a detected noise level V CSL with a reference level V ref and outputs a detection signal DET according to a comparison result (S30).

[0113] For example, if the detected noise level V CSLis higher than the reference level V ref The CSL level detection circuit 60 outputs a detection signal DET having a first level. Subsequently, the scheduler 52 of the control logic 50 activates a plurality of state machines 54 and 56 in response to the detection signal DET having the first level.

[0114] Accordingly, the access controller 28 performs two program verify operations F and S at each program loop PL1 to PL5 on each of a plurality of memory cells where a program operation is performed (S40).

[0115] That is, each of the plurality of state machines 54 and 56 outputs a level selection code or level setting code under the control of the scheduler 52. The scheduler 52 may activate the state machine 54 before the state machine 56.

[0116] When an activated state machine 54 outputs a level select code, the read / verify level generator 30-1 and the row decoder 40 output a first program verify voltage Vvfyi', where i is 1, 2, or 3, to a word line voltage Vwl during a first program verify operation F.

[0117] The first program verify voltage Vvfy1', Vvfy2' or Vvfy3' is used to narrow a distribution range of cutoff voltages of non-volatile memory cells caused by noise of the CSL.

[0118] When a state machine 56 in the activated state outputs a level setting code or level selecting code, the read / verify level generator 30-1 and the row decoder output a second program verify voltage Vvfyi ≥ Vvfyi', where i is 1, 2 or 3 to a word line voltage V WL during a second program verification operation S.

[0119] However, if the detected noise level V CSL is lower than the reference level V ref , the CSL level detection circuit 60 outputs a detection signal DET having a second level. Accordingly, the scheduler 52 of the control logic 50 activates the state machine 56 only in response to the detection signal DET having the second level.

[0120] Accordingly, the access circuit 28 in the example of Fig. 7A to 7C performs only one program verify operation S at each program loop PL6 to PL8 in each of the plurality of memory cells where the program operation is performed (S50).

[0121] That is, when an activated state machine 56 outputs a level selection code, the read / verify level generator 30-1 and the row decoder 40 apply a second program verify voltage Vvfy1, Vvfy2, or Vvfy3 to a word line voltage V WLoutput during a program verification operation S.

[0122] The two program verification operations F and S performed at each program loop PL1 to PL5 are performed sequentially during a first loop time (LT1), and the single program verification operation S performed at each program loop PL6 to PL8 is performed during a second loop time (LT2) shorter than the first loop time. The first loop time (LT1) represents a maximum verification time at each program loop PL1 to PL5. The second loop time (LT2) represents a maximum verification time at each program loop PL6 to PL8. Accordingly, the control circuit 48 adjusts a maximum verification time based on a result of comparing a detected noise level with a reference level. For example, LT1=2*LT2.

[0123] According to an exemplary embodiment, which is described for example in Fig. As shown in Figure 7B, each of the two program verify operations F and S can be performed using different program verify voltages Vvfy1' and Vvfy1, Vvfy2 and Vvfy2', or Vvfy3 and Vvfy3'.

[0124] According to another exemplary embodiment, which is described for example in Fig. As shown in Figure 7C, when Vvfy1 is set equal to Vvfy1', Vvfy2 is set equal to Vvfy2', and Vvfy3 is set equal to Vvfy3', each of two program verify operations F and S can be performed using an identical program verify voltage Vvfy1' and Vvfy1, Vvfy2' and Vvfy2, or Vvfy3' and Vvfy3.

[0125] The time to perform each of the two program verification operations F and S is the same as the time to perform the single program verification operation S. That is, LT1=2*LT2.

[0126] The majority of memory cells where the programming operation is performed are provided or made available by the page.

[0127] The Fig. 8A and Fig. 8B are conceptual diagrams for explaining a method of adjusting the frequency of a read operation based on a result of comparing a noise level of a common source line with a reference level according to another exemplary embodiment of the present invention, and Fig. 10 is a flowchart for explaining a method for frequency adjustment of a read operation based on a result of comparing a noise level of a common source line with a reference level according to another exemplary embodiment of the present invention. Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 8A, Fig. 8B and Fig. 10, a read operation is performed on the non-volatile memory device 10 (S110). The non-volatile memory device 10 receives a read command and an address output from an external source, such as a memory controller or host, and reads data stored in the memory cell array 20 according to the address and read command.

[0128] At a certain time Ta of a bit line precharge operation, a word line precharge operation, or a read operation, the CSL level detection circuit 60 detects a noise level of the CSL (S20).

[0129] The CSL level detection circuit 60 compares a detected noise level V CSL with a reference level V ref and outputs a detection signal DET (S130).

[0130] For example, if a detected noise level V CSL is higher than a reference level V refThe CSL level detection circuit 60 outputs a detection signal DET having a first level. Subsequently, the scheduler 52 of the control logic 50 activates the plurality of state machines 54 and 56 in response to a detection signal DET having a first level.

[0131] Accordingly, the access circuit 28 performs two read operations F and S on each of a plurality of memory cells where a read operation is performed sequentially (S140). This means that the non-volatile memory device 10 performs two read operations according to a single read command CMD.

[0132] That is, each of a plurality of state machines 54 and 56 outputs a level selection code under the control of scheduler 52. Scheduler 52 may activate state machine 54 before state machine 56.

[0133] When the activated state machine 54 outputs a level selection code, the read / verify level generator 30-1 and the row decoder 40 output a first read voltage Vrdi', ie, Vrd1', Vrd2', or Vrd3' to a word line voltage V WL during a first read operation F.

[0134] When the activated state machine 56 outputs a level selection code, the read / verify level generator 30-1 and the row decoder 40 output a second read voltage Vrdi, ie, Vrd1, Vrd2, or Vrd3, to a word line voltage V WL during a second read operation S.

[0135] However, if a recorded noise level V CSL less than or equal to a reference level V refis, the CSL level detection circuit 60 outputs a detection signal DET having a second level. Accordingly, the scheduler 52 of the control logic 50 only activates the state machine 56 in response to a detection signal DET having a second level.

[0136] Accordingly, the access circuit performs only one read operation S on each of the plurality of memory cells where the read operation is performed ( Fig. 8B).

[0137] That is, when the activated state machine 56 outputs a level selection code, the read / verify level generator 30-1 and the row decoder 40 apply a second read voltage Vrd1, Vrd2, or Vrd3 to a word line voltage V WL output S during a read operation.

[0138] During the period while the detected noise level V CSL is higher than a reference level V ref, two reading operations F and S are performed consecutively during a first loop time (T1); and during a period when the detected noise level V CSL is lower than a reference level V ref Only one read operation S is performed during a second loop time (T2), which is shorter than the loop time (T1). The first loop time (T1) and the second loop time (T2) represent maximum read times. Accordingly, the control circuit 48 adjusts a maximum read time based on a result of comparing a detected noise level with a reference level. For example, T1=2*T2.

[0139] According to an exemplary embodiment, each of the two read operations F and S may be performed using a different read voltage Vrd1' and Vrd1, Vrd2' and Vrd2, or Vrd3' and Vrd3, respectively.

[0140] According to another exemplary embodiment, when Vrd1 and Vrd1' are selected to be equal, Vrd2 and Vrd2' are selected to be equal, and Vrd3 and Vrd3' are selected to be equal, each of the two read operations F and S can be performed using an identical read voltage Vrd1' and Vrd1, Vrd2' and Vrd2, or Vrd3' and Vrd3.

[0141] The time to perform each of the two read operations F and S is the same time as to perform one read operation S.

[0142] The majority of memory cells on which the read operation is performed are provided by a page.

[0143] As described above, the non-volatile memory device 10 can perform a program verification operation multiple times per program loop to reduce an error caused by CSL noise. However, the non-volatile memory device 10 can only perform one program verification operation and program loop after the noise becomes lower than a reference value. Therefore, the non-volatile memory device 10 can reduce the number of program verification operations.

[0144] Furthermore, while the embodiments were described as performing two program or read operations when the detected CSL noise was greater than a threshold, the present invention is not limited to this number. Instead, more than two program or read operations may be performed. Similarly, while the embodiments were described as performing one program or read operation when the detected CSL noise was not greater than a threshold, the present invention is not limited to this number. Instead, a program or read operation may be performed multiple times, as long as the number is less than the number of program or read operations performed when the detected CSL noise is greater than the threshold.

[0145] Fig. 11 shows an exemplary embodiment that includes an electronic device that is Fig. 1. Referring to Fig. 11, the electronic device 100 may be embodied in a mobile phone, a personal digital assistant (PAD), or a wireless Internet device.

[0146] The electronic device 100 includes the non-volatile memory device 10 and a memory controller 150 that can control an operation of the non-volatile memory device 10 (e.g., provides the instructions, addresses, etc.).

[0147] The memory controller 150 may control a data access operation of the non-volatile memory device 10, such as a program operation, an erase operation, or a read operation, according to a control of the processor 110.

[0148] Data programmed in the non-volatile memory device 10 may be displayed by a display 120 according to a processor 110 and a control of the memory controller 150.

[0149] A wireless transceiver 130 can exchange a wireless signal via an antenna ANT. For example, the wireless transceiver 130 can convert a wireless signal received by an antenna ANT into a signal that is processed at the processor 110.

[0150] Accordingly, the processor may process a signal output from the wireless transceiver 130 and transmit a processed signal to the memory controller 150 or the display 120. The memory controller 150 may store a signal processed by the processor 110 in the non-volatile memory device 10.

[0151] In addition, the wireless transceiver 130 may convert a signal output from the processor 110 into a wireless signal and output a modified wireless signal to an external device through the antenna ANT.

[0152] An input device 140 is a device that can input a control signal for controlling an operation of the processor 110 or data to be processed by the processor 110, and which can be embodied as a pointing device such as a touchpad and / or a computer mouse, a keypad, a keyboard, etc.

[0153] The processor 110 may control an operation of the display 120 so that a data output from the wireless transceiver 130 or a data output from the input device 140 may be displayed by the display 120.

[0154] According to an exemplary embodiment, the memory controller 150, which may control an operation of the non-volatile memory device 10, may be implemented in a part of the processor 110 or a chip separate from the processor 110.

[0155] Fig. 12 shows another exemplary embodiment of an electronic device incorporating the non-volatile memory device shown in Fig. 1. An electronic device 200, which is shown in Fig. 12 may be embodied in a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0156] The electronic device 200 includes the non-volatile memory device 10 and the memory controller 240, which can control a data processing operation of the non-volatile memory device 10.

[0157] A processor 210 may display data stored in the non-volatile memory device 10 through a display 230 according to data input by an input device 220. For example, the input device 220 may be embodied in a pointing device such as a touchpad or a computer mouse, a keypad, a keyboard, etc.

[0158] The processor 210 may control an overall operation of the electronic device 200 and an operation of the memory controllers 240.

[0159] According to an exemplary embodiment, the memory controller 240, which may control operation of the non-volatile memory device 10, may be implemented in a portion of the processor 210 or as a chip separate from the processor 210.

[0160] Fig. 13 shows yet another exemplary embodiment of an electronic device incorporating the non-volatile memory device shown in Fig. 1. An electronic device 300, which is shown in Fig. 13, may be embodied in a memory card or a smart card. The electronic device 300 includes the non-volatile memory device 10, a memory controller 310, and a card interface 320.

[0161] The memory controller 310 can control data exchange between the memory device 10 and the card interface 320.

[0162] According to an exemplary embodiment, the card interface 320 may be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface.

[0163] The card interface 320 may interface data exchange between a host and the memory controller 310 according to a protocol of a host.

[0164] According to an exemplary embodiment, the card interface 320 may support a universal serial bus (USB) protocol, an inter-chip (IC) USB protocol. Here, a card interface may refer to hardware that can support a protocol that a host uses, software embodied in the hardware, or a signal transmission method.

[0165] When an electronic device 300 is connected to a host such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a video console game hardware, or a digital set-top box, the host can perform data communication with the non-volatile memory device 10 through the card interface 320 and the memory controller 310.

[0166] Fig. 14 shows yet another exemplary embodiment of an electronic device incorporating the non-volatile memory device shown in Fig. 1. An electronic device 400, which is shown in Fig. 14 may be implemented in an image processing device, such as a digital camera or a mobile phone with a built-in digital camera.

[0167] The electronic device 400 includes the non-volatile memory device 10 and a memory controller 440 that can control a data processing operation of the non-volatile memory device, such as a programming operation, an erasing operation, or a reading operation.

[0168] An image sensor 420 of the storage system 400 converts an optical image into digital signals, and the converted digital signals are transmitted to a processor 410 or a memory controller 440. Under the control of the processor 410, the converted digital signals may be displayed by a display 430 or stored in the non-volatile memory device 10 by a memory controller 440. Additionally, data stored in the non-volatile memory device 10 is displayed by the display 430 under the control of the processor 410 or the memory controller 440.

[0169] According to an exemplary embodiment, the memory controller 440, which may control operation of the non-volatile memory device 10, may be implemented in a portion of the processor 410 or as a chip separate from the processor 410.

[0170] Fig. 15 shows yet another exemplary embodiment of an electronic device incorporating the non-volatile memory device shown in Fig. 1 is illustrated.

[0171] Referring to Fig. 15, an electronic device 500 includes the non-volatile memory device 10 and a central processing unit (CPU) 510 that can control an operation of the non-volatile memory device 10.

[0172] The electronic device 500 includes a memory device 550 that can be used as an operational memory of the CPU 510. The memory device 550 can be implemented as a non-volatile memory such as a read-only memory (ROM) or a volatile memory such as a static random access memory (SRAM).

[0173] A host connected to the electronic device 500 can perform data communication with the non-volatile memory device 10 through a memory interface 520 and a host interface 540.

[0174] An error correction code (ECC) block 530 may detect an error bit included in data output from the non-volatile memory device 10 through the memory interface 520, correct the error bit, and transmit error-corrected data to a host through the host interface 540 under control of the CPU 510.

[0175] The CPU 510 may control data communication between the memory interface 520, an ECC block 530, the host interface 540, and the storage device 550 through a bus 501.

[0176] The electronic device 500 may be embodied in a flash memory drive, a USB memory drive, an IC-USB memory drive, or a memory stick.

[0177] Fig. 16 shows yet another exemplary embodiment of an electronic device incorporating the non-volatile memory device shown in Fig. 1 is illustrated.

[0178] Referring to Fig. 16, an electronic device 600 may be embodied in a processing device, such as a solid-state drive (SSD). The electronic device 600 may include a plurality of storage devices 10 and a storage controller 610 that may control a data processing operation of each of the plurality of storage devices 10. According to an exemplary embodiment, the electronic device 600 may be embodied in a storage module.

[0179] Fig. 17 shows an exemplary embodiment of a data processing device comprising an electronic device which is Fig. 16. Referring to the Fig. 16 and Fig. 17, a data processing device 700 implemented in a redundant array of independent disks (RAID) system may include a RAID controller 710 and a plurality of electronic devices 600-, 1-600-n, where n is a natural number.

[0180] Each of the plurality of electronic devices 600-, 1-600-n may be an electronic device 600 which is in Fig. 16. The plurality of electronic devices 600-, 1-600-n can form a RAID array. The data processing device 700 can be embodied in a personal computer (PC) or an SSD.

[0181] During a programming operation, a RAID controller 710 may output program data received from a host according to a program command received from the host to at least one of the plurality of electronic devices 600-, 1-600-n based on a RAID level.

[0182] During a read operation, the RAID controller 710 may transfer data to be read by at least one of the plurality of electronic devices 600-, 1-600-n according to a read command issuance from a host to a host.

[0183] In order to improve the performance of a read operation or a program operation, a non-volatile memory device of the present invention can adjust the frequency of the read operation or a program verify operation according to a result of comparing a noise level of a source line with a reference level.

[0184] Accordingly, the non-volatile memory device can reduce errors during a read operation or a program operation.

Claims

[1] A method of operating a non-volatile memory device, comprising: receiving an operation command; detecting a noise level of a common source line (S20); adjusting the frequency that an operation is to be performed on a memory cell based on the detected noise level in response to the operation command, wherein the step of adjusting adjusts the frequency that a program verify operation of each of program loops is to be performed on the memory cell based on the detected noise level when the operation command is a programming command, and wherein the adjusting comprises: first, performing a first number of program verify operations on the memory cell when the detected noise level exceeds a threshold noise level and the operation command is a program command (S30); second, performing a second number of program verify operations on the memory cell if the detected noise level does not exceed a threshold noise level and the operation command is a program command, the second number being less than the first number (S50). [2] The method of claim 1, wherein each of the first number of program verify operations uses a different voltage. [3] The method of claim 2, wherein at least one of the first number of program verify operations uses a higher voltage than a preceding one of the first number of read operations. [4] The method of claim 1, wherein each of the first number of program verify operations uses a same voltage. [5] The method of claim 1, wherein the second execution is performed in a shorter time than the first execution. [6] The method of claim 1, wherein each of the first number of program verify operations occupies a first equal time, each of the second number of program verify operations occupies a second equal time, and the first equal time is equal to the second equal time. [7] The method of claim 1, wherein the first number is 2 or more and the second number is 1. [8] The method of claim 7, wherein each of the first number of program verify operations in the first execution takes the same time as the program verify operation in the second execution. [9] Non-volatile memory device comprising: A memory cell array (20) comprising a plurality of memory cells connected in series between a bit line (BL1 - BLm) and a common source line; a detection circuit (60) configured to detect a noise level of a common source line; and a control circuit (48) configured to perform a method according to any one of claims 1 to 8. [10] Electronic device comprising: The storage device of claim 9; and a processor (110) which processes an output from the second program verification operation. [11] Memory card that has the following: a card interface (320); and a controller for controlling an exchange of data between the card interface (320) and the storage device according to claim 9. [12] Data storage device comprising: a plurality of storage modules constituting a RAID array, each comprising at least one storage device and a storage controller for controlling operation of the associated at least one storage device; and a RAID controller (710) for controlling operation of the plurality of modules, wherein each of the storage devices is the storage device of claim 9.

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