Circuit arrangement with a plurality of on-chip monitoring circuits and a control circuit and associated method

Abstract

A circuit arrangement (100, 400, 700) comprising: a plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), each of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) being configured to measure a parameter of a semiconductor chip; and a control device (106, 406, 706) coupled to the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), wherein the control device (106, 406, 706) is configured to receive a measurement result from at least one on-chip monitoring circuit (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) and to control a calibration of another one of the plurality of on-chip monitoring circuits (104, 404, 704) in accordance with the measurement result; wherein the control device (106, 406, 706) is configured to mark the calibration of the other of the plurality of on-chip monitoring circuits (104, 404, 704) as invalid if at least one measurement result from the at least one on-chip monitoring circuit (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) deviates from a predetermined range.

Description

[0001] Various embodiments relate to a circuit arrangement comprising a plurality of on-chip monitoring circuits (i.e. monitoring circuits arranged or provided on the chip) and a control circuit and associated methods.

[0002] Modern electronic systems, such as mobile phones, digital cameras, and PDAs (Personal Digital Assistants), have an ever-increasing demand for highly integrated and energy-efficient semiconductor circuits. To meet these requirements, the physical size of field-effect transistors (FETs) within semiconductor circuits is being reduced. Due to this shrinking size, the FETs become vulnerable to variations in semiconductor circuit parameters, such as process, supply voltage, device aging, and temperature. Traditionally, these variations are modeled using guard bands, meaning that safety margins can be added to enable robust operation of the semiconductor circuit. However, safety margins are expensive in terms of area requirements and power dissipation.

[0003] US 2005 / 0 256 660 A1 describes a sensor with a compensation circuit based on a Padé approximation, which is integrated into the sensor. The compensation circuit implements a linearization of the sensor's characteristic curve. Furthermore, US 2010 / 0 312 513 A1 discloses a magnetic field sensor having a calibration module that performs a calibration based on historical measurement data of a magnetic field sensor. US 7 209 013 B2 describes a self-calibrating integrated circuit with a memory in which environmental parameters of an analog function are stored. US 2011 / 0 029 266 A1 describes an integrated circuit with a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to detect a process parameter that describes a semiconductor process by means of which the integrated circuit was manufactured.

[0004] On-chip monitoring circuits can be implemented to measure the actual status of semiconductor circuits with respect to specific variations. Countermeasures or adaptive techniques can be initiated at the circuit level or system level in response to the measurement results of the on-chip monitoring circuits. A specific on-chip monitoring circuit is typically designed to measure a specific effect with high measurement accuracy, such as the process power class. Other variations, such as process or supply voltage, act as disturbing effects during the measurement and reduce the measurement accuracy of a specific on-chip monitoring circuit.

[0005] The sensitivity of the on-chip monitoring circuit to disturbing effects should be as low as possible to avoid distorting the measurement results. A thorough design of the on-chip monitoring circuit can reduce the sensitivity to disturbing effects. If the sensitivity of the on-chip monitoring circuit to disturbing effects cannot be completely eliminated, calibration of the on-chip monitoring circuit may be required to compensate for the disturbing effects. Calibration can be performed during manufacturing, after manufacturing, or during operation of the on-chip monitoring circuit.Calibration of an on-chip monitoring circuit can be implemented by providing a circuit that modifies the electrical behavior of the monitoring circuit, i.e., the operation of the monitoring circuit can be switched between several predetermined configuration settings. During calibration, a specific predetermined configuration setting that provides the best measurement accuracy can be selected and stored for later use of the monitoring circuit in a monitoring mode. The selected configuration setting can be stored in a register, volatile memory, non-volatile memory, or an electrical fuse, such as an electrical fuse.The register, volatile memory, non-volatile memory, or electrical fuse may be implemented or provided on the same semiconductor substrate as the on-chip monitoring circuit or on a separate semiconductor substrate.

[0006] The invention is based on the object of providing reliable calibration of an on-chip monitoring circuit. This object is achieved by the subject matter of the independent patent claims. Further developments are specified in the dependent patent claims.

[0007] In various embodiments, a circuit arrangement is provided which may comprise a plurality of on-chip monitoring circuits, wherein each of the plurality of on-chip monitoring circuits may be configured to measure a parameter of a semiconductor chip, and a control device which may be coupled to the plurality of on-chip monitoring circuits, wherein the control device may be configured to obtain a measurement result from at least one on-chip monitoring circuit of the plurality of on-chip monitoring circuits and to control a calibration of another one of the plurality of on-chip monitoring circuits in accordance with the measurement result.

[0008] According to further embodiments of the circuit arrangement, at least two on-chip monitoring circuits of the plurality of on-chip monitoring circuits may be of the same type.

[0009] According to further embodiments of the circuit arrangement, the plurality of on-chip monitoring circuits can be configured to measure parameters of the semiconductor chip simultaneously.

[0010] According to further embodiments of the circuit arrangement, the plurality of on-chip monitoring circuits can be arranged in different regions of the semiconductor chip.

[0011] According to further embodiments of the circuit arrangement, the control device may be configured to control the calibration by adjusting a setting of another of the plurality of on-chip monitoring circuits.

[0012] According to further embodiments of the circuit arrangement, the control device can be configured to repeat the calibration if the measurement result deviates from a predetermined range.

[0013] According to further embodiments of the circuit arrangement, the control device may be configured to receive a plurality of measurement results from at least one of the plurality of on-chip monitoring circuits within a predetermined time and to control the calibration in accordance with a combination of the plurality of measurement results.

[0014] According to further embodiments of the circuit arrangement, the control device can be configured to receive a plurality of measurement results from the plurality of on-chip monitoring circuits and to detect whether at least one of the plurality of measurement results deviates from a predetermined range.

[0015] According to further embodiments of the circuit arrangement, the control device may be configured to adapt a parameter of the semiconductor chip in accordance with a combination of the plurality of measurement results if none of the plurality of measurement results deviates from a predetermined range.

[0016] In various embodiments, a circuit arrangement is provided which may comprise: a plurality of on-chip monitoring circuits, which may be arranged in a network, wherein each of the plurality of on-chip monitoring circuits may be configured to measure at least one parameter of a semiconductor chip; a control device, which may be coupled to the network of on-chip monitoring circuits, wherein the control device may be configured to receive measurement results from the plurality of on-chip monitoring circuits and generate an output in accordance with an evaluation of the measured values; and at least one feedback loop, which may be coupled to the control device and the network, wherein the at least one feedback loop may be configured to control a calibration of at least one of the plurality of on-chip monitoring circuits in accordance with the output.

[0017] According to further embodiments of the circuit arrangement, the control device can be configured to adapt a parameter of the semiconductor chip in accordance with a combination of measurement results.

[0018] According to further embodiments of the circuit arrangement, at least one of the plurality of on-chip monitoring circuits may comprise a calibration control word and the feedback loop may be configured to control the calibration by adjusting the calibration control word in accordance with the output.

[0019] According to further embodiments of the circuit arrangement, the network of the plurality of on-chip monitoring circuits may be configured to operate simultaneously.

[0020] According to further embodiments of the circuit arrangement, the plurality of on-chip monitoring circuits may be implemented in a dedicated circuit block and the control device may be implemented in a processor.

[0021] In various embodiments, a method for supervising an on-chip monitoring circuit is provided, the method comprising: (a) starting a measurement of at least one of a plurality of on-chip monitoring circuits, wherein each of the plurality of on-chip monitoring circuits may be configured to measure a parameter of the semiconductor chip; (b) starting a measurement of an on-chip monitoring circuit to be supervised, wherein the on-chip monitoring circuit to be supervised may be configured to measure a parameter of the semiconductor chip; (c) processing at least one measurement result of the at least one of the plurality of on-chip monitoring circuits;and (d) indicating that a measurement result of the on-chip monitoring circuit to be supervised is invalid if at least one measurement result of the at least one of the plurality of on-chip monitoring circuits deviates from a predetermined range;

[0022] According to further embodiments of the method, the on-chip monitoring circuit to be supervised may be configured to measure a parameter that differs from the parameters measured by the plurality of on-chip monitoring circuits.

[0023] According to further embodiments of the method, the measurement of an on-chip monitoring circuit to be supervised can be started after the measurement of at least one of the plurality of on-chip monitoring circuits has been started.

[0024] According to further embodiments, the method may further comprise repeating at least steps (a) to (c) if at least one measurement result of the on-chip monitoring circuit to be supervised is marked as invalid.

[0025] According to further embodiments, the method may further comprise activating a measurement mode and adjusting a parameter of the semiconductor chip in accordance with the measurement result of the on-chip monitoring circuit to be supervised if the measurement result of the on-chip monitoring circuit to be supervised is not marked as invalid.

[0026] According to further embodiments, the method may further comprise receiving a plurality of measurement results from the at least one of the plurality of on-chip monitoring circuits within a predetermined time, wherein processing the measurement results in step (c) may comprise processing the plurality of measurement results.

[0027] In various embodiments, a method for calibrating an on-chip monitoring circuit is provided, the method comprising: (a) activating a plurality of on-chip monitoring circuits that may be configured to measure at least one parameter of the semiconductor chip; (b) activating an on-chip monitoring circuit to be calibrated; (c) combining the measurement results from the plurality of on-chip monitoring circuits; and (d) controlling a calibration of the on-chip monitoring circuit to be calibrated in accordance with the combination of the measurement results.

[0028] According to further embodiments of the method, the calibration may comprise adjusting a setting of the on-chip monitoring circuit to be calibrated.

[0029] According to further embodiments of the method, controlling a calibration may comprise repeating the first (a) and second (b) activation steps and the combining step (c) if at least one measurement result deviates from a predetermined range.

[0030] In various embodiments, a system is provided which may include circuitry, functional circuitry, and regulation circuitry. The circuitry may include: a plurality of on-chip monitoring circuits, wherein each of the plurality of on-chip monitoring circuits may be configured to measure a parameter of a semiconductor chip; a controller coupled to the plurality of on-chip monitoring circuits, wherein the controller is configured to receive a measurement result from at least one on-chip monitoring circuit of the plurality of on-chip monitoring circuits and to control a calibration of another one of the plurality of on-chip monitoring circuits in accordance with the measurement result. The functional circuitry may be configured to perform a function of the semiconductor chip.The regulation circuit, which may be coupled to the circuit arrangement and the functional circuit, may be configured to regulate a parameter of the functional circuit in accordance with at least one measurement result of at least one of the plurality of on-chip monitoring circuits.

[0031] According to further embodiments of the system, the plurality of on-chip monitoring circuits and the functional circuit may be arranged on the semiconductor chip.

[0032] The detailed description is provided with reference to the accompanying drawings. In the drawings, the leftmost digit of a reference symbol identifies the drawing in which the reference symbol first appears. The use of similar reference symbols in different instances in the description and the drawings may refer to similar or identical items. Fig. 1 shows an exemplary circuit arrangement with a plurality of on-chip monitoring circuits and a control device. Fig. Figure 2 shows a graph illustrating a supply voltage of an on-chip monitoring circuit to be calibrated during calibration. Fig. 3 shows another graph showing a supply voltage of an on-chip monitoring circuit to be calibrated during calibration. Fig. 4 shows another exemplary circuit arrangement with a plurality of on-chip monitoring circuits and a control device. Fig. Figure 5 shows an exemplary self-calibrating on-chip monitoring circuit. Fig. Figure 6 shows an exemplary on-chip monitoring circuit with external calibration. Fig. 7 shows an exemplary circuit arrangement with a plurality of monitoring circuits on the chip, a control circuit and a plurality of post-processors, Fig. Figure 8 shows an exemplary system with a circuit arrangement, a functional circuit and a control circuit. Fig. Figure 9 shows a flowchart containing a number of operations that monitor an on-chip monitoring circuit. Fig. Figure 10 shows a flowchart containing a number of operations that calibrate a monitoring circuit on the chip.

[0033] Techniques and methods for monitoring a parameter of a semiconductor chip are disclosed. According to one implementation, a circuit arrangement may include a plurality of on-chip monitoring circuits. Each of the plurality of on-chip monitoring circuits is configured to measure a parameter of the semiconductor chip. The circuit arrangement may further include a controller coupled to the plurality of on-chip monitoring circuits. The controller may be configured to receive a measurement result from at least one of the plurality of on-chip monitoring circuits and to control a calibration of another of the plurality of on-chip monitoring circuits in accordance with the measurement result.

[0034] In various embodiments, the controller may be implemented using any type of logic, for example, digital logic, such as hard-wired logic and / or programmable logic. In various embodiments, the controller may be implemented, for example, using a processor, for example, a microprocessor (for example, a CISC (complex instruction set computer) microprocessor or a RISC (reduced instruction set computer) microprocessor), or as a programmable gate array (PGA) or a field programmable gate array (FPGA), or the like.

[0035] According to a further implementation, a circuit arrangement may comprise a plurality of on-chip monitoring circuits arranged in a network. Each of the plurality of on-chip monitoring circuits may be configured to measure at least one parameter of the semiconductor chip. The circuit arrangement may further comprise a controller coupled to the network of on-chip monitoring circuits. The controller may be configured to receive measurement results from the plurality of on-chip monitoring circuits and generate an output in accordance with an evaluation of the measurement results. The circuit arrangement may further comprise at least one feedback loop coupled to the controller and the network.The at least one feedback loop may be configured to control a calibration of at least one of the plurality of on-chip monitoring circuits in accordance with the output.

[0036] According to a further embodiment, a method for monitoring an on-chip monitoring circuit is provided. A measurement of at least one of a plurality of on-chip monitoring circuits is started (e.g., at least one of the plurality of on-chip monitoring circuits then begins to perform the measurement), and each of the plurality of on-chip monitoring circuits can be configured to measure a parameter of a semiconductor chip. Furthermore, a measurement of an on-chip monitoring circuit to be monitored can be started, and the on-chip monitoring circuit to be monitored can be configured to measure a parameter of the semiconductor chip. Furthermore, at least one measurement result of at least one of the plurality of on-chip monitoring circuits can be processed.A measurement result from an on-chip monitoring circuit may be marked as invalid if the at least one measurement result from at least one of the plurality of on-chip monitoring circuits deviates from a predetermined range.

[0037] According to a further embodiment, a method for calibrating an on-chip monitoring circuit is provided. A plurality of on-chip monitoring circuits configured to measure at least one parameter of a semiconductor chip can be activated. Furthermore, an on-chip monitoring circuit to be calibrated can be activated. Measurement results from the plurality of on-chip monitoring circuits can be combined or summarized. Furthermore, a calibration of the on-chip monitoring circuit to be calibrated (ie, the on-chip monitoring circuit to be calibrated) can be controlled in accordance with the combination of the measurement results.

[0038] The implementations described and illustrated herein can enable accurate calibration of an on-chip monitoring circuit and accurate measurement of chip parameters. Variations in operating conditions can be detected during a calibration phase or a measurement phase, and a calibration or measurement can be repeated if significant variations in operating conditions exist. Additionally, the implementations shown and illustrated herein can have a small area requirement and low power consumption.

[0039] The techniques described here can be implemented or realized in a variety of ways. Examples and contexts are provided below with reference to the attached drawings and the further description.

[0040] Fig. 1 shows a schematic diagram of an exemplary circuit arrangement 100 comprising a plurality of on-chip monitoring circuits 102 and 104 and a controller 106. Each of the plurality of on-chip monitoring circuits 102 and 104 is configured to measure a parameter of a semiconductor chip. The controller 106 is coupled to the plurality of on-chip monitoring circuits 102 and 104 and is configured to receive at least one measurement result from at least one (e.g., the on-chip monitoring circuit 104) of the plurality of on-chip monitoring circuits 102, 104. The controller 106 is further configured to control calibration of another one (e.g., the on-chip monitoring circuit 102) of the plurality of on-chip monitoring circuits 102 and 104 in accordance with the measurement result.

[0041] As in Fig. 1, the plurality of on-chip monitoring circuits 102 and 104 may comprise two on-chip monitoring circuits 102 and 104, i.e., a first on-chip monitoring circuit 102 and a second on-chip monitoring circuit 104. Alternatively, the plurality of on-chip monitoring circuits may comprise more than two on-chip monitoring circuits. Each of the plurality of on-chip monitoring circuits 102 and 104 may be configured to measure one or more parameters of the semiconductor chip. A measurement result provided by one of the on-chip monitoring circuits 102 and 104 may correspond to a current state of a parameter of the semiconductor chip.An on-chip monitoring circuit may be configured to measure a parameter, for example, a temperature, a supply voltage, a circuit delay, a frequency, an aging condition, a process variation, a dynamic power dissipation, or a leakage current. Additionally or alternatively, an on-chip monitoring circuit may be configured to measure CMOS (complementary metal oxide semiconductor) device parameters, such as a drive current and threshold voltage, or a resistance and coupling capacitances of on-chip interconnections (i.e., interconnections on the chip). An on-chip monitoring circuit may, for example, comprise a ring oscillator, an array of delay elements, and / or a time-to-digital converter to measure the one or more parameters.Additionally or alternatively, the on-chip monitoring circuit may include a sensor, such as a thermal sensor, to measure the one or more parameters. The on-chip monitoring circuit may include entirely digital logic, entirely analog logic, or both digital and analog logic.

[0042] The controller 106 may monitor a calibration of the first on-chip monitoring circuit 102 by receiving a measurement result from the second on-chip monitoring circuit 104 and checking whether the measurement result falls within a predetermined range. If the measurement result deviates from the predetermined range, the calibration of the first on-chip monitoring circuit 102 may be invalid, and the calibration may be repeated. For example, the controller 106 may interrupt the calibration and initiate a restart of the calibration of the first on-chip monitoring circuit 102. If the measurement result does not deviate from the predetermined range, the calibration of the first on-chip monitoring circuit may be valid and complete.

[0043] In one implementation, the first on-chip monitoring circuit 102 may be an on-chip monitoring circuit to be calibrated, and the second on-chip monitoring circuit 104 may be an on-chip monitoring circuit that monitors a calibration of the on-chip monitoring circuit 102 to be calibrated. For example, the monitoring on-chip monitoring circuit 104 may measure a supply voltage VDD of the on-chip monitoring circuit 102 to be calibrated during the calibration of the on-chip monitoring circuit 102 to be calibrated. The controller 106 may receive a plurality of measurement results of the supply voltage VDD from the monitoring on-chip monitoring circuit 104 within a predetermined time.The control device 106 can control the calibration of the on-chip monitoring circuit 102 to be calibrated in accordance with a combination of the plurality of measurement results obtained. Additionally or alternatively, the control device 106 can detect whether at least one of the plurality of measurement results deviates from a predetermined range.

[0044] Fig. 2 shows a graph illustrating a supply voltage VDD of the on-chip monitoring circuit 102 to be calibrated during a calibration. The calibration of the on-chip monitoring circuit 102 to be calibrated may require a predetermined time period t1, which is referred to below as calibration phase t1. During the calibration phase t1, the monitoring on-chip monitoring circuit 104 may perform ten measurements of the supply voltage VDD and may provide ten measurement results 1, 2, 3, ... 10 to the control device 106. The control device 106 may check each of the ten measurement results 1, 2, 3, ... 10 to determine whether it deviates from a predetermined or predefined voltage range, which is determined by a lower voltage level VDDmin and an upper voltage level VDDmax. For example, as in Fig. 2, the measurement results numbered 4 and 5 exceed the upper voltage level VDDmax, and the measurement result numbered 8 falls below the lower voltage level VDDmin. Since at least one of the measurement results deviates from the predetermined range, the controller 106 may flag the calibration of the on-chip monitoring circuit 102 to be calibrated as invalid. Additionally, the controller 106 may control the calibration of the on-chip monitoring circuit 102 by initiating a repetition of the calibration.

[0045] In principle, substantial variations in operating conditions can prevent accurate calibration of the on-chip monitoring circuit 102 to be calibrated. For example, significant variations in the supply voltage VDD can prevent accurate calibration of the on-chip monitoring circuit 102 to be calibrated. By continuously monitoring the supply voltage VDD during the calibration phase t1 of the on-chip monitoring circuit 102 to be calibrated, a calibration corruption caused by temporal variations in the supply voltage VDD can be detected. The calibration of the on-chip monitoring circuit 102 to be calibrated can be marked as invalid and discarded if the supply voltage VDD varies significantly during the calibration phase t1, i.e., if the supply voltage VDD is not stable.The calibration of the on-chip monitoring circuit 102 to be calibrated can be interrupted and restarted.

[0046] Fig. 3 shows another graph illustrating a supply voltage VDD of the on-chip monitoring circuit to be calibrated during a calibration. The calibration of the on-chip monitoring circuit 102 to be calibrated may take a predetermined time period t2, which is referred to as calibration phase t2. During the calibration phase t2, the monitoring on-chip monitoring circuit 104 may perform ten measurements of the supply voltage VDD and may provide ten measurement results 1, 2, 3, ... 10 to the control device 106. Each of the ten measurement results 1, 2, 3, ... 10 may lie within a predetermined or predefined voltage range, which is determined (defined) by a lower voltage level VDDmin and an upper voltage level VDDmax.Accordingly, the controller 106 may mark the calibration of the on-chip monitoring circuit 102 to be calibrated as valid, and the calibration of the on-chip monitoring circuit 102 to be calibrated may be completed.

[0047] During the calibration phase t2 of the on-chip monitoring circuit 102 to be calibrated, no significant variations in the supply voltage VDD may occur, and the calibration of the on-chip monitoring circuit 102 to be calibrated may be undisturbed. An accurate calibration of the on-chip monitoring circuit to be calibrated can be performed with the supply voltage VDD, which is stable during the calibration phase t2.

[0048] Fig. 4 shows a schematic circuit diagram of another exemplary circuit arrangement 400, which includes a plurality of on-chip monitoring circuits 402, 404, 408, and 410 and a controller 406. The plurality of on-chip monitoring circuits 402, 404, 408, and 410 are arranged in a network, and each of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 can be coupled to all of the other plurality of on-chip monitoring circuits 402, 404, 408, and 410. The controller 406 is coupled to the network of on-chip monitoring circuits 402, 404, 408, and 410 and is configured to receive measurement results therefrom. The controller 406 is further configured to generate an output 412 in accordance with an evaluation of the measurement results. At least one feedback loop 414 is coupled to the controller 406 and the network.The at least one feedback loop 414 is configured to control a calibration of at least one 402 of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 in accordance with the output 412.

[0049] Each of the plurality of on-chip monitoring circuits 402, 404, 408 and 410 may be configured to measure one or more parameters of the semiconductor chip, as described above in connection with Fig. 1. The controller 406 may provide the output 412 based on a combination of measurement results received from the plurality of on-chip monitoring circuits 402, 404, 408, and 410.

[0050] In one embodiment, one of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 may be an on-chip monitoring circuit to be calibrated (e.g., on-chip monitoring circuit 402). The remaining on-chip monitoring circuits 404, 408, and 410 may oversee the calibration of the on-chip monitoring circuit to be calibrated. For example, the on-chip monitoring circuit 402 to be calibrated may be a temperature monitor, the first supervisory on-chip monitoring circuit 404 may be a supply voltage monitor, the second supervisory on-chip monitoring circuit 408 may be a process monitor, and the third supervisory on-chip monitoring circuit 410 may be an aging monitor.During a calibration phase of the temperature monitoring device 402 to be calibrated, each of the supervising on-chip monitoring circuits 404, 408, and 410 can provide measurement results to the control device 406. The control device 406 can combine the measurement results obtained from the supervising on-chip monitoring circuits 404, 408, and 410. For example, the control device can check whether the supply voltage deviates from a predetermined voltage range and, in doing so, can take into account the status of the semiconductor chip with regard to the process and aging. In principle, by supervising the on-chip monitoring circuits 404, 408, and 410, the control device 406 can detect variations in operating conditions during the calibration phase of the temperature monitoring device 402 to be calibrated.Depending on the measurement results obtained, the control device 406 can mark the calibration of the temperature monitoring device 402 to be calibrated as valid or invalid.

[0051] The controller 406 may provide a signal at output 412 based on a combination of the measurement results obtained from the monitoring on-chip monitoring circuits 404, 408, and 410. The signal at output 412 may be provided to the network of on-chip monitoring circuits 402, 404, 408, and 410 via the feedback loop 414. The feedback loop 414 may control the calibration of the temperature monitoring device 402 to be calibrated. For example, the controller 406 may initiate a restart of a calibration of the temperature monitoring device 402 to be calibrated via the feedback loop 414. By combining the measured values ​​obtained from the multiple monitoring sources 404, 408 and 410, the calibration accuracy of the on-chip monitoring circuit 402 to be calibrated can be improved.

[0052] The circuit arrangement 400, as in connection with Fig. 4, has only one feedback loop 414. In one embodiment, the circuitry 400 may have multiple feedback loops. For example, each of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 may be coupled to the controller 406 via a feedback loop. The controller 406 may control calibration of each of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 via the feedback loop, and supervised calibration of some or all of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 may be performed simultaneously or sequentially.

[0053] In one implementation, circuitry 400 may include a network of autonomously operating on-chip monitoring circuits 402, 404, 408, and 410. Controller 406 may control operation of the network of autonomously operating on-chip monitoring circuits 402, 404, 408, and 410. On-chip monitoring circuits 402, 404, 408, and 410 may operate independently of one another. For example, controller 406 may start or restart calibration of the network of autonomously operating on-chip monitoring circuits 402, 404, 408, and 410. The calibration of the network of autonomously operating on-chip monitoring circuits 402, 404, 408 and 410 can be performed without further interaction.

[0054] With reference to Fig. 1 and Fig. 4, a calibration of the on-chip monitoring circuit 102 and 104 to be calibrated can be performed during the manufacture of the semiconductor chip, which has the on-chip monitoring circuits 102 and 104 to be calibrated. For example, the calibration can be performed before and / or after mounting and housing / packaging of the semiconductor chip. Additionally or alternatively, the calibration of the on-chip monitoring circuit 102 and 104 to be calibrated can be performed during runtime. For example, the calibration can be performed each time the semiconductor chip is set or reset and / or each time operating conditions of the semiconductor chip change, such as changing the supply voltage VDD and / or the clock frequency.

[0055] With reference to Fig. 1 and Fig. 4, in one embodiment, the plurality of on-chip monitoring circuits 102 and 104 and the network of on-chip monitoring circuits 402, 404, 408, and 410 may be configured to operate simultaneously, i.e., they may be configured to measure parameters of the semiconductor chip simultaneously. Referring to Fig. 4, for example, during the calibration of the temperature monitoring device 402, the temperature monitoring device 402, the supply voltage monitoring device 404, the process monitoring device 408, and the aging monitoring device 404 can be operated or operate simultaneously. The control device 406 can start or activate the network of on-chip monitoring circuits 402, 404, 408, and 410 at the same time, and the network of on-chip monitoring circuits 402, 404, 408, and 410 can be active at the same time. The on-chip monitoring circuits 404, 408, and 410 can have different measurement times. For example, the aging monitor 410 may have a longer measurement time than the supply voltage monitor 404. Consequently, the end times of the measurement phases may be different, even though the measurement phases of the on-chip monitoring circuits 404, 408, and 410 begin at the same time.

[0056] With reference to Fig. 1 and Fig. 4, at least two of the on-chip monitoring circuits of the plurality of on-chip monitoring circuits 102 and 104, or of the network of on-chip monitoring circuits 402, 404, 408, and 410, may be of the same type. For example, at least two on-chip monitoring circuits may measure the same parameter of the semiconductor chip. Additionally or alternatively, at least two on-chip monitoring circuits may be constructed in the same or similar manner. For example, on-chip monitoring circuits 402 and 404 may be monitors, and on-chip monitoring circuits 408 and 410 may be supply voltage monitoring circuits.

[0057] In one implementation, the plurality of on-chip monitoring circuits 102 and 104 or the network of on-chip monitoring circuits 402, 404, 408, and 410 may be arranged in different regions of the semiconductor chip and may form a monitoring system. For example, the at least two on-chip monitoring circuits of the same type may be arranged in different regions of the semiconductor chip. At least two on-chip monitoring circuits may measure a temperature of the semiconductor chip, and they may be arranged at different locations on the semiconductor chip, since regions of the semiconductor chip may have different local temperatures or may operate at different local temperatures.Additionally or alternatively, at least two on-chip monitoring circuits can measure a supply voltage of the semiconductor chip at different locations on the semiconductor chip, since regions of the semiconductor chip can have or be operated at different local supply voltages.

[0058] Each of the plurality of on-chip monitoring circuits 102 and 104, as described in connection with Fig. 1, and each on-chip monitoring circuit of the network of on-chip monitoring circuits 402, 404, 408 and 410 as described and illustrated in connection with Fig. 4, may be implemented or provided in a dedicated circuit block. Additionally or alternatively, the controller 106 and 406 may be implemented as a dedicated circuit or it may be implemented in a processor. For example, the controller 106 and 406 may be implemented in a programmable microcontroller, a digital signal processor, or an application-specific processor equipped with local memory.

[0059] The plurality of on-chip monitoring circuits 102 and 104 and the network of on-chip monitoring circuits 402, 404, 408 and 410, as described in connection with Fig. 1 and Fig. 4 described and illustrated, can be self-calibrating. As described in conjunction with Fig. 1 and Fig. 4, the controller 106 and 406 may start a calibration of a self-calibrating on-chip monitoring circuit 102 and 402. If the calibration is invalid, the controller 106 and 406 may initiate a restart of the calibration. Otherwise, the calibration is valid and complete. Except for the start or restart, the operation of the self-calibrating on-chip monitoring circuit 102 and 402 may be unaffected by the controller 106 and 406.

[0060] Fig. 5 shows a schematic circuit diagram of a self-calibrating on-chip monitoring circuit 502. The self-calibrating on-chip monitoring circuit 502 includes a measurement circuit 518, a logic circuit 520, and a configuration register 522. The configuration register 522 is coupled to the measurement circuit 518 and can control operation of the measurement circuit 518. The measurement circuit 518 can receive a control signal 514, which can be provided by a controller, for example, by the controller 106 in Fig. 1 or by the control device 406 in Fig. 4. The control signal 514 can initiate a start or restart of a calibration by starting or restarting a measurement of a chip parameter within the measurement circuit 518. The logic circuit 520 is coupled to the measurement circuit 518 and the configuration register 522. The logic circuit 520 can receive a measurement result of a chip parameter from the measurement circuit 518 and can control a setting (or writing) of the configuration register 522 in response to the received measurement result. For example, the measurement circuit 518 can have an internal delay line, and a tap within the delay line can be adjusted according to the setting of the configuration register 522. The calibration of the self-calibrating on-chip monitoring circuit 502 can be performed by repeatedly measuring the chip parameter and repeatedly adjusting the setting of the configuration register 522.In principle, the calibration can be performed after starting or restarting a calibration of the self-configuring on-chip monitoring circuit 502 and can be completed without any interaction with other circuits outside the self-calibrating on-chip monitoring circuit 502.

[0061] Alternatively, the plurality of on-chip monitoring circuits 102 and 104 may be configured to form the network of on-chip monitoring circuits 402, 404, 408, and 410, as described in connection with Fig. 1 and Fig. 4, on-chip monitoring circuits with external calibration. Unlike a self-calibrating on-chip monitoring circuit, an on-chip monitoring circuit with external calibration can interact with circuits outside the on-chip monitoring circuit multiple times during a calibration phase.

[0062] Fig. 6 shows a schematic circuit diagram of an on-chip monitoring circuit with external calibration 602. The on-chip monitoring circuit with external calibration 602 includes a measurement circuit 618 and a configuration register 622, referred to herein as calibration control word 622. A control signal 614 may initiate a start or restart of a calibration by starting or restarting a measurement of a chip parameter within the measurement circuit 618. The measurement circuit 618 is coupled to the calibration control word 622, which may configure a setting of the measurement circuit 618. A setting of the calibration control word 622 may be controlled by a signal 624. The signal 624 may be provided by a controller, for example, by the controller 106 in Fig. 1 or by the control device 406 in Fig. 4. That is, the controller may control the calibration of the on-chip monitoring circuit with external calibration 602 by adjusting a setting of the calibration control word 622. Referring to Fig. 4, for example, the feedback loop 414 may control the calibration by adjusting the calibration control word 622 in accordance with the output 412. During calibration of the on-chip monitoring circuit with external calibration 602, the calibration control word 620 may be updated several times.

[0063] In principle, calibration of the plurality of on-chip monitoring circuits 102 and 104 and the network of on-chip monitoring circuits 402, 404, 408 and 410, as described in connection with Fig. 1-6, by adjusting the monitoring functionality by adjusting the configuration registers 522 and 622, as described in connection with Fig. 5 and Fig. 6. As described and illustrated above in connection with Fig. 5, an internal delay line can be adjusted in accordance with the setting of the configuration register 522 and 622. Additionally or alternatively, a measuring range, a measuring resolution, a measuring time, an internal data flow, an internally locally generated voltage, an internally locally generated current, an internal local capacitance, an internal resistance, an internal frequency, or an internal phase difference can be adjusted within the on-chip monitoring circuit.

[0064] Each of the plurality of on-chip monitoring circuits 102 and 104 and the network of on-chip monitoring circuits 402, 404, 408 and 410, as described in connection with Fig. 1 and Fig. 4, can operate in one of three different modes: a calibration mode, a measurement mode, or a power-off mode. In the power-off mode, a power supply to at least one of the on-chip monitoring circuits 102, 104, 402, 404, 408, and 410 can be turned off to conserve energy.

[0065] The circuit arrangements 100 and 400, as used in connection with Fig. 1 and Fig. 4, can be operated in one of two different modes, an attended calibration mode and an attended measurement mode. In the attended calibration mode, the circuitry 100 and 400 can operate as in conjunction with Fig. 1 to 6. The supervised on-chip monitoring circuitry 102 and 402 may be operated in the calibration mode, and the supervising on-chip monitoring circuitry 104, 404, 408, and 410 may be operated in the measurement mode.

[0066] In the following, in connection with Fig. 4 the supervised measurement mode is described. However, it should be noted that the supervised or monitored measurement mode also applies to the Fig. 1 may be used. In the supervised measurement mode, each of the plurality of on-chip monitoring circuits 402, 404, 408, and 410 may operate in the measurement mode. During a measurement phase, one 402 of the plurality of on-chip monitoring circuits 402, 404, 408, and 410, which shall be referred to below as characterizing on-chip monitoring circuit 402, may provide measurement results of a chip parameter to be measured or characterized. The other on-chip monitoring circuits 404, 408 and 410 of the plurality of on-chip monitoring circuits 402, 404, 408 and 410, which shall be referred to as supervising on-chip monitoring circuits 404, 408 and 410 hereinafter, may provide measurement results of chip parameters to be monitored or supervised during the measurement phase.

[0067] The controller 406 may receive the measurement results from the characterizing on-chip monitoring circuit 402 and from the supervisory on-chip monitoring circuits 404, 408, and 410. The controller 406 may combine the measurement results received from the supervisory on-chip monitoring circuits 404, 408, and 410. For example, the controller 406 may detect or determine if at least one of the measurement results received from the supervisory on-chip monitoring circuits 404, 408, and 410 deviates from a predetermined range.The controller 406 may mark the measurement results received from the characterizing on-chip monitoring circuit 402 as invalid if at least one of the measurement results from the supervisory on-chip monitoring circuits 404, 408, and 410 deviates from the predetermined range, and the controller 406 may initiate a repeat of the measurement phase. If none of the measurement results from the supervisory on-chip monitoring circuits 404, 408, and 410 deviate from the predetermined range, the measurement results received from the characterizing on-chip monitoring circuit 402 may be marked as valid, and the measurement phase may be completed.

[0068] The control device 406 may provide a further output 416 in accordance with a combined evaluation of the measurement results it receives from the plurality of on-chip monitoring circuits 402, 404, 408, and 410. A signal may be provided at the further output 416 if the measurement results received from the characterizing on-chip monitoring circuit 402 are marked as valid. A further circuit may receive the signal provided by the further output 416, and the further circuit may be configured to adjust a parameter of the semiconductor chip in response to the signal. The parameter to be adjusted may be one of the parameters that are associated with Fig. 1 above. Basically, the control device 406 is configured to adjust a parameter of the semiconductor chip in accordance with a combination of the measurement results it can receive from the plurality of on-chip monitoring circuits 402, 404, 408, and 410 if the measurement results received from the characterizing on-chip monitoring circuit 402 are identified as valid.

[0069] For example, in the supervised measurement mode, a supervised measurement of a temperature of the semiconductor chip or a portion of the semiconductor chip can be performed. The characterizing on-chip monitoring circuit 402 can be a temperature monitor, the supervising on-chip monitoring circuit 404 can be a supply voltage monitor, the supervising on-chip monitoring circuit 408 can be an aging monitor, and the supervising on-chip monitoring circuit 410 can be a process monitor. During a temperature measurement phase, the control device 406 can receive measurement results from the characterizing temperature monitor 402. In addition, the control device 406 can collect measurement results from the supervising on-chip monitoring circuits 404, 408, and 410.The controller 406 may check each of the measurement results received from the supervisory on-chip monitoring circuits 404, 408, and 410 to determine whether it deviates from a predetermined range. If none of the measurement results received from the supervisory monitoring circuits 404, 408, and 410 deviate from the predetermined range, the measurement results received from the temperature monitoring device 402 may be marked as valid. Otherwise, the measurement results received from the temperature monitoring device 402 may be marked as invalid.

[0070] For example, the control device 406 can detect, by means of the supply voltage monitoring device 404, a sudden IR drop (ohmic voltage drop), which can occur during the temperature measurement phase and which can falsify the measurement performed by the temperature monitoring device 402. In the event of a sudden IR drop, the measurement results received by the temperature monitoring device 402 can be marked as invalid. If the measurement results received by the temperature monitoring device 402 are marked as valid, the control device 406 can provide a signal at the further output 416, which can correspond to the temperature measured during the measurement phase. A further circuit can receive the signal provided at the further output 416, and the further circuit can, for example, adjust the clock frequency of the semiconductor chip according to the signal.For example, the further circuit may reduce a frequency of a clock of the semiconductor chip if the temperature measured by the temperature monitoring device 402 has increased. If the CMOS circuit performance decreases with decreasing temperature, such as in modern CMOS technologies with minimum feature sizes below 65 nm, for example, at 45 nm technology nodes or 28 nm technology nodes, or in ultra-low VDD (positive supply voltage of MOS circuits) operating states with VDD voltages less than 1 volt, the further circuit may reduce the frequency or increase the supply voltage to prevent a system crash. In principle, the further circuit may initiate a countermeasure in accordance with the signal received from the further output 416.

[0071] In principle, in the supervised measurement mode, the control device 406 can determine a status of the semiconductor chip based on the measurement results received from the characterizing on-chip monitoring circuit 402 and from the supervising on-chip monitoring circuits 404, 408, and 410. A signal provided at the further output 416 can correspond to or characterize the status of the semiconductor chip. A further circuit can be coupled to the further output 416 of the semiconductor circuit 400, and the further circuit can change the status of the semiconductor chip in response to the signal received from the further output 416. By supervising one or more chip parameters during a measurement phase of a chip parameter to be characterized, an accurate measurement of the chip parameter to be characterized can be enabled.It can be detected whether significant temporal variations in the monitored chip parameters distort or impair the measurement of the chip parameter being characterized. This prevents the status of the semiconductor chip from being erroneously changed.

[0072] The controller 406 may calculate the status of the semiconductor chip according to a predefined algorithm. As described in connection with Fig. 1 described above, for example, the controller 406 may check whether the measurement results received from the supervisory on-chip monitoring circuits 404, 408, and 410 deviate from a predetermined range. Additionally or alternatively, the controller 406 may apply a different algorithm to the measurement results received from the plurality of on-chip monitoring circuits 402, 404, 408, and 410. For example, the controller 406 may perform an averaging of the measurement results or may compare the measurement results to a predetermined threshold.

[0073] The further circuit may be implemented on the same semiconductor chip as the plurality of on-chip monitoring circuits 402, 404, 408, and 410, i.e., they may be implemented on the same silicon substrate. Alternatively, the further circuit may be implemented on a different semiconductor chip or silicon substrate. The further circuit may include at least one power management circuit, a clock generator, a clock circuit, a programmable delay element in clock paths and combinational logic paths, and / or a wake-up circuit of a computing circuit.The further circuit can change the state of the semiconductor chip by changing a supply voltage and / or a substrate voltage of an nFET transistor (n-channel FET transistor) and / or a pFET transistor (p-channel FET transistor) and / or a clock frequency and / or a propagation delay in clock paths and combination logic paths. Additionally or alternatively, the further circuit can change the state of the semiconductor chip by blocking the propagation of clock edges into a block and / or by activating an additional computing circuit.

[0074] As in connection with Fig. 1 and Fig. 4 above, each on-chip monitoring circuit of the plurality of on-chip monitoring circuits 102 and 104 and of the network of on-chip monitoring circuits 402, 404, 408, and 410 may provide multiple measurement results to the controller 106 and 406 during a measurement phase or a calibration phase. Alternatively, at least one of the plurality of on-chip monitoring circuits 102 and 104 and of the network of on-chip monitoring circuits 402, 404, 408, and 410 may provide only one measurement result to the controller 106 and 406 during a measurement phase or a calibration phase. The controller 106 and 406 may combine the one or more measurement results received from the plurality of on-chip monitoring circuits 102 and 104 and the network of on-chip monitoring circuits 402, 404, 408, and 410.

[0075] Fig. 7 shows another exemplary circuit arrangement 700, which includes a plurality of on-chip monitoring circuits 702, 704, 708, and 710 and a controller 706. Additionally, the circuit arrangement 700 includes a plurality of post-processors 718, 720, 722, and 724 and a calibration circuit 726. Each of the post-processors 718, 720, 722, and 724 may be coupled to a dedicated on-chip monitoring circuit 702, 704, 708, and 710. Each of the post-processors 718, 720, 722 and 724 may receive measured raw data 726, 728, 730 and 732 from the dedicated on-chip monitoring circuitry 702, 704, 708 and 710 and may perform data conversion into a digital output signal 734, 746, 738 and 740. The digital data output 734, 736, 738 and 740 of each of the post-processors 718, 720, 722 and 724 may be provided to the controller 706.The data conversion within the post-processors 718, 720, 722 and 724 may include at least one analog-to-digital conversion and / or a comparison and / or a lookup table functionality and / or a signal processing functionality, such as filtering, averaging, minimum and maximum functions or arithmetic logic calculations.

[0076] The plurality of post-processors 718, 720, 722, and 724 may be coupled to the controller 706, and operation of the plurality of post-processors 718, 720, 722, and 724 may be controlled by post-processor control signals 742, 745, 746, and 748 provided by the controller 706. For example, the controller 706 may configure an operating mode of the plurality of post-processors 718, 720, 722, and 724 via the post-processor control signals 742, 744, 746, and 748.

[0077] The controller 706 may further provide monitoring control signals 750, 752, 754, and 756 to the plurality of on-chip monitoring circuits 702, 704, 708, and 710, and may control operation of the plurality of on-chip monitoring circuits 702, 704, 708, and 710 using the monitoring control signals 750, 752, 754, and 756. For example, the controller 706 may start, stop, or restart the plurality of on-chip monitoring circuits 702, 704, 708, and 710, or may place the plurality of on-chip monitoring circuits 702, 704, 708, and 710 in a calibration mode, a measurement state, and / or a power-off state. Change mode.

[0078] The controller 706 may provide an output signal 716 corresponding to the chip status or the state of the chip. The output signal 716 may be determined by a combined evaluation of the post-processor measurement results 734, 736, 738, and 740 from the plurality of on-chip monitoring circuits 702, 704, 708, and 710.

[0079] Calibration circuitry 726 may be coupled to controller 706 and the plurality of on-chip monitoring circuits 702, 704, 708, and 710, and may control operation of the plurality of on-chip monitoring circuits 702, 704, 708, and 710 during a calibration phase. Calibration circuitry 726 may receive a calibration control signal 758 from controller 706 and may receive information regarding a calibration waiting or stopping and / or a calibration validity or invalidity via control signal 758. At an output 712, the calibration circuit 726 may provide a control signal to the plurality of on-chip monitoring circuits 702, 704, 708, and 710 via a feedback loop 714.

[0080] The calibration circuit 726 may initiate a start or restart of a calibration of at least one of the plurality of on-chip monitoring circuits 702, 704, 708, and 710 via the feedback loop 714.

[0081] As in Fig. 7, each of the post-processors 718, 720, 722, and 724 may be coupled to a dedicated on-chip monitoring circuit 702, 704, 708, and 710. Alternatively, at least two of the plurality of on-chip monitoring circuits 702, 704, 708, and 710 may be coupled to a common post-processor.

[0082] Combined with Fig. Implementations described and illustrated in Figures 1 to 7 may enable accurate calibration of on-chip monitoring circuits and accurate measurement of chip parameters despite transient variations in operating conditions. The circuit arrangements 100, 400, and 700, as described in connection with Fig. 1 to 7, these variations can be detected and the calibration or measurement can be repeated. All or part of the circuit arrangements 100, 400, and 700 can be implemented digitally. Consequently, implementations of the circuit arrangements 100, 400, and 700 can have a small footprint, and the power consumption of the circuit arrangements 100, 400, and 700 can be low.

[0083] Features of the implementations, as in connection with Fig. 1 to 7 may be combined, unless explicitly stated otherwise. For example, in one implementation, the circuit arrangement 100 may be Fig. 1 may have more than two on-chip monitoring circuits and / or the on-chip monitoring circuits of the circuit arrangement 100 may be connected to one another, similar to the case in connection with Fig. 4. In a further implementation, the plurality of on-chip monitoring circuits 402, 404, 408 and 410, as described in connection with Fig. 4, may not be interconnected in a similar manner to the circuit arrangement 100 as described in connection with Fig. 1 described and illustrated.

[0084] Fig. 8 shows a system 858 comprising a circuit arrangement 800, a functional circuit 860, and a regulation circuit 862. The circuit arrangement 800 may comprise one of the circuit arrangements as described in connection with Fig. 1 to 7 above. The circuit arrangement 800 may be coupled to the regulation circuit 862 and may provide a signal at an output 816 to the regulation circuit 862. As described in connection with Fig. 4, the signal provided at output 816 may correspond to a status or condition of the semiconductor chip.

[0085] As in Fig. 8, the regulation circuit 862 may be coupled to the functional circuit 860, and the functional circuit 860 may provide at least a portion of the functionality of a semiconductor chip or perform at least a portion of the tasks of a semiconductor chip. For example, the functional circuit 860 may perform arithmetic operations or memory operations. The regulation circuit 862 may include a phase-locked loop (PLL) 864 and may provide a clock signal 866 to the functional circuit 860. Additionally or alternatively, the regulation circuit 862 may include a power management circuit (PMU) 868 and may provide a supply voltage signal 860 to the functional circuit 860.The regulation circuit 862 may adjust a frequency provided via the clock signal 866 and a voltage level provided via the supply voltage signal 870 in response to the signal provided at the output 816 of the circuit arrangement 800.

[0086] In one implementation, circuitry 800 and functional circuitry 860 may be arranged on the same semiconductor chip, i.e., they may be implemented or arranged on the same silicon substrate. During a measurement phase, circuitry 800 may determine a current state of the semiconductor chip and provide a signal at output 816 corresponding to the current status of the semiconductor chip. Regulation circuitry 862 may regulate a parameter of the semiconductor chip in response to the signal received from output 816 of circuitry 800. Regulation circuitry 862 may adjust the parameter of the semiconductor chip by changing a feature or characteristic of at least one of signals 866 and 870 provided to functional circuitry 860.For example, if the circuit arrangement 800 detects an increase in temperature, the regulation circuit 862 may reduce a frequency of the clock signal 866 provided by the functional circuit 860.

[0087] By providing circuitry 800 and functional circuitry 860 on the same semiconductor chip, circuitry 800 and functional circuitry 860 may both be subject to the same operating conditions. In one implementation, the on-chip monitoring circuitry of circuitry 800 may comprise similar CMOS circuitry as functional circuitry 860, and effects acting on functional circuitry 860 may also affect the on-chip monitoring circuitry of circuitry 800. Regulatory circuitry 862 may be implemented on the same semiconductor chip as circuitry 800 and functional circuitry 860. Alternatively, regulatory circuitry 862 may be implemented on a different semiconductor chip.

[0088] In addition to the Fig. 8, the functional circuit 860 may provide information to the circuit arrangement 800. For example, the functional circuit 860 may provide information to the circuit arrangement 800 regarding running applications and / or power requirements. Additionally or alternatively, the regulation circuit 862 may provide information to the circuit arrangement 800. For example, the regulation circuit 862 may provide information regarding operating conditions, such as upper / lower supply voltage range, to the circuit arrangement 800. The circuit arrangement 800 may provide the signal at the output 816 in accordance with the information received from the functional circuit 860 and / or the regulation circuit 862.In principle, the circuit arrangement 800 may be capable of taking into account information provided by the environment of the system in which it is implemented. Accordingly, the circuit arrangement 800 may be implemented flexibly.

[0089] Fig. 9 shows a flowchart 900 comprising a number of supervisory operations of an on-chip supervisory circuit. Fig. 10 shows a flowchart 1000 comprising a number of calibration operations of an on-chip monitoring circuit. Unless otherwise stated, the order in which the operations are described is not to be construed as limiting. Operations may be repeated, may be combined in any order, and / or may be executed in parallel to implement the process. In portions of the following description, reference may be made to the Fig. 1 to 8 and their content. The information in connection with Fig. 9 and Fig. The methods described in 10 can be realized using the implementations described above.

[0090] Referring to Fig. 9, in block 902, a measurement of at least one of a plurality of on-chip monitoring circuits is started. Each of the plurality of on-chip monitoring circuits is configured to measure a parameter of the semiconductor chip. At least one of the plurality of on-chip monitoring circuits is referred to herein as a supervising or monitoring on-chip monitoring circuit. The supervising on-chip monitoring circuit is configured to measure a parameter of the semiconductor chip, which is referred to herein as a parameter to be supervised or monitored.

[0091] In block 904, a measurement of an on-chip monitoring circuit to be supervised is started, so that, for example, the on-chip monitoring circuit to be supervised begins executing the measurement process. The on-chip monitoring circuit to be supervised is configured to measure a parameter of the semiconductor chip, which is referred to here as the parameter to be characterized.

[0092] In block 906, at least one measurement result from the supervising on-chip monitoring circuit is processed. For example, the processing may include comparing the at least one measurement result from the supervising on-chip monitoring circuit to a predetermined range.

[0093] In block 908, a measurement result from the supervised on-chip monitoring circuit is marked as invalid if at least one measurement result from the supervising on-chip monitoring circuit deviates from a predetermined range.

[0094] By monitoring the parameter to be monitored during a measurement phase of a parameter to be characterized, an accurate measurement of the parameter to be characterized can be achieved. It can be detected whether variations in the chip parameters to be monitored distort or impair the measurement of the chip parameter to be characterized.

[0095] In one implementation, the on-chip monitoring circuit to be supervised is configured to measure a parameter that is different from the parameters measured by the majority of on-chip monitoring circuits. This means that the parameter to be characterized may be different from the parameters to be supervised, which in this case act as supervisory parameters with respect to the parameter to be characterized.

[0096] In another implementation, the measurement of the on-chip monitoring circuit to be supervised is started temporally after the start of the measurement of the supervising on-chip monitoring circuit. Consequently, the supervising on-chip monitoring circuit can already measure the parameter to be supervised at the time the on-chip monitoring circuit to be supervised begins measuring the parameter to be characterized.

[0097] In a further implementation, at least the steps of blocks 902 to 906 are repeated if at least one measurement result of the on-chip monitoring circuit to be supervised is marked as invalid. The steps of blocks 902 to 906 may be repeated until at least one measurement result of the on-chip monitoring circuit to be supervised is marked as valid. Once the at least one measurement result of the on-chip monitoring parameter to be supervised is marked as valid, the measurement of the on-chip monitoring circuit to be supervised may be completed.

[0098] In further implementations, a measurement mode is activated and a parameter of the semiconductor chip is adjusted in accordance with the measurement result of the on-chip monitoring circuit to be supervised, unless the measurement result of the on-chip monitoring circuit to be supervised is marked as invalid. By adjusting the parameter of the semiconductor chip, a status or state of the semiconductor chip can be changed. The status of the semiconductor chip can be changed based on the measurement result of the on-chip monitoring circuit to be supervised. For example, countermeasures can be initiated or triggered in response to the measurement result of the on-chip monitoring circuit to be supervised. However, the countermeasure can only be triggered if the measurement result of the on-chip monitoring circuit to be monitored is marked as valid.This avoids incorrect updating of the status of the semiconductor chip.

[0099] In further implementations, a plurality of measurement results are received by the supervising on-chip monitoring circuit (which generates them) within a predetermined time, for example, by the controller. Processing the measurement results at block 906 includes processing the plurality of measurement results. By processing a plurality of measurement results, the accuracy of the measurement of the chip parameter to be characterized can be improved.

[0100] Referring to Fig.10, a plurality of on-chip monitoring circuits are activated at block 1002. The plurality of on-chip monitoring circuits are configured to measure at least one parameter of the semiconductor chip, and these on-chip monitoring circuits are referred to herein as supervisory on-chip monitoring circuits.

[0101] At block 1004, an on-chip monitoring circuit to be calibrated is activated.

[0102] At block 1006, measurement results from the supervising on-chip monitoring circuitry are combined. For example, the combining may include checking whether each of the measurement results is within a predetermined range.

[0103] At block 1008, a calibration of the on-chip monitoring circuit to be calibrated is controlled in accordance with the combination of the measurement results.

[0104] By monitoring at least one parameter of the semiconductor chip during a calibration phase of the on-chip monitoring circuit to be calibrated, an accurate calibration of the on-chip monitoring circuit to be calibrated can be enabled. It can be detected whether substantial temporal variations of at least one parameter corrupt or impair the calibration of the on-chip monitoring circuit to be calibrated.

[0105] In one implementation, controlling the calibration comprises adjusting a setting of the on-chip monitoring circuit to be calibrated. By adjusting the setting, the functionality of the on-chip monitoring circuit to be calibrated can be changed. For example, the functionality of the on-chip monitoring circuit to be calibrated can be changed with respect to the measurement characteristics of the on-chip monitoring circuit to be calibrated.

[0106] In a further embodiment, controlling the calibration comprises repeating the activation steps of blocks 1002 and 1004 and the combining step of block 1006 if at least one of the measurement results deviates from a predetermined range. If at least one measurement result deviates from a predetermined range, the calibration of the on-chip monitoring circuit to be calibrated can be marked as invalid. If none of the measurement results from the plurality of on-chip monitoring circuits has deviated from a predetermined range, the calibration of the on-chip monitoring circuit to be calibrated can be marked as valid and completed. The activation steps of blocks 1002 and 1004 and the combining step of block 1006 can be repeated until the calibration of the on-chip monitoring circuit to be calibrated is marked as valid.

[0107] In the specification and in the following claims, the term "coupled" has been used to describe how various elements are connected or linked to one another. The connection of various elements described in this way can be either direct or indirect. Although the subject matter of this application has been described in language specific to the structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are given as exemplary forms of implementation of the claims. Combining various features of the different implementations and claims to obtain variations thereof is intended to be covered within the scope of protection.

Claims

[1] A circuit arrangement (100, 400, 700), comprising: a plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), each of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) being configured to measure a parameter of a semiconductor chip; and a control device (106, 406, 706) coupled to the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), wherein the control device (106, 406, 706) is configured to receive a measurement result from at least one on-chip monitoring circuit (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) and to control a calibration of another one of the plurality of on-chip monitoring circuits (104, 404, 704) in accordance with the measurement result; wherein the control device (106, 406, 706) is configured to mark the calibration of the other of the plurality of on-chip monitoring circuits (104, 404, 704) as invalid if at least one measurement result from the at least one on-chip monitoring circuit (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) deviates from a predetermined range. [2] The circuit arrangement (100, 400, 700) of claim 1, wherein at least two on-chip monitoring circuits of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) are of the same type. [3] Circuit arrangement (100, 400, 700) according to claim 1 or 2, wherein the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) are arranged to measure parameters of the semiconductor chip simultaneously. [4] Circuit arrangement (100, 400, 700) according to one of claims 1 to 3, wherein the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) are arranged in different regions of the semiconductor chip. [5] Circuit arrangement (100, 400, 700) according to one of claims 1 to 4, wherein the control device (106, 406, 706) is arranged to control the calibration by adjusting a setting of the other of the plurality of on-chip monitoring circuits (104; 404; 704). [6] Circuit arrangement (100, 400, 700) according to one of claims 1 to 5, wherein the control device (106, 406, 706) is arranged to repeat the calibration if the measurement result deviates from a predetermined range. [7] Circuit arrangement (100, 400, 700) according to one of claims 1 to 6, wherein the control device (106, 406, 706) is arranged to receive a plurality of measurement results from at least one of the plurality of on-chip monitoring circuits (102; 402; 702) within a predetermined time and to control the calibration in accordance with a combination of the plurality of measurement results. [8] Circuit arrangement (100, 400, 700) according to one of claims 1 to 7, wherein the control device (106, 406, 706) is arranged to receive a plurality of measurement results from the plurality of on-chip monitoring circuits (102; 402; 702) and to detect whether at least one of the plurality of measurement results deviates from a predetermined range. [9] Circuit arrangement (100, 400, 700) according to one of claims 1 to 8, wherein the control device (106, 406, 706) is arranged to adapt a parameter of the semiconductor chip in accordance with a combination of the plurality of measurement results if none of the plurality of measurement results deviates from a predetermined range. [10] A circuit arrangement (400, 700) comprising: a plurality of on-chip monitoring circuits (402, 404; 702, 704) arranged in a network, each of the plurality of on-chip monitoring circuits (402, 404; 702, 704) being configured to measure at least one parameter of a semiconductor chip; a control device (406, 706) coupled to the network of on-chip monitoring circuits, wherein the control device (406, 706) is configured to receive measurement results from the plurality of on-chip monitoring circuits (402; 702) and to generate an output in accordance with an evaluation of the measurement values; and at least one feedback loop (414, 714) coupled to the control device (406, 706) and the network, wherein the at least one feedback loop (414, 714) is configured to control a calibration of at least one on-chip monitoring circuit (404, 704) to be calibrated from the plurality of on-chip monitoring circuits (402, 404; 702, 704) in accordance with the output; wherein the control device (406, 706) is configured to mark the calibration as invalid if at least one measurement result of at least one on-chip monitoring circuit (402, 702) monitoring the calibration from the plurality of on-chip monitoring circuits (402, 404; 702, 704) deviates from a predetermined range. [11] Circuit arrangement (400, 700) according to claim 10, wherein the control device (406, 706) is arranged to adapt a parameter of the semiconductor chip in accordance with a combination of measurement results. [12] The circuit arrangement (400, 700) of claim 10 or 11, wherein at least one of the plurality of on-chip monitoring circuits (402, 404; 702, 704) comprises a calibration control word, and wherein the feedback loop (414, 714) is configured to control the calibration by adjusting the calibration control word in accordance with the output. [13] Circuit arrangement (400, 700) according to one of claims 10 to 12, wherein the network of the plurality of on-chip monitoring circuits is arranged to be operated simultaneously. [14] Circuit arrangement (400, 700) according to one of claims 10 to 13, wherein the plurality of on-chip monitoring circuits (402, 404; 702, 704) is implemented in a dedicated circuit block and wherein the control device (406, 706) is implemented in a processor. [15] A method (900) for supervising an on-chip monitoring circuit of a semiconductor chip, the method comprising: (a) starting (902) a measurement of at least one (102, 402, 702) of a plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), each of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) being configured to measure a parameter of the semiconductor chip; (b) starting (904) a measurement of an on-chip monitoring circuit (104, 404, 704) to be supervised, wherein the on-chip monitoring circuit (104, 404, 704) to be supervised is configured to measure a parameter of the semiconductor chip; (c) processing (906) at least one measurement result from the at least one (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704); and (d) Indicating (908) that a measurement result of the on-chip monitoring circuit (104, 404, 704) to be supervised is invalid if at least one measurement result of the at least one (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) that supervises the on-chip monitoring circuit (104, 404, 704) to be supervised deviates from a predetermined range. [16] The method of claim 15, wherein the on-chip monitoring circuit (104, 404, 704) to be supervised is configured to measure a parameter that is different from the parameters measured by the plurality of on-chip monitoring circuits (102, 402, 702). [17] Method according to claim 15 or 16, wherein starting the measurement of an on-chip monitoring circuit (104, 404, 704) to be supervised occurs temporally after starting the measurement of at least one (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704). [18] A method according to any one of claims 15 to 17, further comprising: Repeating at least steps (a) to (c) if at least one measurement result of the on-chip monitoring circuit (104, 404, 704) to be supervised is marked as invalid. [19] Method according to one of claims 15 to 18, further comprising: Activating a measurement mode and adjusting a parameter of the semiconductor chip in accordance with the measurement result of the on-chip monitoring circuit (104, 404, 704) to be supervised if the measurement result of the on-chip monitoring circuit (104, 404, 704) to be supervised is not marked as invalid. [20] A method according to any one of claims 15 to 19, further comprising: Receiving a plurality of measurement results from the at least one (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) within a predetermined time, wherein processing the measurement results in step (c) comprises processing the plurality of measurement results. [21] A method (1000) for calibrating an on-chip monitoring circuit, the method comprising: (a) activating (1002) a plurality of on-chip monitoring circuits (102, 402, 702) configured to measure at least one parameter of a semiconductor chip; (b) activating (1004) an on-chip monitoring circuit (104, 404, 704) to be calibrated; (c) combining (1006) the measurement results from the plurality of on-chip monitoring circuits (102, 402, 702); (d) controlling (1008) a calibration of the on-chip monitoring circuit (104, 404, 704) to be calibrated in accordance with the combination of the measurement results; and e) Indicating that the calibration of the on-chip monitoring circuit (104, 404, 704) to be calibrated is invalid if at least one measurement result of at least one on-chip monitoring circuit (102; 402; 702) monitoring the calibration of the plurality of on-chip monitoring circuits (102; 402; 702) deviates from a predetermined range. [22] The method of claim 21, wherein the calibration comprises adjusting a setting of the on-chip monitoring circuit (104, 404, 704) to be calibrated. [23] A method according to claim 21 or 22, wherein controlling a calibration comprises repeating the first (a) and second (b) activation steps and the combining step (c) if at least one measurement result deviates from a predetermined range. [24] A system (858) comprising: a circuit arrangement (800) comprising: a plurality of on-chip monitoring circuits, each of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) being configured to measure a parameter of a semiconductor chip; a control device (106, 406, 706) coupled to the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704), wherein the control device (106, 406, 706) is configured to receive a measurement result from at least one (102, 402, 702) on-chip monitoring circuit of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) and to control a calibration of another (104, 404, 704) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) in accordance with the measurement result, wherein the control device (106, 406, 706) is configured to mark the calibration as invalid if the measurement result from the at least one on-chip monitoring circuit (104, 404, 704) monitoring the calibration from the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) deviates from a predetermined range; a functional circuit (860) configured to perform a function of the semiconductor chip; and a regulation circuit (862) coupled to the circuit arrangement (800) and the functional circuit (860), wherein the regulation circuit (862) is configured to regulate a parameter of the functional circuit (860) in accordance with at least one measurement result of at least one (102, 402, 702) of the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704). [25] The system of claim 24, wherein the plurality of on-chip monitoring circuits (102, 104; 402, 404; 702, 704) and the functional circuit (860) are arranged on the semiconductor chip.

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