Storage device and non-volatile storage device and operating methods thereof

Abstract

Storage device (120) comprising the following: a user area (126) of a memory cell arrangement; a buffer area (124) configured to temporarily store compressed data to be written to the user area (126); and a management logic (123, 1370, 6213) for compressed data, which is configured to control the user space (126) and the buffer space (124) such that compressed data stored in the buffer space (124) is written to the user space (126), where the management logic (123, 1370, 6213) for compressed data manages compressed data which is to be written to the user area (126) using an ECC block unit, where during a write operation compressed data which is stored in the buffer area (124) is written to the user area (126) with a programming unit which is larger than the ECC block unit.

Description

BACKGROUND 1. Technical field

[0001] The inventive concepts described herein relate to a storage device, and more specifically to a non-volatile storage device and a method of operation thereof. 2. Discussion of the state of the art

[0002] Semiconductor memory devices use memory devices that include volatile memory types, such as dynamic RAM (DRAM), static RAM (SRRAM), and the like, and non-volatile memory types, such as electrically erasable and programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), flash memory, and the like. Volatile memory loses its stored contents when the device is powered off, while non-volatile memory retains its stored contents even when powered off.

[0003] In recent years, the number and types of consumer electronics devices (CEDs) using non-volatile memory have increased. For example, MP3 players, digital cameras, mobile phones, camcorders, flash cards, and solid-state drives (SSDs) can all use non-volatile memory as a data storage device. Flash memory is a type of non-volatile storage that can electrically erase data from individual cells within a block. This allows flash memory to be widely used as a storage device in place of a hard disk drive.

[0004] As the storage capacity required by the user increases, a technique for efficiently utilizing the storage space of a flash memory is desirable.

[0005] US Patent 2011 / 0154160A1 discloses a system and a method for error correction of tax data in a storage device. SUMMARY

[0006] Exemplary embodiments of the inventive concept provide a storage device comprising a user area consisting of a (non-volatile) memory cell arrangement; a buffer area (e.g., RAM) configured to temporarily store compressed data to be written to the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written to the user area. The compressed data management logic manages compressed data to be written to the user area using an ECC block unit (e.g., multiple pages).During a programming operation, compressed data collected and stored in the buffer area is written to the user area with a programming unit (e.g., one or more page sizes) larger than the ECC block unit.

[0007] In exemplary embodiments, the ECC block unit is a bit size that ensures the reliability of the compressed data to be written to the user space.

[0008] In exemplary embodiments, the ECC block unit has a data bit area, which is user data information, and an ECC bit area, which is used to detect and correct an error in the data bit area.

[0009] In exemplary embodiments, the programming unit is an integer multiple of the ECC block unit.

[0010] In exemplary embodiments, the buffer area temporarily stores first compressed data and second compressed data, and the compressed data management logic programs the collected first and second compressed data into the same page in the user area.

[0011] In exemplary embodiments, the storage device further includes a compressor configured to compress write-requested raw data; and an ECC circuit configured to add an ECC bit to raw data compressed by the compressor to produce compressed data to be written to user space.

[0012] In exemplary embodiments, the storage device further includes a compressed data management table configured to manage location information of compressed data stored in the user space, wherein the compressed data management table manages location information of compressed data stored in the user space by means of an ECC block unit smaller than the programming unit (for example, one or more page sizes) according to a compressed data management logic control.

[0013] In exemplary embodiments, the compressed data management table manages information associated with the physical address of compressed data stored in the user space, information associated with the starting number of the ECC block of the compressed data stored in the user space, and information associated with the ECC block length of the compressed data stored in the user space.

[0014] In exemplary embodiments, the compressed data management table further manages information that is linked to a logical address which corresponds to the physical address of the compressed data stored in the user space.

[0015] In exemplary embodiments, the compressed data management table manages information that is linked to the physical addresses of the first and second compressed data stored in the user space, and the first and second compressed data have the same physical address.

[0016] In exemplary embodiments, the management logic for compressed data determines whether or not to program second compressed data into the user space containing first compressed data, based on the bit size of an empty area of ​​the first compressed data.

[0017] In exemplary embodiments, if the bit size of the empty area of ​​the first compressed data is larger than the bit size of the second compressed data, the first and second compressed data are programmed into the same page of the user space.

[0018] In exemplary embodiments, if the bit size of the empty area of ​​the first compressed data is smaller than the bit size of the second compressed data, the first compressed data is programmed into the user area.

[0019] In exemplary embodiments, a write request time for the first compressed data occurs before a write request time for the second compressed data.

[0020] In exemplary embodiments, the buffer area includes a waiting area which temporarily stores a plurality of compressed data, and the compressed data management logic compares the bit size of write-requested compressed data with an empty area of ​​each of the plurality of compressed data stored in the waiting area.

[0021] In exemplary embodiments, if the bit size of the write-requested compressed data is smaller than an empty area selected from a plurality of compressed data stored in the waiting area, the compressed data management logic places the write-requested compressed data and the selected compressed data into the same page of the user area.

[0022] In exemplary embodiments, if the bit size of the write-requested compressed data is larger than the empty areas of a plurality of compressed data stored in the wait area, the compressed data management logic transfers the write-requested compressed data to the wait area.

[0023] In exemplary embodiments, the compressed data management logic compares the bit size of the wait area with a reference bit size and programs selected one from a plurality of compressed data items stored in the wait area if the bit size of the wait area is larger than the reference bit size.

[0024] In exemplary embodiments, the compressed data management logic compares the bit size of an empty area of ​​the first compressed data with the bit size of the second compressed data and subdivides the second compressed data if the bit size of the empty area of ​​the first compressed data is smaller than the bit size of the second compressed data.

[0025] In exemplary embodiments, the compressed data management logic subdivides the second compressed data into first and second subdivided compressed data, and the bit size of the first subdivided compressed data is smaller than the bit size of an empty area of ​​the first compressed data.

[0026] In exemplary embodiments, the management logic for compressed data programs the first compressed data and the first subdivided compressed data into the same page of the user space.

[0027] In exemplary embodiments, the management logic for compressed data temporarily stores the second subdivided compressed data in the buffer area.

[0028] In exemplary embodiments, the management logic for compressed data simultaneously programs at least one or more compressed data items, which are stored in the buffer area, into a plurality k from the user area. The number k from the user area is preferably less than the number of compressed data items.

[0029] Another aspect of the inventive concept provides a non-volatile storage device comprising a non-volatile memory configured to perform a programming operation with a programming unit having a bit size of k times the bit size of a page of the non-volatile memory, where k is an integer; a buffer memory configured to temporarily store compressed data to be programmed into the non-volatile memory; and compressed data management logic configured to control the non-volatile memory and the buffer memory such that the compressed data stored in the buffer memory is programmed into the non-volatile memory. The compressed data management logic manages the compressed data stored in the non-volatile memory by means of awith an ECC block unit that is smaller than the bit size of a page of non-volatile memory. During a programming operation, compressed data collected and stored in the buffer memory is written to the non-volatile memory with a programming unit (for example, one or more page sizes) larger than the ECC block unit.

[0030] In exemplary embodiments, the buffer memory contains a plurality of collected compressed data, wherein the plurality of compressed data stored in the buffer memory is to be programmed simultaneously into the non-volatile memory if the bit size of a plurality of compressed data stored in the buffer memory is smaller than the programming unit of k pages.

[0031] In exemplary embodiments, the non-volatile storage device further includes a compressed data management table configured to manage location information of compressed data stored in the non-volatile memory. The compressed data management table manages the location information of compressed data stored in the non-volatile memory through an ECC block unit smaller than the bit size of a page, under the control of the compressed data management logic.

[0032] In exemplary embodiments, the compressed data management table manages information associated with the physical address of compressed data stored in non-volatile memory, information associated with a starting number of the ECC block of the compressed data stored in non-volatile memory, and information associated with the ECC block length of the compressed data stored in non-volatile memory.

[0033] In exemplary embodiments, the compressed data management table also manages information associated with a logical address of the compressed data stored in the non-volatile memory.

[0034] In exemplary embodiments, the non-volatile memory has a plurality of compressed data which are programmed by a programming operation, and predetermined compressed data of the plurality of compressed data are subdivided so that they are stored in at least two sides of the non-volatile memory.

[0035] Another aspect of the inventive concept provides for an operating method of a non-volatile storage device which includes compressing write-requested data; collecting the compressed data in a read / write (RAM = Random Access Memory) buffer; programming or encoding the compressed data collected in the RAM into non-volatile memory; and updating a compressed data management table which manages compressed data stored in the non-volatile memory by means of an ECC block unit.

[0036] In exemplary embodiments, the operating procedure further involves comparing the bit size of the write-requested data with the bit size of an empty area of ​​previously compressed data. If the bit size of the write-requested data is smaller than the bit size of the empty area of ​​the previously compressed data, then the write-requested data and the previously compressed data are programmed into the same page of non-volatile memory.

[0037] In exemplary embodiments, the operating procedure further involves comparing the bit size of the write-requested data with the bit size of each empty area of ​​a plurality of compressed data stored in the RAM. If the bit size of the write-requested data is smaller than the bit size of an empty area of ​​selected compressed data stored in the RAM, then the write-requested data and the selected compressed data are programmed into the same page of non-volatile memory.

[0038] In exemplary embodiments, the bit size of the write-requested data is larger than the bit size of empty areas of a plurality of compressed data stored in the RAM; the data of the write request is stored in the RAM.

[0039] In exemplary embodiments, the operating procedure further involves comparing the bit size of a plurality of compressed data stored in RAM with a reference bit size when the write-requested data is stored in RAM. If the bit size of the plurality of compressed data stored in RAM is larger than the reference bit size, then predetermined compressed data from the plurality of compressed data stored in RAM is programmed into non-volatile memory.

[0040] Another aspect of the inventive concept provides for an operating method of a non-volatile storage device, which includes: sequentially receiving first write-requested data and second write-requested data; sequentially compressing first write-requested data and second write-requested data; collecting the first and second compressed data in a read / write (RAM = Random Access Memory) buffer; programming the first and second compressed data collected in the RAM into non-volatile memory; and updating a compressed data management table to manage compressed data stored in the non-volatile memory.During a programming operation, compressed data collected and stored in RAM is written to non-volatile memory with a programming unit (e.g., one or more page sizes) larger than the ECC block unit.

[0041] The inventive concept will be described in more full below with reference to the accompanying drawings, which show some exemplary embodiments. However, this inventive concept can be implemented in many different forms and should not be considered limited to the embodiments described herein. Rather, these embodiments are intended so that this disclosure will be careful and complete and will fully convey the scope of the present inventive concept to those skilled in the art. In the drawings, bit sizes and relative bit sizes may be exaggerated for clarity. Identical reference numerals refer throughout to the same elements. BRIEF DESCRIPTION OF THE FIGURES

[0042] The above and other features will become apparent from the following description with reference to the following figures, where identical reference numerals correspond to equal parts across the different figures unless otherwise specified, and wherein: Fig. 1 a block diagram of a storage system according to an embodiment of the inventive concept; Fig. 2. A flowchart is a diagram that describes the operating procedure of the storage system. Fig. 1 illustrates; Fig. 3 a block diagram of a flash memory system according to an embodiment of the inventive concept; Fig. 4 is a block diagram which schematically shows a cell arrangement and a side buffer in the flash memory of the Fig. 3 illustrated; Fig. 5 is a diagram which schematically represents a structure of data which is in a page in the page buffer in Fig. 4 are stored, illustrated; Fig. 6-8 diagrams are shown, which illustrate the operation of the flash memory system of the Fig. 3 illustrate; Fig. 9 is a flowchart which shows the operating procedure of the flash memory system which is in the Fig. 6-8 is described and illustrated; Fig. 10 is a flowchart which illustrates an operating procedure of the flash memory system in Fig. 3 illustrated according to another embodiment of the inventive concept; Fig. 11 is a diagram illustrating a RAM (Random Access Memory) or a read / write memory according to an embodiment of the inventive concept; Fig. 12 is a flowchart which describes an operating procedure of the flash memory system of the Fig. 3 illustrated according to yet another embodiment of the inventive concept; Fig. 13 is a diagram which shows the operation of the flash memory system of the Fig. 3 illustrated according to yet another embodiment of the inventive concept; Fig. 14 is a flowchart which shows an operating procedure of the flash memory system of the Fig. 3 illustrated according to yet another embodiment of the inventive concept; Fig. 15 a block diagram of a cell arrangement in the flash memory system of the Fig. 3 according to another embodiment of the inventive concept; Fig. 16 and Fig. There are 17 diagrams which illustrate the operation of the flash memory system of the Fig. 1. Illustrate when multiple pages are programmed simultaneously; Fig. 18-20 block diagrams are shown, illustrating different applications of a storage system according to one embodiment of the inventive concept; Fig. 21 is a block diagram of a memory card system to which a flash memory system is applied according to an embodiment of the inventive concept; Fig. 22 is a block diagram of a solid-state drive in which a storage system according to the inventive concept is used; Fig. 23 a block diagram of the SSD controller in the solid-state drive system of the Fig. 22 is; Fig. 24 a block diagram of an electronic device which has a flash memory system according to an embodiment of the inventive concept; Fig. 25 a block diagram of a flash memory which is applied to the inventive concept; Fig. 26 is a perspective view which schematically shows a 3D structure of a memory block in the flash memory of the Fig. 25 illustrated; and

[0063] Fig. 27 a circuit diagram or circuit diagram of an equivalent circuit of the memory block of the Fig. 26 is. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0043] Fig. Figure 1 is a block diagram of a storage system according to an embodiment of the inventive concept. Referring to Fig. In Figure 1, a storage system 100 comprises a host 110 and a storage device 120. The storage device 120 comprises a controller 121 and non-volatile memory 125.

[0044] Controller 121 controls the overall operation of the storage device 120 in response to a request from the host 110. For example, controller 121 can control the read and write operations of the non-volatile memory 125 in response to a read and write request from the host 110.

[0045] The non-volatile memory 125 can be controlled by the controller 121 and can perform operations (e.g., read or write) according to the requests of the controller 121. The non-volatile memory 125 has a user area 126, which is used to store data (e.g., compressed user data).

[0046] The storage system 100 according to one embodiment of the inventive concept can manage compressed data through the ECC block. The ECC block can be smaller than the bit size of a page of the storage device. The storage system 100 according to one embodiment of the inventive concept can be configured to compress data, collect compressed data, and write the collected compressed data. Hereinafter, this operation may be referred to as the "collective write operation" for collected data. With the collective write operation, compressed data can be accumulated in a RAM buffer 124, and two or more pieces of compressed data accumulated in the buffer 124 can be written according to the programming unit (for example, the size of one or more pages) of the user area 126.

[0047] The controller 121 according to an embodiment of the inventive concept comprises a compressor 122, a management logic 123 for compressed data and the buffer memory 124.

[0048] Compressor 122 can be configured to compress data transmitted from host 110. The compressed data can be temporarily stored in buffer 124. Compressed data management logic 123 can be configured to manage compressed data stored in buffer 124 and user space 126 using an ECC block unit. The ECC block unit can be a unit of minimal size capable of ensuring data reliability.

[0049] Storage System 100 can maximize the use of user space 126 by managing compressed data through the ECC block unit and performing a "collective write operation" on the compressed data. Furthermore, Storage System 100 can minimize the number of programming operations required to program compressed data into user space 126.

[0050] Below are described the cases in which compressed data is managed by or with an ECC block unit (for example, 1K bytes) and in which compressed data is managed by or with a unit (for example, 8 kilobytes) larger than the ECC block unit.

[0051] For the sake of simplicity, it is assumed that the buffer memory 124 has the bit size of a first unit (for example, 8 KB), and data stored in the buffer memory 124 is stored in a memory location of the user space 126, which has the first unit (for example, a memory location of 8 kilobytes). It is also assumed that the ECC block unit has a second unit, which is smaller than the first unit. Furthermore, it is assumed that the first and second compressed data (for example, 5 KB and 2 KB), which have a bit size smaller than the first unit and larger than the second unit, are programmed into the user space 126.

[0052] In the case where data stored in buffer memory 124 and user area 126 is managed by the first unit (8 KB), the first and second compressed data points must each be programmed independently into user area 126. If the first and second compressed data points are programmed into the same memory location (8 KB) of user area 126, the controller 121 may not partition the first and second compressed data points. This can result in wasted memory space in user area 126. For example, if the bit size of the first compressed data point is 5 KB, 3 KB (8 KB minus 5 KB) of memory space may be wasted.

[0053] To eliminate the disadvantage described above, according to one embodiment of the inventive concept, the storage device 120 can manage compressed data by means of a second unit (or ECC block unit) of 1 KB. In this case, although the first and second compressed data are programmed into the same memory location (for example, a memory location of 8 KB), the controller 121 can subdivide the first and second compressed data.

[0054] Since the first and second compressed data are collected at or near the buffer memory 124, and the first and second compressed data collected at the buffer memory 124 are programmed in the user area 126 according to a programming instruction, the storage device 120 can reduce the number of programming operations compared to the case where compressed data is managed by the first unit.

[0055] Fig. 2 is a flowchart which shows a procedure for operating the storage system in Fig. 1 illustrates.

[0056] In step S110, the storage device can receive 120 source data from a host 110.

[0057] In step S120, a compressor 122 of the storage device 120 can compress raw data. Here, raw data can mean data that is not compressed by the compressor 122 and corresponds to a compression unit of the compressor 122. If the bit size of the source data is larger than the compression unit of the compressor 122, a controller 121 can partition or split the source data with the compression unit to create raw data, and then the compressor 122 can compress the raw data.

[0058] In step S130, data compressed by the compressor 122 can be collected at a buffer memory 124. If the buffer memory 124 has a bit size of 8 KB, the first compressed data has a bit size of 5 KB, and the second compressed data has a bit size of 2 KB, the first compressed data and the second compressed data can be collected sequentially at the buffer memory 124.

[0059] In step S140, multiple compressed data sets collected in buffer 124 can be programmed into user space 126. For example, the first and second compressed data sets collected in buffer 124 can be programmed simultaneously into user space 126 using a programming instruction. A compressed data management logic 123 can manage the first and second compressed data sets using an ECC block unit (e.g., 1 KB). Therefore, the compressed data management logic 123 can efficiently and accurately locate the positions of the first and second compressed data sets within user space 126.

[0060] As described above, according to one embodiment of the inventive concept, the storage device 100 supports a collective write operation for compressed data and manages data stored in the user area 126 through the ECC block unit. Therefore, it is possible to use the storage space of the user area 126 efficiently.

[0061] The storage device 100 can also include an ECC circuit. When data is programmed into non-volatile memory 125, the ECC circuit performs encoding using the ECC block unit. When data is read from non-volatile memory 125, the ECC circuit can perform decoding using the ECC block unit. Data reliability can be ensured by managing the data within the size of the ECC block unit. Furthermore, it is possible to maximize the use of user area 126 storage space.

[0062] A non-volatile memory 125 in Fig. 1 can be implemented using various types of memory. For example, the non-volatile memory 125 can be formed from flash memory, magnetic RAM (MRAM = Magnetic RAM), spin transfer torque MRAM (STT-MRAM = Spin Transfer Torque MRAM), conductive bridging RAM (CBRAM = Conductive Bridging RAM), phase-change RAM (PRAM = Phase-Change RAM), called Ovonic Unified Memory (OUM), resistive RAM (RRAM or Re-RAM = Resistive RAM), nanotube RAM, polymer RAM (PoRAM = Polymer RAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, insulator resistance-change memory, or the like.

[0063] An exemplary embodiment is described below, in which the non-volatile memory 125 is located in Fig. 1 is formed from a flash memory.

[0064] Fig. Figure 3 is a block diagram of a flash memory system according to an embodiment of the inventive concept. A flash memory system 1000 comprises a host 1100 and a flash memory device 1200. To efficiently utilize the storage space of a flash memory 1400, the flash memory device 1200 supports a "collective write operation" and manages data stored in the flash memory 1400 by means of an ECC block unit.

[0065] Referring to Fig. Figure 3 shows that the flash storage device 1200 comprises a controller 1300 and the flash memory 1400. The controller 1300 manages the overall operation of the flash memory 1400 in response to a request from the host 1100. For example, the controller 1300 can control writing to or reading from the flash memory 1400. The controller 1300 includes a host interface 1310, a storage media interface 1320, a CPU 1330, RAM 1340, an ECC circuit 1350, a compressor 1360, and compressed data management logic 1370.

[0066] Host interface 1310 is configured to interface with host 1100, and storage interface 1320 is configured to interface with flash memory 1400. Host interface 1310 can be connected to host 1100 via one or more channels (or ports). For example, host interface 1310 can be connected to host 1100 via a parallel AT attachment (PATA) bus and a serial AT attachment (SATA) bus, or via both the PATA and SATA buses. Alternatively, host interface 1310 can be connected to host 1100 via SCSI, USB, or similar interfaces.

[0067] The CPU 1330 controls the overall operation of the flash memory device 1200. Although in Fig. Since 3 is not shown, the CPU 1330 may be implemented, so that it has a processor, an SRAM, a DRAM controller and the like.

[0068] The RAM 1340 can operate in response to the control of the CPU 1330 or the management logic 1370 for compressed data, and can be used as main memory, buffer memory, cache memory, and / or the like. The RAM 1340 can consist of one or more chips.

[0069] When the RAM 1340 is used as the main memory, it can be used to temporarily store data that is being processed by the CPU 1330.

[0070] When the RAM 1340 is used as the buffer memory, it can be used to temporarily store and collect compressed data to be transferred to, or from, the Flash memory 1400. For example, the RAM 1340 can be used to temporarily store a compressed data point or multiple compressed data points to be transferred to the Flash memory 1400.

[0071] The RAM 1340 can be used as a driver memory to drive a Flash Translation Layer (FTL). The Flash Translation Layer can translate logical addresses from the host 1100 into physical addresses of the memory cell array 1410 and can be used to manage merge operations of the Flash Memory 1400, mapping tables, and the like. The RAM 1340 can be used to store a mapping table managed by the Flash Translation Layer or a compressed data management table managed by the compressed data management logic 1370. The RAM 1340 can also be used to store a combined mapping table that contains both the mapping table and the compressed data management table.

[0072] The ECC circuit 1350 generates an error correction code (ECC) to correct erroneous bits in the data received from the flash memory 1400. The ECC circuit 1350 can encode data intended for the flash memory 1400 to produce data to which ECC (or parity) information is appended. The ECC / parity information can be stored in a meta-area of ​​the cell array 1410. The ECC circuit 1350 can decode output data to assess the success of the decoding operation. Based on the assessment result, the ECC circuit 1350 can output a signal and correct erroneous bits in the output data using the ECC information.

[0073] The ECC 1350 circuit can perform error correction using an LDPC (Low Density Parity Check) code, a BCH code, a turbo code, a Reed-Solomon code, a convolution code, an RSC (Recursive Systematic Code), coded modulation such as TCM (Trellis Coded Modulation), BCM (Block Coded Modulation), or the like. The ECC 1350 circuit can incorporate one or all of the following: an error correction circuit, an error correction system, and an error correction device.

[0074] The Compressor 1360 can operate in response to the control of the CPU 1330 (or the management logic 1370 for compressed data) and can sequentially compress data provided by the Host 1100 according to a compression unit. For example, data provided by the Host 1100 can be stored in the RAM 1340, and data stored in the RAM 1340 can be subdivided by the compression unit according to the control of the CPU 1330 (or the management logic 1370 for compressed data). The Compressor 1360 can then sequentially compress data that has been subdivided according to the compression unit.

[0075] The ECC circuit 1350 can append ECC information to data compressed by the compressor 1360, and the resulting data can be collected in a predetermined area of ​​the RAM 1340. Afterwards, the compressed data collected in the RAM 1340 can be programmed into the cell array 1410 via a side buffer 1420. The compressor 1360 can decompress data read from the flash memory 1400 in response to the control of the CPU 1330 (or the compressed data management logic 1370).

[0076] The compressed data management logic 1370 manages compressed data stored in the 1400 flash memory using an ECC block unit. The minimum bit size of the ECC block unit is sufficient to ensure the reliability of data stored in the 1400 flash memory. It is assumed that ECC information is added to compressed data with a bit size of 8 KB. In this case, the reliability of the compressed data can be ensured by a 1 KB unit that uses ECC information. Here, the ECC block unit can also have a bit size of 1 KB.

[0077] The compressed data management logic 1370 manages compressed data stored in the flash memory 1400 via the ECC block unit. The compressed data management logic 1370 can collect multiple compressed data sets at the RAM 1340 and control the flash memory 1400 such that the majority of the compressed data sets collected at the RAM 1340 are collectively programmed into the cell array 1410 via the page buffer 1420 at the same time.

[0078] The compressed data management logic 1370 manages location information (or physical address (PA) information) of compressed data stored in cell array 1410 using the compressed data management table. Alternatively, the compressed data management logic 1370 can manage location information of compressed data stored in cell array 1410 by combining the compressed data management table and a mapping table managed by the flash translation layer. The flash memory 1400 contains cell array 1410 and page buffer 1420.

[0079] The cell array 1410 can store data transferred by the host 1100 or data compressed by the compressor 1360. The page buffer 1420 can temporarily store data to be programmed into the cell array 1410 or data read from the cell array 1410. The flash memory 1400 is described in more detail with reference to the Fig. 4 and Fig. 5 will be described.

[0080] Fig. 4 is a block diagram which schematically shows a cell arrangement and a side buffer in the flash memory of the Fig. Figure 3 illustrates this. For the sake of clarity, it is assumed that a cell arrangement 1410 is formed in a plane of a semiconductor. Referring to Fig. In cell arrangement 1410, level 1411 is shown, which contains a plurality of memory blocks 1412 to 1413. Each memory block can contain a plurality of pages.

[0081] During programming (writing), data stored in page buffer 1420 can be written to cell array 1410 page by page. During reading, data stored on a page of cell array 1410 can be read through page buffer 1420 at the page unit level (i.e., page by page).

[0082] When data stored in cell array 1410 is managed by the page unit, different data may be stored on separate pages. This can be done to prevent different data from being recognized as a single piece of data when different data is programmed into and then read from a single page. However, the storage space on each page can be wasted when data stored in cell array 1410 is managed by the page unit.

[0083] Aspects of the invention eliminate the disadvantage described above, since a management logic 1370 for compressed data according to an embodiment of the inventive concept can manage data which is stored in the cell arrangement 1410 by or with an ECC block unit (for example, a bit size smaller than a page).

[0084] Fig. 5 is a diagram that schematically illustrates a structure of data which is located in or on one side of the page buffer in Fig. 4 are stored. Fig. 5 is the first page of a memory block 1412 in Fig. Figure 4 illustrates this by way of example. For the sake of clarity, it is assumed that a page contains 8 ECC blocks.

[0085] Referring to Fig. 5 can have a first page of 8 ECC blocks. Each ECC block can have at least one data bit (i.e., data bits) and one ECC bit (i.e., ECC bits). The data bit can represent a date or data with a write request from the host 1100, and the ECC bit can represent a parity bit, which is defined by an ECC circuit 1350 (see reference to Fig. 3) is added to ensure the reliability of the data bit(s).

[0086] For example, if 8 KB of data is stored on the first page, each data bit can have a bit size of 1 KB, and each ECC bit can be appended to each 1 KB data bit. In this case, the ECC block can have a bit size equal to the sum of the 1 KB data bit and the ECC bit. The reliability of data stored on the first page can be ensured by the ECC block unit. The bit size of the ECC bit can be negligible compared to the bit size of the data bit. Therefore, the inventive concept will be described assuming that the bit size of the ECC block is similar to that of the data bit.

[0087] Different compressed data can be stored on one page by managing data stored in a cell arrangement of 1410 (refer to Fig. 4) through or with the ECC block unit. This means that multiple compressed data sets can be stored in or on a single physical page.

[0088] For example, it is assumed that the first compressed data and the second compressed data have bit sizes of 5 KB and 2 KB, respectively. Furthermore, it is assumed that the first compressed data and the second compressed data, with a RAM of 1340 (refer to...), Fig. 4) collected and then programmed into the first to seventh ECC blocks of the first page.

[0089] Since data is managed by the ECC block unit, the compressed data management logic 1370 can know that the first compressed data is stored in the first five ECC blocks of the first page. Furthermore, the compressed data management logic 1370 can know that the second compressed data is stored in the sixth and seventh ECC blocks of the first page.

[0090] As with reference to the Fig. 3, Fig. 4 to Fig. As described in section 5, a flash memory device 1200 according to one embodiment of the inventive concept can be configured to manage compressed data stored in a flash memory by or with the ECC block unit and to support a "collective write operation" on compressed data. Accordingly, the flash memory device 1200 according to one embodiment of the inventive concept can minimize the waste of storage space in the memory cell arrangement 1410.

[0091] The bit size of compressed data can be smaller than that of the ECC block unit. For example, compressed data can have a bit size of 900 bytes. Furthermore, the bit size of compressed data may not exactly match that of the ECC block unit. For example, compressed data can have a bit size of 1 KB. Nevertheless, the flash memory device can manage 1200 bytes of compressed data using the ECC block unit to ensure data reliability. Therefore, 900 bytes of compressed data can be managed as equivalent to one ECC block, and 1.9 KB of compressed data can be managed as equivalent to two ECC blocks.

[0092] The Flash Memory Device 1200 and the collective write operation can be variably changed or modified, which will be described in more detail below.

[0093] The Fig. 6, Fig. 7 to Fig. 8 are diagrams illustrating the operation of the flash memory system of the Fig. 3. The following illustrates the case where a programming operation is performed page by page, with reference to Fig. 3 will be described.

[0094] For the sake of simplicity, it is assumed that both the bit size of a page and the bit size of a space allocated to collected compressed data within a RAM 1340 are 8 KB. Furthermore, it is assumed that an ECC block unit has a bit size of 1 KB. A storage device 1200 can sequentially receive a first write request and a second write request from a host 1100.

[0095] Referring to Fig. 6. The first write request and initial source data can be transferred from the host 1100 to a controller 1300. In response to the initial write request, the controller 1300 can compress the initial source data and store the compressed initial source data at a RAM 1340. This will be described in more detail below.

[0096] The initial source data can be temporarily stored in RAM 1340. This initial source data can then be partitioned according to the compression unit of a compressor 1360, controlled by the compressed data management logic 1370 (or the CPU 1330). The partitioned or divided source data, corresponding to the compression unit of the compressor 1360, can be referenced as raw data.

[0097] To simplify the description, it can be assumed that the compression unit of the 1360 compressor corresponds to a page unit (i.e., 8 KB) and that the initial source data has a bit size of 8 KB. With this assumption, as described in Fig. Figure 6 illustrates how the initial source data is converted into initial raw data.

[0098] After that, the 1360 compressor can compress the first raw data, and an ECC circuit 1350 (refer to) Fig. 3) An ECC bit can be appended to the compressed data. Therefore, the first compressed data CD1 can be generated. For example, as in Fig. Figure 6 illustrates how the initial raw data of 8 KB is converted into the initial compressed data CD1 of 5 KB by the compressor 1360. The initial compressed data CD1 can then be stored in RAM 1340 under the control of the compressed data management logic 1370.

[0099] After the first source data, corresponding to the first write request, is stored in RAM 1340, a second write request and second source data can be provided to controller 1300. The second source data can be converted into second raw data in the same way as the first source data. Compressor 1360 can compress the second raw data, and ECC circuit 1350 can append an ECC bit to the compressed data. As in Fig. As illustrated in Figure 6, the second raw data of 8 KB can be converted into the second compressed data CD2 of 2 KB by the compressor 1360. The second compressed data CD2 can be stored in RAM 1340 under the control of the compressed data management logic 1370.

[0100] After being sequentially stored in RAM 1340, the first and second compressed data sets can be programmed into a cell array 1410. For example, as shown in Fig. Figure 6 illustrates that the first and second compressed data are programmed into a first page of a memory block 1420.

[0101] The management logic 1370 for compressed data can update location information that is assigned to or linked with the first and second compressed data points. For example, as in Fig. Figure 7 illustrates the management logic 1370 for compressed data. It manages location information for the first and second compressed data sets by updating a compressed data management table. This will be described in more detail below.

[0102] As in Fig. As illustrated in Figure 6, the first compressed data can be programmed into the first five ECC blocks of the first page. This assumes that the physical address of the first page is "1". In this case, as shown in Figure 6, the first compressed data can be programmed into the first five ECC blocks of the first page. Fig. Figure 7 illustrates that the compressed data management logic 1370 updates the compressed data management table such that a physical address PA is set to "1", a starting number of an ECC block SNE is set to "1", and the ECC block length EBL is set to "5". Therefore, the compressed data management logic 1370 can know exactly one location of the first compressed data CD1, which corresponds to the first raw data, using the compressed data management table.

[0103] The second compressed data set can be programmed into the sixth and seventh ECC blocks of the first page. Therefore, as in Fig. Figure 7 illustrates that the compressed data management logic 1370 updates the compressed data management table such that a physical address PA is set to "1", a starting number of an ECC block SNE is set to "6", and the ECC block length EBL is set to "2". Therefore, the compressed data management logic 1370 can know exactly one location of the second compressed data CD2, which corresponds to the second raw data, using the compressed data management table.

[0104] The management table for compressed data in Fig. Figure 7 can be an example. However, the inventive concept is not limited to this. For example, the compressed data management logic 1370 can manage compressed data using a mapping table managed by a Flash translation layer, without separately generating the compressed data management table. Therefore, as in Fig. As illustrated in Figure 8, the mapping table and the compressed data management table are combined to form a unified mapping table. In this case, mapping information associated with uncompressed data can also be managed by the unified mapping table. Fig. 8. Compressor information CI marked with "Y" indicates that data is compressed, and compression information CI marked with "N" indicates that data is uncompressed. This will be described in more detail below.

[0105] It can be assumed that a logical address LA of first raw data is "1" and a logical address of second raw data is "2", and that a physical address PA of a first page is "1".

[0106] As in Fig. As illustrated in section 6, the first raw data can correspond to the first compressed data, and the first compressed data can be programmed into the first five ECC blocks of the first page. After that, as shown in Fig. Figure 8 illustrates that the compressed data management logic 1370 updates the compressed data management table such that a logical address LA is set to "1", a physical address PA is set to "1", the starting number of an ECC block SNE is set to "1", and the ECC block length EBL is set to "5". This means that data (i.e., the initial raw data) corresponding to the logical address LA of "1" is stored in the first five ECC blocks of the first page. Similarly, the compressed data management logic 1370 can update the compression information CI, which is set to "Y". This means that data (i.e., the initial raw data) corresponding to the logical address LA of "1" is stored in a compressed state.

[0107] Similarly, as in Fig. As illustrated in Figure 6, the second raw data corresponds to the second compressed data, and the second compressed data can be programmed into a sixth and seventh ECC block of the first page. Therefore, as shown in Figure 6, the following applies: Fig. Figure 8 illustrates that the compressed data management logic 1370 updates the compressed data management table such that a logical address LA is set to "2", a physical address PA is set to "1", the starting number of an ECC block SNE is set to "6", and the ECC block length EBL is set to "2". Therefore, it is understood that data (i.e., the second raw data) corresponding to the logical address LA of 2 is stored in the sixth and seventh ECC blocks of the first page. Similarly, the compressed data management logic 1370 can update the compressor information CI, which is to be set to "Y". Therefore, it is understood that data (i.e., the second raw data) corresponding to the logical address LA of 2 is stored in a compressed state.

[0108] As with reference to the Fig. As described in Figures 6-8, a flash storage device 1200 according to one embodiment of the inventive concept can manage compressed data through or with the ECC block unit using a compressed data management table or a unified mapping table. Accordingly, the flash storage device 1200 can minimize the wastage of storage space in a cell array 1410 by storing a plurality of compressed data on one page.

[0109] Fig. 9 is a flowchart illustrating an operating procedure of the flash memory system, which is located in the Fig. 6, Fig. 7 to Fig. As described in section 8, this is illustrated.

[0110] In step S210, a flash storage device 1200 can receive source data. If the bit size of the source data differs from that of a compression unit of a compressor 1360, the source data can be partitioned according to the compression unit under the control of the compressed data management logic 1370 (or the CPU 1330).

[0111] In step S220, raw data can be compressed and an ECC bit can be added to the compressed data. Here, "raw data" refers to source data that is identical up to the compression unit. Therefore, a compressor 1360 can compress the source data (or raw data partitioned according to the compression unit), and an ECC circuit 1350 can add the ECC bit to the compressed data. Thus, compressed data can be generated.

[0112] In step S230, the compressed data can be collected using a RAM 1340. For example, as referenced in the Fig. 6, Fig. 7 to Fig. As described in section 8, various data are compressed by the compressor 1360, which is collected in the RAM 1340.

[0113] In step S240, compressed data collected at RAM 1340 can be programmed into cell array 1410. For example, if multiple compressed data points are collected at RAM 1350, the majority of these compressed data points can be programmed into the same side of cell array 1410.

[0114] In step S250, a compressed data management table can be updated. Therefore, a compressed data management logic 1370 can manage data stored in cell arrangement 1410 using an ECC block unit that employs a compressed data management table, and it can update the compressed data management table to include location information for newly programmed compressed data.

[0115] An operating method of the Flash Memory System 1000, which is in Fig. The example described in Section 9 can be considered exemplary. However, the inventive concept is not limited to this. For instance, after compressed data collected at RAM 1340 has been programmed into cell arrangement 1410, the compressed data management table can be updated (S250). As another example, after the compressed data management table has been updated, compressed data collected at RAM 1340 can be programmed into cell arrangement 1410.

[0116] Fig. 10 is a flowchart which illustrates an operating procedure of the flash memory system in Fig. Figure 3 illustrates another embodiment of the inventive concept. The operation of a 1000-bit flash memory system in Fig. 10 can be analogous to the one which, with reference to the Fig. 6, Fig. 7, Fig. 8 to Fig. 9 is described, and a difference between them will be described.

[0117] For the sake of clarity, it can be assumed that data compressed by a compressor 1360 according to a previous write request is referred to as previously compressed data, and data compressed by a compressor 1316 according to a current write request is referred to as newly compressed data. It is also assumed that the bit size of the RAM 1340 for collecting compressed data matches the bit size of the programming unit (for example, one or more page sizes) (for example, a page that has 8 KB).

[0118] In step S310, source data can be transferred to a Flash Memory Device 1200.

[0119] In step S320, the compressor 1360 can compress raw data, and an ECC circuit 1350 can add an ECC bit to the compressed data. Therefore, newly compressed data can be generated.

[0120] In step S330, the management logic 1370 for compressed data can compare the bit size of the compressed data with the bit size of an empty area. Here, the empty area represents the difference between the bit size of data being programmed simultaneously and the bit size of previously compressed data collected in a RAM 1340. For example, as referenced in the Fig. 6, Fig. 7, Fig. 8 to Fig. As described in section 9, in a case where a programming operation is executed page by page, an empty area is the difference between the page bit size and the bit size of previously compressed data collected in RAM 1340. For example, if a page bit size is 8 KB and the bit size of previously compressed data collected in RAM 1340 is 5 KB, the bit size of the empty area can be 3 KB.

[0121] If the bit size of the newly compressed data is less than or equal to the bit size of the empty area, the newly compressed data can be collected at RAM 1340 in step S340. In step S350, the newly compressed data and the previously compressed data collected at RAM 1340 can be programmed into the same page. In step S360, the compressed data management logic 1370 can update a compressed data management table (or a unified mapping table).

[0122] If the bit size of newly compressed data is larger than the bit size of the empty area, in step S370 the previously compressed data stored in RAM 1340 can be programmed into a predetermined page of cell array 1410. In step S380, the compressed data management logic 1370 can update the compressed data management table (or the unified mapping table). In step S390, newly compressed data can be collected from RAM 1340.

[0123] As described above, a flash memory system 1000 according to an embodiment of the inventive concept can determine a collective write operation based on a comparison result between the bit size of compressed data and an empty area of ​​a page buffer 1420.

[0124] The operation of a flash memory system is described under the condition that the bit size of the RAM 1340 for collecting compressed data matches the programming unit (one or more page sizes). However, the inventive concept is not limited to this. The inventive concept can be modified or adapted in various ways. For example, the bit size of the RAM 1340 can be larger than that of the programming unit. The inventive concept is described below under the condition that the bit size of the RAM 1340 is larger than that of the programming unit.

[0125] Fig. Figure 11 is a diagram illustrating a read / write memory (RAM = Random Access Memory = read / write memory) according to an embodiment of the inventive concept. Referring to Fig. 11. A section of RAM 1340 can be assigned or allocated as a wait area 1341, and the wait area 1341 can temporarily store previously compressed data. For example, the case where the first previously compressed data CD1 and the second previously compressed data CD2 are temporarily stored in the wait area 1341 is described in Fig. 11 illustrated.

[0126] In exemplary embodiments, the compressed data management logic 1370 can compare the bit size of newly compressed data with the bit size of an empty area of ​​any previously compressed data stored in the wait area 1341. If the bit size of the newly compressed data is smaller than the bit size of an empty area of ​​any previously compressed data, the newly compressed data and the selected previously compressed data can be programmed onto a page at the same time.

[0127] The newly compressed data can be data compressed by Compressor 1360 according to a current write request, and the previously compressed data can be data compressed by Compressor 1360 according to a previous write request. An empty area of ​​previously compressed data corresponds to the difference between the bit size of data capable of being programmed at the same time (i.e., the programming unit) and the bit size of previously compressed data.

[0128] For example, in the case where a programming operation is performed page by page, an empty area of ​​previously compressed data means the difference between a page's bit size and the bit size of the preceding compressed data. For example, if the page bit size is 8 KB and the bit size of the first previously compressed data CD1 is 5 KB, then an empty area of ​​the first previously compressed data is 3 KB.

[0129] Fig. 12 is a flowchart which illustrates an operating procedure of the flash memory system of the Fig. 3 illustrates yet another embodiment of the inventive concept. As in Fig. As illustrated in Figure 11, a RAM 1340 of a flash memory system 1000 has a wait area 1341. Operating a flash memory system in Fig. 12 may be analogous to the one which, with reference to Fig. 10 is described, and the difference between them will be described.

[0130] In step S410, source data can be transferred to a Flash Memory Device 1200.

[0131] In step S420, a compressor 1360 compresses raw data, and an ECC circuit 1350 adds an ECC bit to the compressed data. Therefore, new compressed data can be generated.

[0132] In step S425, the management logic 1370 for compressed data compares the bit size of newly compressed data with the bit size of an empty area of ​​at least one compressed data point stored in the waiting area 1341. For example, as in Fig. Figure 11 illustrates that, in the case where two previously compressed data sets CD1 and CD2 are stored in the waiting area 1341, the compressed data management logic 1370 compares the bit size of newly compressed data sets with the bit size of an empty area of ​​each of the first and second previously compressed data sets CD1 and CD2.

[0133] If the bit size of the newly compressed data is smaller than the bit size of an empty area of ​​any of the plurality of previously compressed data stored in wait area 1341, the newly compressed data and corresponding previously compressed data can be collected at RAM 1340. Then, in step S432, the newly and previously compressed data collected at RAM 1340 can be programmed into a page of a cell array 1410. In step S4330, the compressed data management logic 1370 can update a compressed data management table (or a unified mapping table).

[0134] If the bit size of the newly compressed data is larger than the bit sizes of empty areas of all previously compressed data stored in wait area 1341, the newly compressed data can be transferred to wait area 1341 in step S440. In step S445, the compressed data management logic 1370 can compare the bit size of compressed data stored in wait area 1341 with a reference bit size ref.bit-size.

[0135] If the bit size of compressed data stored in wait area 1341 is larger than the reference bit size ref.bit-size, the compressed data management logic 1370 can perform a series of operations to reduce the bit size of wait area 1341. Specifically, in step S451, predetermined compressed data from previously compressed data stored in wait area 1341 can be programmed into cell arrangement 1410. In step S452, the compressed data management table (or the unified mapping table) can be updated.

[0136] If the bit size of compressed data stored in wait area 1341 is smaller than the reference bit size ref.bit-size, the flash memory device 1200 can maintain a wait state to receive the next programming instruction.

[0137] As described above, a flash memory system 1000 according to one embodiment of the inventive concept can compare the bit size of newly compressed data with the bit sizes of empty areas of previously compressed data stored in the wait area 1341 and determine an optimal collective write operation based on the comparison result. Likewise, if the bit size of the wait area 1341 is larger than a reference bit size, a series of operations can be performed to reduce the bit size of the wait area 1341.

[0138] Fig. 13 is a diagram illustrating the operation of the flash memory system of the Fig. Figure 3 illustrates another embodiment of the inventive concept. If the bit size of newly compressed data is larger than the bit size of an empty area, the compressed data management logic 1370, according to one embodiment of the inventive concept, can measure the bit size of the empty area and subdivide the newly compressed data based on the measured bit size.

[0139] Here, the empty space can represent a difference between the bit size of simultaneously programmed data (i.e., the programming unit) and the bit size of compressed data collected in a RAM 1340. For example, as with reference to the Fig. 6, Fig. 7, Fig. 8 to Fig. As described in section 9, when a programming operation is performed page by page, an empty area represents a difference between a page bit size and the bit size of compressed data collected in the RAM 1340.

[0140] To facilitate the description, as in Fig. As illustrated in Figure 13, it can be assumed that the ECC block length EBL 11 of newly compressed data is "5", and that the ECC block length EBL of an empty area of ​​RAM 1340 is "2". With this assumption, the compressed data management logic 1370 can divide the newly compressed data into first newly compressed data, which has an ECC block length EBL of "3", and second newly compressed data, which has an ECC block length EBL of "2". Subsequently, the first compressed data and the second newly compressed data can be programmed under the control of the compressed data management logic 1370.

[0141] Fig. 14 is a flowchart which illustrates an operating procedure of the flash memory system of the Fig. Figure 3 illustrates yet another embodiment of the inventive concept. The operation of a 1000-bit flash memory system in Fig. 14 may be analogous to the one which, with reference to the Fig. 10 is described, and a difference between them will be described.

[0142] In step S510, source data can be transferred to a flash storage device 1200. In step S520, a compressor 1360 can compress raw data, and an ECC circuit 1350 can append an ECC bit to the compressed data. Thus, compressed data can be generated.

[0143] In step S530, the compressed data management logic 1370 can check the bit size of an empty area. In step S540, the compressed data management logic 1370 can subdivide compressed data according to the bit size of the empty area. In step S550, a selected subdivided piece of compressed data and the preceding compressed data can be programmed into cell arrangement 1410. In step S560, a compressed data management table (or a unified mapping table) can be updated.

[0144] As described above, a flash memory system 1000 according to one embodiment of the inventive concept can subdivide compressed data according to an empty area of ​​a page buffer 1420 in order to perform a collective write operation. However, the inventive concept is not limited to this. For example, a cell array 1410 of a flash memory system 1000 has a plurality of levels, and a plurality of pages can be programmed at the same time.

[0145] In a case where multiple pages can be programmed simultaneously, a set of pages being programmed at the same time can be referred to as a superpage. A programming operation performed by or with a superpage will be described in more detail below.

[0146] Fig. 15 is a block diagram of an arrangement in the flash memory system of the Fig. 3 according to another embodiment of the inventive concept. In contrast to a cell arrangement in Fig. 4 has a cell arrangement of 1410 in Fig. 15 a plurality of levels. To facilitate illustration, in Fig. Figure 15 illustrates that the cell arrangement 1410 has two levels. However, the inventive concept is not limited to this. For example, the cell arrangement 1410 can be configured to have three or more levels.

[0147] Referring to Fig. In cell arrangement 1410, there is a first and a second level, 1411 and 1412. Each of the first and second levels, 1411 and 1412, has a plurality of memory blocks, each of which has a plurality of pages.

[0148] A page buffer block 1420 has a first and a second page buffer 1421 and 1422. The first page buffer 1421 can correspond to a first level 1411. The first page buffer 1421 can be configured to temporarily store data that is to be programmed into a page of the first level 1411, or data that is read from a page of the first level 1411. The second page buffer 1422 can correspond to a second level 1412. The second page buffer 1422 can be configured to temporarily store data that is to be programmed into a page of the second level 1412, or data that is read from a page of the second level 1412.

[0149] When a programming operation is executed, data in the first page buffer 1421 and data in the second data buffer 1422 can be programmed into the cell array 1410 simultaneously. Therefore, two pages of the cell array 1410 can be programmed at the same time. In this case, the programming unit (for example, one or more page sizes) can correspond to the sum of the bit sizes of two pages.

[0150] The inventive concept can also be applied to the case where multiple pages are programmed simultaneously. Accordingly, in the case where multiple pages are programmed simultaneously, the management logic 1370 for compressed data, according to one embodiment of the inventive concept, can manage data stored in the cell arrangement 1410 by means of an ECC block unit and control a flash memory 1400 such that multiple compressed data are programmed simultaneously through the first and second page buffers 1421 and 1422.

[0151] The Fig. 16 and Fig. 17 are diagrams illustrating the operation of the flash memory system of the Fig. 1. Illustrate when multiple pages are programmed simultaneously. In the Fig. 16 and Fig. 17. Operation of a flash memory system may be similar to those described with reference to the Fig. 6 and Fig. 7 is described, will be carried out, and a difference between them will be described.

[0152] To simplify the description, it can be assumed that a first to third write request is intended sequentially for a controller 1300 from a host 1100, that a page bit size and a page buffer bit size are 8KB, that the bit size of a RAM 1340 for collecting compressed data is 16KB, and that two pages are programmed simultaneously.

[0153] Referring to Fig. 16. An initial write request and initial source data can be transferred from the host 1100 to the controller 1300. The controller 1300 can partition the initial source data according to a compression unit of a compressor 1360. For the sake of simplicity, it can be assumed that the initial source data and initial raw data each have a bit size of 8 KB.

[0154] After that, the 1360 compressor can compress the initial raw data to create the first compressed data CD1. For example, as in Fig. Figure 16 illustrates that the first compressed data CD1 of 6KB is generated by compressing the first raw data of 8KB. The first compressed data CD1 can be collected in a RAM 1340 under the control of the compressed data management logic 1370.

[0155] After the first compressed data CD1 has been collected by the RAM 1340, a second write request and second source data can be provided to the controller 1300. The second source data can be compressed to obtain second compressed data CD2 in the same way as the first source data. For example, as shown in Fig. Figure 16 illustrates that the second compressed data CD2 has a bit size of 4 KB and can be collected at the RAM 1340.

[0156] Then a third write request and third source data can be provided for the Controller 1300. The third source data can be compressed to obtain third compressed data CD3 in the same way as the first source data. For example, as shown in Fig. Figure 16 illustrates that the third compressed data CD3 has a bit size of 6 KB and can be collected at the RAM 1340.

[0157] After being collected at RAM 1340, the first to third compressed data CD1 to CD3 can be simultaneously transferred to cell arrangement 1410 via a side buffer block 1420 (reference is made to Fig. 15) be programmed. For example, as in Fig. Figure 16 illustrates that the first to third compressed data CD1 to CD3 are programmed simultaneously into a first page of a memory block 1413 and a first page of a memory block 1415.

[0158] After that, the management logic 1370 can update the location information of the first to third compressed data sets, CD1 to CD3, for compressed data. For example, as in Fig. Figure 17 illustrates how the management logic 1370 updates a unified mapping table for compressed data.

[0159] In particular, with reference to Fig. 16, the first compressed data CD1 is stored in the first to sixth ECC blocks of a first page. Therefore, if a physical address PA of the first page is "1", then as in Fig. Figure 17 illustrates that the management logic 1370 for compressed data updates the unified mapping table such that a physical address PA is set to "1", a starting number of the ECC block SNE is set to "1", and the ECC block length EBL is set to "6".

[0160] Similarly, with reference to Fig. 16. The second compressed data CD2 can be stored in a seventh and eighth ECC block of the first page and a first and second ECC block of a second page, and can have an ECC block length EBL of "4". As in Fig. As illustrated in Figure 17, the management logic 1370 for compressed data can update the unified mapping table such that a physical address PA is set to "1", a starting number of the ECC block SNE is set to "7", and the ECC block length EBL is set to "4".

[0161] Similarly, the management logic 1370 for compressed data can update the location information of the third compressed data CD3 (i.e., the unified mapping table) such that a physical address PA is set to "2", a starting number of the ECC block SNE is set to "3", and the ECC block length EBL is set to "6".

[0162] When a read request is made for the first to third raw data, the management logic 1370 for compressed data can refer to the unified mapping table to find the exact locations where the first to third raw data are stored.

[0163] The Fig. 18, Fig. 19 to Fig. Figure 20 are block diagrams illustrating various applications of a storage system according to one embodiment of the inventive concept. Referring to Fig. 18, Fig. 19 to Fig. In section 20, a storage system 2000 / 300 / 4000 has a host 2100 / 3100 / 4100 and a storage device 2200 / 3200 / 4200. The storage device 2200 / 3200 / 4200 has a controller 2210 / 3210 / 4210 and non-volatile memory 4220 / 3220 / 4220.

[0164] The 2200 / 3200 / 4200 storage device includes a memory card (e.g., SD, MMC, etc.) or a storage medium such as an attachable mobile storage device (e.g., USB flash drive, etc.). The 2200 / 3200 / 4200 storage device can be connected to a 2100 / 3100 / 4100 host. The 2200 / 3200 / 4200 storage device can exchange data with the 2100 / 3100 / 4100 host through a host interface. The 2200 / 3200 / 4200 storage device can be powered by the 2100 / 3100 / 4100 host.

[0165] Referring to Fig. 18. A management logic 2230 for compressed data can be formed from software (S / W) or firmware, not from hardware (H / W). The management logic 2230 for compressed data can be operated or driven on volatile memory. Referring to Fig. 19. The management logic 2230 for compressed data can be implemented so that it is contained within the storage medium 3220. Referring to Fig. 20 A compressor 4240 can be provided within the host 4100 and a controller 4210 can receive compressed data.

[0166] The storage system 2000 / 3000 / 4000 according to one embodiment of the inventive concept can manage data stored in non-volatile memory 2200 / 3200 / 4200 by means of an ECC block unit and supports a collective write operation for compressed data. Therefore, it is possible to use the storage space of the 2200 / 3200 / 4200 storage medium efficiently.

[0167] Fig. Figure 21 is a block diagram of a memory card system to which a flash memory system according to an embodiment of the inventive concept is applied. A memory card system 5000 comprises a host 5100 and a memory card 5200. The host 5100 comprises a host controller 5110, a host connection unit 5120, and a DRAM 5130.

[0168] The host 5100 can write data to and read data from the memory card 5200. The host controller 5110 can send a command (for example, a write command), a clock signal CLK, which is generated by a clock generator (not shown) in the host 5100, and data to the memory card 5200 via the host connection unit 5120. The DRAM 5130 can be the main memory of the host 2100.

[0169] The 5200 memory card comprises a card connection unit 5210, a card controller 5220, and a flash memory 5230. The card controller 5220 can store data in the flash memory 5230 in response to a command input via the card connection unit 5210. The data can be stored in synchronization with a clock signal generated by a clock generator (not shown) in the card controller 5220. The flash memory 5230 can store data transferred from the host 5100. For example, if the host 5100 is a digital camera, the flash memory 5230 can store image data.

[0170] In the 5000 memory card system in Fig. 21. The card controller 5220 features compressed data management logic and a compressor, which are provided within the host controller 5110, the card controller 5220, or the flash memory 5230. As described above, it is possible to efficiently manage storage space by managing data through or with an ECC block unit and supporting a collective write operation for compressed data.

[0171] Fig. Figure 22 is a block diagram of a solid-state drive in which a storage system according to the inventive concept is used. Referring to Fig. 22. A solid state drive (SSD) system 6000 has a host 6100 and an SSD 6200. The host 6100 has a host interface 6111, a host controller 6120, and a DRAM 6130.

[0172] The host 6100 can write data to or read data from the SSD 6200. The host controller 6120 can transmit signals (SGL), such as commands, addresses, control signals, and the like, to the SSD 6200 via the host interface 6111. The DRAM 6130 can serve as main memory for the host 6100.

[0173] The SSD 6200 can exchange SGL signals with the host 6100 via the host interface 6211 and can be powered via a power connector 6221. The SSD 6200 features multiple non-volatile memory modules 6201 to 620n, an SSD controller 6210, and an auxiliary power supply 6220. These non-volatile memory modules 6201 to 620n can be implemented not only as NAND flash memory, but also as non-volatile memory such as PRAM, MRAM, ReRAM, and the like.

[0174] Most 6201 to 620n non-volatile memory modules can be used as storage media for the 6200 SSD. Most 6201 to 620n non-volatile memory modules can be connected to the 6210 SSD controller via multiple channels (CH1 to CHn). A channel can be connected to one or more non-volatile memory modules. Non-volatile memory modules connected to a channel can be connected to the same data bus.

[0175] The SSD controller 6210 can exchange SGL signals with the host 6100 via the host interface 6211. These SGL signals contain commands, addresses, data, and other information. The SSD controller 6210 can be configured to write or read data to or from a corresponding non-volatile memory according to a command from the host 6100. The SSD controller 6210 is described in more detail in the following section. Fig. 23 will be described.

[0176] The auxiliary power supply 6220 can be connected to the host 6100 via the power connector 6221. The auxiliary power supply 6220 can be charged by a power PWR from the host 6100. The auxiliary power supply 6220 can be located inside or outside the SSD 3200. For example, the auxiliary power supply 6220 can be placed on a motherboard to provide auxiliary power to the SSD 6200.

[0177] Fig. Figure 23 is a block diagram of the SSD controller in the solid-state drive system of the Fig. 22. Referring to Fig. 23 An SSD controller 6210 has an NVM interface 6211, a host interface 6212, a management logic 6213 for compressed data, a control unit 6214, an SRAM 6215 and a DRAM 6216.

[0178] The NVM interface 6211 can distribute data transferred from the main memory of a host 6100 to channels CH1 through CHn. The NVM interface 6211 can also transfer data read from non-volatile memory modules 6201 through 620n to the host 6100 via the host interface 6212.

[0179] The 6212 host interface can connect to an SSD 6200 using the 6100 host protocol. The 6212 host interface can communicate with the 6100 using USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI Express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), etc. The 6212 host interface can perform disk emulation, allowing the 6100 host to recognize the SSD 6200 as a hard disk drive (HDD).

[0180] The 6213 compressed data management logic, as described above, can manage data stored in non-volatile memory units 6201 to 620n using an ECC block unit and support collective write operations for compressed data. The 6214 control unit can analyze and process a signal input from the 6100 host. The 6214 control unit can control the 6100 host via the 6212 host interface or the 6201 to 620n non-volatile memory units via the 6211 NVM interface. The 6214 control unit can manage the 6201 to 620n non-volatile memory units according to the firmware for driving the 6200 SSD.

[0181] The SRAM 6215 can be used to drive or operate software that efficiently manages the non-volatile memory modules 6201 to 620n. The SRAM 6315 can store metadata inputs from the host's main memory 6100 or cache data. In the event of a sudden shutdown, metadata or cache data stored in the SRAM 6215 can be written to the non-volatile memory modules 6201 to 620n using an auxiliary power supply 6220.

[0182] The DRAM 6216 can temporarily store compressed data and provide a space for collecting compressed data. Likewise, as described above, a section of the DRAM 6216 can be designated as a wait area. Returning to Fig. 22. An SSD system can efficiently manage storage space by managing data through or with an ECC block unit and supporting a collective write operation for compressed data.

[0183] The DRAM 6216 can be placed inside the SSD controller 6210. However, the inventive concept is not limited to this. For example, the DRAM 6216 can be implemented outside the SSD controller 6210. In the Fig. 22 and Fig. 23. The SRAM 6215 and the DRAM 6216 can be replaced by non-volatile memory. Therefore, the SSD system 6000 can be configured such that non-volatile memory (for example, PRAM, RRAM, MRAM, and the like) performs the roles of the SRAM 6215 and the DRAM 6216.

[0184] Fig. Figure 24 is a block diagram of an electronic device comprising a flash memory system according to an embodiment of the inventive concept. In this context, an electronic device 7000 can be a personal computer or a handheld electronic device such as a notebook computer, a mobile phone, a PDA, a camera, or the like.

[0185] Referring to Fig. 24 The electronic device 7000 comprises a memory system 7100, a power supply device 7200, an auxiliary power supply 7250, a CPU 7300, a DRAM 7400, and a user interface 7500. The memory system 7100 comprises a flash memory 7110 and a memory controller 7120. The memory system 7100 can be embedded within the electronic device 7000.

[0186] As described above, the Electronic Device 7000 can efficiently manage a storage space by managing data through or with an ECC block unit and supporting a collective write operation for compressed data.

[0187] A storage system according to an embodiment of the inventive concept is applicable to a flash memory which has a three-dimensional structure as well as to a flash memory which has a two-dimensional structure.

[0188] Fig. 25 is a block diagram of a flash memory, which is applied to the inventive concept. Referring to Fig. 25 A flash memory 8000 has a three-dimensional (3D) cell arrangement 8110, a data input / output circuit 8120, an address decoder 8130 and a control logic 8140.

[0189] The 3D cell array 8110 comprises multiple memory blocks BLK1 to BLKz, each configured to have a three-dimensional (or vertical) structure. For a memory block with a two-dimensional (horizontal) structure, memory cells can be arranged horizontally to a substrate. For a memory block with a three-dimensional structure, memory cells can be arranged perpendicular to the substrate. Each memory block can be an erase unit of the 8000 flash memory.

[0190] The 8120 data input / output circuit can be connected to the 8110 3D cell array via multiple bit lines. The 8120 data input / output circuit can receive data from an external device or output data read by the 8110 3D cell array to the external device. The 8130 address decoder can be connected to the 8110 3D cell array via multiple word lines and GSL and SSL select lines. The 8130 address decoder can select the word lines in response to an ADDR address.

[0191] The 8140 control logic can control programming, erasing, reading, etc. of the 8000 flash memory. For example, during programming, the 8140 control logic can control the 8130 address decoder in such a way that a programming voltage is provided for a selected word line, and it can control the 8120 data input / output circuit in such a way that data is programmed.

[0192] Fig. 26 is a perspective view which schematically depicts a 3D structure of a memory block located in the flash memory of the Fig. 25 is illustrated. Referring to Fig. 26. A storage block BLK1 can be formed perpendicular to a substrate SUB in one direction. An n+ doping region can be formed on the substrate SUB. A gate electrode layer and an insulating layer can be deposited or arranged sequentially or alternately on the substrate SUB. A charge storage layer can be formed between the gate electrode layer and the insulating layer.

[0193] If the gate electrode layer and the insulating layer are patterned or structured in a vertical direction, a V-shaped column can be formed. The column can be connected to the substrate SUB via the gate electrode layer and the insulating layer. An outer section O of the column can be formed from a channel semiconductor, and an inner section I can be formed from an insulating material such as silicon oxide.

[0194] The gate electrode layer of memory block BLK1 can be connected to a ground selector line GSL, a plurality of word lines WL1 to WL8, and a string selector line SSL. The column of memory block BLK1 can be connected to a plurality of bit lines BL1 to BL3. Fig. Figure 13 illustrates the case where a memory block BLK1 has two selection lines SSL and GSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3. However, the inventive concept is not limited to this.

[0195] Fig. Figure 27 is a circuit diagram of an equivalent circuit of the memory block of the Fig. 26. Referring to Fig. 27. NAND strings NS11 to NS33 can be connected between bit lines BL1 to BL3 and a common source line CSL. Each NAND string (for example, NS11) has a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST.

[0196] The string selector transistors SST can be connected to string selector lines SSL1 to SSL3. The memory cells MC1 to MC8 can each be connected to corresponding word lines WL1 to WL8. The ground selector transistors GST can be connected to the ground selector line GSL. A string selector transistor SST can be connected to a bit line, and a ground selector transistor GST can be connected to a common source line GSL.

[0197] Word lines (e.g., WL1) that have the same height can be connected together, and the string selection lines SSL1 to SSL3 can be separate. When programming memory cells (which constitute a page) connected to a first word line WL1 and containing NAND strings NS11, NS12, and NS13, a first word line WL1 and a first string selection line SSL1 can be selected.

Claims

[1] Storage device (120) comprising the following: a user area (126) of a memory cell arrangement; a buffer area (124) configured to temporarily store compressed data to be written to the user area (126); and a management logic (123, 1370, 6213) for compressed data, which is configured to control the user space (126) and the buffer space (124) such that compressed data stored in the buffer space (124) is written to the user space (126), where the management logic (123, 1370, 6213) for compressed data manages compressed data which is to be written to the user area (126) using an ECC block unit, where during a write operation compressed data which is stored in the buffer area (124) is written to the user area (126) with a programming unit which is larger than the ECC block unit. [2] Storage device (120) according to claim 1, wherein the ECC block unit is a bit size which increases the reliability of compressed data to be written to the user space (126). [3] Storage device (120) according to claim 2, wherein the ECC block unit has a data bit which is user data information and an ECC bit which is used to correct an error in the data bit. [4] Storage device (120) according to claim 1, wherein the programming unit is an integer multiple of the ECC block unit. [5] Storage device (120) according to claim 1, wherein the buffer area (124) temporarily stores first compressed data and second compressed data and the compressed data management logic (123, 1370, 6213) writes the first and second compressed data to the same page of the user area (126). [6] Storage device (120) according to claim 1, further comprising: a compressor (122, 1360) configured to compress raw data requested for writing; and an ECC circuit which is configured to add an ECC bit to raw data which is compressed by the compressor (122, 1360) and to generate the compressed data which is to be written to the user space (126). [7] Storage device (120) according to claim 1, further comprising: a compressed data management table configured to manage location information of compressed data stored in the user space (126), wherein the compressed data management table manages location information of compressed data stored in the user space (126) with an ECC block unit smaller than the programming unit according to the control of the compressed data management logic (123, 1370, 6213). [8] Storage device (120) according to claim 7, wherein the compressed data management table manages the following: Information which is linked to the physical address of the compressed data which is stored in the user area (126), Information which is linked to the starting number of the ECC block of the compressed data which is stored in the user area (126), and Information which is linked to the ECC block length of the compressed data which is stored in the user area (126). [9] Storage device (120) according to claim 8, wherein the compressed data management table further manages information which is associated with a logical address which corresponds to the physical address of the compressed data which is stored in the user area (126). [10] Storage device (120) according to claim 7, wherein the compressed data management table manages information which is associated with a physical address of first and second compressed data which are stored in the user area (126), and wherein the first and second compressed data have the same physical address. [11] Storage device (120) according to claim 1, wherein the management logic (123, 1370, 6213) for compressed data determines, based on the bit size of an empty area of ​​the first compressed data, whether or not to write second compressed data to the user area (126) containing first compressed data. [12] Storage device (120) according to claim 11, wherein, when the bit size of the empty area of ​​the first compressed data is larger than the bit size of the second compressed data, the first and second compressed data are programmed into the same side of the user area (126). [13] Storage device (120) according to claim 11, wherein if the bit size of the empty area of ​​the first compressed data is smaller than the bit size of the second compressed data, the first compressed data is programmed into the user area (126). [14] Storage device (120) according to claim 11, wherein the time of a write request of the first compressed data is before the time of a write request of the second compressed data. [15] Storage device (120) according to claim 1, wherein the buffer area (124) has a waiting area (1341) which temporarily stores a plurality of compressed data, while the compressed data management logic (123, 1370, 6213) compares the bit size of compressed data that is requested to be written with an empty area of ​​each of the plurality of compressed data which is stored in the waiting area (1341). [16] Storage device (120) according to claim 15, wherein, if the bit size of the write-requested compressed data is smaller than an empty area of ​​selected compressed data from a plurality of compressed data stored in the wait area (1341), the compressed data management logic (123, 1370, 6213) writes the write-requested compressed data and the selected compressed data to the same page of the user area (126). [17] Storage device (120) according to claim 16, wherein, if the bit size of the write-requested compressed data is larger than empty areas of a plurality of compressed data stored in the wait area (1341), the compressed data management logic (123, 1370, 6213) transfers the write-requested compressed data to the wait area (1341). [18] Storage device (120) according to claim 17, wherein the management logic (123, 1370, 6213) for compressed data compares the bit size of the wait area (1341) with a reference bit size and writes selected data from a plurality of compressed data stored in the wait area (1341) when the bit size of the wait area (1341) is larger than the reference bit size. [19] Storage device (120) according to claim 1, wherein the management logic (123, 1370, 6213) for compressed data compares the bit size of an empty area of ​​first compressed data with the bit size of second compressed data and splits the second compressed data if the bit size of the empty area of ​​the first compressed data is smaller than the bit size of the second compressed data. [20] Storage device (120) according to claim 19, wherein the management logic (123, 1370, 6213) for compressed data divides the second compressed data into first and second subdivided compressed data and the bit size of the first subdivided compressed data is smaller than the bit size of an empty area of ​​the first compressed data. [21] Storage device (120) according to claim 20, wherein the management logic (123, 1370, 6213) for compressed data writes the first compressed data and the first subdivided compressed data to the same side of the user area (126). [22] Storage device (120) according to claim 20, wherein the management logic (123, 1370, 6213) for compressed data provisionally stores the second subdivided compressed data in the buffer area (124). [23] Storage device (120) according to claim 1, wherein the management logic (123, 1370, 6213) for compressed data simultaneously writes at least one compressed data which is stored in the buffer area (124) to a plurality of pages of the user area (126). [24] Non-volatile storage device comprising the following: a non-volatile memory (2220, 3220, 4220) configured to perform a programming operation with a programming unit of a plurality of pages; a buffer memory (124) configured to temporarily store compressed data to be programmed into the non-volatile memory (2220, 3220, 4220); and a management logic (123, 1370, 6213) for compressed data, which is configured to control the non-volatile memory (2220, 3220, 4220) and the buffer memory (124) such that compressed data stored in the buffer memory (124) is programmed into the non-volatile memory (2220, 3220, 4220), wherein the management logic (123, 1370, 6213) for compressed data manages compressed data which is stored in the non-volatile memory (2220, 3220, 4220) with an ECC block unit smaller than the bit size of a page of the non-volatile memory (2220, 3220, 4220), wherein during a write operation compressed data which is stored in the buffer memory (124) is written to the non-volatile memory (2220, 3220, 4220) using a programming unit which is larger than the ECC block unit. [25] Non-volatile storage device according to claim 24, wherein the buffer memory (124) stores a plurality of compressed data, wherein the plurality of compressed data stored in the buffer memory (124) is to be programmed simultaneously into the non-volatile memory (2220, 3220, 4220) when the bit size of the plurality of compressed data stored in the buffer memory (124) is smaller than the programming unit of a plurality of pages. [26] Non-volatile storage device according to claim 24 or 25, further comprising: A compressed data management table configured to manage location information for compressed data stored in non-volatile memory (2220, 3220, 4220). wherein the compressed data management table manages location information of compressed data stored in the non-volatile memory (2220, 3220, 4220), and wherein the compressed data is stored with an ECC block unit smaller than the bit size of a page under the control of the compressed data management logic (123, 1370, 6213). [27] Non-volatile storage device according to claim 24, wherein the non-volatile memory (2220, 3220, 4220) comprises a plurality of compressed data which are programmed by a programming operation, and predetermined compressed data of the plurality of compressed data are subdivided to be stored in at least two sides of the non-volatile memory (2220, 3220, 4220). [28] Operating method of a non-volatile storage device comprising the following: a compression of write-requested data; a collection of the compressed data in a read / write memory (RAM); a programming of compressed data, which is collected in RAM, into non-volatile memory (2220, 3220, 4220); and Updating a compressed data management table to manage compressed data stored in non-volatile memory (2220, 3220, 4220) using an ECC block unit, where, during a write operation, compressed data stored in RAM is written to non-volatile memory (2220, 3220, 4220) using a programming unit larger than the ECC block unit. [29] Operating method according to claim 28, further comprising: a comparison of the bit size of the write-requested data with the bit size of each of the empty areas of a plurality of compressed data stored in the RAM, where, if the bit size of the write-requested data is smaller than the bit size of an empty area of ​​selected one of the majority of compressed data stored in the RAM, the write-requested data and the selected compressed data are programmed into the same page of non-volatile memory (2220, 3220, 4220).

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