Device for operating passive infrared sensors

Abstract

Device for operating a passive infrared detector (PIR) - wherein at least one of the terminals of the passive infrared detector (PIR) is connected by an electrical circuit arrangement (R G ) is discharged and - wherein the equivalent resistance of the electrical circuit arrangement (RG) has a resistance value greater than 1 MOhm and / or greater than 10 MOhm and / or greater than 100 MOhm and / or greater than 1 GOhm and / or greater than 10 GOhm at least at one operating point and - wherein the electrical circuit arrangement (R G ) comprises a switched capacitor circuit and - where the switched capacitor circuit comprises two strands and - where each strand comprises several transfer gates and - where each string comprises several storage capacities and - where the transfer gates are switched alternately with one of two non-overlapping clocks (ϕ1, ϕ2) and - where, apart from the non-overlapping, one measure is the inverse of the other measure and - whereby the storage capacities are designed to transport a certain amount of charge with each half cycle by one node and - wherein the respective strands are designed to be operated in a half-cycle staggered manner to cause a continuous charge discharge and - wherein the device is designed to switch off the clock during measuring phases.

Description

IntroductionVarious methods are known for measuring infrared radiation. An essential sensor principle is the use of passive infrared detectors (PIR detectors).These are distinguished by simple and cost-effective production.Such PIR detectors are two-poles and can be symbolized in the equivalent circuit diagram by a current source which supplies a current I PIR depending on the change in the irradiation and thus the temperature, and to which a capacitance C is connected in parallel in PIR fashion. (See also FIG. 1 )Various problems now occur when evaluating the signal of a PIR sensor:Firstly, the operating point of the PIR detector is shifted by self-charging. On the other hand, the current source I PIR generally supplies only a very low current with a relatively high internal resistance. This internal resistance R PIR is shown in FIG. 1. These boundary conditions result in the requirement for a large dynamic range and a very high internal resistance for the following amplifier and analog-to-digital converter circuit (evaluation circuit).Due to the high internal resistance of an optimum evaluation circuit, charges generated once, however, can no longer flow away. This can lead to the circuit leaving the working range of the evaluation circuit, since the latter is overdriven.An object detection device is known from US 2013 / 0 082 179 A1. The object detection device of US 2013 / 0 082 179 A1 comprises:• a pyroelectric element configured to output a current signal in response to a change in an amount of infrared light;• an I / V conversion circuit including an operational amplifier, a capacitive element serving as a feedback circuit, and a discharge circuit, and configured to convert the current signal into a voltage signal;• an A / D conversion circuit configured to convert the voltage signal to a first digital signal;• a digital filter configured to extract a detection component having a frequency included in a frequency band associated with an object from a waveform represented by the first digital signal by subjecting the first digital signal to arithmetic processing, and generate a second digital signal representing a waveform of the detection component;• a judging circuit configured to detect the target based on the second digital signal; and• a control unit configured to control the discharge circuit based on a period corresponding to a predetermined frequency not greater than a lower limit of the frequency band, to discharge electric charges stored in the capacitive element.WO 2004 / 090 570 A2 discloses a sensor device for detecting a physical parameter such as radiation, temperature or the like. The sensor device of WO 2004 / 090 570 A2 comprises an analog sensor element which is sensitive to the physical parameter to be detected and outputs an analog signal. The sensor device of WO 2004 / 090 570 A2 comprises an analog two-digital converter (ADC) with a MOS input stage for receiving the analog output signal of the sensor element in order to convert the analog output signal into a digital output signal.From US 4 825 079 A a pyroelectric infrared detector is known, which is used e.g. in a intruder alarm system. The pyroelectric infrared detector of U.S. Pat. No. 4,825,079 A has a pyroelectric element, an FET for receiving the output of the pyroelectric element, a capacitor connected in parallel with the pyroelectric element, and other circuit parts. These components of the device of U.S. Pat. No. 4,825,079 A are integrated in a housing according to U.S. Pat. No. 4,825,079 A.The sensor of WO 2007 / 057 179 A2 comprises a housing in which an infrared sensor element having two connecting pins and a circuit connected to the connecting pins of the infrared sensor element are arranged, The method of WO 2007 / 057 179 A2 comprises the steps of repeatedly generating and applying individual known electrical charges to one of the connecting pins at a predetermined frequency per unit time and measuring the voltage between the two connecting pins and indicating a failure of the passive infrared sensor if the voltage deviates from a desired voltage by more than a predetermined value.Object of the InventionIt is the object of the invention to provide an evaluation method and a high-resistance measurement circuit with a large dynamic range for evaluating the signal of a PIR detector without an overload occurring as a result of the charging of the inputs of the PIR detector evaluation circuit. The current consumption is to be minimized.This object is achieved by a device according to claim 1. Further embodiments are the subject matter of the dependent claims.Description of Technical SolutionThe invention relates to an apparatus for operating a passive infrared detector (PIR). According to the invention, at least one of the terminals of the passive infrared detector (PIR) is discharged by an electrical circuit arrangement (R G). According to the invention, the equivalent resistor has a resistance value greater than 1 MOh and / or greater than 10 MOh and / or greater than 100 MOm and / or greater than 1 GOh and / or greater than 10 GOh at least at one operating point.According to the invention, the electrical circuit arrangement (R G) comprises a switched capacitor circuit. The switched capacitor circuit comprises two strings according to the invention. According to the invention, each string comprises a plurality of transfer gates and a plurality of storage capacities. The transfer gates are alternately switched according to the invention with one of two non-overlapping clocks (φ 1, φ 2) with the one clock being the inverse of the other clock except for the non-overlapping. According to the invention, the storage capacitors are designed to continue to convey a certain amount of charge by one node with each half cycle and to be operated offset by one half cycle in order to cause a continuous discharge of charge. In particular, the device according to the invention is configured to switch off the clock in measurement phases. In a first variant according to the invention, the device for operating a passive infrared detector (PIR) is configured such that the cycle of the discharge depends on the input voltage. In a second variant according to the invention, the device for operating a passive infrared detector (PIR) is configured such that at least two of the connections of the passive infrared detector (PIR) are discharged by an electrical circuit arrangement, the equivalent resistance of which in each case has a resistance value greater than 1MOh and / or greater than 10MOh and / or greater than 100MOh and / or greater than 1GOm and / or greater than 10GOm at at least one operating point. In a third variant according to the invention, the device for operating a passive infrared detector (PIR) is configured such that at least one of the connections of the passive infrared detector (PIR) is discharged by an electrical circuit arrangement whose equivalent resistance is greater at least at one working point than at another working point. In a fourth variant according to the invention, the device for operating a passive infrared detector (PIR) is configured such that, for the first, the current through the switched capacitor circuit depends on the input voltage between the electrical terminals of the passive infrared detector (PIR) and / or on the voltage between at least this electrical terminal of the passive infrared detector (PIR) and a reference potential, and, for the second, in a predefined first range (A) of said voltage, the current disappears up to a leakage current, and, for the third, the discharge current disappears with increasing distance of the input voltage between the electrical terminals of the passive infrared detector (PIR), the discharge current outside this range (B, c) and / or is greater than in said first region (A).In a fifth variant according to the invention, the device for operating a passive infrared detector (PIR) is configured such that the average equivalent resistance of at least one electrical circuit arrangement for discharging at least one terminal of the passive infrared detector (PIR) is different at different times, wherein, since the equivalent resistance depends on the clock (φ1, φ2), the averaging of the equivalent resistance is related to a plurality of periods of this clock. In a sixth variant according to the invention, each of the outputs of said passive infrared detector (PIR) is connected to the control input of a respective associated input transistor (T 1, T 2). In a seventh variant according to the invention, in each case one contact of each of these input transistors (T 1, T 2) is connected to an associated current divider output (I a1, I a2) of a controllable current divider (MUX, R M1 to R Mn) and the said current divider (MUX, R M1 to R Mn) divides the current of a reference current source (I ref) as a function of a control input (Val) to the current divider outputs (I a1, Ia2). In an eighth variant according to the invention, in each case one contact of the transistors (T 1, T 2) is in each case connected to in each case one integrating filter and / or one capacitor (C 1, C 2) in each case. In a ninth variant according to the invention, the device is configured such that the output values of these integrating filters and / or capacitances (C 1, C 2) are compared with one another by at least one comparator (CP). In a tenth variant according to the invention, the device is configured so that the comparator output signal (CPO) of this comparator (CP) controls at least one digital integrating filter (Int). In an eleventh variant according to the invention, the control input (Val) of the current divider (MUX, R M1 to R Mn), which divides the current of a reference current source (I ref) depends directly or indirectly on the numerical value of the digital integrating filter (Int). In a twelfth variant according to the invention, the device comprises a differential amplifier stage, wherein the control electrode of the first transistor (T 1) and the control electrode of the second transistor (T 2) form the differential input of the differential amplifier stage. In a thirteenth variant according to the invention, the differential amplifier stage comprises a reference current source (I ref) and a resistor (R M1 to R Mn) which resistor (R M1 to R Mn) comprises a controllable tap connected to said reference current source (I ref). In this thirteenth variant according to the invention, the terminal of the resistor (R M1 to R Mn) is connected to a first transistor (T 1) and the other terminal of the resistor (R M1 to R Mn) is connected to a second transistor (T 2). In this thirteenth variant according to the invention, the control of the tap is controllable by an external variable. In this thirteenth variant according to the invention, each transistor (T 1, T 2) is connected by its third terminal to a load resistor (R 1, R 2, C 1, C 2, IW 1, IW 2) which can be a differential load resistor. In a fourteenth variant according to the invention, the controllable resistor comprises an analog 1:(n-1) multiplexer or an analog 1:n multiplexer or an analog 1:(n+1) multiplexer (MUX) which are connected to the said reference current source (Iref) by the single output which represents the tap of the controllable resistor, wherein the controllable resistor comprises a resistor chain comprising n resistors (R M1 to R Mn) as resistor (R M1 to R Mn) and wherein each of the (n-1) nodes between in each case two of the n resistors (R M1 to R Mn) is connected to an input / output of the analog multiplexer (MUX). In this fourteenth variant according to the invention, in the case of a 1:n multiplexer (MUX), the end or the start of the resistor chain comprising the resistors (R M1 to R Mn) are additionally connected to the multiplexer (MUX). In this fourteenth variant according to the invention, in the case of a 1:(n+1) multiplexer (MUX), the end and the start of the resistor chain comprising the resistors (R M1 to R Mn) are additionally connected to the multiplexer (MUX). In this fourteenth variant according to the invention, the beginning of the resistor chain comprising the resistors (R M1 to R Mn) is connected to at least one first transistor (T 1) and the end of the resistor chain comprising the resistors (R M1 to R Mn) is connected to at least one second transistor (T 2).The technical background and the effects of the technical solutions and the environment of the invention are explained in more detail below.A proposed system is shown in FIG. 1. The passive infrared detector (PIR) is connected with its two connection lines to a discharge network R G. This in turn is connected to an analog-to-digital converter (ADC). The output of the analog-to-digital converter is connected via a first bus (T) having a first bus bandwidth to a digital filter (DF), the output Out of which typically has a greater second bus bandwidth than the first bus bandwidth.During the development of the proposed method for operating a passive infrared detector (PIR), it was recognized that the charging of the inputs represents a major hindrance to a correct operation of the system. As will be explained in more detail below, the proposed ΔΣ converter (ADC) is sensitive to such operating point drift. This increased sensitivity of the proposed ΔΣ converter (ADC), however, enables a particularly efficient suppression of the quantization errors by the comparator of the proposed ΔΣ converter (ADC). Therefore, the proposed ΔΣ converter and the discharge of the passive infrared detector by means of the proposed discharge network (R G) form a proposed unit. Based on this recognition of the erroneous charging of the inputs, the simplest solution to this problem can be achieved by discharging the input nodes by means of a switch when the voltage at the detector reaches the dynamic range. In this case, no evaluation of the voltage at the detector can be made during the discharge and shortly thereafter. Alternatively, the discharge can be effected through a leakage resistor between the terminals of the sensor or from the terminals to the reference ground (R dis_1, R dis_2). A substantial disadvantage of this solution is the continuous attenuation of the signal and the intrinsic noise of the detector. In addition, a giga-ohm resistor cannot be implemented with reasonable effort in a low-cost CMOS technology. In the course of the development, it has been recognized that the discharge of the second output via the internal resistance of the current source of the PIR sensor (PIR) does not lead to satisfactory results. It has been found that the resistance value of these leakage resistors should be greater than 1 MOh and / or preferably greater than 10 MOh and / or preferably greater than 100 MOh and / or preferably greater than 1 GOh and / or preferably greater than 10 GOh. The optimum derivative value depends on the respective PIR detector and the respective application and should be adapted from case to case. In the case of large charge displacements due to rapid temperature changes (temperature shock), disproportionately low leakage resistance values would be necessary, which almost eliminate the signal to be detected. It is clear here that the leakage resistances of the discharge network (R G) should preferably be designed to be the same and as symmetrical as possible, in the technical language "matching". These leakage resistors can also be more complex circuits which only perform the function of a leakage resistor, among other things. In the course of the elaboration of the proposal, it has been found to be advantageous to design the leakage resistors at least partially as a switched capacitor circuit. With such circuits, the relatively high-resistance leakage resistors, which may be required, can be designed relatively easily. For the operation of such a switched capacitor network, it is particularly advantageous if these networks are operated with a non-overlapping two-phase clock. Of course, single-phase and polyphase clocks can also be used, but these can generally be realized more complexly.The requirement for reliable discharge of the PIR detector is in contrast to the highest possible input resistance of the evaluation circuit. It was therefore recognized within the scope of the proposal that it is expedient to make the mean equivalent resistance of at least the discharge resistances of the passive infrared detector dependent on whether or not a measurement of the infrared radiation potential is being carried out by means of the passive infrared sensor (PIR detector). Before a measurement, the discharge resistors are switched to a very high-impedance state (measurement state). After the end of the measurement, the discharge resistors are switched to a state which is lower ohmic compared to the measurement state.Alternatively, the charge state (voltage at the detector) can be measured and the size of the discharge resistors can be readjusted as a function of the charge state.It is conceivable that other operating conditions also require a changeover. For example, it is conceivable to discharge the PIR detector in a defined manner via a switch. In such a mode, a high-impedance switching of the discharge resistors would likewise be expedient. In extreme cases, the measurement state can therefore mean a complete decoupling of a discharge resistor.The resistance values are always oriented at mean values over a plurality of cycles of the operating cycle of the respective switched capacitor network, provided that such a circuit is used for the realization of the discharge resistors. It is therefore an essential proposed idea that the discharge resistances of the PIR detector assume different values depending on states of the sensor system, wherein at least the states measurement and no measurement / discharge should be realized.The proposed ΔΣ converter (ADC) consists, inter alia, of a differential amplifier whose current source is not symmetrically divided, as is customary in normal differential amplifiers, into two branches with symmetrical actuation of the transistors of the differential amplifier, but rather which has a current divider instead of the normally present common node for the transistors in the branches of the differential amplifier and of the operating current source, which divider divides the current differently depending on an external control value. It can be assumed here that the operating current source has a finite internal resistance. In this respect, the use of a real voltage source is also possible. In the device according to the invention, this current divider is realized by a resistor chain which is connected at one end to a transistor of the differential amplifier and at the other end to the other transistor of the differential amplifier. A multiplexer now connects the operating current source to a node of this resistor chain depending on the external control value. The current divider thus behaves as a digitally controlled potentiometer, the tap of which is set by the external parameter. This sets a different current negative feedback for the different branches of the differential amplifier. The current distribution is effected in such a way that the gate-source voltages of the transistors are adjusted by the voltage drop across the resistors of the current divider in such a way that the sum of the currents through the two branches corresponds to the current of the operating current source. The other terminals of the transistors are each connected to a working resistor. It has proven to be particularly advantageous if these load resistors are designed as real current sources, since the differential load resistor and thus the differential amplification are then particularly large.Capacitances can be connected in parallel with these load resistors, which integrate the output signal. The use of Miller capacitances is likewise conceivable. In the case of the ΔΣ converter according to the proposal, these capacitances perform the summing Σ function of the ΔΣ converter and thus eliminate the quantization error by a downstream comparator.The following method is suitable for operating a passive infrared detector: each of the outputs of said passive infrared detector is connected to the control input of an associated input transistor of the described differential amplifier. In this case, a contact of each of these input transistors is connected to an associated current divider output of a controllable current divider. Said current divider distributes the current of a reference current source (I ref) to the current divider outputs as a function of a control input. The other contacts of the transistors are each connected to a working resistor, preferably an integrating filter or a capacitor (C 1, C 2) respectively. The output values of these integrating filters, load resistances and capacitances are now compared with one another by at least one comparator. This generates an inevitable quantization error that is minimized by the feedback described below. The comparator output signal of this comparator is connected to a digital integrating filter which performs a second integration in addition to said capacitances. The control input of said current divider, which divides the current of an operating current source, is connected to the output of the digital integrating filter. When the current divider is analog controlled, a digital-to-analog converter (DAC) and / or a signal format converter is required which converts the output of the digital integrating filter to a suitable format. In the example described here, however, this is not necessary since the multiplexer can be controlled digitally.A similar situation may be required when adapting a digital control input for the current divider to the digital output of the digital integrating filter.In addition to this two-phase version, a single-phase version of an evaluation circuit can also be used. An output of the passive infrared detector controls at least one second current source. This second current source feeds current to a first node (S b). This first node (S b) is connected via an integrating filter to the input of a comparator which compares the signal level of this first node (S b) with an internal level. The output of this comparator is again directly or indirectly connected to said digital integrating filter and thus drives it. The output of this digital integrating filter now again controls a digital-to-analog converter (DAC). The output of this digital-to-analog converter now controls a first current source (I 1), which in turn also feeds its current into the first node (S b). In contrast to the previous version, in this version one connection of the passive infrared detector is connected to ground, while the other connection is connected to the evaluation circuit described above. Such a circuit is also suitable for evaluating thermopiles.For both methods, it is advantageous if the digital integrating filter is realized as an up / down counter which counts in measurement phases in a predetermined or programmable clock. The counting direction is preferably defined by the output of the comparator. The step size of this count and the time intervals in which a count takes place can also be constant and predetermined or programmable. In some applications it has proved to be useful to make the step size of the count dependent on the count itself in order to avoid overflow or underflow and thus total functionality integrity.If the counter reading exceeds a critical upper value, this can be detected, for example, and can cause the measurement state to be left and the discharge state of the detector element to be activated. This is particularly useful in the one-handed variant, since it is capable of measuring the absolute level of an input signal. The output of the digital integrating filter represents the measurement value.In any case, however, it is still expedient to arrange a further digital filter (DF) after the digital integrating filter before the measured value is used. This suppresses the quantization errors from a cutoff frequency.It can be shown that the quantization error becomes zero at a frequency of 0 Hz in the interference spectrum and tends towards a finite value for infinitely high frequencies. The cut-off frequencies are thereby essentially dependent on the load capacitances (C 1, C 2) and the resistance (R M) of the current divider and can thus be well adjusted.It is of course expedient to allow essential parts of this method to run in a signal processor. Only the input stages should then be produced in specially designed electronics. Such an apparatus is then capable of carrying out the method described above.The proposal is explained below with reference to the attached figures: FIG. 1 shows the basic blocks of a device according to the proposal of a passive infrared detector. The device consists of a passive infrared detector (PIR) coupled to the discharge network R G. The purpose of this discharge network is to eliminate charging of the PIR detector and to keep the PIR detector at a working point which is favorable for the subsequent analog-to-digital converter without loading the dynamics of the system. The analog-to-digital converter converts the signal of the discharge network into a first digital signal on a bus T having a first bus width (number of bits). A subsequent digital filter (DF) filters the signal on the first bus T and outputs the data with a greater resolution via an output bus (Out). Therefore, the output bus Out typically has a greater bus width than the first bus T. FIG. 2 shows the non-claimed equivalent circuit diagram of a passive infrared detector (PIR) with a substitute current source (I PIR) and a series circuit of parasitic detector capacitance (C PIR) and associated loss resistance R PIR_C and the internal resistance of the substitute current source (R PIR). This internal resistance of the current source (R PIR) is in parallel with the current source (I PIR) and is typically very high. Too much load on the detector therefore causes the output voltage to break down. FIG. 3 shows a one-handed version of the analog-to-digital converter (ADC) of FIG. 1. a first controlled current source (I 1) ( also referred to as a further current source) is controlled by the feedback path and feeds to the first node (Sb). A second controlled current source (I 2) ( also referred to as current source) is controlled by an output of the passive infrared detector and also feeds to the first node (S b). The sum of the two current source currents charges or blows off a capacitance (C 1b). If the control loop is stable, the second current source (I 2) supplies a current which is different in sign but has the same amount as the first current source (I 1). The comparator (CP b) has its input connected to this capacitor (C 1b) and compares the voltage value at this capacitor and thus at the first node (S b) with an internal comparison value. The up / down counter (Int b) now counts up by one or by one with each system clock in this example, depending on whether the input of the comparator (CP b) is above or below the switching threshold of the comparator (CP b). 6 bits of the counter reading of the up / down counter (Int b) are used for feedback, for example. In this example, these 6 bits are converted by a digital-to-analog converter (DAC) into an analog signal that controls the further current source (I 1). A digital filter (DF) filters the count of the up-down counter (Int b) to the output signal (Out) which is the output bus of the digital filter DF. FIG. 4 likewise shows a one-handed version of the analog-to-digital converter (ADC) from FIG. 1. However, instead of the controllable current source, the one source of the one reference signal is now realized in such a way that the count (Val) of the up / down counter (Int b) now controls the tap (IN FB) on a resistor cascade (R FB) made of individual resistors (not shown). This tap can then be fed to a differential transconductance amplifier having the current output (CS). The current outputs charge and discharge a capacitor (C 1, C 2). The voltages occurring at the capacitors (C 1, C 2) are compared with one another by a comparator (CP), which in turn controls the up / down counter (Int b). FIG. 5 shows a controllable current divider as part of a proposed differential stage consisting of the resistor chain of n resistors R M1 to R Mn, which are typically, but not necessarily, identical. Of the n+1 taps of the resistor string in this example, one is connected to the operating current source (I ref) through an analog multiplexer (MUX). The bus width of the control bus (Val) of the analog multiplexer (Mux) must be chosen sufficiently and should typically be greater than the logarithm of that of n to the base 2. The current divider, the current source and the transistors (T 1, T 2) form a proposed differential stage. FIG. 6 shows the differential stage from FIG. 5 with two load resistors (R L1, R L2). It is obvious that the current dividing resistors (R M1 to R Mn) result in a different current negative feedback for the two branches of the differential amplifier. This different current negative feedback is adjusted by the control signal (Val). In this example, two example outputs (ON, OP) are indicated. FIG. 7 shows the differential stage from FIG. 6 as part of a construction corresponding to FIG. 3; instead of the load resistors (R L1, R L2) from FIG. 6, a capacitor (C 1, C 2) connected in parallel with a load resistor (R 1, R 2) is used. The passive infrared sensor (PIR) corresponding to FIGS. 1 and 2 is connected to the connections IN and IP. FIG. 8 corresponds to FIG. 7 with the difference that the resistors (R 1, R 2) are replaced by real current sources (I W1, I W2). This has the advantage that they have an increased differential resistance. When implemented as a semiconductor integrated circuit, this design represents a solution that is robust with respect to parametric variations. The construction is very simple and for this reason only consumes very little current. At the same time, it has a very high input resistance. Since the source terminals follow the respective gate voltages (on average) as a result of the negative feedback via the current divider, the gate-source voltages do not fluctuate. Therefore, the complex input impedances are very high. The gate-source capacitances do not have to be substantially recharged. The quantization noise of the analog-to-digital converter decreases as the number n of resistors R Mi increases. The aforementioned points represent essential advantages of the proposal over the prior art. FIG. 9 shows a possible realization of the discharge circuit R G from FIG. 1 or of the discharge resistors (R dis_1, R dis_2) in FIG. 1, respectively. The switch capacitor implementation shown in this FIG. 9 operates with transfer gates that are alternately switched with one of two non-overlapping clocks (φ 1, φ 2). Except for the non-overlap, one clock is the inverse of the other clock. The storage capacities in this case each carry a certain amount of charge by one node with each half clock cycle. The figure shows two strands. The strings are operated offset by one half cycle each. This results in a continuous discharge of charge. If the clocks are switched off, which is preferably the case in particular in the measurement phases, then no current any longer flows. The working resistor thus formed becomes high-ohmic. If the cycle of the discharge is selected as dependent on the input voltage, the discharge can be controlled, for example, such that it is larger in the case of larger input voltage differences and smaller in the case of smaller input voltage differences and disappears in a predeterminable range. FIG. 10 shows another example of a discharging network R G as an active network. The transistors T 3 and T 4 are turned on depending on the difference of the input voltage between IP and IN. The differential amplifier forms the amount of the difference at its inputs OP and ON and opens the transistors T 3 and T 4 according to a predetermined function as a function of this amount of difference. Since the characteristic curve of the transistors is non-linear, this leads to a disappearing conductance of the transistors T 3 and T 4. in the case of a disappearing difference amount of the input voltage between IP and IN. FIG. 11 shows a further possible implementation of a discharge network R G. A first current source feeds half of the MOS diodes T9 and T14 with the current I. The current through the MOS diode T14 is decreased by T13. The current through the MOS diode T9 is decreased by T11. A second current source provides a current that is typically 80% of the value of the current of the first current source. Since transistor T11 forms a current mirror with MOS diode T12 and transistor T13 forms a current mirror with the same MOS diode T12, an offset current related to typically 80% of current I is attracted by the currents through T9 and T14, respectively. If the inputs IP and IN are not biased, this leads to an unbalanced current distribution through the differential stage comprising T5 and T6. This is then manifested in such a way that additional current can flow through the MOS diodes T 9 or T 14, which leads to an opening of the transistors T 7 and T 15 or T 8 and T 16 and thus to a discharge of the input nodes IP and IN. FIG. 12 shows an exemplary discharge resistance characteristic curve of a circuit according to FIG. 11 By suitable selection of the current mirror and transistor ratios, it can be achieved that the characteristic curve of the input resistance has an extremely high-ohmic range A, in which the input resistance is practically determined only by the leakage current of the circuit, and a range B, in which a voltage limitation begins, and a range C, in which the input resistance is very low-ohmic.The two terminals are thus discharged by this electrical circuit arrangement, the equivalent resistance of which is significantly greater at an operating point in the region A than at an operating point in the regions B or C.This makes it possible to operate a passive infrared detector such that the electrical terminals are discharged through a current path when the voltage is outside a predetermined range A. The discharge current through this circuit depends on the input voltage between the electrical terminals IP and IN. In the range A of the input voltage which is predetermined by the dimensioning, the discharge current disappears except for the leakage current of the transistors. In this case, the discharge current increases with an increasing absolute value interval of the input voltage outside this range A. The input resistance RIN(IP-IN) depends on the differential voltage V(IP-IN) between the inputs IP and IN of the network R G. The input resistance considered here can be assumed to be located both between the terminals IP and IN and between a terminal IP or IN on the one hand and the reference potential, for example ground, on the other hand. The behavior in Fig. 12 should preferably be similar in each of these two viewing cases.List of reference charactersA voltage range in which the discharge network has a high impedance ADC analog to digital converter B voltage range in which the discharge network has a medium conductivity C voltage range in which the discharge network has a higher conductivity C 1 first capacitance C 1b first integrating filter (third capacitance) C 2 second capacitance CP comparator CP b comparator CPO comparator output C PIR parasitic capacitance of the PIR sensor PIR CS current output of the differential transconductance amplifier DAC digital to analog converter DF downstream digital filter I 1 Further Current source I 2 Current source I a1 First current divider output I a2 Second current divider output IN First terminal for the PIR sensor Int Integrating filter (in the simplest case an up / down counter) Int b Integrating filter (in the simplest case an up / down counter) IN Second terminal for the PIR sensor IN FB Tap on a resistor cascade (R FB) composed of individual resistors I PIR Current source of the equivalent circuit diagram of the PIR sensor I ref Reference current source iw_ner163_Erste current source IW used as a load resistor 2 Second current source MUX used as a load resistor Analog 1:(n-1) or 1:n or 1:(n+1) multiplexer. In this case, n preferably has a value greater than three and / or 4. values of n=(2 m-2) where m>2 or m>3 are particularly advantageous. ON First output of the differential stage OP Second output of the differential stage Out output bus of the digital filter DF (=second filter DF) φ 1 First clock of the SC network for forming a discharge resistor φ 2 Second clock of the SC network for forming a discharge resistor. The clock is substantially inverse to φ 1 and does not overlap with φ 1. PIR PIR PIR sensor R 1 first working resistance R 2 second working resistance R dis_1 first unfavourable discharge resistance in the prior art. This leads to a load on the output IP and to a reduction in the output signal. In the device according to the proposal, this resistance is modulated. R dis_2 Second Unfavorable Discharge Resistance in the Prior Art. This leads to a loading of the output IN and to a reduction of the output signal. In the device according to the proposal, this resistance is modulated. R FB Resistor cascade of individual resistors. A control signal (Val) controls the tap of the output signal IN FB. The resistor cascade therefore behaves as a potentiometer controlled by the variable Val. The implementation takes place in a similar manner to the implementation of the current divider comprising multiplexer MUX and resistor cascade R M1 to R Mn. R G Discharge network. This discharge network prevents the PIR sensor from being charged both to ground and the connections of the PIR sensor from one another. RIN(IP-IN) is an input resistance of the network R G. which is dependent on the differential voltage V(IP-IN) between the inputs IP and IN. The input resistance can be assumed here to be located both between the terminals IP and IN and between a terminal IP or IN on the one hand and the reference potential, for example ground, on the other hand. The behavior in Fig. 12 should preferably be similar in either of these two cases. R L1 first load resistor R L2 second load resistor R M resistor of the current divider. This is the sum value of the resistor chain R M1 to R Mn made of n resistors. R M1 to R Mn resistances of the resistor chain comprising n resistances of the current part of the proposed differential stage R PIR internal resistance of the PIR sensor PIR, which is connected in parallel with the outputs of the PIR sensor (see FIG. 1 ) R PIR_C series resistance of the parasitic capacitance C PIR. S b first node T ADC output with typically a smaller bit width than bus Out T 1 first transistor of differential stage T 2 second transistor of differential stage T 3 third transistor T 4 fourth transistor T5 to T16 transistors of an exemplary further discharge network. Val control input of the multiplexer MUX V(IP-IN) voltage between the outputs of the PIR sensor and thus between the inputs of the discharge network R G V ref reference voltage

Claims

Device for operating a passive infrared detector (PIR) - wherein at least one of the terminals of the passive infrared detector (PIR) is discharged by an electrical circuit arrangement (R G) and - wherein the equivalent resistance of the electrical circuit arrangement (RG) has a resistance value greater than 1MOh and / or greater than 10MOh and / or greater than 100MOh and / or greater than 1GOm and / or greater than 10GOh at least at one operating point and - wherein the electrical circuit arrangement (R G) comprises a switched capacitor circuit and - wherein the switched capacitor circuit comprises two strings and - wherein each string comprises a plurality of transfer gates and wherein each string comprises a plurality of storage capacities and - wherein the transfer gates are alternately switched with one of two non-overlapping clocks (φ 1, φ 2) and - wherein apart from the non-overlapping the one clock is the inverse of the other clock and - wherein the storage capacities are configured to in each case convey a certain amount of charge further around a node with each half clock and - wherein the respective strings are configured to in each case be operated offset by one half clock in order to cause a continuous flow of charge and - wherein the apparatus is configured to switch off the clock in measurement phases.Device for operating a passive infrared detector (PIR) according to claim 1. - wherein the clock of the discharge depends on the input voltage.Device for operating a passive infrared detector (PIR) according to claim 1, wherein - at least two of the terminals of the passive infrared detector (PIR) are discharged by an electrical circuit arrangement, the equivalent resistance of which in at least one operating point each have a resistance value greater than 1MOh and / or greater than 10MOh and / or greater than 100MOh and / or greater than 1GOh and / or greater than 10GOm.Device for sensing a passive infrared detector (PIR) according to one or more of the preceding claims, wherein - at least one of the terminals of the passive infrared detector (PIR) is discharged by an electrical circuit arrangement, the equivalent resistance of which is greater at least at one working point than at another working point.Device for operating a passive infrared detector (PIR) according to one of the preceding claims and claim 2, - wherein the current through the switched capacitor circuit depends on the input voltage between the electrical terminals of the passive infrared detector (PIR) and / or on the voltage between at least this electrical terminal of the passive infrared detector (PIR) and a reference potential, and - wherein in a predefined first range (A) of said voltage the current disappears up to a leakage current, and - wherein the discharge current increases outside this range (B, C) with increasing absolute value distance of the input voltage between the electrical terminals of the passive infrared detector (PIR) and / or is greater than in said first range (A).Device for operating a passive infrared detector (PIR) according to one of the preceding claims, wherein - the average equivalent resistance of at least one electrical circuit arrangement for discharging at least one connection of the passive infrared detector (PIR) is different at different times, and - wherein, since the equivalent resistance depends on the clock (φ1, φ2), the averaging of the equivalent resistance is related to a plurality of periods of this clock.Device for operating a passive infrared detector (PIR) according to any one of the preceding claims - wherein each of the outputs of said passive infrared detector (PIR) is connected to the control input of a respective associated input transistor (T 1, T 2).Device for operating a passive infrared detector (PIR) according to the preceding claim, - wherein in each case one contact of each of these input transistors (T 1, T 2) is connected to an associated current divider output (I a1, I a2) of a controllable current divider (MUX, R M1 to R Mn) and - wherein said current divider (MUX, R M1 to R Mn) divides the current of a reference current source (I ref) as a function of a control input (Val) to the current divider outputs (I a1, I divides a2).Device for operating a passive infrared detector (PIR) according to one of the two preceding claims, - wherein in each case one contact of the input transistors (T 1, T 2) is in each case connected to in each case one integrating filter and / or one capacitor (C 1, C 2) respectively.Device for operating a passive infrared detector (PIR) according to the preceding claim - wherein the device is configured to compare the output values of these integrating filters and / or capacitances (C 1, C 2) with each other by at least one comparator (CP).Device for operating a passive infrared detector (PIR) according to the preceding claim, - the device being configured so that the comparator output signal (CPO) of this comparator (CP) controls at least one digital integrating filter (Int).Device for operating a passive infrared detector (PIR) according to the preceding claim and claim 8, - wherein the control input (Val) of the current divider (MUX, R M1 to R Mn), which divides the current of the reference current source (I ref) depends directly or indirectly on the numerical value of the digital integrating filter (Int).Device for operating a passive infrared detector (PIR) according to one of the preceding claims and claim 7, - wherein it comprises a differential amplifier stage, and - wherein the control electrode of the first input transistor (T 1) and the control electrode of the second input transistor (T 2) form the differential input of the differential amplifier stage.Device according to the preceding claim, - wherein the differential amplifier stage has a reference current source (I ref) and - a resistor (R M1 to R Mn) and - wherein this resistor (R M1 to R Mn) has a controllable tap, which is connected to said reference current source (I ref) and - wherein one terminal of the resistor (R M1 to R Mn) is connected to the first transistor (T 1) and wherein the other terminal of the resistor (R M1 to R Mn) is connected to the second transistor (T 2) and - wherein the control of the tap is controllable by an external variable and - wherein each transistor (T 1, T 2) has its third terminal connected to a working resistor (R 1, R2, C 1, C 2, IW 1, IW 2) which can be a differential working resistor.Device according to the preceding claim, - wherein the controllable resistor comprises an analog 1:(n-1) multiplexer or an analog 1:n multiplexer, or an analog 1:(n+1) multiplexer (MUX) connected to the single output, which represents the tap of the controllable resistor is connected to said reference current source (Iref), and - wherein the controllable resistor comprises a resistor chain of n resistors (R M1 to R Mn) as resistor (R M1 to R Mn) and - wherein each of the (n-1) nodes between two of the n resistors (R M1 to R Mn) is connected to an input / output length of the analog multiplexer (MUX), and - wherein in the case of a 1:n multiplexer (MUX), the end or the start of the resistor chain of the resistors (R M1 to R Mn) is additionally connected to the end and the start of the resistor chain comprising the resistors (R M1 to R Mn) are additionally connected to the multiplexer (MUX), and - wherein in the case of a 1:(n+1) multiplexer (MUX), the start of the resistor chain comprising the resistors (R M1 to R Mn) is connected to at least the first transistor (T 1) and - the end of the resistor chain comprising the resistors (R M1 to R Mn) is connected to at least the second transistor (T 2).

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