METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a trench (216) in a semiconductor body (210), Doping of a part (218) of the semiconductor body (210) via side walls (220a, 220b) of the trench (216) by plasma doping; thereafter Forming an out-diffusion barrier layer (224) lining the trench (216); and Expanding a doping profile of plasma-generated doping by diffusion with a thermal budget.

Description

BACKGROUND

[0001] A key component in semiconductor applications is a solid-state switch. For example, switches in automotive or industrial applications turn loads on and off. Solid-state switches typically include, for example, field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs) or insulated-gate bipolar transistors (IGBTs). Exemplary semiconductor devices are known from German patent applications DE 11 2004 002 608 T5, US 2008 / 0 038 850 A1, US 2007 / 0 278 592 A1, and US 7 892 924 B1.

[0002] Key requirements for solid-state switches are a low inrush current (Ron) and a high breakdown voltage (Vbr). Minimizing the inrush current often comes at the expense of the breakdown voltage. Therefore, a balance between Ron and Vbr must be achieved.

[0003] Superjunction structures are widely used to improve the balance between on-resistance and breakdown voltage. In a conventional n-channel superjunction device, alternating n-doped and p-doped regions replace a comparatively low n-doped drift zone. In an on-state, current flows through the n-doped regions of the superjunction, reducing the on-resistance (Ron). In an off-state, the p-doped and n-doped regions become depleted or compensate for each other to deliver a high breakdown voltage (Vbr). Designing a compensation structure is a key element in improving the balance between Ron and Vbr.

[0004] Accordingly, a method for manufacturing a supertransition device and a supertransition device with an improved compensation structure design are required.

[0005] It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device which meets the above requirements. SUMMARY

[0006] The invention is defined in claim 1. Further developments are the subject of dependent claims.

[0007] After reading the following detailed description and examining the accompanying drawings, the expert will recognize additional features and advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are intended to provide a further understanding of the present invention and are included in and form part of the disclosure. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention. Other embodiments of the invention and many of the intended advantages are immediately appreciated, as they are better understood with reference to the following detailed description. The elements of the drawings are not necessarily to scale with respect to one another. Identical reference numerals indicate corresponding similar parts. Fig. Figure 1 is a schematic process diagram of an embodiment of a method for manufacturing a semiconductor device according to an embodiment. Fig. Figures 2A to 2F are cross-sectional views of a semiconductor body at different process phases during an embodiment of a method for manufacturing a supertransition device. Fig. Figures 3A to 3F illustrate schematic sectional views of a semiconductor body at different process phases during another embodiment of a method for manufacturing a supertransition device. Fig. 3G is a schematic representation of profiles of p-doping and n-doping along a line AA of Fig. 3F. Fig. Figures 4A to 4J illustrate schematic cross-sectional views of a semiconductor body at different phases during yet another embodiment of a method for manufacturing a supertransition device. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments in which the invention can be carried out for illustrative purposes. In this respect, directional terminology such as "above," "below," "front," "back," "leading," "trailing," "above," "over," "below," etc., is used with regard to the orientation of the figure(s) just described. Since components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments can be used and structural or logical modifications can be made without departing from the scope of the present invention.For example, features illustrated or described as part of one embodiment can be used in or together with other embodiments to arrive at yet another embodiment. It is intended that the present invention includes such modifications and changes. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing processes are designated with the same reference numerals in the various drawings, unless otherwise stated.

[0010] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This could, for example, be the surface of a wafer or disk.

[0011] The term “vertical”, as used in the present description, is intended to describe an orientation that is perpendicular to the first surface of the semiconductor substrate or semiconductor body.

[0012] The terms "coupled" and / or "electrically coupled," as used in this description, do not imply that the elements must be directly coupled to one another; intermediate elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-resistance electrical connection between the electrically connected elements.

[0013] In this description, n-doped can refer to a first conductivity type, while p-doped refers to a second conductivity type. It goes without saying that semiconductor devices with opposite doping relationships can be formed, so that the first conductivity type can be the p-doped type and the second conductivity type the n-doped type. Furthermore, some figures illustrate relative doping concentrations by specifying “ - " or " + “next to the doping type. For example, “n” means - “a doping concentration that is smaller than the doping concentration of an “n” doping region, while an “n +The “-doping range has a higher doping concentration than the “n” doping range. However, specifying the relative doping concentration does not mean that doping ranges with the same relative doping concentration have the same absolute doping concentration unless otherwise stated. For example, two different n + -areas have different absolute doping concentrations. The same applies, for example, to an n + - and a p + -Area.

[0014] Specific embodiments described in this application relate to, but are not limited to, power transistor devices controlled by a field effect and in particular to unipolar devices such as MOSFETs.

[0015] The term “field effect”, as used in the present application, is intended to describe the formation of an “inversion channel” mediated by the electric field and / or to control the conductivity and / or shape of the inversion channel in a semiconductor channel region.

[0016] In the context of this application, the term "MOS" (metal-oxide semiconductor) is to be understood as including the more general term "MIS" (metal-insulator semiconductor). For example, the term MOSFET (metal-oxide semiconductor field-effect transistor) is to be understood as including FETs having a gate insulator that is not an oxide; that is, the term MOSFET is used in the more general sense of IGFET (isolated-gate field-effect transistor) or MISFET.

[0017] Fig. Figure 1 illustrates a schematic process diagram of a method for manufacturing a semiconductor device. The method includes forming a trench in a semiconductor body (S100) and doping a portion of the semiconductor body via sidewalls of the trench by plasma doping (S110).

[0018] The semiconductor body can be a pre-processed single-crystal semiconductor substrate, for example, a single-crystal silicon substrate (Si substrate), a SiC substrate, a GaN substrate, a GaAs substrate, or a silicon-on-insulator substrate. The semiconductor body can comprise zero, one, or multiple doped and / or undoped layers on the single-crystal semiconductor substrate, for example, epitaxial semiconductor layers. For example, the thickness of the semiconductor layer(s) formed on the single-crystal semiconductor substrate, as well as the doping of one or more layers, can be appropriately selected with respect to the desired voltage-blocking capability of the semiconductor device to be formed within the semiconductor body. In particular, the doping level of the semiconductor body should be chosen such that the charge balance of the final compensation device is suitable for the desired blocking behavior.

[0019] The trench can be formed by a suitable process, such as dry and / or wet etching. For example, in a silicon body, the trench can be formed by an anisotropic plasma etching process, such as reactive ion etching (RIE), which includes a suitable etching gas, for example, at least one gas consisting of Cl₂, Br₂, CCl₄, CHCl₃, CHBr₃, BCl₃, or HBr. According to one embodiment, the trench sidewalls can be slightly tapered, for example, enclosing a conical angle between 88° and 90°. Slightly tapered trench sidewalls can be advantageous in avoiding trench voids when trenches are filled.

[0020] Plasma doping of the semiconductor body portion across the trench sidewalls allows for high-dose implantation at low energies and is known as PLAD (plasma doping) or PIII (plasma immersion ion implantation). These methods enable precise doping of the semiconductor body portion at the trench sidewalls. Conformal doping of the semiconductor body portion at the trench sidewalls can be achieved by applying a voltage to a substrate surrounded by a radiofrequency (RF) plasma containing a dopant gas. Collisions between ions and neutral atoms, as well as the biasing of the substrate, result in a broad annular distribution of the dopants, allowing for homogeneous doping across the trench sidewalls. A small vertical gradient in the doping dose within the semiconductor body portion can also be achieved through plasma doping.This allows for a vertical change in the charge compensation degree, which improves the stability of the fabrication and / or breakthrough or avalanche robustness. A vertical change in the doping dose can be less than 20%, less than 10%, or less than 5%.

[0021] When PLAD doping is used, the semiconductor substrate, for example, a semiconductor wafer, is exposed to a plasma containing dopant ions. These ions are accelerated to the substrate by an electric field and implanted into an exposed surface of the substrate. The implanted dose can be set or controlled via DC voltage pulses, such as negative voltage pulses. A Faraday system allows for dose adjustment or control. Two sets of coils, i.e., a horizontal coil and a vertical coil, allow for plasma generation and homogeneity. The ion density can be adjusted by varying the distance between the coils and the substrate. Interaction between the vertical and horizontal coils allows for adjustment or control of both homogeneity and ion density.

[0022] The penetration depth of the dopants into the semiconductor body and the implantation dose can be adjusted via a pulsed DC voltage that lies between the semiconductor substrate and a surrounding shield ring.

[0023] According to one embodiment, doping the part of the semiconductor body by plasma doping comprises introducing the dopants into the part of the semiconductor body via the side walls at a dose in the range of 5 × 10 11 cm -2 up to 5 × 10 12 cm -2 or in an area of ​​7 × 10 11 cm -2 up to 2 × 10 12 cm -2 This comparatively low dose requires variations or modifications to the typically used pulsed DC voltage. Typically, doses that are 10 15 cm -2These techniques are used to implant devices that exceed certain parameters. According to one embodiment, the pulse spacing of the DC voltage pulses is set to a range of 100 µs to 10 ms, and particularly between 500 µs and 5 ms. The DC voltage pulse rise time is set to a value less than, for example, 0.1 µs. According to another embodiment, the pulse width is between 0.5 µs and 20 µs, or between 1 µs and 10 µs.

[0024] According to one embodiment, the semiconductor body comprises a drift zone of a first conductivity type. Doping the portion of the semiconductor body by plasma doping comprises doping the portion of the semiconductor body with dopants of a second conductivity type that is complementary to the first conductivity type. According to one embodiment, the doped portion of the semiconductor body forms a charge compensation region, for example, a p-doped column between an n-doped drift zone of a superjunction semiconductor device. According to another embodiment, a transistor or diode device is formed as the semiconductor device and comprises the doped portion of the semiconductor body as a vertical edge termination structure. According to one embodiment, the semiconductor device is a power semiconductor device with a breakdown voltage or a voltage blocking capability of at least 100 V or at least 300 V.

[0025] According to one embodiment, in addition to plasma doping of the semiconductor portion at the sidewalls, a variation or change in the doping along the vertical direction in a silicon semiconductor body can be achieved by high-energy implantation of protons for n-type doping or of helium for p-type doping. This allows for an improvement in the breakdown or avalanche robustness of the device.

[0026] Further process steps for the fabrication of semiconductor zones, such as source, drain, body, highly doped contact zones and gate structures, trench fillings, dielectric layers, intermediate-level dielectrics, conductive layers, such as highly doped semiconductor layer(s) or metal layer(s), may follow to complete the semiconductor device.

[0027] The Fig. 2A to 2F illustrate schematic sectional views of an n --doped semiconductor body 210 during various phases of processing a semiconductor device. A mask 212 is formed on a first side 214 of the semiconductor body 210. Patterning of the mask 212, for example by lithography, leads to mask openings. A trench 216 is formed from the first side 214 into the semiconductor body 210, for example by an anisotropic etching process such as RIE.

[0028] For example, the width w of trench 216 can be between 0.1 µm and 15 µm or between 1 µm and 10 µm. The depth d of trench 16 can be between 10 µm and 120 µm or between 20 µm and 60 µm. For example, the depth d can be selected appropriately with respect to the desired voltage-blocking capability of the semiconductor device to be manufactured.

[0029] Referring to the schematic sectional view of the semiconductor body 210, which is shown in Fig. As illustrated in Figure 2B, plasma doping is performed by PLAD or PIII using a process gas designed for p-doping, for example BF3 and / or B2H6. The plasma doping results in p-doping of a portion 218 of the semiconductor body 210 on sidewalls 220a, 220b, and on a bottom side 222 of the trench 216 ( Fig. 2C). The penetration depth of the dopants, or in other words, the thickness of part 218 after PLAD, is comparatively low, for example, in the range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm, since comparatively low voltages in the range of 100 V to 12 kV are used in the PLAD to accelerate ions to the semiconductor substrate. Regarding further parameters of plasma doping, reference is made to Fig. 1 and the associated part of the description.

[0030] Regarding the schematic cross-sectional view of the semiconductor body 210, which is in Fig. As illustrated in 2D, the mask 212 is removed from the first side 214, for example, by an etching process. Furthermore, an optional diffusion barrier 224 is formed on the side walls 220a, 220b, and on the bottom side 222 of the trench 216. The optional diffusion barrier 224 lines the p-doped portion 218 of the semiconductor body 210. The diffusion barrier 224 counteracts or prevents the diffusion of the p-type dopants introduced into the portion 218 by plasma doping. This allows the implanted dose to be retained within the semiconductor body 210. In other words, the diffusion barrier 224 allows the accuracy of the charge compensation in the superjunction device to be improved.As an example, the diffusion barrier 224 can be formed as a silicon layer by CVD at low temperatures, for example, at temperatures in the range of 300°C to 700°C or in the range of 400°C to 600°C. According to another embodiment, the diffusion barrier 224 can be formed by deposition of an amorphous silicon layer, followed by crystallization of the amorphous silicon layer at temperatures typically between 400°C and 600°C. Alternatively or additionally, the diffusion barrier 224 can consist of or comprise an insulating layer, for example, an oxide layer, formed by CVD or plasma-enhanced CVD (PECVD). In the [reference to be added] Fig. In the embodiment illustrated in Figures 2A to 2F, part 218 covers the bottom side 222 of the trench 216. According to another embodiment, part 218 can be removed from the bottom side 222 of the trench 216, for example, by an etching process. According to yet another embodiment, part 218 covering the bottom side 222 of the trench 216 can be counter-doped, resulting in n-type doping at the bottom side 222. Diffusion of p-type dopants introduced by plasma doping is carried out by thermal heating to expand a profile according to PLAD or PIII, which is comparatively small due to the low penetration depth of the dopants achieved by these methods.

[0031] The diffusion barrier layer 224 and / or an optional insulating layer as part of the diffusion barrier layer 224 can be removed after diffusion, for example by an etching process. However, this is typically not necessary in the case of silicon deposition.

[0032] Regarding the schematic cross-sectional view of the semiconductor body 210, which is in Fig. As illustrated in Figure 2E, the trench 216 is at least partially filled with an insulating material, for example an oxide or nitride, and / or a semiconductor material, for example an epitaxial silicon layer formed by lateral epitaxial processes or by CVD. Thus, the filling material 226 fills the trench 216. In the case of filling the trench 216 with semiconductor material, the semiconductor material may be undoped or typically have a doping concentration below that introduced by the plasma doping of the p-doped portion 218 described above, or it may have a doping concentration similar to that of the semiconductor body 210, so that it can contribute to a low-resistance current flow.

[0033] According to one embodiment, thermal heating is carried out to further extend a lateral doping profile of the p-doped part 218.

[0034] Referring to the schematic sectional view of the in Fig. Further processes for fabricating the superjunction semiconductor device are shown in the semiconductor body 210 shown in Figure 2F. A p-doped semiconductor region 228 is formed on the first side 214, for example, by ion implantation of p-type dopants, such as boron (B). Furthermore, an n +A p-doped source zone 230 is formed in the p-doped body region 228 on the first side 214, for example, by ion implantation of n-type dopants, such as phosphorus (P). Furthermore, a planar gate structure 232 is formed on the first side 214, comprising a gate dielectric 234 and a gate electrode 236. Additional known elements, such as a drain on a second side opposite the first side 214, dielectric layers, such as interlayer dielectrics, and conductive layers, such as metallization layers, which are interconnected or connected to the semiconductor body by contacts, can follow to complete the superjunction device. In an exemplary device described in Fig. As illustrated in Figure 2F, part 218 forms a charge compensation region of the superjunction device. According to other embodiments, trench 216 and part 218 can form a vertical edge termination structure in a border termination region surrounding an active cell region of a transistor device, for example, an IGBT or a MOSFET.

[0035] The Fig. 3A to 3F illustrate schematic sectional views of an n - -doped semiconductor body 310 to different phases of processing a superjunction semiconductor device. A mask 312 is formed on a first face 314 of the semiconductor body 310. Patterning of the mask 312, for example by lithography, leads to mask openings. Trenches 316 are formed from the first face 314 in the semiconductor body 310 by, for example, using an anisotropic etching process such as RIE.

[0036] The dimensions of the Trenches 316, for example a width w and a depth d, can be selected, as shown in the Fig. The embodiment illustrated in Figures 2A to 2F is described. A pitch p between the centers of adjacent trenches 316 can be between 0.2 µm and 50 µm, or between 0.5 µm and 30 µm, or even between 1 µm and 5 µm. Plasma doping using PLAD or PIII, employing a process gas designed for n-doping, for example, PF3 and / or PH3, is performed. The plasma doping results in n-doping of a portion 318 of the semiconductor body 310 at sidewalls 320a, 320b, and at a bottom face 322 of the trenches 316 ( Fig. 3B). The penetration depth of the dopants, or in other words, the thickness of part 318 after PLAD, is comparatively low, for example, in the range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm, since comparatively low voltages in the range of 100 V to 12 kV are used in the PLAD to accelerate ions to the semiconductor substrate. Regarding other parameters of plasma doping, reference is made to Fig. 1 and the corresponding part of the description. According to one embodiment, a dose of dopants introduced by plasma doping over a unit region of the sidewalls 320a, 320b is at least 5 times greater, or even ten or twenty times greater, than a dose of dopants in a part of the semiconductor body 310 between the trenches 316, which corresponds to (pw) / 2 × N, where N is a net doping of the n --doped semiconductor body 310 is located between the trenches 316. Furthermore, the mask 312 is removed from the first side 316, for example by an etching process.

[0037] Referring to the schematic sectional view of the in Fig. In the semiconductor body 310 shown in Figure 3C, a first semiconductor layer 340, for example a conformal, undoped or lightly doped silicon layer, is formed on part 318 in the trenches 316 by lateral epitaxy or CVD. As an example, a lateral epitaxial process or low-pressure CVD (LPCVD) can be used to achieve conformal deposition of the first semiconductor layer 340, which lines the sidewalls 320a, 320b and the bottom side 322 of the trenches 316. As an example, the thickness of the first semiconductor layer 340 can be between 5% and 30% or between 10% and 20% of the width w.

[0038] Referring to the schematic sectional view of the in Fig. In the 3D-shown semiconductor body 310, plasma doping is performed using PLAD or PIII, which employs a process gas designed for p-doping, for example, BF3 and / or B2H6. The plasma doping results in p-doping of the first semiconductor layer 340. The penetration depth of the dopants, or in other words, the thickness of a doped portion 342 of the first semiconductor layer 340 after PLAD, is comparatively low, for example, in a range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm. Fig. 3E). Regarding further parameters of plasma doping, reference is made to the Fig. 1 and the corresponding part of the description. According to one embodiment, a dose of dopants introduced by plasma doping over a unit area of ​​the side walls 320a, 320b differs by less than 10%, or less than 5%, or even less than 3% from the dose of dopants previously introduced into part 318 by plasma doping.

[0039] Furthermore, with reference to the schematic sectional view of the in Fig. In the semiconductor body 310 shown in Figure 3E, the trenches 316 are filled with an insulating material, for example an oxide or nitride, and / or a semiconductor material, for example an epitaxial silicon layer formed by lateral epitaxy or CVD. Thus, a filler material 326 fills the trenches 316. In the case of filling the trenches 316 with semiconductor material, the semiconductor material can be undoped or it can have a doping concentration lower than that introduced by the plasma doping of the n-doped part 318 or the p-doped first semiconductor layer 340 described above.

[0040] Between the plasma doping of the first semiconductor layer 340 and the filling of the trenches 361, an out-diffusion barrier layer, as in Fig. The 2D illustration shows that the first semiconductor layer 340 is formed, followed by thermal heating to expand the lateral profiles of the p- and n-doping in parts 318 and 342. Optionally, a mask to prevent diffusion can also be applied directly after the first plasma doping process, followed by a high-temperature step and optional removal of this mask.

[0041] With reference to the in Fig. Figure 3F illustrates a schematic cross-sectional view of the semiconductor body 310. The semiconductor body 310 is planarized on the first side 340, for example, by chemical-mechanical polishing (CMP) and / or by plasma etching. This removes the first semiconductor layer 340 from the first side 314.

[0042] Further processes for manufacturing a superjunction semiconductor device will follow. For further details in this regard, reference is made to the Fig. 2F and the associated part of the description.

[0043] Fig. 3G is a schematic representation of profiles of p-doping and n-doping along a line AA' of Fig. 3F.

[0044] The lateral width of the profiles depends on a thermal budget, which leads to profile expansion through diffusion. A doping profile N of a species or type of n-doping material decreases from a maximum Nmax in part 318 to a minimum doping plateau Nmin in a drift zone that forms part of a semiconductor body 310 between trenches 316. The doping value at the maximum Nmax is at least ten or twenty times greater than the doping at the minimum plateau Nmin. Depending on the degree of lateral expansion or extension of the profile N, the minimum plateau may be a minimum. A doping profile P of a species of p-doping material has a maximum Pmax in part 342.

[0045] The Fig. Figures 4A to 4J illustrate schematic sectional views of an n --doped semiconductor body 410 during various phases of processing a superjunction semiconductor device. A mask 412 is formed on a first face 414 of the semiconductor body 410. Patterning of the mask 412, for example by lithography, results in mask openings. Trenches 416 are formed from the first face 414 into the semiconductor body 410 by, for example, an anisotropic etching process such as RIE.

[0046] The dimensions of the Trenches 416, for example a width w and a depth d, can be selected, as shown in the Fig. 2A to 2F illustrate the exemplary embodiment described.

[0047] Plasma doping using PLAD or PIII, employing a process gas designed for n-doping, such as PF3 and / or PH3, is performed. The plasma doping results in n-doping of a portion 418 of the semiconductor body 410 on sidewalls 420a, 420b, and on a bottom side 422 of the trenches 416 ( Fig. 4B). The penetration depth of the dopants, or in other words, the thickness of part 418 after PLAD, is comparatively low, for example, in a range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm. Regarding other parameters of plasma doping, reference is made to the Fig. 1 and the associated part of the description. According to one embodiment, a dose of dopants introduced by plasma doping over a unit region of the sidewalls 420a, 420b is at least five times greater than a dose of dopants in a part of the semiconductor body 410 between the trenches 416, which corresponds to (pw) / 2 × N, where N is a net doping of the n - -doped semiconductor body 410 is located between the trenches 416. Furthermore, the mask 412 is removed from the first side 414, for example, by an etching process.

[0048] With reference to the in Fig. Figure 4C illustrates a schematic cross-sectional view of the semiconductor body 410. A first semiconductor layer 440, for example a conformal, undoped or lightly doped silicon layer, is formed on part 418 in the trenches 416 by lateral epitaxy or CVD. For example, lateral epitaxy or low-pressure CVD (LPCVD) can be used to achieve conformal deposition or fabrication of the first semiconductor layer 440, which lines the sidewalls 420a, 420b and the bottom side 422 of the trenches 416. For example, the thickness of the first semiconductor layer 440 can be between 2% and 30% or between 5% and 20% of the width w.

[0049] With reference to the in Fig. In the schematic sectional view of the semiconductor body 410 shown in 4D, plasma doping is performed using PLAD or PIII, employing a process gas designed for p-doping, for example, BF3 and / or B2H6. The plasma doping results in p-doping of the first semiconductor layer 440. The penetration depth of the dopants, or in other words, the thickness of the doped portion 442 of the first semiconductor layer 440 after PLAD doping, is comparatively small, for example, in the range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm. For further parameters of the plasma doping, reference is made to... Fig. 1 and the associated part of the description. Furthermore, masking layers that prevent diffusion can be formed as described above. According to one embodiment, a dose of p-dopers introduced into a unit area of ​​part 442 by plasma doping is between 170% and 230%, or between 190% and 210%, or between 195% and 205% of the dose of n-dopers previously introduced into part 418 by plasma doping.

[0050] With reference to the in Fig. Figure 4E illustrates a schematic cross-sectional view of the semiconductor body 410. The first semiconductor layer 440 is removed from the first side 414 and the bottom side 422 of the trenches 416, for example, by an anisotropic etching process. A second semiconductor layer 450, for example, a conformal undoped or lightly doped silicon layer, is formed on the doped portion 442 in the trenches 416, on the bottom side 422, and on the first side 414 by lateral epitaxy or by CVD. As an example, lateral epitaxy or low-pressure CVD (LPCVD) can be used to achieve conformal deposition or deposition of the second semiconductor layer 450, which lines the side walls 420a, 420b, and the bottom side 422 of the trenches 416.

[0051] With reference to the in Fig. Figure 4F illustrates a schematic cross-sectional view of the semiconductor body 410. Plasma doping is performed by PLD or PIII using a process gas designed for n-doping, for example, PF3 and / or PH3. The plasma doping results in n-doping of the second semiconductor layer 450. The penetration depth of the dopants, or in other words, the thickness of a doped portion 452 of the second semiconductor layer 450 after PLAD, is comparatively low, for example, in the range between 0.2 nm and 20 nm, or between 0.5 nm and 10 nm, or even between 1 nm and 3 nm. Further parameters of the plasma doping are described in the following sections. Fig. 1 and the associated part of the description. According to one embodiment, a dose of dopants introduced into part 452 by plasma doping over a unit area of ​​the side walls 420a, 420b corresponds to the dose introduced into part 418 by plasma doping.

[0052] With reference to the in Fig. 4G illustrated schematic cross-sectional view of the semiconductor body 410 shows the second semiconductor layer 450 being removed from the first side 414 and from the bottom side 422 of the trenches 416, for example, by an anisotropic etching process.

[0053] With reference to the in Fig. Figure 4H illustrates a schematic cross-sectional view of the semiconductor body 410. The trenches 416 are filled with a semiconductor material, for example, an epitaxial silicon layer formed by lateral epitaxy or CVD. Thus, the filler material 466 fills the trenches 416. The semiconductor material can be undoped or have a doping concentration below that introduced into the n-doped part 452 by the plasma doping described above.

[0054] With reference to the in Fig. 4I, a schematic cross-sectional view of the semiconductor body 410, illustrates that the semiconductor body 410 is planarized on the first side 440, for example, by chemical-mechanical polishing (CMP) and / or by plasma etching. This removes the filler material 466 from the first side 414.

[0055] With reference to the in Fig. Figure 4J, a schematic cross-sectional view of the semiconductor body 410, illustrates further processes for fabricating a superjunction semiconductor device. A p-doped semiconductor region 428 is formed on the first side 414, for example, by ion implantation of p-type dopants, such as boron (B). Furthermore, an n +A p-doped source zone 430 is formed in the p-doped body region 428 on the first side 414, for example, by ion implantation of n-type dopants, such as phosphorus (P). Furthermore, a planar gate structure 432 with a gate dielectric 434 and a gate electrode 436 is formed on the first side 414. A drain contact 438 is formed on a second side 472 opposite the first side 414. Additional known elements, such as dielectric layers, e.g., interlayer dielectrics, and conductive layers, such as metallization layers, which can be interconnected or connected to the semiconductor body by contacts, can follow and complete the superjunction device.

[0056] The n-dose introduced in Part 418 defines, as in the Fig. 4A, Fig. Figure 4B illustrates n-doping in drift zone parts 481a, 481b, and 481c. The p-dose introduced in part 442 is defined as shown in the Fig. Figure 4D shows p-doping in charge compensation regions 482a, 482b, 482c, 482d. The n-dose introduced in Part 452 defines how in Fig. 4F shows an n-doping in drift zone parts 483a, 483b.

[0057] The embodiments described above allow the manufacture of supertransition devices that have precise charge compensation and a compact design, with homogeneous trench sidewall doping.

[0058] Terms such as "first", "second", and the like are used to describe different elements, areas, sections, and are not limiting. Similar terms are used to describe similar elements in this patent application.

[0059] Terms like "encompass," "contain," "exhibit," and similar terms are open-ended, meaning that in addition to the "encompassed" elements, other elements may be present. Elements marked with definite and indefinite articles can be singular or plural unless explicitly stated otherwise.

[0060] It should be understood that features of the various embodiments described here can be combined with one another, unless specifically stated otherwise.

[0061] Although specific embodiments are illustrated and described here, it is obvious to those skilled in the art that a multitude of alternative and / or equivalent embodiments can be used for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover all adaptations or modifications of the specific embodiments discussed herein. Therefore, this invention is to be limited only by the claims and their equivalents.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a trench (216) in a semiconductor body (210), Doping a part (218) of the semiconductor body (210) via side walls (220a, 220b) of the trench (216) by plasma doping; thereafter Forming an out-diffusion barrier layer (224) lining the trench (216); and Extending a dopant profile of plasma doping by diffusion with a thermal budget. [2] The method of claim 1, wherein the semiconductor device has a breakdown voltage of at least 100 V. [3] Method according to claim 1 or 2, wherein the doping of the part (218) of the semiconductor body (210) by plasma doping comprises introducing dopants into the part (218) of the semiconductor body (210) via the side walls (220a, 220b) of the trench (216) at a dose in a range of 5 x 10 11 cm -2up to 5 × 10 12 cm -2 includes. [4] Method according to one of claims 1 to 3, wherein doping a part (218) of the semiconductor body (210) by plasma doping comprises setting a DC pulse spacing in a range of 100 µs to 10 ms. [5] Method according to one of claims 1 to 4, wherein doping a part (218) of the semiconductor body (210) by plasma doping comprises setting a DC pulse width in a range of 0.5 µs to 20 µs. [6] Method according to one of claims 1 to 5, wherein doping the part (218) of the semiconductor body (210) by plasma doping comprises setting a DC voltage pulse rise time to a value less than 0.1 µs. [7] The method of any one of claims 1 to 6, further comprising filling the trench (216) with an insulating material (226). [8] The method of any one of claims 1 to 6, further comprising filling the trench (216) with a semiconductor material. [9] The method of any one of claims 1 to 8, further comprising forming a first semiconductor layer (340) on the doped portion (318) of the semiconductor body (310). [10] The method of claim 9, wherein forming the first semiconductor layer (340) on the doped portion (318) of the semiconductor body (310) comprises forming a silicon layer by lateral epitaxy or low temperature chemical vapor deposition. [11] The method of claim 9 or 10, wherein forming the first semiconductor layer (340) on the doped portion (318) of the semiconductor body (310) comprises: Forming an amorphous silicon layer on the doped part (318) of the semiconductor body (310) and Crystallizing the amorphous silicon layer through heat treatment. [12] The method of any one of claims 1 to 11, wherein the out-diffusion barrier layer (224) is an insulating out-diffusion barrier layer (224). [13] A method according to any one of claims 1 to 12, wherein a superjunction device is formed as the semiconductor device having the doped portion (218, 318) of the semiconductor body (210, 310) as a charge compensation layer. [14] The method of any one of claims 1 to 12, wherein a transistor device is formed as the semiconductor device having the doped portion (218, 318, 418) of the semiconductor body (210, 310, 410) as an edge termination structure. [15] Method according to one of claims 1 to 14, wherein the semiconductor body (210, 310, 410) comprises a drift zone of a first conductivity type, wherein the doping of the part (218, 318, 418) of the semiconductor body (210, 310, 410) by plasma doping comprises doping the part (218, 318, 418) of the semiconductor body (210, 310, 410) with dopants of a second conductivity type that is complementary to the first conductivity type. [16] The method according to any one of claims 1 to 14, wherein the semiconductor body (410) comprises a drift zone of a first conductivity type and wherein the doping of the part (418) of the semiconductor body (410) by plasma doping comprises doping the part (418) of the semiconductor body (410) with dopants of the first conductivity type, the method further comprising: Forming a first semiconductor layer (440) over the part (418) of the semiconductor body (410) in the trench (416) and doping the first semiconductor layer (440) by plasma doping with dopants of a second conductivity type that is complementary to the first conductivity type. [17] The method of claim 16, further comprising filling the trench (416) with an insulating material (466). [18] The method of claim 16, further comprising filling the trench (416) with a semiconductor material. [19] A method according to any one of claims 16 to 18, further comprising: Removing the first semiconductor layer (440) from a bottom side of the trench (416), Forming a second semiconductor layer (450) over the first semiconductor layer (440) in the trench (416) and Doping the second semiconductor layer (450) by plasma doping with dopants of the first conductivity type.

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