Electrical devices, voltage-suppressor diode and method for manufacturing an electrical device

Abstract

Electrical device (10, 20, 30) comprising the following: a first doped layer (12) with a first conductivity type; a second doped layer (14) with a second conductivity type that is opposite to the first conductivity type; and a self-conducting layer (16) arranged between the first layer (12) and the second layer (14), wherein the self-conducting layer (16) has a reduced thickness in at least one section which is filled with a doped material of the second conductivity type, wherein the at least one section with the reduced thickness is formed by one or more indenters (22) having the second conductivity type, wherein the one or more indenters (22) are electrically connected to the second layer (14) and extend into the self-conducting layer (16), wherein a region (18) of the one or more indenters (22) is less than 30% of an active region in which the first layer (12) and the second layer (14) are opposite each other; where the depth of the indenter (22) is at least 10% smaller compared to the thickness of the self-conducting layer (16).

Description

TECHNICAL FIELD

[0001] The embodiments of the invention relate to electrical devices having a reduced turn-on time, a transient voltage suppression diode, and a method for manufacturing an electrical device. The preferred embodiments relate to a diode and a transistor having a reduced turn-on time. STATE OF THE ART

[0002] US 5,111,265 A relates to a collector-top transistor, and in particular to one with a tunnel-emitter structure. WO 99 / 53553 A2 discloses a semiconductor component with a rectifying junction and a corresponding manufacturing method. US 2006 / 0180857 A1 relates to a semiconductor component and a power switching element, and a corresponding manufacturing method. BACKGROUND

[0003] A transistor is an electrical device that has an adjustable transfer characteristic so that a signal can be amplified or switched. In a broader sense, a transistor can also be considered a diode, for example, if its base is left floating. A diode has an asymmetrical transfer characteristic. Therefore, a diode can be used to conduct current in a forward direction and to block current in a reverse direction. A commonly used diode is a semiconductor diode, which comprises two different semiconductor materials with opposite conduction types, such that a pn junction is formed between the two materials. By varying the semiconductor materials, the transfer characteristic can be adjusted. Semiconductor diodes often have a nonlinear current-voltage characteristic, so they can be used to regulate voltages or protect circuits.

[0004] A junction suppressor diode, for example, is used to protect a circuit from high-voltage surges. Such a junction suppressor diode is also called an avalanche diode, which is designed to undergo avalanche breakdown (in the reverse direction) at a specific reverse bias voltage. The time difference between the time of the high-voltage surge and the avalanche breakdown is called the turn-on time. Junction suppressor diodes, or electrical devices in general, are often optimized for their turn-on time. SUMMARY OF THE INVENTION

[0005] One embodiment provides an electrical device comprising a first layer, a second layer, and an intrinsic layer. The first layer has a first conductivity type, wherein the second layer has a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and second layers and has a reduced thickness in at least one section. An area of ​​the at least one section is less than 50% of an active area in which the first and second layers face each other. Further features are defined by independent claim 1.

[0006] Another embodiment provides an electrical device having a vertical layer arrangement. The layer arrangement comprises a substrate having a lower layer with a first conductivity type and an upper layer with a second conductivity type opposite to a first conductivity type, and an intrinsic layer arranged between the lower layer and the upper layer. Furthermore, the layer arrangement comprises one or more indenters extending from the upper layer into the intrinsic layer such that the intrinsic layer has a reduced thickness in at least one section, wherein an area of ​​the one or more indenters is less than 30% of an active area in which the first and second layers face each other.The indenters comprise polysilicon and have a depth that is at least 10% smaller than a thickness of the intrinsic layer, wherein the indenters have the second conductivity type.

[0007] Another embodiment provides a junction voltage suppressor diode comprising a first layer having a first conductivity type disposed on a substrate having a second conductivity type opposite to the first conductivity type, a second layer having the second conductivity type, and an intrinsic layer disposed between the first and second layers. The intrinsic layer has a reduced thickness in at least one portion, wherein a region of the at least one portion is less than 30% of an active area where the first and second layers oppose each other. Further features are defined by independent claim 18.

[0008] Another embodiment provides an electrical device comprising a first layer having a first conductivity type, a second layer having a second conductivity type opposite to the first conductivity type, and an intrinsic layer disposed between the first and second layers. Furthermore, the electrical device comprises means for partially reducing a thickness of the intrinsic layer to reduce a turn-on time of the electrical device.

[0009] A further embodiment provides a method for manufacturing an electrical device, the method comprising the steps of providing a first layer having a first conductivity type and providing an intrinsic layer on the first layer. Furthermore, the method comprises the steps of providing one or more trenches in the intrinsic layer and filling the one or more trenches with a material having a second conductivity type opposite to the first conductivity type. The final step of the method is providing a second layer having a second conductivity type on the intrinsic layer. Further features are defined by independent claim 19. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present invention will be described below with reference to the figures, among which: Fig. 1 shows, by way of example, a cross-sectional view of an electrical device comprising an intrinsic layer with a partially reduced thickness, according to one embodiment; Fig. 2a shows, by way of example, a cross-sectional view of an electrical device including an indenter to partially reduce a thickness of an intrinsic layer, according to one embodiment; Fig. 2b shows a top view of an electrical device comprising a plurality of indenters, according to an embodiment, by way of example; Fig. 3a to 3b show cross-sectional views of electrical devices including indenters according to further embodiments by way of example; Fig. 4 exemplifies a method of manufacturing an electrical device comprising an intrinsic layer with a partially reduced thickness, according to one embodiment; and Fig. 5a to 5b show two exemplary graphs resulting from a device simulation of a TVS diode and a PIN diode according to the embodiments to illustrate the improvements in turn-on time. DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

[0011] Various embodiments of the teachings disclosed herein are then described with reference to Fig. 1 to Fig. 5. In the drawings, identical reference numerals are provided for objects having identical or similar functions, so that the objects referred to by identical reference numerals within the various embodiments are interchangeable and their descriptions are mutually applicable.

[0012] Fig. 1 shows an electrical device 10 comprising a first layer 12 and a second layer 14, wherein an intrinsic layer 16 is arranged between the first and second layers 12 and 14. The first layer 12 has a first conductivity type, e.g., an n+-doped layer, while the second layer 14 has a second conductivity type opposite to the first conductivity type, e.g., a p+-doped layer. The two layers 12 and 14 are arranged such that they face each other and form an active region with a pn junction therebetween. The intrinsic layer 16, which may have a low doping concentration, e.g., n-- (i.e., approximately 1 10 13 cm -3). In general, an intrinsic layer 16 has such a low doping that the layer is depleted of all free charge carriers, even when no bias voltage is applied. The intrinsic layer 16, which may be an epitaxial layer, has in at least one section a thickness w n1 (e.g. 5 µm to 20 µm) of the intrinsic layer 16 a reduced thickness w n2 (e.g., 2 µm to 10 µm). It should be noted that this area 18 of the at least one portion is less than 50%, or less than 30%, or even less than 10% of the active area where layers 12 and 14 overlap.

[0013] Due to the intrinsic layer 16 (the depleted zone) in between, a so-called PIN diode 10 is formed. Such a PIN diode 10 can be used in forward mode operation as a bypass diode for ESD (electrostatic discharge) protection, particularly for circuits with only one polarity. The PIN diode 10 preferably has, depending on the thickness w n1 the intrinsic layer 16 has a small capacitance. A reduced capacitance can be achieved by increasing the thickness w n1 (the base width w n1 ) can be achieved. Due to the increase in the total thickness w n1 However, the time required to switch from the blocking state to the conducting state is also increased. This time is called the turn-on time t and is given by the formula t=wn12 / 2μ defined, where µ is the mobility of the minority charge carriers in the base or intrinsic layer 16. This increased turn-on time t in combination with the small capacitance can lead to an overshoot voltage that builds up during the turn-on time t. The background to this is that the electrical charges of an applied current surge, which cannot be discharged while the diode 10 is in the blocking state, are charged into the diode 10 and build up the overshoot voltage due to the small capacitance. Therefore, the goal is to reduce the turn-on time t to avoid the overshoot voltage while maintaining the small capacitance of the device 10. Therefore, the embodiments are based on the principle that the thickness w n2of the intrinsic layer 16 is only partially reduced, namely in the region 18. The reason for this is that the capacity depends mainly on the region, with the turn-on time t mainly depending on the base width w n2 Therefore, the base width w n2 only in the limited area 18. In other words, the area 18 which has the reduced thickness w n2 forms another diode connected in parallel with the PIN diode 10, which further diode has a reduced turn-on time t. Due to the reduced area 18, e.g., 5% of the active area, the turn-on time t can be significantly reduced, while the capacitance is only slightly changed.

[0014] In this embodiment, the region 18 of the section with the reduced thickness w n2be realized by a trench that extends, for example, 4 µm or 6 µm into the intrinsic layer 16 and is filled with the material of the second layer 14. The trench and consequently a portion of the second layer 14 typically extends over more than 30% or 50% of the thickness w n1 the intrinsic layer 16 into the intrinsic layer 16.

[0015] Fig. Figure 2a shows an electrical device 20 which essentially corresponds to the electrical device 10, wherein the region 18 having the reduced thickness w n2 is formed by an indenter 22. The indenter 22 extends from the second layer 14 into the intrinsically conductive layer 16 to a depth of 50% or 80% of the thickness w n1The indenter 22 comprises a material having the same conductivity type as the second layer 14, e.g., a p- or p+-doped polysilicon, and is connected to the second layer 14. Here, the indenter 22 is provided after the second layer 14 (the upper layer) has been provided, so that it extends through the thin upper layer 14 (whose thickness is preferably smaller than the thickness of the intrinsic layer 16, e.g., less than 1 µm) into the intrinsic layer 16.

[0016] As explained above, the indenter 22 has the purpose of determining the thickness w n2 of the intrinsic layer 16 in order to accelerate the turn-on time t.

[0017] According to another embodiment, the electrical device 20 may include an optional metallization layer 24 disposed on the upper layer 14 to establish electrical contact with the layer 14 (the anode contact). Electrical contact with the lower layer 12 may be established via the substrate (the cathode contact) comprising the lower layer 12. Therefore, the lower layer 12 may be disposed on the substrate or may be formed by the substrate, which may be doped, for example. It should be noted that according to another embodiment in which opposite conductivity types are provided (the substrate is p-doped and the upper layer 14 is n-doped), the substrate forms the anode contact and the upper layer 14 forms the cathode contact.

[0018] Fig. Figure 2b shows a plan view of an electrical device 21 which corresponds to the device 20 according to Fig. 2a, but further comprises a plurality of indenters 22. The indenters 22 are arranged in the same active region and embedded in the upper layer 14 and in the intrinsic layer (not shown).

[0019] Consequently, the plurality of indenters 22 form a plurality of diodes that are connected in parallel with the actual electrical device 21 or with the diode 21. According to further embodiments, the square-shaped indenters 22, which have a size of 2 × 2 µm 2 may have, be evenly distributed laterally across the active area, so that the total area of ​​the plurality of indenters 22 is less than 50% or 10% of the active area. Therefore, a distance between two adjacent indenters 22 is typically greater than three times or five times the diameter or side length of the respective indenter 22.

[0020] The Fig. 3a and Fig. 3b show another electrical device 30. The electrical device 30 comprises the lower layer 12, e.g., a p-doped layer, arranged on a substrate 32, e.g., an n+-doped substrate. Furthermore, the electrical device 30 comprises the upper layer 14, e.g., an n+-doped layer, and the intrinsic layer 16 between the lower and upper layers 12 and 14. As in the embodiment according to Fig. 2a, the indenter 22 extends from the upper layer 14 into the intrinsic layer 16 to partially reduce the thickness of the intrinsic layer 16. Optionally, the electrical device 30 may include the metallization layer 24 to establish an electrical connection with the upper layer 14.

[0021] In this embodiment, the electrical device 30 can be used as a transistor, with the substrate 32 forming the collector, the upper layer 14 forming the emitter, and the lower layer 12 together with the intrinsic layer 16 forming the base. Consequently, the base width w b1 defined by the distance between the collector 32 (the pn junction) and the emitter 14. In the same way as in the embodiment according to Fig. 2, the switch-on time t of the electrical device 30 is reduced by the base width w b2 compared to the base width w b1 is partially reduced (where the reduced base width w b2the distance between the collector 32 and the indenter 22). Consequently, a capacitance surge can be avoided. In other words, the indenter 22 forms a parallel transistor (connected in parallel with the transistor 30) having a reduced turn-on time t that is quadratically related to the reduced base width w b2 According to a further embodiment, the electrical circuit 30 may comprise a plurality of indenters 22, as described with respect to Fig. 2b is shown.

[0022] If the base is left floating, the device 30 shown forms a diode, namely a so-called junction voltage suppressor (TVS) diode, which serves to protect electronic circuits against damaging high voltages. The junction voltage suppressor diode 10, also referred to as a Zener or avalanche diode, is typically connected to the circuit so that it is reverse-biased, e.g., via the n-type side (see layer 12). Here, the junction voltage suppressor diode 10 is non-conductive if the voltage is below the avalanche breakdown voltage, e.g., 30 V or 70 V. If the voltage exceeds this avalanche breakdown voltage, e.g., in the case of a high-voltage surge, the diode switches from the reverse-biased state to the avalanche state, where it begins to conduct the overshoot current, e.g., to ground. The avalanche breakthrough occurs at the transition between the substrate 32 and the lower layer 12.As explained above, the turn-on time t (switching from the lock state to the avalanche state) is reduced due to the provided indenters 22.

[0023] Fig. Figure 4 illustrates the method of manufacturing an electrical device including an indenter 22, wherein only the steps of reducing the thickness w b1 the intrinsic layer 16 and for providing the indenter 22.

[0024] Therefore, the steps shown are performed after providing the lower (first) layer (not shown) and the intrinsic layer 16 on the first layer. It should be noted that the intrinsic layer 16 is provided such that it has a constant thickness, e.g., using epitaxy. To achieve the thickness w b1To partially reduce the thickness of the intrinsic layer 16, the layer is etched in the region 18, e.g., by trench or deep trench etching (see step 1). The trench may, for example, have a depth of 4 µm or up to 16 µm, or have a depth that is smaller than the thickness w b1 the intrinsic layer 16 is smaller (at least e.g. 2%, 5%, 10% or 30%).

[0025] The next step is to fill the trench with a material, e.g., p-doped polysilicon, of the same doping type as the upper layer. This step can be performed by depositing the polysilicon (see step 2). Due to the deposition of the polysilicon, the surface of the intrinsic layer 16 is also covered with polysilicon. This polysilicon can directly form the upper (second) layer 14. According to another embodiment, the polysilicon on the surface can be removed (see step 3), e.g., by reactive ion etching (RIE), so that a further second layer, e.g., with a different doping concentration, can be provided. Consequently, the unremoved material in the trench (see region 18) forms the indenter 22, which is embedded in the intrinsic layer 16.After these three steps 1, 2 and 3, the second layer 14 can be provided so that it has the conductivity type of the indenter 22 (if applicable with a different doping concentration) and so that it is electrically connected to the indenter 22.

[0026] It should be noted that the three illustrated steps of providing the trench (step 1), filling the trench with the doped material (step 2), and removing the doped material from the surface (step 3) may alternatively be performed after providing the upper (second) layer 14, such that the indenter 22 extends through the upper layer 14.

[0027] In the Fig. 5a and Fig. Figure 5b illustrates the results of two device simulations, namely a TVS diode (operating in avalanche mode) and a PIN diode (operating in forward mode). Such simulations are used to demonstrate the performance improvement of a device. This evaluation method is based on a simulated transmission line pulse applied to the respective device within a 50 Ω system. The result of each simulation is shown by a plot of the respective diode's voltage resulting from the transmission line pulse versus time.

[0028] Fig. 5a shows the result for a 4000-µm 2A TVS diode operating in avalanche mode, to which a transmission line pulse 38a, e.g., a 20-ampere pulse, has been applied. This transmission line pulse 38a increases the current for up to 0.5 ns, after which it forms a plateau (20 A). During this increase in current, a so-called overshoot voltage builds up due to the parasitic capacitance of the diode until the avalanche breakdown fully begins. The overshoot voltage for a conventional diode is designated by reference numeral 40a, while the overshoot voltage for the improved diode incorporating the indenter is designated by reference numeral 40'a. As illustrated by graph 40a for the conventional diode, a maximum overshoot voltage of, e.g., 70 V is built up before the diode avalanches. Here the avalanche breakthrough begins at about 0.3 ns and is completed after about 0.6 ns (cf. 40a).Plot 40a of the improved diode shows that due to the reduced turn-on time t, almost no overshoot voltage builds up. This means that the improved diode conducts current before the transmission line pulse has fully begun.

[0029] Fig. Figure 5b illustrates the result of the power simulation of a PIN diode operating in the forward mode to which a 20-ampere transmission line pulse 38b has been applied. Similar to the Fig. 5a, the overshoot voltage 40b of a conventional PIN diode (e.g. 30 V) is measured using the improved version, which has a partially reduced base width w n2 (cf. 40b) is avoided due to its reduced turn-on time t.

[0030] In Fig. 1 and Fig. 2a, it should be noted that the conductivity types of layers 12 and 14 may be selected such that an NIP diode is formed, i.e., layer 12 comprises a p+ dopant instead of an n+ dopant, and layer 14 comprises an n+ dopant instead of a p+ dopant. Analogously, the conductivity types used for the layers of the electrical circuit 30 may change, such that the substrate 32 may comprise a p+ dopant (instead of an n+ dopant), the lower layer 12 may comprise an n+ dopant (instead of a p+ dopant), and the upper layer 14, as well as the indenter 22 (instead of an n+ dopant), may comprise a p+ dopant. According to an alternative embodiment, the applied doping concentration of the individual materials (e.g.,for the first or second layer 12 and 14) so ​​that a lower (-) or higher (++) doping concentration can be used.

[0031] In Fig. 1 it should be indicated that the area 18, which has the reduced thickness w n2 is not necessarily embedded in the intrinsic layer 16. That is, the region 18 which, in terms of its thickness, w n2 reduced, a region of the intrinsic layer 16 which has a non-reduced thickness w n1 In other words, the intrinsic layer 18 is provided so that it forms a step.

[0032] In the Fig. 2b and Fig. 2c, it should be stated that the size and shape of the indenter 22 may alternatively be different, so that the indenter 22 may have a round or elongated shape with a diameter in the range between 1 µm and 10 µm or 20 µm.

[0033] In the Fig. 3a and Fig. 3b, it should be noted that the vertical transistor 30 shown may include further layers such as a buried layer, which is a low resistance layer embedded in a high resistance substrate 32.

[0034] Although the layer arrangement according to the Fig. 3a and Fig.3b in the context of a transistor, it should be noted that the stacked array can also be used as a junction voltage suppressor diode, with substrate 32 forming the cathode and upper layer 14 forming the anode. In the case of an NPN stacked array, substrate 32 forms the anode, while upper layer 14 forms the cathode.

Claims

[1] Electrical device (10,20,30) comprising: a first doped layer (12) having a first conductivity type; a second doped layer (14) having a second conductivity type opposite to the first conductivity type; and an intrinsic layer (16) arranged between the first layer (12) and the second layer (14), the intrinsic layer (16) having a reduced thickness in at least one section which is filled with a doped material of the second conductivity type, the at least one section with the reduced thickness being formed by one or more indenters (22) having the second conductivity type, the one or more indenters (22) being electrically connected to the second layer (14) and extending into the intrinsic layer (16), a region (18) of the one or more indenters (22) being less than 30% of an active region in which the first layer (12) and the second layer (14) are opposite one another; wherein a depth of the indenters (22) is at least 10% smaller than a thickness of the intrinsically conductive layer (16). [2] The electrical device (10,20,30) of claim 1, wherein the indenters (22) comprise polysilicon. [3] Electrical device (10, 20, 30) according to one of claims 1 to 2, wherein the region (18) of the at least one section has a square shape, a circular shape or an oval shape. [4] Electrical device (10,20,30) according to one of claims 1 to 3, wherein more than one section is evenly distributed laterally over the active area. [5] Electrical device (10,20,30) according to claim 4, wherein a lateral distance between two adjacent laterally distributed sections is greater than three times a diameter of the section. [6] Electrical device (10, 20, 30) according to one of claims 1 to 5, wherein the intrinsic layer (16) arranged between the first doped layer (12) and the second doped layer (14) comprises a pn junction of a diode. [7] Electrical device (10, 20, 30) according to one of claims 1 to 6, wherein the electrical device is a PIN diode comprising a p-dopant material in the regions of the first conductivity type and an n-dopant material in the regions of the second conductivity type. [8] Electrical device (10,20,30) according to one of claims 1 to 6, wherein the electrical device is a NIP diode comprising an n-type dopant in the regions of the first conductivity type and a p-type dopant in the regions of the second conductivity type. [9] The electrical device (10,20,30) of any one of claims 1 to 8, further comprising a substrate comprising the first layer (12). [10] The electrical device (10,20,30) of claim 9, wherein the substrate has the second conductivity type. [11] Electrical device (10, 20, 30) according to one of claims 1 to 6, wherein the electrical device is a transistor in which a collector is formed by the substrate, a base is formed by the first layer (12) and the intrinsic layer (16), and an emitter is formed by the second layer (14). [12] Electrical device (10,20,30) according to one of claims 9 to 11, wherein a buried layer is embedded in the substrate, and wherein the buried layer comprises a p-doped layer. [13] The electrical device (10, 20, 30) of claim 11 or 12, wherein a ratio of a reduced base width and a base width is less than 2 / 3, wherein the base width is a distance between the collector and the emitter, and wherein the reduced base width is a distance between the collector and the region of the at least one section. [14] Electrical device (10, 20, 30) according to one of claims 11 to 13, wherein the transistor comprises a p-dopant material in the regions of the first conductivity type and an n-dopant material in the regions of the second conductivity type. [15] Electrical device (10, 20, 30) according to one of claims 11 to 13, wherein the transistor comprises an n-dopant material in the regions of the first conductivity type and a p-dopant material in the regions of the second conductivity type. [16] Electrical device (10, 20, 30) according to one of claims 1 to 15, wherein the regions of the intrinsic layer (16) having different thicknesses are arranged adjacent to one another so that the intrinsic layer (16) forms a step. [17] An electrical device (10, 20, 30) having a vertical layer arrangement, the device comprising: a substrate comprising a lower layer (12) having a first conductivity type; an upper layer (14) having a second conductivity type opposite to the first conductivity type; an intrinsically conductive layer (16) disposed between the lower layer and the upper layer; and one or more indenters (22) extending from the upper layer (14) into the intrinsic layer (16) such that the intrinsic layer (16) has a reduced thickness in at least one portion, wherein an area of the one or more indenters (22) is less than 30% of an active area in which the first and second layers are opposite each other, wherein the indenters (22) comprise polysilicon and are electrically connected to the upper layer and have a depth which is at least 10% smaller than a thickness of the intrinsic layer (16), wherein the indenters (22) have the second conductivity type. [18] Transient voltage suppressor diode comprising: a first doped layer having a first conductivity type disposed on a substrate having a second conductivity type opposite to the first conductivity type; a second doped layer (14) having the second conductivity type; and an intrinsic layer (16) arranged between the first and second layers (14), wherein the intrinsic layer (16) has a reduced thickness in at least one section which is filled with a doped material of the second conductivity type, wherein an area of the at least one section is less than 30% of an active area in which the first and second layers (14) face each other, wherein the at least one portion having the reduced thickness is formed by one or more indenters (22) having the second conductivity type, wherein the one or more indenters (22) are electrically connected to the second layer (14) and extend into the intrinsic layer (16), wherein a depth of the indenters (22) is at least 10% smaller than a thickness of the intrinsically conductive layer (16). [19] A method of manufacturing an electrical device (10, 20, 30), the method comprising: Providing a first layer (12) having a first conductivity type; Providing an intrinsically conductive layer (16) on the first layer (12); Providing one or more trenches in the intrinsic layer (16); Filling the one or more trenches with a material having a second conductivity type opposite to the first conductivity type; and Providing a second layer (14) having the second conductivity type on the intrinsic layer (16), such that one or more indenters (22) extending from the second layer (14) into the intrinsic layer (16) and electrically connected to the second layer (14) are formed, namely such that the intrinsic layer (16) has a reduced thickness in at least one section, wherein an area of the one or more indenters (22) is less than 30% of an active area in which the first (12) and the second layer (14) face each other, wherein the indenters (22) have a depth that is at least 10% smaller than a thickness of the intrinsic layer (16), wherein the indenters (22) have the second conductivity type. [20] The manufacturing method of claim 19, wherein providing the one or more trenches and filling the one or more trenches are performed after providing the second layer (14) such that the filled trenches extend through the second layer (14) into the intrinsic layer (16). [21] A manufacturing method according to claim 19 or 20, wherein filling the one or more trenches is carried out by epitaxy of polysilicon. [22] A manufacturing method according to claim 21, wherein the method comprises etching the polysilicon. [23] Manufacturing method according to one of claims 19 to 22, wherein filling the one or more trenches and providing the second layer (14) are carried out simultaneously.

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