Procedure for improved gap filling

Abstract

A method for manufacturing a semiconductor structure (100), comprising: Providing a substrate (102) including one or more rib structures (104) on the substrate (102); Coating a first solution onto the substrate (102) to form a first dielectric layer (112), the first solution having a first viscosity, and the uppermost surface of the first dielectric layer (112) being below a top surface of the one or more fin structures (104); and Coating a second solution onto the first dielectric layer (112) to form a second dielectric layer (114) to cover the fin structures (104), the second solution having a second viscosity, the second viscosity being greater than the first viscosity.

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technical advances in IC materials and IC design have spawned generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a manufacturing process) has decreased. This process of downscaling generally realizes benefits by increasing production efficiency and reducing the costs associated with production. Such downscaling has also increased the complexity of IC processing and manufacturing; and for these advances to be realized, similar developments in IC processing and manufacturing are necessary.

[0002] When the critical dimension (KA) of a feature is scaled down, the feature may have a high aspect ratio (the ratio of the feature's height to its width). Such downscaling has also increased the complexity of IC structure and processing; and for these advances to be realized, similar developments in IC processing and manufacturing are necessary. For example, a three-dimensional (3D) transistor has been introduced to replace a planar transistor. Although existing structures and methods for fabricating semiconductor devices have generally been sufficient for their intended purposes, they have not proven entirely satisfactory in all respects.For example, the introduction of a three-dimensional semiconductor structure featuring high aspect ratio features poses a challenge for the development of semiconductor device processes. Accordingly, there is a need for improvements in this area.

[0003] KR 10 2004 0 001 476 A discloses a semiconductor structure comprising a plurality of fin structures on a substrate, a first dielectric layer with a low viscosity on the substrate, and a second dielectric layer with a higher viscosity on the first dielectric layer. The first dielectric layer is partially arranged on the fin structures.

[0004] Further prior art relating to the subject matter of the invention can be found, for example, in CN 102 097 361 B, US 2013 / 0 307 079 A1, US 2010 / 0 167 496 A1, US 2005 / 0 026 443 A1, US 2006 / 0 003 596 A1 and US 2011 / 0 193 178 A1.

[0005] The invention provides a method for producing a semiconductor structure according to claim 1. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are used for illustrative purposes only. The dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1A, Fig. 2A and Fig. 3A are schematic drawings illustrating a semiconductor structure during various manufacturing steps for an improved gap filling process, according to some embodiments. Fig. 1B, Fig. 2B and Fig. 3B are cross-sectional views of the semiconductor structure along the line AA of the Fig. 1A, Fig. 2A and 3A, respectively, during various manufacturing steps for an improved gap filling process according to some embodiments. Fig. 4 is a flowchart illustrating a method for improving the gap filling process, according to some embodiments. Fig. Figure 5 is a cross-sectional view of the semiconductor structure along line BB of Fig. 3A after performing a gate replacement process and forming the gate structure according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically imply a relationship between the various embodiments and / or configurations discussed.Furthermore, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation besides the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. That is, the exemplary term "below" can encompass both an above and below orientation.The device may also be oriented differently (rotated by 90 degrees, or other orientations), and the spatially relative descriptors used in this text may also be interpreted accordingly.

[0009] Fig. 1A, Fig. 2A and Fig. 3A are schematic drawings illustrating a semiconductor structure 100 during various manufacturing steps, and Fig. 1B, Fig. 2B and Fig. 3B are cross-sectional views of the semiconductor structure 100 along the line AA of the Fig. 1A, Fig. 2A and 3A, respectively, during various manufacturing steps. Semiconductor structure 100 may include an n-type finFET or a p-type finFET. Semiconductor structure 100 may be included in an integrated circuit (IC), such as a microprocessor, a memory device, and / or another IC device.

[0010] We turn to the Fig. 1A-1B. The semiconductor structure 100 includes a substrate 102 and semiconductor features, such as fins 104 and gate structures 106, formed on the substrate 102. Gaps (e.g., gap 105) are formed between two adjacent semiconductor features. In some embodiments, the substrate 102 is a silicon substrate.In some alternative embodiments, the substrate 102 includes other elemental semiconductors, such as germanium (Ge), a compound semiconductor including silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (gap), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0011] We stick with the Fig. 1A-1B. In some embodiments, the substrate 102 further includes additional features and / or material layers, such as various isolation features. The isolation features may be formed from silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. The isolation features may be shallow trench isolation (STI) features. In some embodiments, the isolation features are STI features and are formed by etching trenches in the substrate 102. The trenches may then be filled with isolation material, followed by a chemical mechanical polishing (CMP) process. Other manufacturing techniques for the isolation features are also possible.The isolation structures may include a multilayer structure, such as one or more liner layers. The substrate 102 may also include various doped regions, such as p-type and / or n-type regions, configured and coupled to form various devices and functional features. All doping features may be formed by a suitable process, such as ion implantation using various steps and techniques.

[0012] We turn Fig. 1A. The fins 104 may include silicon or another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. The fins 104 may be fabricated using any suitable process, including photolithography and etching processes. The photolithography processes may include forming a photoresist (resist) layer over the substrate, exposing the resist to a radiation source using a mask, performing a post-exposure firing process, and developing the resist to form the resist structures.The resist structures can then be used to protect regions of the substrate while an etching process forms recesses in the silicon layer, leaving an extending ridge. The recesses can be etched using a reactive ion etch (RIE) and / or other suitable processes. Numerous other embodiments of methods for forming ridges 104 on substrate 102 may also be suitable. It should also be understood that the ridges 104 shown in FIGS. Fig. 1A-1B, 2A-2B and 3A-3B are merely examples and are not intended to limit the shapes and / or sizes of the fin structures in the semiconductor structure 100.

[0013] We stay with Fig. 1A. In some embodiments, the gate structures 106 are poly gates that are to be replaced in a subsequent replacement poly gate (RPG) process, for example, to form metal gate structures or high-k gate structures. In some embodiments, the gate structures 106 include polysilicon.

[0014] In some embodiments, the height of the ridges 104 may range from about 20 nm (200 Å) to about 50 nm (500 Å). The height of the gate structures 106 may range from about 90 nm (900 Å) to about 130 nm (1300 Å). In some embodiments, the width of the gaps (e.g., gap 105) between the ridges 104 and / or gate structures 106 may range from about 8 nm (80 Å) to about 19 nm (190 Å). Therefore, the aspect ratio of the gaps may range from about 5 to about 23. In some preferred embodiments, the aspect ratio of the gaps ranges from about 5 to about 16. As the critical dimension (KA) of the semiconductor features, such as fins 104 and gate structures 106, is scaled down, the aspect ratio of the semiconductor features may increase.

[0015] In some embodiments, when one or more material layers (e.g., dielectric layers) are formed using deposition techniques, the deposition solution may not completely fill the gaps (e.g., gap 105) due to the increased aspect ratio. Vacant spaces, such as air bubbles, may be trapped when the material layers fill the high aspect ratio gaps. In some embodiments, when the aspect ratio of the gaps is greater than about 8 or the width of the gaps is less than about 15 nm (150 Å), vacancies may be observed in the material layers. The vacancies trapped in the material layer can interfere with etching processes, trap contaminants, and degrade device performance. Therefore, it is desirable to have a method that improves gap filling.

[0016] Before forming the first dielectric layer, in some embodiments, the surface of the substrate 102 is treated to improve the surface affinity between the substrate 102 and a material layer to be formed on the substrate, such as a first dielectric layer 112, as described later with reference to the Fig. 2A-2B. In some embodiments, the surface of the substrate 102 is treated with cleaning, dehydration, and / or surface priming processes such that the surface of the substrate 102 has good adhesion between the substrate 102 and the first dielectric layer 112 to be formed on the substrate 102. In some examples, the cleaning process may include wet cleaning and / or rinsing with distilled water to remove contaminants. In some embodiments, the dehydration process may be performed in a closed chamber to remove adsorbed water on the surface of the substrate 102. In some embodiments, polymers with suitable adhesion functional groups may be applied to treat the surface of the substrate 102 in a surface priming process.In some embodiments, the functional groups contain hydrophilic groups or hydrophobic groups, depending on the hydrophilic or hydrophobic property of the material layer to be formed on the substrate, such as the first dielectric layer 112.

[0017] We turn to the Fig. 2A-2B. A first dielectric layer 112 is formed on the substrate 102. In some embodiments, the first dielectric layer 112 is formed using a coating solution with a controlled viscosity to facilitate the process of filling the gaps (e.g., gap 105) and the uneven surface profiles between the semiconductor features (e.g., fins 104 and / or gates 106). In some embodiments, as discussed in detail later in the present disclosure, the viscosity of the coating solution may be controlled by tuning the concentration of solutes in the coating solution and / or adding surfactants to the coating solution. The filling process may also be facilitated by using a reflow process and / or performing a surface treatment on the substrate.The first dielectric layer 112 provides a planar surface over the substrate. Furthermore, the dielectric material in the first dielectric layer 112 may provide suitable etch selectivity for etching in the one or more subsequent patterning processes.

[0018] In some embodiments, the first dielectric layer 112 is formed using a coating technique. A first coating solution is used in the coating technique to form the first dielectric layer 112. In some embodiments, the solute of the first coating solution includes at least one of the following: acrylate, methacrylate, polyhydroxystyrene, or other polymers containing crosslinking functional groups. In some embodiments, the solvent used in the first coating solution includes at least one of the following: propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), ethyl lactate (EL), cyclohexanone, or other suitable solvent materials. In some embodiments, a first viscosity of the first coating solution ranges from about 0.001 Pa s (1 centipoise (cP)) to about 0.0015 Pa s (1.5 cP).In some embodiments, the first viscosity of the first coating solution is controlled by adjusting the concentration of the solute dissolved in the solvent. For example, the concentration of the solute in the first coating solution can be controlled to a range of about 0.1% to about 10%.

[0019] In some embodiments, the first viscosity can also be adjusted by adding suitable additive materials to the first coating solution, such as materials with crosslinking groups. For example, the additive materials can include tetrabutylammonium hydroxide (TBAH) and / or tetrabutylammonium lactate. The amount of additive materials added to the first coating solution can be controlled within a range of about 0.5% to about 98%.

[0020] In some embodiments, the solvent of the first coating solution is also adjusted to improve the affinity between the first dielectric layer 112 and the substrate 102. The first coating solution can be adjusted to reduce the surface tension and improve the affinity between the first dielectric layer 112 and the fins 104 and / or gate structures 106. For example, Hansen solubility parameters can be used to assess the affinity between different layers.

[0021] In some embodiments, surfactants may be added to the first coating solution in a range of about 0.01% to about 1% to reduce the surface tension between the first material layer 112 and the substrate 102. In some embodiments, the surfactants include one or more materials selected from the group consisting of ammonium lauryl sulfate (ALS), octyl and nonylphenol ethoxylates, alcohol (primary and secondary) ethoxylates, amine ethoxylates, glucosides, glucamine, polyethylene glycols, poly(ethylene glycol-copropylene glycol), and combinations thereof. In some examples, the surfactants may include Triton ® X-surfactants and TERGITOL™ TMN-6 (The Dow Chemical Company, US).

[0022] The first coating solution is then coated onto the substrate 102 to form the first dielectric layer 112. In some examples, the coating process may include a spin-coating process with a spin-coating rate in a range of about 500 rpm to about 2500 rpm. During the spin-coating process, the solvent may be partially or completely evaporated. In some embodiments, the spin-coating process may include a dielectric spin-coating process. In some embodiments, the coating process may also include other types of coating processes, such as a dip-coating process.

[0023] After coating the first coating solution, a firing process is performed to evaporate the solvent in the coated film layer. In some embodiments, the firing process is performed at a temperature ranging from about 80°C to about 300°C. In some embodiments, the firing process is performed for a time ranging from about 5 seconds to 3 minutes.

[0024] In some embodiments, the first dielectric layer 112 includes one or more organic dielectric materials, such as acrylate, methacrylate, polyhydroxystyrene, or other polymers containing cross-linking functional groups, and combinations thereof. In some embodiments, the first dielectric layer 112 is used as an anti-reflection (ARC) layer configured to suppress unwanted light reflections during the lithography process, as discussed later. In some embodiments, the ARC layer has a reflection index in a range of about 1 to about 2.2. In some embodiments, the first dielectric layer 112 is used as a mask during subsequent etching processes.For example, before removing the source / drain regions of the n-type region, the first dielectric layer 112 is used to cover the p-type region to protect the p-type region from etching; or before removing the source / drain regions of the p-type region, the first dielectric layer 112 is used to cover the n-type region to protect the n-type region from etching. Alternatively, the first dielectric layer 112 may be used as an etch stop layer for the following one or more etch processes, such as a contact etch process. In some embodiments, the first dielectric layer 112 is removed after the etch processes.

[0025] In some embodiments, the first dielectric layer 112 includes one or more inorganic dielectric materials, such as silicon nitrides, silicon silicates, and / or silicon oxides. In some embodiments, the first dielectric layer 112 may be included in one or more interlayer dielectric (ILD) layers. In some embodiments, the first dielectric layer 112 may also include a hard mask layer used for patterning in subsequent processes.

[0026] We stick with the Fig. 2A-2B. In some embodiments, the first dielectric layer 112 may fill the gaps between the semiconductor features, but may not be formed to completely cover the semiconductor features (e.g., the fins 104 and the gate structures 106). In some examples, as in Fig. 2A, the height (H) of the semiconductor features (e.g., the height of the gate structures 106) is greater than the thickness (T1) of the first material layer 112. In some embodiments, the first dielectric layer 112 has a thickness (T1) in a range from about 10 nm (100 Å) to about 600 nm (6000 Å). In some preferred embodiments, the thickness (T1) is in a range from about 10 nm (100 Å) to about 80 nm (800 Å). As shown in the Fig. 2A-2B, after forming the first dielectric layer 112, the aspect ratio of the gaps, for example, the gap 105, may be reduced so that the subsequent gap filling processes may be facilitated.

[0027] After forming the first dielectric layer 112, in some embodiments, a thermal reflow process is performed on the first dielectric layer 112 to increase the fluidity of the first dielectric layer 112 such that gap filling in the semiconductor features (e.g., fins 104 and / or gate structures 106) may be improved. In some embodiments, the thermal reflow process includes heating the first dielectric layer 112 to a temperature in a range of about 150°C to about 300°C. In some embodiments, the thermal reflow process is performed for a time period in a range of about 5 seconds to about 10 minutes. During the thermal reflow process, the material in the first dielectric layer 112 may become movable to fill the gaps (e.g., gap 105) between the semiconductor features on the substrate 102.

[0028] We turn to the Fig. 3A-3B. A second dielectric layer 114 is formed on the first dielectric layer 112. In some embodiments, the second dielectric layer 114 is formed to fill the gaps and cover the semiconductor features, including fins 104 and gate structures 106.

[0029] In some embodiments, the second dielectric layer 114 is formed using a coating process. A second coating solution is used to form the second dielectric layer 114. In some embodiments, the second coating solution may contain substantially similar materials to the materials used in the first coating solution. In some embodiments, the solute of the second coating solution contains at least one of the following: acrylate, methacrylate, polyhydroxystyrene, or other polymers containing crosslinking functional groups. The solvent of the second coating solution contains at least one of the following: propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), ethyl lactate (EL), cyclohexanone, or other suitable solvent materials.In some alternative embodiments, the second coating solution may also contain different materials or solvents than the first coating solution. In some embodiments, the second coating solution has a second viscosity that is different from the first viscosity. In some embodiments, the second viscosity is greater than the first viscosity. The second viscosity may range from about 0.0018 Pa s (1.8 cP) to about 0.002 Pa s (2 cP). The higher viscosity of the second coating solution may improve the efficiency of forming the second dielectric layer 114, such that less time and less solvent are needed to form the second dielectric layer 114. In some embodiments, the viscosity is tuned by controlling the concentration of the solute in the second coating solution.The concentration of the solute in the second coating solution can be controlled to be at least about 10% higher than the concentration of the first coating solution.

[0030] In some embodiments, the viscosity can also be adjusted by adding suitable additive materials, such as materials with cross-linking groups, to the second solution to change the properties and compositions of the solution. For example, the additive materials can include tetrabutylammonium hydroxide (TBAH) and / or tetrabutylammonium lactate. The amount of additive materials added to the first and / or second coating solutions can be controlled within a range of about 0.5% to about 98%. In some embodiments, the amount of additive materials added to the second coating solution is at least about 10% more than the amount of additive materials added to the first coating solution.

[0031] In some embodiments, the second coating solution can also be adjusted to reduce surface tension and improve the affinity between the second dielectric layer 114 and the fins 104 and / or gate structures 106. For example, Hansen solubility parameters can be used to assess the affinity between different layers. In some embodiments, surfactants can also be added to the second coating solution. The surfactant materials are substantially similar to those used in the first dielectric layer 112.

[0032] In some embodiments, the second dielectric layer 114 is coated onto the first dielectric layer 112. In some embodiments, the coating process of the second coating solution may be substantially similar to the coating process of the first coating solution. In some embodiments, the coating process of the second coating solution includes a spin-on process with a lower spin-on rate than the coating process of the first coating solution. In some embodiments, because the viscosity of the second solution is greater than the viscosity of the first solution, the thicknesses of the first material layer and the second material layer may be dominated by the viscosities of the first coating solution and the second coating solution, respectively. In some embodiments, the coating process may also include other types of coating processes, such as a dip-coating process.In some embodiments, the coating process may also include other types of coating methods, such as a dip coating process.

[0033] After coating the first coating solution, a firing process is performed to evaporate the solvent in the coated film layer. In some embodiments, the firing process is performed at a temperature ranging from about 80°C to about 300°C. In some embodiments, the firing process is performed for a time ranging from about 5 seconds to 3 minutes.

[0034] In some embodiments, the second dielectric layer 114 includes substantially similar materials as discussed with respect to the first dielectric layer 112. In some embodiments, the second dielectric layer 114 includes an organic dielectric material, such as acrylate, methacrylate, polyhydroxystyrene, or other polymers containing cross-linking functional groups, and combinations thereof. The second dielectric layer 114 may function as an anti-reflection (ARC) layer configured to suppress unwanted light reflections during the subsequent lithography process. The ARC layer may have a reflection index in a range of about 1 to about 2.2. The second dielectric layer 114 may be used as a mask during subsequent etching processes.In some examples, before removing the source / drain regions of the n-type region, the second dielectric layer 114 may be used to cover the p-type region to protect the p-type region from etching; or before removing the source / drain regions of the p-type region, the second dielectric layer 112 may be used to cover the n-type region to protect the n-type region from etching. Alternatively, the second dielectric layer 114 may be used as an etch stop layer for the following one or more etch processes, such as a contact etch process. The second dielectric layer 114 is removed after the etch processes.

[0035] In some embodiments, the second dielectric layer 114 includes one or more inorganic dielectric materials, such as silicon nitrides, silicon silicates, and / or silicon oxides. In some embodiments, the second dielectric layer 114 may be included in the one or more interlayer dielectric (ILD) layers. In some embodiments, the second dielectric layer 114 may also include a hard mask layer used for patterning in subsequent processes.

[0036] In some embodiments, the thickness (T1) of the first dielectric layer 112 plus the thickness (T2) of the second dielectric layer 114 is greater than the height (H) of the semiconductor features. In some embodiments, the second dielectric layer 114 has a thickness (T2) in a range from about 10 nm (100 Å) to about 600 nm (6000 Å). In some preferred embodiments, the thickness (T2) is in a range from about 10 nm (100 Å) to about 200 nm (2000 Å). The second dielectric layer 114 is configured to provide a planar surface and to provide suitable etch selectivity for etching in the following one or more patterning processes.

[0037] Fig. 4 is a flowchart illustrating a method 200 for forming the semiconductor structure 100 to enhance the gap filling process, according to some embodiments of the present disclosure. The method 200 begins at step 202 with providing the substrate 102 containing semiconductor features, such as fins 104 and gate structures 106. Gaps (e.g., gap 105) are formed between the fins 104 and / or gate structures 106, as shown in FIGS. Fig. 1A-1B shown.

[0038] The method 200 proceeds to an optional step 204 of treating the surface of the substrate 102 to improve the surface affinity between the substrate 102 and a material layer to be formed on the substrate, such as a first dielectric layer 112, as will be discussed later with reference to step 206. The details of the surface treatment at step 204 were described above in the present disclosure with reference to Fig. 1A-1B. In some embodiments, step 202 of method 200 may proceed directly to step 206 without performing step 204.

[0039] The method 200 proceeds to step 206 where a first coating solution is prepared that is used to form the first dielectric layer 112. The solute and solvent used to form the first coating solution were previously described in the present disclosure with reference to the Fig. 2A-2B discussed.

[0040] The method 200 proceeds to step 208, where the first coating solution is coated onto the substrate 102 to form a first dielectric layer 112. In some examples, the coating process may include a spin-on process or other suitable coating methods, such as a dip-coating process.

[0041] The method 200 proceeds to step 210, where the deposited first dielectric layer 112 is fired. The firing process is performed to evaporate the solvent in the first dielectric layer 112.

[0042] We stay with Fig. 4. The method 200 proceeds to an optional step 212 where the first dielectric layer 112 is reflowed. In some embodiments, the thermal reflow process may be performed on the first dielectric layer 112 to increase the fluidity of the first dielectric layer 112 so that the filling of the gaps in the semiconductor features (e.g., fins 104 and / or gate structures 106) may be improved. In some embodiments, the thermal reflow process is performed in step 212 after the deposited first dielectric layer 112 has been fired at step 210 to evaporate further solvent. In some alternative embodiments, the thermal reflow process is performed after the first coating solution is deposited in step 208, without firing the deposited layer.In some embodiments, with respect to method 200, step 210 may proceed directly to step 214 without reflowing first dielectric layer 112 in step 212.

[0043] The method 200 proceeds to step 214 where a second coating solution is prepared that is used to form the second dielectric layer 114. The solute and solvent used to form the second coating solution were previously described in the present disclosure with reference to the Fig. 3A-3B discussed.

[0044] The method 200 proceeds to step 216, where the second coating solution is coated onto the first dielectric layer 112 to form the second dielectric layer 114. In some examples, the coating process may include a spin-on process. The spin-on process may include a dielectric spin-on process. In some embodiments, the coating process may also include other types of coating processes, such as a dip-coating process.

[0045] After the coating process, the method 200 proceeds to step 218 where the second dielectric layer 114 is fired to evaporate the solvent in the second dielectric layer 114.

[0046] Although the formation of the first dielectric layer 112 and the second dielectric layer 114 is described with reference to the flowchart of Fig. 4, the first dielectric layer 112 and the second dielectric layer 114 may also be formed using any suitable combinations of different steps to enhance the filling of the gaps in the semiconductor structure 100. In some embodiments, a planarization process (e.g., a CMP process) is performed after forming the first and second dielectric layers. In some embodiments, no planarization process (e.g., a CMP process) is required because the first dielectric layer 112 and the second dielectric layer 114 discussed in the present disclosure may create planar surfaces.

[0047] We stay with Fig. 4. After forming the first dielectric layer 112 and the second dielectric layer 114, the method 200 proceeds to step 220, where a resist layer is formed on the second dielectric layer 114 for the following lithography processes. In some embodiments, the resist layer is a photoresist layer. In some embodiments, the resist layer is an electron beam sensitive layer. The electron beam sensitive material is patterned by an electron beam lithography process. In some embodiments, the resist layer may be formed using a spin-on technique. The resist layer may have a thickness in a range of about 5 nm to about 1000 nm. Step 220 of method 200 may also include firing the resist layer to evaporate the solvent in the resist layer.In some embodiments, the firing temperature may range from about 30°C to about 300°C, and the firing time may range from about 5 seconds to about 3 minutes.

[0048] The method 200 proceeds to step 222, where the resist layer is exposed to an exposure beam. The exposure beam may include ultraviolet (UV), deep ultraviolet (DUV), and / or extreme ultraviolet (EUV) light, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser or a 193 nm beam from an argon fluoride (ArF) excimer laser. In some embodiments, the exposure process of step 214 is performed using a reticle having a predetermined pattern (or a negative pattern). The lithography process may also use other exposure modes or technologies, such as on-axis, off-axis, quadrupole, or dipole exposure technologies.In some alternative embodiments, the exposure process in step 214 may also be implemented or replaced by other suitable methods, such as a maskless lithography technique and electron beam lithography.

[0049] The method 200 proceeds to step 224, where the resist layer is developed using a developer chemistry to form resist patterns. In some examples, the developer chemistry includes tetramethylammonium hydroxide (TMAH) solution at a suitable concentration in a range of about 2% to about 5%. In a preferred embodiment, the concentration of the TMAH solution is in a range of about 2% to about 3%. The method 200 may then proceed to rinsing, drying, and / or other suitable processes. The resist patterns may be used as a masking element in performing one or more processes on underlying layers, such as etching, ion implantation, and / or other suitable processes. The resist patterns may then be etched away during subsequent processes in the fabrication of the semiconductor device.In some embodiments, the resist structures may then be stripped from the substrate.

[0050] In some embodiments, the resist layer is patterned to be used as an etch mask for the following gate replacement process. In some embodiments, in step 226 of the method 200, the poly gate 106 is removed to form a gate trench (e.g., gate trench 500) defined in the first dielectric layer 112 and the second dielectric layer 114. In some embodiments, removing the poly gate 106 may include a planarization process used to remove a portion of the second dielectric layer 114 and expose a top surface of the poly gate 106. In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process. After exposure, the poly gate 106 may be completely or partially removed by suitable wet and / or dry etch processes.

[0051] In some embodiments, after forming the gate trenches, a plurality of spacers 501 are exposed on sidewalls of the gate trenches (e.g., gate trench 500). In some embodiments, spacers 501 are formed before or after forming the source / drain regions and along poly gate 106. In some embodiments, spacers 501 are formed using a deposition process and an etch process (e.g., an anisotropic etch process). In some embodiments, spacers 501 include a suitable dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. In some embodiments, a contact etch stop layer (CESL) 503 is also formed on spacer 501 and on substrate 102.In some embodiments, the CESL 503 includes silicon nitride, silicon oxide, silicon oxynitride, and / or other suitable materials. In some embodiments, the CESL 503 is formed using a native oxide growth process. In some embodiments, the CESL 503 may also be formed using a chemical vapor deposition (CVD) process and / or another suitable deposition process.

[0052] Fig. 5 is a cross-sectional view of the semiconductor structure 100 along the line BB of Fig.3A after performing a gate replacement process to form a gate structure 502. After removing the poly gate 106, a gate structure 502 is formed to fill the gate trench 500. In some embodiments, the gate structure 502 includes one or more layers, such as a high-k dielectric layer 504, a barrier layer 506, a trigger working layer 508, and a gate layer 510. However, other embodiments may be possible that include additional layers and / or fewer layers. For example, the gate structure may further include one or more cap layers, etch stop layers, and / or other suitable layers. In some embodiments, a CMP process is performed to create a planar surface of the final gate structure.The semiconductor structure 100 also includes the first dielectric layer 112 disposed on the substrate 102 and the second dielectric layer 114 disposed on the first dielectric layer 112. The materials, manufacturing processes, and layer thicknesses of the first dielectric layer 112 and the second dielectric layer 114 were discussed in detail earlier in the present disclosure. In some embodiments, the first dielectric layer 112 has a thickness (T1) in a range from about 10 nm (100 Å) to about 600 nm (6000 Å). In some preferred embodiments, the thickness (T1) is in a range from about 10 nm (100 Å) to about 80 nm (800 Å). In some embodiments, the second dielectric layer 114 has a thickness (T2) in a range of about 10 nm (100 Å) to about 600 nm (6000 Å).In some preferred embodiments, the thickness (T2) is in a range of about 10 nm (100 Å) to about 200 nm (2000 Å).

[0053] In some embodiments, the high-k dielectric layer 504 is formed by chemical oxidation, thermal oxidation, an atomic layer deposition (ALD) process, CVD, and / or other suitable formation processes. In some embodiments, the high-k dielectric layer 504 includes a high-k dielectric layer, such as hafnium oxide (HfO2). Alternatively, the high-k dielectric layer 504 may optionally include other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, combinations thereof, or other suitable materials. In some embodiments, the barrier layer 506 may include TaN or another suitable material.

[0054] The trigger work layer 508 may be an n-type or p-type trigger work layer. Example p-type trigger work metals that may be included in the gate structures 502 are TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type trigger work materials, or combinations thereof. Example n-type trigger work metals that may be included in the gate structures 502 are Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type trigger work materials, or combinations thereof. A triggering energy value is linked to the material composition of the triggering energy layer, and therefore, the material of the first triggering energy layer is selected accordingly so that its triggering energy value is tuned to achieve a desired threshold voltage Vt in the device to be formed in the respective region. The triggering energy layer may contain multiple layers.The one or more trigger working layers may be deposited by CVD, PVD and / or other suitable processes.

[0055] The gate layer 510 may include Al, W, or Cu and / or other suitable materials. The gate layer 510 may be formed by CVD, PVD, plating, and / or other suitable processes. The gate layer 510 may be deposited over the trigger working metal layer 508, thereby filling the remaining portion of the gate trenches. The semiconductor device 100 may also include other layers and / or other structural elements not explicitly illustrated, such as additional source / drain regions, contacts, interconnects, and / or other suitable structural elements.

[0056] The present embodiments describe one or more cost-effective and feasible mechanisms for improving gap filling in high aspect ratio semiconductor features. The mechanisms include forming a first dielectric layer using a first solution having a first viscosity and forming a second dielectric layer using a second solution having a second viscosity greater than the first viscosity. The mechanisms also include reflowing the first dielectric layer. The mechanisms also include treating the substrate to improve the surface affinity between the substrate and the first dielectric layer. The mechanisms effectively avoid the formation of voids during the gap filling process.The mechanisms also allow for providing suitable etch selectivity for the etching processes in the one or more subsequent patterning processes. The process conditions are flexible, and the disclosed mechanisms can be applied to various types of layers within a semiconductor structure. The disclosed mechanisms can further be combined with other chemical or other processes to form various structures on the substrate.

Claims

[1] A method of manufacturing a semiconductor structure (100), comprising: Providing a substrate (102) including one or more rib structures (104) on the substrate (102); Coating a first solution onto the substrate (102) to form a first dielectric layer (112), the first solution having a first viscosity, and the uppermost surface of the first dielectric layer (112) being below a top surface of the one or more fin structures (104); and Coating a second solution onto the first dielectric layer (112) to form a second dielectric layer (114) to cover the fin structures (104), the second solution having a second viscosity, the second viscosity being greater than the first viscosity. [2] The method of claim 1, wherein the first dielectric layer (112) is configured to include an anti-reflective coating having a reflection index in a range of about 1 to about 2.

2. [3] The method of claim 1 or 2, wherein the semiconductor structure (100) further includes one or more gate structures (106), and wherein a gap (105) is formed between the gate structures (106). [4] The method of claim 3, wherein an aspect ratio of the gap (105) is in a range of about 5 to about 23. [5] A method according to any one of the preceding claims, wherein the first viscosity is in a range of about 0.001 Pa·s to about 0.0015 Pa·s. [6] A method according to any one of the preceding claims, wherein the second viscosity is in a range of about 0.0018 Pa·s to about 0.002 Pa·s. [7] Method according to one of the preceding claims, wherein a height of the one or more rib structures (104) is greater than a thickness of the first dielectric layer (T1). [8] The method of claim 7, wherein a sum of the thickness of the first dielectric layer (T1) and a thickness of the second dielectric layer (T2) is greater than the height of the rib structures (104). [9] A method according to any one of the preceding claims, wherein the first solution has a first concentration of one or more solutes in a range of about 0.1% to about 10%, and wherein the second solution has a second concentration of one or more solutes that is at least about 10% more than the first concentration. [10] A method according to any one of the preceding claims, wherein the first viscosity and the second viscosity are adjusted by adding one or more additive materials containing crosslinking functional groups. [11] The method of claim 10, wherein an amount of the additive materials added to the second coating solution is at least about 10% greater than an amount of the additive materials added to the first coating solution. [12] A method according to any one of the preceding claims, further comprising: Reflowing the first dielectric layer (112) using a thermal reflow process after coating the first solution onto the substrate (102). [13] The method of claim 12, wherein the thermal reflow process is carried out at a temperature in a range of about 150°C to about 300°C. [14] A method according to any one of the preceding claims, further comprising: Treating the substrate (102) to improve the surface affinity between the substrate (102) and the first dielectric layer (112). [15] The method of any preceding claim, wherein the first dielectric layer (112) has a first thickness (T1) in a range of about 10 nm to about 80 nm, and wherein the second dielectric layer (114) has a second thickness (T2) in a range of about 10 nm to about 200 nm. [16] A method according to any one of the preceding claims, wherein the first solution is prepared by adding one or more surfactants to the first solution in a range of about 0.01% to about 1%. [17] The method of claim 16, wherein the one or more surfactants are selected from the group consisting of ammonium lauryl sulfate, octyl and nonylphenol ethoxylates, primary and secondary alcohol ethoxylates, amine ethoxylates, glucosides, glucamine, polyethylene glycols, poly(ethylene glycol-co-propylene glycol), and a combination thereof.

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