IMPROVED POWER SWITCHING CONVERTER WITH SPLIT PARTITIONING

Abstract

Power converter that features: a FET or SFET chip (22) comprising at least one FET or SFET switch (30) coupled to a circuit node (18) of a power stage (34); and a CMOS chip (20) which features: at least one CMOS switch (32) coupled to the circuit node (18) of the power stage (34), at least one measuring line (16B) configured to transmit a current measurement signal containing information about a current level of a current through the at least one CMOS switch (32), and a controller unit (24) configured to control the at least one FET or SFET switch (30) and the at least one CMOS switch (32) of the power stage (34) at least partially based on the current measurement signal transmitted through the at least one measuring line (16B) in order to generate an output power at the circuit node (18) of the power stage (34).

Description

[0001] This disclosure relates to power converters and, in particular, techniques and circuits associated with power switching converters.

[0002] Circuits can use power converters that receive power from a power source and convert the input power into output power (e.g., stepping it up or stepping it down) that has a (e.g., regulated) voltage or current level different from the voltage or current level of the input power. The converter outputs the power to a filter to supply power to a component, circuit, or other electrical device. Switch-based power converters can use half-bridge circuits and signal modulation techniques to regulate the current or voltage level of a power output. In some examples, power converters may additionally use feedback control circuits and techniques (e.g., voltage sensing, current sensing, and the like) to improve accuracy and control the voltage or current level of the power output.These previously mentioned techniques and circuits for improving the accuracy and controlling the voltage or current of the power output can decrease the overall efficiency of the power converter and / or increase the physical size, complexity and / or cost of the power converter.

[0003] In general, techniques and circuits are described that enable a system-in-package (SiP) power converter to output power at a current level that can not only reach or exceed five amperes, but also be maintained within a narrow (e.g., precise) current level tolerance window, all without increasing the size, cost, and / or efficiency of the SiP power converter. A SiP power converter, regardless of whether it is a buck or boost converter, can contain one or more power switches, driver / control logic, and a feedback control circuit (e.g., a current sensing circuit) distributed across just two chips in the SiP power converter package. One chip is a CMOS (Complementary Metal Oxide Semiconductor) chip and the other chip is a FET (Field-Effect Transistor) or SFET (Superconductor Field-Effect Transistor) chip.The one or more power switches of the SiP power converter contain a power stage (e.g., a single-phase half-bridge, a multi-phase half-bridge, etc.). Some of the one or more power switches (e.g., either the low-side or high-side of the power stage half-bridge) are located on the FET or SFET chip, while the remainder (e.g., the side of the power stage half-bridge not located on the FET or SFET chip) are located on the CMOS chip. The CMOS chip also contains driver / control logic and feedback control circuitry (e.g., a current-sensing circuit).

[0004] By incorporating some of the one or more power switches into the FET or SFET chip, the efficiency of the SiP power converter can be improved, since at least part (e.g., the high-side) of the SiP power converter's power stage can contain high-efficiency FET or SFET power switches. Additionally, the accuracy of the SiP power converter's power output can be improved by co-locating the driver / control logic, the feedback control circuitry (e.g., the current-sensing circuitry), and the remainder (e.g., the low-side) of the one or more power switches. This is because the power output can be controlled using high-precision sense FETs without being susceptible to electromagnetic interference (EMI) and other noise generated by the switching of the FET or SFET switches.Furthermore, the current sensing circuit can operate without the use of a charge pump by operating the current sensing circuit on the same CMOS chip as the rest of the power switches and driver / control logic.

[0005] US Patent 2008 / 0002446 A1 describes a power converter with a power transistor and a start-up circuit that includes another transistor. The power transistor and the start-up circuit are integrated into a first semiconductor chip, and a drive circuit for controlling the power transistor is integrated into a second semiconductor chip separate from the first.

[0006] US 2006 / 0245224 A1 describes a power module with a power chip and a control chip arranged on a common chip contact area (the pad).

[0007] US Patent 6,462,522 B2 describes a voltage regulator with a power transistor integrated into a single chip, where this chip is mounted on a substrate using flip-chip technology. The substrate is, in turn, mounted on a printed circuit board.

[0008] German patent DE 10 2008 064 368 A1 describes an arrangement with a voltage regulator integrated in a first chip and a load integrated in a second chip. The first chip and the second chip are arranged on a common substrate and in a common package.

[0009] German patent DE 199 43 146 C1 describes a bridge circuit for switching high currents, comprising multiple high-side and low-side switches designed as vertical MOS transistors on two separate chips. The low-side switches utilize common-source technology and each has a source located on the back of a chip and a drain located on the front of a chip, with the drain of a low-side switch connected to the source of a corresponding high-side switch.

[0010] US Patent 2012 / 0133348 A1 describes a power converter comprising a half-bridge with a high-side switch and a low-side switch. The switches of the half-bridge are controlled by a feedback signal, which in turn depends on an output voltage of the power converter.

[0011] CN 101621056 A discloses a multi-chip module for a power supply circuit, consisting of two MOSFETs, a driver, and a controller. Each MOSFET has a gate electrode to which the driver is connected. The controller is connected to the driver to provide it with an internal PWM signal. The multi-chip module enables a shorter feedback path to the controller and a reduction in power losses and noise.

[0012] The object underlying the invention is to provide an improved power converter and an improved power conversion method. This object is achieved, in each case, by a power converter according to claim 1 and 14 and by a method according to claim 13.

[0013] The details of one or more examples are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the disclosure are apparent from the description and the drawings, as well as from the claims. Fig. Figure 1 is a block diagram illustrating an example system for converting power from a power source according to one or more aspects of the present disclosure. Fig. 2 is a block diagram that shows an example of a power converter of the in Fig. 1. Example system shown illustrates this. Fig. 3 is a block diagram that shows another example of a power converter of the type in Fig. 1. Example system shown illustrates this. Fig. Figure 4 is a flowchart illustrating example operations of an exemplary power converter according to one or more aspects of the present disclosure. The Fig. 5A and Fig. 5B are circuit diagrams showing the cross-sections of the Fig. The two exemplary power converters shown illustrate this.

[0014] In some applications, a switch-based power converter (hereinafter referred to as a "power converter" or simply a "converter") can receive input power and convert it (e.g., by stepping up or stepping down) into a power output with a voltage or current level that differs (e.g., by regulation) from the voltage or current level of the input power, for example, to supply the output power to a filter for powering a load (e.g., a device). For the purposes of this description, the term "step-up converter" refers to a power converter configured to receive an input power signal with a first voltage level and output a power signal with a second voltage level that is higher than the first voltage level. Furthermore, for the purposes of this description, the term "step-down converter" refers to a power converter configured to receive an input power signal with a first voltage level and output a power signal with a second voltage level that is higher than the first voltage level.: “step-down converter”) to a power converter designed to receive an input power signal with a first voltage level and to output a power signal with a second voltage level that is lower than the first voltage level.

[0015] In any case, a power converter can have one or more switches (e.g., MOS power switching transistor-based switches, gallium nitride (GaN)-based switches, or other types of switching devices) arranged in a power stage configuration (e.g., a single-phase or multi-phase half-bridge configuration, etc.) which the power converter controls according to one or more modulation techniques to change the current or voltage level of the power output. A single-phase half-bridge can have one high-side switch coupled to a low-side switch at a circuit node, while a multi-phase half-bridge can have multiple high-side switches coupled to multiple low-side switches at a circuit node.

[0016] A power converter can include one or more gate drivers and control logic to control the one or more switches of the power stage using modulation techniques (e.g., turning them on and off). Such modulation of the power stage switches can operate according to pulse density modulation (PDM), pulse width modulation (PWM), pulse frequency modulation (PFM), or any other suitable modulation technique. By controlling the switches of a power stage using modulation techniques, a power converter can regulate the current or voltage level of the power output by the power converter.

[0017] Some power converters may incorporate feedback circuitry and techniques for performing current and / or voltage measurements to obtain information about the current or voltage level of an output power. The power converter can use this information, along with feedback circuitry and techniques, to improve the accuracy of the output power. For example, the power converter may use the feedback information to maintain the voltage or current level of an output power within a specific tolerance or threshold range to meet the power requirements of a load. Some power converters may employ current measurement as an example of feedback circuitry and techniques to determine the real-time current level of the power delivered to a load.If the power converter detects that the current level does not meet the power requirements of the load, then the power converter can adjust or change how it controls the circuit breakers to adjust or change the current level of the output power until the current level of the output power is within the tolerance window and meets the current level associated with the power requirements of the load.

[0018] Some power converters have individual and discrete high-side and low-side power switches that are separate from the converter's driver / control logic and / or feedback control circuitry. A power converter using individual and discrete power switches may operate at a lower efficiency than some other types of power converters. For example, a system-in-package (SiP) power converter may have a higher efficiency than a power converter using individual and discrete power switches.

[0019] Instead of relying on individual and discrete power switches, a SiP power converter incorporates power switches, along with driver / control logic and feedback control circuitry, into a single integrated circuit (IC) or chip package. While integrated packaging can result in SiP power converters operating at higher efficiency than other types of power converters, it can also increase the complexity and / or cost associated with the design and manufacture of the power converter. As a result of this increased complexity and cost, a SiP power converter may be unsuitable (e.g., too complex and / or too expensive) for certain low-cost and less complex power converter applications.

[0020] Even if the components of the SiP are contained in a single package, the size of the SiP package can make the SiP power converter too large for some applications. For example, a SiP power converter might contain one or more chips (e.g., of the CMOS type) that include all the driver / control logic and feedback control circuitry of the power converter, as well as two or more other chips (e.g., of the FET type, SFET type, etc.), each containing one or more high-efficiency high-side and low-side power switches (e.g., FET, SFET, etc.). Therefore, a SiP power converter can have a minimum of three separate and individual chips within the single integrated circuit or chip package. The resulting size, complexity, and cost of designing and manufacturing a SiP power converter can be proportional to the number of chips contained within the SiP.By including three and often more than three individual chips within a single integrated circuit or chip package, the complexity, cost and / or size of the SiP converter may exceed the corresponding complexity, cost and / or size requirements of the application of the SiP power converter.

[0021] Although some SiP power converters may have an integrated feedback control circuit to perform on-chip current and / or voltage sensing, this integrated feedback control circuit can, in some cases, provide inaccurate information about the current or voltage level of a power output. The inaccuracy of integrated feedback control (e.g., measurement) circuits in a SiP power converter may be due to increased sensitivity of the circuit's measurement lines to operational noise (e.g., during a switching cycle when the SiP power converter's power switches transition between an on-state and an off-state).

[0022] For example, a SiP power converter can integrate the driver / control logic and the feedback control circuitry onto a single CMOS chip. The SiP power converter can further integrate the high-side power switches onto a first FET or SFET chip and the low-side power switches onto a second FET or SFET chip. By separating the feedback control circuitry from the power switches, the SiP power converter may require additional sensing leads (e.g., wires or traces) placed between the CMOS chip and one or both of the two FET or SFET chips to couple the feedback control (e.g., sensing) circuitry to the power switches.

[0023] Sense leads located outside the chip containing the feedback control circuitry, and positioned between two separate chips of an integrated circuit or chip package, can be susceptible to electromagnetic interference (EMI) or other types of electrical noise, especially when high-efficiency FET or SFET power switches are used and are required to cycle between an on and off state (e.g., turning on or off). Additionally, when specific types of sensing or feedback control techniques (e.g., current sensing with a current-sensing FET) are implemented on one side of a half-bridge (e.g., the low-side), a large charge pump (e.g., with high capacitance) may be required by the feedback control (e.g., sensing) circuitry to obtain accurate information related to the current level of a power output.

[0024] According to some examples, to minimize the effects that noise can have on the measurement circuitry of a power converter, a system-on-a-chip (SoC) power converter with monolithic integration can be used. The SoC power converter integrates the driver / control logic and feedback control circuitry of the power converter with the power converter's power switches on a single chip within the same chip or package.By integrating all the power switches, driver / control logic, and feedback control circuitry onto a single chip, the feedback control circuitry's measurement lines are also contained within the single chip and can be less susceptible to EMI or other electrical noise and obtain more accurate information about the current and / or voltage level of a power output than the measurement circuitry used by some other power converters.

[0025] Although a monolithic integrated SoC power converter may have improved sensing circuitry, it can still be less efficient than some other power converters because its power switches can dissipate more power during each switching cycle (e.g., each transition between operating in an on-state and an off-state) than the power lost by the power switches of some other power converters in a single switching cycle. For example, instead of using more efficient FET or SFET power-switching technology, an SoC power converter might use less efficient CMOS circuitry, which is integrated on the same chip (e.g., CMOS) along with the driver / control logic and current sensing.

[0026] The less efficient power switch technology of SoC power converters can lead to an R DS(ON)exhibiting higher resistance than the circuit breakers of other power converters. This is a result of a higher resistance. DS(ON) Can the power switches of a SoC power converter dissipate more power during each switching cycle than the power lost during each switching cycle of the power switch-power converters, the switches with the lower R DS(ON) (e.g., FET or SFET switches). Additionally, the CMOS switches of the SoC power converter can limit the current level of the SoC power output to less than five amperes.

[0027] In general, the circuits and techniques of this disclosure enable a system-in-package (SiP) power converter to output power at a current level that can not only reach or exceed five amperes, but also be maintained within a narrow (e.g., precise) current level tolerance window, all without increasing the package size, cost, and / or efficiency of the SiP power converter. A SiP power converter, whether a buck or boost converter, can incorporate one or more power switches, driver / control logic, and a feedback control circuit (e.g., a current sensing circuit) distributed across only two chips in the SiP power converter package. One chip is a CMOS chip, and the other is a FET or SFET chip. The one or more power switches of the SiP power converter contain a power stage (e.g., a half-bridge).Some of the one or more power switches (e.g., either the low-side or high-side switch of a power stage half-bridge) are located on the FET or SFET chip, while the remainder of the one or more power switches (e.g., the side of the power stage half-bridge not located on the FET or SFET chip) are located on the CMOS chip. The CMOS chip also contains all the driver / control logic and the feedback control circuitry (e.g., a current sensing circuit).

[0028] In this disclosure, the terms “CMOS” and “FET or SFET” are used to describe two different types or forms of semiconductor chips for use in implementing the circuits and techniques described herein. A CMOS chip referred to herein describes a semiconductor chip that primarily contains CMOS transistors, or that the semiconductor chip is primarily manufactured according to a CMOS fabrication process, or that the semiconductor chip contains substantially more CMOS transistors than transistors of any other type. A FET or SFET chip referred to herein describes a semiconductor chip that primarily contains FET or SFET transistors (e.g., instead of CMOS transistors, which are primarily found in a CMOS chip), or that the semiconductor chip is primarily manufactured by a FET or SFET-type fabrication process (e.g.,instead of using a CMOS manufacturing process that can be used to produce a CMOS chip), or that the semiconductor chip contains significantly more FET or SFET transistors than transistors of other types (e.g., of the CMOS type).

[0029] By integrating some of the one or more power switches onto the FET or SFET chip, at least a portion (e.g., the high-side) of the SiP power converter's power stage can utilize highly efficient FET or SFET power switches. Furthermore, the combined placement of the driver / control logic, current sensing circuitry, and the remainder (e.g., the low-side) of the one or more power switches on the CMOS chip allows the SiP power converter to be controlled using a high-precision current-sensing FET circuit, eliminating the need for a separate charge pump for the current-sensing FET. Additionally, by integrating the remainder of the one or more power switches, the current sensing circuitry, and the driver / control logic onto a single chip, electromagnetic interference (EMI) or other noise disturbances (e.g., interference) can be minimized.caused by the switching of the FET or SFET switches on the FET or SFET chip) at the measuring lines of the current measuring circuit can be reduced.

[0030] In this way, the SiP power converter can operate more efficiently by using high-efficiency FET or SFET power switches for at least some of its power switches, according to the following circuits and techniques, and it can output power at higher current levels than some SoC and other SiP power converters. Furthermore, by including the current-sensing circuitry on the same chip as the driver / control logic and the rest of the power switches, the SiP power converter can be controlled using high-precision (e.g., sensing FET) current-sensing technology, without requiring a charge pump, to provide a more accurate power output with a current level maintained within a narrow tolerance window.Additionally, because a charge pump is not required and therefore only two chips are used, the SiP power converter can fit into a smaller, less complex and cheaper package than some larger, more complex and more expensive SoC and SiP power converters.

[0031] Fig. Figure 1 is a block diagram illustrating a system 1 for converting power from a power source 2 according to one or more aspects of the present disclosure. Fig. Figure 1 shows a system with four separate and distinct components represented as power source 2, power converter 4, filter 6, and load 8; however, system 1 may have additional or fewer components. For example, power source 2, power converter 4, filter 6, and load 8 may be four individual components, or they may represent a combination of one or more components that provide the functionality of system 1 described herein.

[0032] System 1 contains a power source 2 that supplies electrical power to System 1. Various examples of power sources 2 exist, and they can include, but are not limited to, power grids, generators, transformers, batteries, solar panels, wind turbines, regenerative braking systems, hydroelectric or wind-powered generators, or any other type of device capable of supplying electrical power to System 1.

[0033] System 1 includes a power converter 4, which operates as a switch-based power converter that converts one form of electrical power provided by the power source 2 into another usable form of electrical power to supply power to a load 8. The power converter 4 can be a boost converter, which outputs electrical power at a voltage level higher than the voltage level of any input power received by the boost converter. An example of such a boost converter is a boost converter. Alternatively, the power converter 4 can be a buck converter, which is configured to output power at a voltage level lower than the voltage level of any input power received by the buck converter. An example of such a buck converter is a step-down converter.The term "buck converter" is used in some examples. According to other examples, the power converter 4 can be a step-up and step-down converter (e.g., a buck-boost converter) capable of outputting power at a voltage level higher or lower than the voltage level of the input power received by the step-up and step-down converter. Examples of a power converter 4 include battery chargers, microprocessor power supplies, and the like. Power converters 4 can operate as DC-to-DC, DC-to-AC, or AC-to-DC converters.

[0034] System 1 further includes a filter 6 and a load 8. After the power has passed through the filter 6, the load 8 receives the electrical power (e.g., voltage, current, etc.) converted by the power converter 4. In some examples, the load 8 uses the filtered electrical power from the power converter 4 and the filter 6 to perform a function. Numerous examples of a filter 6 exist, and they can include any suitable electronic filter for filtering power for the load. Examples of a filter 6 include, but are not limited to, passive or active electronic filters, analog or digital filters, high-pass, low-pass, band-pass, notch, or all-pass filters, resistor-capacitor filters, diode-capacitor filters, inductor-capacitor filters, resistor-inductor-capacitor filters, and the like.Likewise, various examples of load 8 exist, and they include, but are not limited to, computing equipment and related components such as microprocessors, electrical components, circuits, laptop computers, desktop computers, tablet computers, mobile phones, batteries, loudspeakers, lighting units, automotive / marine / space / railway related components, motors, transformers, or any type of electrical device and / or circuit that receives a voltage or current from a power converter.

[0035] Power source 2 can supply electrical power at a first voltage or current level via connection 10. Load 8 can receive electrical power at a second voltage or current level via connection 14, which has been converted by power converter 4 and filtered by filter 6. Connections 10, 12, and 14 represent any means capable of transmitting electrical power from one location to another. Examples of connections 10, 12, and 14 include, but are not limited to, physical and / or wireless electrical transmission means such as electrical wires, electrical conductors, conductive gas tubes, twisted-pair cables, and the like. Each of connections 10 and 12 enables electrical coupling between power source 2 and power converter 4, and between power converter 4 and filter 6, respectively.Connection 14 provides electrical coupling between filter 6 and load 8. Additionally, connection 14 constitutes a feedback loop or feedback circuit for transmitting information associated with the characteristics of the filtered output power from filter 6 to power converter 4.

[0036] In the example of system 1, electrical power supplied by power source 2 can be converted by converter 4 into power with a regulated voltage and / or current level that meets the power requirements of load 8. For example, power source 2 can output power with a first voltage level at terminal 10, and power converter 4 can receive this power. Power converter 4 can convert this power with the first voltage level into power with a second voltage level, as required by load 8. Power converter 4 can output this power with the second voltage level at terminal 12. Filter 6 can receive the power from converter 4 and output the filtered power with the second voltage level at terminal 14.

[0037] Load 8 can receive the filtered power, which has the second voltage level, at connection 14. Load 8 can use the filtered power, which has the second voltage level, to perform a function (e.g., supplying power to a microprocessor). The power converter 4 can contain information via connection 14 that is associated with the filtered power, which has the second voltage level. For example, a feedback control circuit (e.g.,Current measurement) of the power converter 4 detects the voltage or current level of the filtered output power at connection 14 and the driver control logic of the converter 4 can adjust the output power at connection 12 based on the detected voltage or current level to cause the filtered output power to assume a different voltage or current level that is within a voltage or current level tolerance window required by the load 8.

[0038] Fig. Figure 2 is a block diagram showing an example of a power converter 4 of the in Fig. System 1 is illustrated. For example, it shows Fig. 2 a more detailed exemplary view of a power converter 4 of system 1 of Fig. 1 and the electrical connections provided by connections 11, 12 and 14 with the power source 2, the filter 6 and the load 8.

[0039] The power converter 4 is shown as a switch-based SiP power converter comprising several electrical components and traces (e.g., connections or wires) that can be arranged together within a single integrated circuit or chip package. The various electrical components and traces of the power converter 4 are distributed across two separate chips of the converter 4, designated as chip 20 and chip 22. The power converter 4 can be a boost converter (e.g., a step-up converter), a buck converter (e.g., a step-down converter), or a step-up / step-down converter (e.g., a step-down boost converter).

[0040] In Fig. Figure 2 shows an elliptical dashed line to illustrate the various components of a power stage 34 of the power converter 4, including one or more switches 30 of the chip 22, which are coupled at a circuit node 18 to one or more switches 32 of the chip 22. The switches 30 can be high-side or low-side switches of a half-bridge of the power stage 34, a full-bridge of the power stage 34, or any other type of power stage configuration for outputting power from a switch-based power converter. If switches 30 are high-side switches of power level 34, then switches 32 are low-side switches of power level 34. Conversely, if switches 30 are low-side switches of power level 34, then switches 32 are high-side switches of power level 34.

[0041] In the example according to Fig. Chip 20 contains a controller unit 24, a driver 40, and a driver 42, which represent the driver / control logic and the feedback control circuit of the power converter 4. Chip 20 also contains one or more switches 32, which represent one half (e.g., the low-side or the high-side) of the power stage 34 of the converter 4. Chip 22 of the converter 4 does not contain any of the driver / control logic or the feedback control circuit of the power converter 4. Chip 22 contains one or more switches 30, which represent the other half (e.g., the high-side or the low-side) of the power stage 34 of the converter 4, which is not contained in Chip 20.

[0042] According to some examples, chip 20 and chip 22 may have additional or fewer components than those in Fig. 2 components shown. For example, chip 22 may contain an overcurrent protection circuit that requires placement on a FET or SFET chip (e.g., chip 22) and may not be compatible with placement on a CMOS chip (e.g., chip 20). In other words, FET or SFET devices that require placement on a FET or SFET chip can be arranged together with the switches 32 on chip 22.

[0043] Chip 22 can be a FET or SFET chip, and the various components contained within chip 22 can be FET or SFET components. For example, switches 30 can be one or more FET or SFET switches. Chip 22 contains various other components in Fig. 2 electrical FET or SFET devices not shown. As FET or SFET switches, the switches 30 can be high-efficiency switching elements that perform either the high-side or low-side switching operations of the converter 4. For example, the switches 30 can be a single GaN-based switch arranged with switches 32 and a circuit node 18 in a single-phase half-bridge configuration of the power stage 34. The switches 30 can also be multiple GaN-based switches arranged with switches 32 and a circuit node 18 in a multi-phase half-bridge configuration of the power stage 34. In each case, the switches 30 have a lower R DS(ON)They are more efficient than some other types of switches and therefore dissipate less energy during a switching cycle (e.g., during the transition from operation in an off state to an on state) than other, less efficient switch types.

[0044] Chip 20 can be a CMOS chip, and the various electrical CMOS components contained within it can be called chips. For example, chip 20 contains a controller unit 24, drivers 40 and 42, and one or more switches 32. The controller unit 24 contains a modulation unit 28 (e.g., a driver / control logic block) and a feedback control unit 26 (e.g., a feedback control circuit). The switches 32 of chip 20 can perform switching operations of converter 4 that are not performed by the switches 30 of chip 22. In other words, in cases where the switches 30 of chip 22 perform low-side switching operations for power stage 34, the switches 32 of chip 20 can perform high-side switching operations for power stage 34.Conversely, the switches 32 of the chip can perform 20 low-side switching operations for the power stage 34 if the switches 30 of the chip perform 22 high-side switching operations.

[0045] The switches 32 of chip 20 can be single or multiple CMOS switching devices for performing the switching operations of the power stage 34 that are not performed by the switches 30 of chip 20. As CMOS switching devices, the switches 32 of chip 20 may operate less efficiently than other types of switches. For example, the switches 32 may have a higher R DS(ON) exhibit more energy than some other types of switches (e.g., the switches 30 of the FET or SFET chip 22) and, as a result, dissipate more energy during a switching cycle (e.g., during the transition from operation in an off state to an on state) than other, more efficient switch types.

[0046] The power converter 4 has three terminals for connecting it to external devices using connections 10, 12, and 14. The power converter 4 includes input / output terminals 50 and 52, as well as a feedback terminal 54. The feedback terminal 54 can be connected to terminal 14 according to... Fig. 1 must be coupled to supply the load 8 via connection 14 with feedback information that indicates a voltage or current level of the filtered power output from the filter.

[0047] Depending on the specific configuration of the converter 4, the input / output terminal 52 couples the circuit node 18 to either terminal 10 or terminal 12. For example, if the power converter 4 operates as a buck converter, the input / output terminal 52 acts as an output and couples the circuit node 18 to terminal 12. Conversely, if the power converter 4 operates as a boost converter, the input / output terminal 52 acts as an input and couples the circuit node 18 to terminal 10. If the power converter 4 operates as both a boost and buck converter, it includes additional switching logic (not shown) to cause the input / output terminals 50 and 52 to operate as either inputs or outputs.Depending on the specific configuration of the converter 4, the input / output port 50 additionally couples the switches 30 via a connection 56A either to the connection 10 or the connection 12, or the input / output port 52 couples the switches 32 via a connection 56B either to the connection 10 or the connection 12.

[0048] For example, switches 30 are high-side switches of a half-bridge of power stage 4, and switches 32 are low-side switches of a half-bridge of power stage 34. When power converter 4 operates as a buck converter, input / output terminal 50 acts as an input and couples connection 10 to high-side switches 30 via connection 56A. Conversely, when power converter 4 operates as a boost converter, input / output terminal 50 acts as an output and couples connection 12 to high-side switches 30 via connection 56A.

[0049] In an alternative example, switches 32 are high-side switches of a half-bridge of power stage 34, and switches 30 are low-side switches of a half-bridge of power stage 34. When power converter 4 operates as a buck converter, input / output terminal 50 acts as an input and couples connection 10 to high-side switches 32 via connection 56B. Conversely, when power converter 4 operates as a boost converter, input / output terminal 50 acts as an output and couples connection 12 to high-side switches 32 via connection 56B.

[0050] In each example, when operating as a buck converter, the power converter 4 can receive power from source 2 at input / output terminal 50 via connection 10. The power converter 4 can control switches 30 and 32 according to modulation techniques to convert the input power into an output power with a lower voltage level than the input power. The power converter 4 can output the power at input / output terminal 52 via connection 12 to filter 6. Conversely, when operating as a boost converter, the power converter 4 can receive input power from source 2 at input / output terminal 52 via connection 10. The power converter 4 can control switches 30 and 32 according to modulation techniques to convert the input power into an output power with a higher voltage level than the input power.The power converter 4 can output the power at input / output terminal 50 to filter 6 via connection 12. In each example where the power converter 4 operates as a boost and buck converter, the power converter 4 includes additional switching logic (not shown) to cause input / output terminals 50 and 52 to operate as either input or output terminals.

[0051] Connections 16A-16E (collectively “connections 16”) represent various “internal” conductor tracks and / or vias of the chip 20 that electrically couple and connect the components 24, 26, 28, 40, 42 and 32 contained in the chip 20. For example, connection 16A provides a path for the transmission of electrical information between the feedback control unit 26 and the modulation unit 28. Connection 16B represents a measuring line between switches 32 and (e.g., a current-sensing FET current-sensing circuit) the feedback control unit 26. Connections 16C and 16D are driver control lines for transmitting driver control signals (e.g., based on a pulse density modulation (PDM) signal, a pulse width modulation (PWM) signal, a pulse frequency modulation (PFM) signal, or any other suitable modulation technique) from the controller unit 24 to the drivers 40 and 42.Connection 16E represents a switch control line for transmitting switch control signals from the driver 42 to one or more switches 32.

[0052] Connections 17A-17D (collectively “connections 17”) represent “external” traces and / or vias that electrically couple or connect components of one chip 20 or 22 to the feedback terminal 54, the circuit node 18, and / or the internal components of the other chip 20 or 22. For example, connection 17A couples the feedback terminal 54 to the feedback control unit 26 of the controller unit 24 of chip 20 to transmit information related to the characteristics of a filtered output power provided by the filter 6 at connection 14. Connection 17B represents a switch control line for transmitting a switch control signal from the driver 40 of chip 20 to one or more switches 30 of chip 20.Connections 17C and 17D couple one or more switches 32 of chip 22 to one or more switches 30 of chip 20 at circuit node 18 and input / output terminal 52.

[0053] Many examples of one or more switches exist, and they could be any type of switching device that can be contained in a CMOS chip and which, when arranged in a power stage configuration, are suitable for stepping down / dampening or stepping up / boosting the voltage level of a power input. For example, some examples of one or more switches might include silicon (Si), gallium nitride (GaN), and / or silicon carbide (SiC)-based switching devices, self-conducting or self-blocking type switches, GaN high-electron-mobility transistors (HEMTs), n-MOSFET-based switching devices, p-MOSFET-based switching devices, diodes, IGBT switching devices, drain-extended (i.e., 10-phase) transistors, and other types of switching devices.: “drain extended”) MOS switching devices (deMOS) or any other type of power switching transistors or switching devices that can operate in a power stage arrangement on a CMOS chip.

[0054] Likewise, many examples of one or more switches exist, and they could be any type of switching device that can be contained in a FET or SFET chip and which, when arranged in a power stage configuration, are suitable for stepping down / dark-shifting or stepping up / boosting a voltage level of an input power. For example, some examples of one or more switches could be Si, GaN, and / or silicon carbide-SiC-based switching devices, self-conducting or self-blocking switching devices, HEMT (GaN), diodes, JFETs (SiC self-conducting or self-blocking), vertical or lateral switching devices, metal-gate switching devices, poly-Si-gate switching devices, or any other type of power switching transistor or switching device that can operate in a FET or SFET chip in a power stage configuration.

[0055] Driver(s) 40 and driver(s) 42 represent one or more individual gate drivers for controlling each of one or more individual switches 30 and (or) 32. For the sake of simplicity, Fig. 2 is explained as if each of the drivers 40 and 42 is a single driver for controlling each of the one or more individual switches 30 and 32. However, according to some examples, the driver(s) 40 and 42 each represent an array of multiple drivers, with each driver of the array of driver 40 being used to control one of each of the one or more switches 30, and with each driver of the array of driver 42 being used to control one of each of the one or more switches 32.

[0056] Driver 40 is coupled to one or more switches 30 via a connection 17B such that an output signal generated by driver 40 can cause one or more switches 30 to switch between an on state and an off state (e.g., turning on or off). Driver 42 is coupled to one or more switches 32 via a connection 16E such that an output signal generated by driver 42 can cause one or more switches 32 to switch between an on state and an off state. Drivers 40 and 42 each receive control signals from the modulation unit 28 of the controller unit 24 via connections 16C and 16D, respectively.An output of driver 40 can be based on a driver control signal received via connection 16C, and an output of driver 42 can be based on a driver control signal received via connection 16D.

[0057] The controller unit 24 of chip 20 represents a combination of driver / control logic and feedback control circuitry of the converter 4 for implementing modulation and feedback techniques to control drivers 40 and 42, causing switches 30 and 32 to modulate the output power at junction 12. The controller unit 24 may include any suitable arrangement of hardware, software, firmware, or any combination thereof to execute any of the techniques attributed herein to the controller unit 24. For example, the controller unit 24 may include a digital circuit, an analog circuit, or any combination thereof to control and regulate a switching converter.The controller unit 24 can contain any or more microprocessors, signal processors, application-specific integrated circuits (ASICs), user-programmable gate arrays (FPGAs), comparators, operational amplifiers, fully and / or semi-custom digital logic, registers for storing control data (e.g. parameters), analog and / or digital filter stages, non-linear control blocks or any other equivalent integrated digital or analog circuit, as well as any combination of such components.

[0058] If the controller unit 24 contains software or firmware, the controller unit 24 also contains hardware for storing and executing the software or firmware, such as one or more digital or analog processors or computing units. In general, a computing unit can contain one or more microprocessors, signal processors, ASICs, FPGAs, comparators, operational amplifiers, or any other equivalent integrated digital or analog circuit, as well as any combination of such components. Even if this is in Fig. Not shown in Figure 2, the controller unit 24 may contain memory configured to store data. The memory may be of any volatile or non-volatile medium, such as random-access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically erasable programmable ROM (EEPROM), flash memory, and the like. According to some examples, the memory may be located outside the controller unit 24 and / or the power converter; for example, it may be located outside the housing in which the controller unit 24 and / or the power converter 4 are enclosed.

[0059] The controller unit 24 can rely on the feedback control unit 26 to detect the voltage or current level of an output power at junction 24 and to detect or "measure" the magnitude of the current at the power stage 34. For example, the feedback control unit 26 can include a measuring FET current sensing circuit, a voltage sensing circuit, or other types of current or voltage sensing circuits to measure a current or voltage level across junction 16B through switches 32 and the power stage 34. Because junction 16B is internally contained within chip 20, the feedback control unit 26 can perform a highly accurate measurement of the current at the power stage 34. In other words, because the feedback control unit 26 does not rely on "external" measuring lines running between two or more separate chips of the converter 4, the measuring lines of the feedback control unit 26 (e.g.Connection 16B is less susceptible to EMI or other noise interference. As a result, the state of the information received by the feedback control unit 26 from the switches 32 via connection 16B arrives intact and unchanged compared to the state of the information when it is first transmitted.

[0060] By integrating the feedback control unit 26 and the switches 32 within the same CMOS chip 20, the measurement circuit of the feedback control unit 26 can perform current and / or voltage measurements without requiring a high-capacity (e.g., large) charge pump, which is necessary in some other measurement circuits and techniques. In other words, the feedback control unit 26 can perform a current measurement, specifically a measurement FET current measurement, at the CMOS-type switches 32 to determine the current level at the power stage 34 without using a high-capacity charge pump, which may be required in other SoC or SiP power converters.

[0061] The controller unit 24 can rely on the modulation unit 28 to generate driver control signals (e.g., based on a pulse density modulation (PDM) signal, a pulse width modulation (PWM) signal, a pulse frequency modulation (PFM) signal, or another suitable modulation technique) to control the turn-on and / or turn-off signals of switches 30 and 32 of the power stage 34, in order to cause the converter 4 to provide output power at connection 12. For example, the modulation unit 28 can receive information from the feedback control unit 26 that adjusts a voltage or current level of an output power, and the modulation unit 28 can, based on the adjustment information, modify the properties or characteristics of the driver control signals that the modulation unit 28 outputs to the drivers 40 and 42.

[0062] The modulation unit 28 can provide PWM-based driver control signals via connections 16C and 16D, which cause the drivers 40 and 42 to switch the switches 30 and 32 of the power stage 34 between an on-state and an off-state. In response to the voltage or current level of an output power detected by the feedback control unit 26 at connection 14, and further in response to the current level detected by the feedback control unit 26 at the power stage 34, the modulation unit 28 can change the duty cycle of the PWM-based driver signal.For example, the modulation unit 28 and the feedback control unit 26 can use current and / or voltage level thresholds to determine an adjustment of the duty cycle of the PWM-based driver signal that controls the switches 30 and 32 in order to modulate a specific output power at junction 12 within a specific current or voltage level tolerance window. By changing the duty cycle of the PWM-based driver signal based on information detected by the feedback control unit 26, the modulation unit 28 can change the voltage or current level of the output power provided by the converter 4 at junction 12.

[0063] The modulation unit 28 can provide PDM-based driver control signals via connections 16C and 16D, which cause the drivers 40 and 42 to switch the switches 30 and 32 of the power stage 34 between an on-state and an off-state operation. In response to the voltage or current level of an output power detected by the feedback control unit 26 at connection 14, and further in response to the current level detected by the feedback control unit 26 at the power stage 34, the modulation unit 28 can modify the average value of the PDM-based driver signal.For example, the modulation unit 28 and the feedback control unit 26 can use current and / or voltage level thresholds to determine an adjustment of the duty cycle of the PDM-based driver signal that controls switches 30 and 32 to modulate a specific output power at junction 12 within a specific current or voltage level tolerance window. By changing the average value of the PDM-based driver signal based on information detected by the feedback control unit 26, the modulation unit 28 can modify the voltage or current level of the output power provided by the converter 4 at junction 12.

[0064] By integrating the switches 30 into the chip 22, at least a portion (e.g., the high-side or low-side) of the power stage 34 can operate using highly efficient FET or SFET power switches without interfering with the current or voltage measurement performed by the feedback control unit 26 of the controller unit 24 of the chip 20. Furthermore, by integrating the controller unit 24, the drivers 40 and 42, and the switches 32 together within the chip 20, the controller unit 24 can control the switches 30 and 32 using information obtained from the high-precision current-sensing FET circuit of the feedback control unit 26, without requiring an additional charge pump for the current-sensing FET circuit of the feedback control unit 26.Furthermore, the arrangement of the switches 32 together with the feedback control unit 26, the modulation unit 28 and the drivers 40 and 42 on a single chip 20 can minimize the amount of EMI and other noise disturbances caused during the switching of the switches 30 of the chip 22 on the measuring lines (e.g. the connection 16B) of the current measuring circuit of the feedback control unit 26.

[0065] By using high-efficiency FET or SFET power switches for at least some of the power switches in a power stage (e.g., including a single-phase half-bridge, a multi-phase half-bridge, etc.), the power converter can operate more efficiently according to these circuits and techniques and can output power at higher current levels than some SoC and other SiP power converters. Furthermore, by integrating the current feedback control circuitry with the driver / control logic and the rest of the power stage's power switches onto the same chip, the power converter can be controlled using more accurate (e.g., sensing FET) current sensing technology without the need for a charge pump to provide more accurate output power with a current level within a narrow tolerance window.Additionally, because a charge pump is not required and only two chips are used, the power converter according to these circuits and techniques can fit into a smaller, less complex, and cheaper package than some larger, more complex, and more expensive SoC and SiP power converters.

[0066] In some examples, the control unit 24 does not include a feedback control unit 26 and therefore does not perform any voltage or current measurement at the switches 32. Additionally, without a feedback control unit 26, the controller unit 24 does not control the switches 30 and 32 based on the voltage or current detected by the feedback control unit 26. In some examples, the switches 30 can be a diode; for instance, if the converter 4 operates as a boost converter and the switches 30 of the power stage 34 represent the high-side switches of the converter 4, the switches 30 can be a single diode or multiple diodes.

[0067] Fig. Figure 3 is a block diagram showing another example of the power converter 4 of the in Fig. 1 system shown illustrates. Fig. 3 is subsequently referred to in the context of the power converter 4 according to Fig. 2 and of system 1 according to Fig. 1 described.

[0068] Converter 4 is described in the context of being configured as a multiphase half-bridge-based buck or boost converter. Converter 4 according to Fig. 3 contains a feedback connection 54 to couple the converter 4 with connection 14, as well as input / output connections 50 and 52 to couple the converter 4 with connections 10 and 12.

[0069] Converter 4 contains a CMOS chip 20 and a FET or SFET chip 22. Chip 22 contains high-side SFET switches 90A and 90B. Chip 20 contains a controller unit 24, a feedback control unit 26, and a modulation unit 28. Additionally, chip 20 contains high-side drivers 80A and 80B for controlling the high-side SFET switches 90A and 90B of chip 20, as well as drivers 82A and 82B for controlling the low-side CMOS switches 92A and 92B contained in chip 20.

[0070] The high-side SFET switch 90A is coupled to the low-side CMOS switch 92A at circuit node 94A. The high-side SFET switch 90B is coupled to the low-side CMOS switch 92B at circuit node 94B. A filter 96A is arranged between circuit node 94A and input / output terminal 52, and a filter 96B is arranged between circuit node 94B and input / output terminal 52. In some examples, filters 96A and 96B can be inductor-capacitor (LC)-based filters. In other examples, filters 96A and 96B can be located outside the enclosure of converter 4, for example, as part of filter 6. Fig. 1. According to some examples, filters 96A and 96B can be arranged together inside chip 20 or chip 22.

[0071] The current-sensing FET circuit of the feedback control unit 26 can receive information related to a current level detected at the low-side CMOS switches 92A and 92B via measuring lines 98A and 98B contained within the chip 20. By enclosing the measuring lines 98A and 98B inside the chip 20, the information transmitted via these lines is less susceptible to EMI or other noise generated during the switching operations of the high-side SFET switches 90A and 90B. Additionally, the measuring FET current measuring circuit of the feedback control unit 26 can perform a current measurement by integrating the low-side CMOS switches 92A and 92B together with the feedback control unit 26 in the chip 20, without requiring a large (e.g., high-capacitance) charge pump.The converter 4 can gain the advantage of operating more economically by using high-side SFET switches 90A and 90B in the chip 20, while also employing highly accurate current sensing techniques to output power at the junction 12 that has a current level within a narrow current level tolerance window required by the load 8.

[0072] In the example according to Fig. The high-side switches 90A and 90B are housed in the SFET chip 22. The example according to Fig. Figure 3 further illustrates an optional current sensing circuit (indicated by the three lines arranged between the CMOS chip 20 and the SFET chip 22). The low-side switches 92A and 92B, together with the feedback control unit 26, which performs current sensing using sensing MOSFETs on the CMOS chip 20, are integrated into the CMOS chip 20.

[0073] Fig. Figure 4 is a flowchart illustrating various operations of an example power converter according to one or more aspects of the present disclosure. Fig. 5 is subsequently referred to in the context of the power converter 4 according to Fig. 2 and of system 1 according to Fig. 1 described.

[0074] The power converter 4 can detect a current level at one or more switches 32 of a half-bridge of a power stage located at the chip 20. For example, the feedback control unit 26 of the controller unit 24, located at the chip 20 of the power converter 4, can detect a current level at the switches 32. The current level can be received by the feedback control unit 26 via a connection 16B (e.g., one or more sensing lines connecting the switches 32 to the sensing FET current sensing circuit of the feedback control unit 26). In some examples, the current level detected at the one or more switches 32 is detected based on a sensing FET current sensing signal received by the feedback control unit 26 via one or more current sensing lines contained in the chip 20.The one or more current measuring lines can be arranged between the feedback control unit 26 at the chip 20 and the one or more switches 32 at the chip 20.

[0075] The power converter 4 can, from chip 20, control one or more switches 30 of the half-bridge of the power stage 34, located on chip 22 of the power converter 4, at least partially based on the current level detected at the switches 32 on chip 20. For example, the feedback control unit 26 can send information to the modulation unit 28 indicating the current level detected at the power stage 34 by the current-sensing FET circuit of the feedback control unit 26. Additionally, the modulation unit 28 can receive information indicating the current or voltage level of a filtered output power transmitted at connection 24. Based on the information received by the feedback control unit 26, the modulation unit 28 can generate a driver control signal (e.g.,(a PWM-based signal, a PDM-based signal, or a signal based on any other modulation technique) to cause the driver 40 to control the switches 30 on the chip 22. The modulation unit 28 can output the driver control signal to the driver 40. The driver control signal can cause the driver 40 to issue a command, which travels from the chip 20 via connection 17B to the chip 22, to toggle the switches 30 between an on-state and an off-state.

[0076] From chip 20, the power converter 4 can control one or more switches 32 of the power stage 34 located on chip 20 of the power converter 4, at least partially, based on the current level detected at the switches 32 on chip 20. For example, the modulation unit 28 can generate a driver control signal (e.g., a PWM-based signal, a PDM-based signal, or a signal based on any other modulation technique) based on information received from the feedback control unit 26 to cause the driver 42 to control the switches 32 on chip 20. The modulation unit 28 can output the driver control signal to the driver 42. The driver control signal can cause the driver 42 to issue a command that (e.g.,The connection 16E (located in the chip 20) causes the switches 32 to transition between an on-state operation and an off-state operation.

[0077] The Fig. 5A and Fig. 5B are circuit diagrams, the sectional views of the power converter 4 according to Fig. 2. Illustrate. For example, shows Fig. 5A a "face down" SiP configuration of the power converter according to Fig. 2 including cross-sectional views of chips 20 and 22. Fig. Figure 5B shows a "face up" SiP configuration of the power converter 4 according to Fig. 2 including cross-sectional views of chips 20 and 22.

[0078] The power converter 4, by using only two chips, chip 20 and chip 22, can fit into a smaller SiP package than other SiP power converters. For example, other power converters might contain the high-side switches of a power stage on one chip, the low-side switches on another, and the driver / control logic and feedback control circuitry on one or more additional chips. In any case, some converters may require a minimum package size of approximately 49 square millimeters (i.e., seven millimeters by seven millimeters) to accommodate more than two chips.

[0079] Conversely, the components of converter 4, which uses only two chips, can fit into a smaller package size. According to some examples, converter 4 can fit into a package size smaller than 49 square millimeters and approximately 36 square millimeters (i.e., 6 millimeters by 6 millimeters). Due to its smaller package size compared to some other power converters, the manufacturing costs for converter 4 are also lower than for some other converters.A SiP power converter based on these techniques and circuits can not only fit into a smaller package size, which costs less to manufacture than some other converters, but the SiP power converter based on these circuits and techniques can also operate more efficiently and provide a better controlled and more accurate output power than some converters by using FET or SFET switching on one chip while simultaneously employing a highly accurate measuring FET current sensing on the other chip.

[0080] Clause 1. Power converter comprising: a first chip comprising one or more first switches coupled to a circuit node of a power stage; and a second chip comprising: one or more second switches coupled to a circuit node of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage to produce output power at the circuit node of the power stage.

[0081] Clause 2. Power converter according to Clause 1, wherein the first one or more switches comprise one or more high-side switches of a half-bridge of the power stage and the second one or more switches comprise one or more low-side switches of the half-bridge of the power stage.

[0082] Clause 3. Power converter according to one of Clauses 1-2, wherein the one or more second switches have one or more high-side switches of the half-bridge of the power stage and the one or more first switches have one or more low-side switches of the half-bridge of the power stage.

[0083] Clause 4. Power converter according to one of Clauses 1-3, wherein the second chip further comprises a feedback control unit configured to detect a current level at one or more second switches of the power stage, wherein the control unit further comprises controlling one or more first switches and one or more second switches of the power stage at least partially based on the current level detected by the feedback control unit.

[0084] Clause 5. Power converter according to Clause 4, wherein the feedback control unit is further configured to detect the current level at one or more second switches based on a measuring FET current sensing signal.

[0085] Clause 6. Power converter according to Clause 5, wherein the second chip further comprises: one or more measuring lines contained in the second chip which couple the feedback control unit to the one or more second switches of the power stage, wherein the one or more measuring lines are configured to transmit information associated with a current or voltage level of the power stage to the feedback control unit.

[0086] Clause 7. Power converter according to Clause 6, wherein one or more measuring lines are further configured to transmit a measuring FET current measuring signal associated with a current level of the power stage to the feedback control unit.

[0087] Clause 8. Power converter according to any of Clauses 4-7, wherein the feedback control unit is further configured to detect a voltage or current level of a power output of the power converter, and wherein the control unit is further configured to control the one or more first switches and the one or more second switches of the power stage at least partially based on the voltage or current level of the power output detected by the feedback control unit.

[0088] Clause 9. Power converter according to any of clauses 1-8, wherein the first chip is a FET or SFET chip.

[0089] Clause 10. Power converter according to one of clauses 1-9, wherein one or more of the first switches are SFET switches.

[0090] Clause 11. Power converter according to one of clauses 1-10, wherein the second chip is a CMOS chip.

[0091] Clause 12. Power converter according to one of clauses 1-11, wherein one or more of the second switches are CMOS switches.

[0092] Clause 13. Power converter according to any of Clauses 1-12, wherein the second chip further comprises at least one first driver configured to control the one or more first switches and at least one second driver configured to control the one or more second switches.

[0093] Clause 14. Power converter according to any of Clauses 1-13, wherein the power converter includes a step-down converter, wherein the power output has a first voltage level that does not exceed a second voltage level of a power input received at the half-bridge.

[0094] Clause 15. Power converter according to any of Clauses 1-14, wherein the power converter includes a boost converter, wherein the power output has a first voltage level equal to or exceeding a second voltage level of a power input received at the half-bridge.

[0095] Clause 16. Power converter according to any of Clauses 1-15, wherein the control unit is further configured to output at least one of a pulse density modulation signal, a pulse width modulation signal and a pulse frequency modulation signal in order to control one or more first switches and one or more second switches of the power stage.

[0096] Clause 17. Power converter according to any of Clauses 1-16, wherein the power stage comprises a single-phase half-bridge, wherein the first one or more switches comprise a single high-side switch of the single-phase half-bridge and wherein the second one or more switches comprise a single low-side switch of the single-phase half-bridge.

[0097] Clause 18. Power converter according to any of Clauses 1-17, wherein the power stage comprises a multi-phase half-bridge, wherein the first one or more switches comprise two or more high-side switches of the multi-phase half-bridge and wherein the second one or more switches comprise two or more low-side switches of the multi-phase half-bridge.

[0098] Clause 19. Method comprising: detecting, by means of a feedback control unit at a second chip of a power converter, a current level at one or more second switches at the second chip of the power converter, wherein the one or more second switches at a circuit node of a power stage are coupled to one or more first switches at a first chip of the power converter; controlling the one or more first switches of the power stage at the first chip by means of a controller unit at least partially based on a driver signal, wherein the driver signal is based at least partially on the current level detected at the one or more second switches; and controlling the one or more second switches of the power stage at the second chip by means of the control unit at the second chip by means of the controller unit at least partially based on the driver signal.

[0099] Clause 20. Power converter comprising: means for detecting a current level at one or more second switches at a second chip of a power converter, wherein the one or more second switches at a circuit node of the power stage are coupled to one or more first switches at a first chip of the power converter; means for controlling the one or more first switches of the power stage at the first chip from the second chip at least partially based on a driver signal, wherein the driver signal is based at least partially on the current level detected at the one or more second switches; and means for controlling the one or more second switches of the power stage at the second chip from the second chip at least partially based on the driver signal.

[0100] The techniques of this disclosure can be implemented in a wide variety of components or devices, including an integrated circuit (IC) or a set of ICs (e.g., a chipset). This disclosure describes various components, modules, or units to highlight the functional aspects of components designed to perform the disclosed techniques; however, they need not necessarily be implemented by different hardware units. Rather, as described above, different units can be combined in a single hardware unit or provided by an assemblage of interoperable hardware units, including one or more microprocessors as described above, in conjunction with suitable software and / or firmware.

Claims

[1] Power converter which features: a FET or SFET chip (22) comprising at least one FET or SFET switch (30) coupled to a circuit node (18) of a power stage (34); and a CMOS chip (20) which features: at least one CMOS switch (32) coupled to the circuit node (18) of the power stage (34), at least one measuring line (16B) configured to transmit a current measurement signal containing information about a current level of a current through the at least one CMOS switch (32), and a controller unit (24) configured to control the at least one FET or SFET switch (30) and the at least one CMOS switch (32) of the power stage (34) at least partially based on the current measurement signal transmitted by the at least one measuring line (16B) in order to generate an output power at the circuit node (18) of the power stage (34). [2] Power converter according to claim 1, wherein the at least one FET or SFET switch (30) has at least one high-side switch of a half-bridge of the power stage (34) and the at least one CMOS switch (32) has at least one low-side switch of the half-bridge of the power stage (34). [3] Power converter according to claim 1 or 2, wherein the at least one CMOS switch (32) has at least one high-side switch of the half-bridge of the power stage (34) and the at least one FET or SFET switch has at least one low-side switch of the half-bridge of the power stage (34). [4] Power converter according to any of the preceding claims, wherein the CMOS chip (20) further comprises a feedback control unit (26) configured to detect the current level at the at least one CMOS switch (32) of the power stage, wherein the controller unit (24) is further configured to control the at least one FET or SFET switch (30) and the at least one CMOS switch (32) of the power stage (34) at least partially based on the current level detected by the feedback control unit (26). [5] Power converter according to claim 4, wherein the feedback control unit (26) is further configured to detect the current level at the at least one CMOS switch (32) based on a measuring FET current sensing signal. [6] Power converter according to claim 5, wherein the at least one measuring line couples the feedback control unit (26) with the at least one CMOS switch (32) of the power stage (34). [7] Power converter according to one of the preceding claims, wherein the CMOS chip (20) further comprises at least one first driver (40) configured to control the at least one FET or SFET switch (30) and at least one second driver (42) configured to control the at least one CMOS switch (32). [8] Power converter according to any one of claims 1 to 7, wherein the power converter comprises a step-down converter, wherein the power output has a first voltage level which does not exceed a second voltage level of a power input received at the half-bridge. [9] Power converter according to any one of claims 1 to 7, wherein the power converter comprises a boost converter, wherein the power output has a first voltage level which corresponds to or exceeds a second voltage level of a power input received at the half-bridge. [10] Power converter according to one of the preceding claims, wherein the controller unit (24) is further configured to output at least one of a pulse density modulation signal, a pulse width modulation signal and a pulse frequency modulation signal in order to control the at least one FET or SFET switch (30) and the at least one CMOS switch (32) of the power stage (34). [11] Power converter according to any one of claims 1 to 10, wherein the power stage (34) has a single-phase half-bridge, wherein at least one FET or SFET switch (30) comprises a single high-side switch of the single-phase half-bridge and wherein at least one CMOS switch (32) has a single low-side switch of the single-phase half-bridge. [12] Power converter according to any one of claims 1 to 10, wherein the power stage (34) comprises a multiphase half-bridge, wherein the at least one FET or SFET switch (30) comprises two or more high-side switches of the multiphase half-bridge and wherein at least one CMOS switch (32) has two or more low-side switches of the multiphase half-bridge. [13] Method which features: Detect, by means of a feedback control unit (26) in a CMOS chip (20) of a power converter, a current level of a current through at least one CMOS switch (32) in the CMOS chip (20) based on a current measurement signal transmitted through at least one measuring line (16B) in the CMOS chip (20) and which contains information about a current level of a current through the at least one CMOS switch (32), wherein the at least one CMOS switch (32) is coupled at a circuit node (18) of a power stage (34) of the power converter to at least one FET or SFET switch (30) in a FET or SFET chip (22) of the power converter; Control of the at least one FET or SFET switch (30) of the power stage (34) in the FET or SFET chip (22) by a controller unit (24) at least partially based on a driver signal, wherein the driver signal is at least partially based on the current level detected at the at least one CMOS switch (32); and Control of at least one CMOS switch (32) of the power stage (34) in the CMOS chip (20) by the controller unit (24) in the CMOS chip (20) at least partially based on the driver signal. [14] Power converter which features: Means for detecting a current level of a current through at least one CMOS switch (32) in a CMOS chip (20) of a power converter based on a current measurement signal transmitted through at least one measuring line (16B) in the CMOS chip (20) and containing information about a current level of a current through the at least one CMOS switch (32), wherein the at least one CMOS switch (32) is coupled at a circuit node (18) of a power stage (34) to at least one FET or SFET switch (30) in a FET or SFET chip (22) of the power converter; Means for controlling the at least one FET or SFET switch (30) of the power stage (34) in the FET or SFET chip by the CMOS chip (20) at least partially based on a driver signal, wherein the driver signal is at least partially based on the current level detected at the at least one CMOS switch (32); and Means for controlling at least one CMOS switch (32) of the power stage (34) by the CMOS chip (20) at least partially based on the driver signal.

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