Semiconductor drive device and semiconductor device

Abstract

Semiconductor drive device (11) configured to drive a high-voltage side semiconductor switching element (1a) and a low-voltage side semiconductor switching element (1b) connected in series between a high potential and a low potential, the semiconductor drive device (11) comprising: a negative overvoltage detection circuit (32) that detects whether a negative overvoltage occurs at a junction (1c) between the high-voltage side semiconductor switching element (1a) and the low-voltage side semiconductor switching element (1b); and a level shifter circuit (31) that maintains a drive voltage used when driving the high-voltage side semiconductor switching element (1a) when the negative overvoltage detection circuit (32) detects the occurrence of the negative overvoltage;wherein the level-shifting circuit (31) is configured to maintain the drive voltage in response to a first potential at the junction point (1c), a predetermined second potential, the low potential, and a detection result of the circuit (32) for detecting a negative overvoltage by level-shifting a second signal (main signal) generated on the basis of the first potential, the second potential, and an input signal, wherein the circuit (32) for detecting a negative overvoltage comprises a first Zener diode (33c) and a second Zener diode (33d), and upon occurrence of the negative overvoltage, a potential between the first Zener diode (33c) and the second Zener diode (33d) is a predetermined potential.

Description

The present invention relates to a semiconductor control device capable of controlling a semiconductor switching element on the high-voltage side and a semiconductor switching element on the low-voltage side connected in series between a high potential and a low potential, and relates to a semiconductor device comprising the semiconductor control device. In semiconductor drive devices that control semiconductor switching elements such as inverters, a semiconductor switching element on the high-voltage side and a semiconductor switching element on the low-voltage side are repeatedly switched to turn them on and off. During the switching process, a negative overvoltage occurs, which causes a malfunction in the circuit. Various techniques have been developed to suppress the adverse effects of this negative overvoltage (for example, JP 2004-072942-A). Meanwhile, the level shifter circuit with the monostable drive circuit, the SR flip-flop latching circuit, the D flip-flop latching circuit, or the like were used in the semiconductor drive device, as described above. Recently, however, the always-on level shifter circuit with, for example, the D latching circuit has been developed for use instead of the circuits mentioned above. In the always-on level converter circuit that has been developed recently, a negative overvoltage can occur and have an adverse effect. US Patent 6,664,822 B2 describes a device with a level shifter, a masking circuit, and an RS flip-flop. The additional use of a dummy circuit removes unwanted noise superimposed on the level-shifted control signal at the output of the level shifter, thereby preventing malfunctions. US Patent 5,105,099 A describes how to avoid unwanted common-mode interference caused by current flows through stray capacitances and resistances when driving an inductive load. This is achieved by detecting similar signal values ​​at the control terminals of high- and low-side semiconductor switching elements. The patent also discloses the generation of a suppression signal to prevent a switching operation that would otherwise result from the detected common-mode interference. The present invention was carried out in view of the problems mentioned above, and one object of it is to create a technique that can suppress an adverse effect of a negative overvoltage in a level converter circuit with, for example, a D-locking circuit. According to the invention, this problem is solved by a semiconductor control device according to claim 1 and a semiconductor device according to claims 8 and 9. A semiconductor driver is configured to drive a high-voltage side semiconductor switching element and a low-voltage side semiconductor switching element connected in series between a high potential and a low potential. The semiconductor driver includes a negative overvoltage detection circuit that detects whether a negative overvoltage occurs at a junction between the high-voltage side semiconductor switching element and the low-voltage side semiconductor switching element, and a level shifter circuit that maintains a drive voltage used to drive the high-voltage side semiconductor switching element when the negative overvoltage detection circuit detects the occurrence of a negative overvoltage. The level shifter circuit is configured to maintain the drive voltage in response to a first potential at the junction point, a predetermined second potential (the low potential), and a detection result of the circuit for detecting a negative overvoltage by level shifting a second signal generated on the basis of the first potential, the second potential, and an input signal. Furthermore, the circuit for detecting a negative overvoltage includes a first Zener diode and a second Zener diode, and when the negative overvoltage occurs, a potential between the first Zener diode and the second Zener diode is a predetermined potential. A drive voltage used to drive a semiconductor switching element on the high-voltage side is maintained when a negative overvoltage detection circuit detects the occurrence of a negative overvoltage. Consequently, an adverse effect of the negative overvoltage in a level shifter circuit can be suppressed, for example, by a D-latching circuit. Advantageous further developments of the invention result from the dependent claims. Further features and advantages of the invention will become apparent from the description of embodiments of the invention with reference to the figures. Of the figures: Fig. 1 and Fig. 2 show circuit diagrams depicting a configuration of a related semiconductor device, which as such is not the subject of the invention; Fig. 3 shows a circuit diagram depicting an equivalent circuit of a D-latching circuit; Fig. 4 shows a timing diagram depicting an operation of the related semiconductor device; Fig. 5 shows a circuit diagram depicting a configuration of an HVIC driver according to a first preferred embodiment; Fig. 6 shows a circuit diagram depicting a configuration of a semiconductor device according to the first preferred embodiment; Fig. 7 shows a timing diagram depicting an operation of the semiconductor device according to the first preferred embodiment; Fig.Figure 8 shows a circuit diagram illustrating a configuration of an HVIC driver according to a second preferred embodiment; Figure 9 shows a circuit diagram illustrating a configuration of an HVIC driver according to a third preferred embodiment; Figure 10 shows a circuit diagram illustrating a configuration of an HVIC driver according to a fourth preferred embodiment; Figure 11 shows a circuit diagram illustrating a configuration of an HVIC driver according to a fifth preferred embodiment; Figure 12 shows a circuit diagram illustrating a configuration of an HVIC driver according to a sixth preferred embodiment; Figure 13 shows a circuit diagram illustrating a configuration of an HVIC driver according to a seventh preferred embodiment; Figure 14 shows a timing diagram illustrating an operation of a semiconductor device according to the seventh preferred embodiment; FigureFigure 15 shows a circuit diagram showing a configuration of an HVIC driver according to an eighth preferred embodiment; and Figure 16 shows a circuit diagram showing a configuration of a semiconductor device according to a ninth preferred embodiment. <Verwandte Halbleitervorrichtung> Before explaining a semiconductor control device and a semiconductor device with the semiconductor control device according to a first preferred embodiment of the present invention, a related semiconductor device (hereinafter referred to as "related semiconductor device") is described which as such is not the subject of the invention. Fig. 1 is a circuit diagram showing a configuration of the related semiconductor device that serves as an inverter control device. The related semiconductor device is configured to include a P-side switching element (P-side SW element) 1a connected to a high-potential P terminal, an N-side switching element (N-side SW element) 1b connected to a low-potential N terminal (ground potential), a P-side reverse-flow diode 2a, an N-side reverse-flow diode 2b, power supplies 51, 52, and 53, and an eight-terminal HVIC driver 11 (a VCC terminal, a HIN terminal, a LIN terminal, a GND terminal, a VB terminal, an HO terminal, a VS terminal, and an LO terminal). The P-side switching element 1a (high-voltage side semiconductor switching element) and the N-side switching element 1b (low-voltage side semiconductor switching element) form an inverter and are connected in series between the P and N terminals. A gate terminal of the P-side switching element 1a is connected to the HO terminal of the HVIC driver 11, and a gate terminal of the N-side switching element 1b is connected to the LO terminal of the HVIC driver 11. A junction 1c between the P-side switching element 1a and the N-side switching element 1b is connected to the VS terminal of the HVIC driver 11 and is also connected to a load (not shown) via an L terminal. Two ends of the P-side backflow diode 2a are connected to a source terminal and a drain terminal of the P-side SW element 1a, and two ends of the N-side backflow diode 2b are connected to a source terminal and a drain terminal of the N-side SW element 1b. A positive and a negative electrode of power supply 51 are connected to the P terminal and the N terminal, respectively. The positive and negative electrodes of power supply 52 are connected to the VCC terminal and the GND terminal of HVIC driver 11, respectively. The positive and negative electrodes of power supply 53 are connected to the VB terminal and the VS terminal of HVIC driver 11, respectively. In the related semiconductor device with the configuration described above, the HVIC driver 11 controls a gate voltage of the P-side SW element 1a and a gate voltage of the N-side SW element 1b based on an input signal applied to the HIN and LIN terminals, respectively, to turn the P-side SW element 1a and the N-side SW element 1b on and off. In other words, the HVIC driver 11, acting as a semiconductor driver, can control the P-side SW element 1a and the N-side SW element 1b. The load, which is not shown and is connected to junction 1c via the L terminal, typically has an inductance, such as a coil. Even when the HVIC driver 11's control circuit switches the P-side SW element 1a from on to off, a current consequently flows continuously from junction 1c through the L terminal to the load. The current, flowing, for example, through the N terminal at ground potential, the N-side return diode 2b, junction 1c, and the L terminal in that order, flows continuously. Consequently, a negative overvoltage occurs, where the potential at the VS terminal (connection point 1c) is lower than at the GND terminal (ground potential) by the amount of the value obtained as the product of a leakage inductance and dI / dt (hereinafter referred to in some cases as "negative VS overvoltage"). Moreover, the negative VS overvoltage can occur outside of the time when the P-side SW element 1a is switching from on to off. The occurrence of the negative VS overvoltage, as described above, is a known cause of malfunction in a circuit, and the negative VS overvoltage can even occur in a case where the HVIC driver 11 is equipped with a high-voltage level shifter circuit with a D-latching circuit 17, which has been developed recently. Fig. 2 is a circuit diagram showing an example of a configuration in which the HVIC driver 11 in Fig. 1 is provided with a level converter circuit 31 (always-on level converter circuit) with the D-locking circuit 17. An HVIC driver 11, as shown in Fig. 2, is configured to include always-on control circuits 12a and 12b, resistors 13a and 13b, high-voltage transistors 14a and 14b, diodes 15a and 15b, logic inversion elements 16a and 16b, the three-terminal D-latch circuit 17 (one D-terminal, one STB-terminal and one Q-terminal) and buffer circuits 18a and 18b. Among these, the always-on control circuit 12a, the resistors 13a and 13b, the high-voltage transistors 14a and 14b, the diodes 15a and 15b, the logic inversion elements 16a and 16b, the D-latching circuit 17, and the buffer circuit 18a form the level-shifting circuit 31, as mentioned above. The reason for this is omitted, but the level-shifting circuit 31 can suppress malfunctions of both high-latching and low-latching circuits and reduce the required circuit area, even when the pulse width is small and the voltage variation over time is large. Next, each structural component of the HVIC driver 11 will be described in detail. The HIN terminal, into which an input signal is primarily used to control the P-side SW element 1a, is connected to one end of the always-on control circuit 12a. Resistor 13a and high-voltage transistor 14a are connected in series between the VB terminal and the GND terminal, and one gate terminal of high-voltage transistor 14a is connected to the other end of the always-on control circuit 12a. Resistor 13a and high-voltage transistor 14a are connected to junction 61a, and junction 61a is connected to the VS terminal via diode 15a. Furthermore, junction 61a is connected to the D terminal of the D-latching circuit 17 via logic inversion element 16a. In the following descriptions, a signal output from the logic inversion element 16a is referred to as the "main signal". The main signal (second signal) is generated based on a potential (first potential) at the VS terminal (connection point 1c), a potential (predetermined second potential) at the VB terminal, and an input signal from the HIN terminal. Resistor 13b and high-voltage transistor 14b are connected in series between the VB terminal and the GND terminal, and one gate terminal of high-voltage transistor 14b is connected to the GND terminal. Resistor 13b and high-voltage transistor 14b are connected to junction 61b, and junction 61b is connected to the VS terminal via diode 15b. Furthermore, junction 61b is connected to the STB terminal of the D-latching circuit 17 via logic inversion element 16b. In the following descriptions, a signal output from the logic inversion element 16b is referred to as the "first mask signal". The first mask signal is generated based on the potential (first potential) at the VS terminal (connection point 1c), the potential (predetermined second potential) at the VB terminal, and a potential (low potential) at the GND terminal. Fig. 3 is a circuit diagram showing an equivalent circuit of the D-interlock circuit 17. The D-interlock circuit 17 generates a signal based on the first mask signal input to the STB terminal and the main signal input to the D terminal, and outputs the generated signal from the Q terminal. The D-interlock circuit 17 outputs a high (H) signal from the Q terminal if the first mask signal is low (L) and the main signal is high (H). The D-interlock circuit 17 outputs a low (L) signal from the Q terminal if the first mask signal is low (L) and the main signal is low (L). In other words, if the first mask signal is low (L), the D-interlock circuit 17 outputs a signal with the same logic value as the main signal from the Q terminal.On the other hand, in a case where the first mask signal = H, the D-locking circuit 17 maintains a logic value (H or L) of the signal output from the Q terminal at the time when the first mask signal = H, until the first mask signal = L. Referring back to Fig. 2, the buffer circuit 18a is connected between the Q terminal of the D interlocking circuit 17 and the HO terminal. The LIN terminal, into which an input signal is primarily used to control the N-side SW element 1b, is connected to the always-on control circuit 12b. The buffer circuit 18b generates a signal based on a potential difference between the VCC terminal and the GND terminal and a signal from the always-on control circuit 12b (essentially the input signal of the LIN terminal) and outputs the generated signal to the LO terminal. Since the potential difference between the VCC terminal and the GND terminal corresponds to the voltage of the power supply 52, as shown in Fig. 1, the power supply 52 is used for the N-side SW element 1b. In the related semiconductor device with the aforementioned configuration, a mode that fails to produce a correct output is generated in the event of a negative VS overvoltage. This is described with reference to a timing diagram in Fig. 4, which shows an operation of the related semiconductor device. The mode that fails to produce a correct output is generated in a period from t2 to t4, as shown in Fig. 4. In the description, starting from time t1, the HIN connection is switched from L to H at time t1. Next, the negative overvoltage, which makes a VS potential (potential at the VS terminal) negative, occurs at approximately time t2. Consequently, the first mask signal is not inverted, and a signal generated with a level-shift resistor, the main signal, and the like are inverted, resulting in an inversion of an HO potential (potential at the HO terminal) from high to low. In other words, even if a HIN potential (potential at the HIN terminal) is high from approximately time t2, when the negative overvoltage occurs, until time t3, when the VS potential is the active boundary, the HO potential is inverted to low. At time t3, the main signal switches from L to H, and the first mask signal also switches from L to H. It is conceivable that, for some reason, the first mask signal could switch before the main signal. In such a case, due to the operation of the D-interlock circuit 17, described with reference to Fig. 3, it is conceivable that the output from the HO terminal, after time t3 when the main signal switches to H, remains at L instead of switching to H. In this case, the output from the HO terminal is unstable until the VS potential becomes positive (time t4). In contrast, an HVIC driver 11 and a semiconductor device according to a first preferred embodiment of the present invention can solve the problems. The HVIC driver 11 and the semiconductor device according to the first preferred embodiment will be described next. <Erste bevorzugte Ausführungsform> Fig. 5 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a first preferred embodiment. Fig. 6 is a circuit diagram showing a configuration of a semiconductor device according to the first preferred embodiment with the HVIC driver 11. In the first preferred embodiment, the same or similar structural components as those described in the related semiconductor device are designated with the same reference numerals, and the main differences are described below. The HVIC driver 11 shown in Fig. 5 and Fig. 6 is configured to further include a logic summing element 20 and a circuit 32 for detecting a negative overvoltage in addition to the structural components of the HVIC driver 11 shown in Fig. 2. Circuit 32 for detecting a negative overvoltage detects whether the negative overvoltage occurs at the VS terminal, specifically at connection point 1c shown in Fig. 2. Circuit 32 compares the VS potential with a VB potential (potential at the VB terminal). If the VS potential is lower than the VB potential, circuit 32 detects that the negative VS overvoltage is not present and outputs a detection signal (L-signal) indicating the detection result to the logic summing element 20. On the other hand, if the VS potential is greater than the VB potential, the circuit 32 for the detection of a negative overvoltage detects that the negative VS overvoltage occurs and outputs a detection signal (H signal) indicating the detection result to the logic sum element 20. The detection signal output from circuit 32 for the detection of a negative overvoltage is referred to below as the "second mask signal". The logic summing element 20 forms a level converter circuit 31 according to the first preferred embodiment with the always switched-on control circuit 12a, the resistors 13a and 13b, the high-voltage transistors 14a and 14b, the diodes 15a and 15b, the logic inversion elements 16a and 16b, the D-locking circuit 17 and the buffer circuit 18a. The logic summing element 20 outputs a signal indicating the logical sum of the first mask signal output from the logic inversion element 16a and the second mask signal output from the circuit 32 for negative overvoltage detection. The output from the logic summing element 20 is fed into the STB terminal of the D-interlock circuit 17. Below, a signal output from the logic summing element 20 is referred to as the "third mask signal." The first mask signal is generated based on the potential at the VS terminal, the potential at the VB terminal, and the potential at the GND terminal. The second mask signal, on the other hand, corresponds to a detection result from circuit 32 for detecting a negative overvoltage. Therefore, the third mask signal (first signal), generated based on the first and second mask signals, is generated based on the potential (first potential) at the VS terminal (connection point 1c), the potential at the VB terminal (predetermined second potential), the potential (low potential) at the GND terminal, and the detection result of circuit 32 for detecting a negative overvoltage. The D-interlock circuit 17 generates a signal based on the third mask signal input to the STB terminal and the main signal input to the D terminal, and outputs the generated signal from the Q terminal. In other words, if the third mask signal is low (L), the D-interlock circuit 17 outputs a signal with the same logic value as the main signal from the Q terminal. Conversely, if the third mask signal is high (H), the D-interlock circuit 17 maintains a logic value (high or low) of the signal output from the Q terminal from the time the third mask signal is high until the third mask signal is low (L). The level-shifting circuit 31 converts the level of the main signal according to the third mask signal, as described above. Consequently, the level-shifting circuit 31 can maintain a drive voltage used when driving the P-side SW element 1a when the circuit 32 detects the occurrence of the negative VS overvoltage. This will be described in detail below. <operation> Fig. 7 is a timing diagram showing an operation of the semiconductor device according to the first preferred embodiment. In the semiconductor device according to the first preferred embodiment, similar to the related semiconductor device, in a case where the VS potential is greater than the active VS limit and the VS potential shifts in a positive direction (dV / dt is positive), the signal, which is H, is inputted into the STB terminal of the D-locking circuit 17. Additionally, in the semiconductor device according to the first preferred embodiment, even in a case where the VS potential shifts in a negative direction (dV / dt is negative) and a negative VS overvoltage occurs, the signal, which is H, is inputted into the STB terminal of the D-locking circuit 17. The operation of the semiconductor device according to the first preferred embodiment is described in detail below.The times t2, t3 and t4 in Fig. 7 correspond to the times t2, t3 and t4 in Fig. 4 . Under normal conditions, the third mask signal is L. Consequently, switching transistor 14a on and off with a high voltage toggles the main signal between H and L. As a result, the output from the HO terminal is switched between H and L. In other words, the HO output logic is determined and stabilized. In a case where the VS potential shifts from a GND potential (potential at the GND terminal) to a high voltage (in a case where dV / dt is positive), a displacement current flows from the VB terminal to the GND terminal. High-voltage transistor 14b turns on when the generation of this displacement current is detected, so that at time t0, the first mask signal switches from L to H, and the third mask signal also switches from L to H. The third mask signal, which is H, is fed into the STB terminal, and the D-latch circuit 17 is logic-locked. In other words, the D-latch circuit 17 maintains the logic value of the signal output from the Q terminal at this time. Therefore, before the VS terminal shift to the high voltage has any effect on the main signal, the logic value (the potential) at the HO terminal can be locked. Conversely, if the VS potential shifts in the negative direction (dV / dt is negative) and the negative VS overvoltage occurs around time t2, the VS potential is lower than the GND potential. Consequently, the VB potential, which is connected to the VS terminal via the power supply 53 (Fig. 6), is also lower than the GND potential, namely a drain potential (potential at a drain terminal) of the high-voltage transistor 14b. As a result, the order of the source / drain potentials of the high-voltage transistor 14b, namely the high and low potentials, is reversed, causing a current to flow from the GND terminal to the VB terminal. Consequently, the VS potential is higher than the VB potential by the product of the current value and the resistance value of resistor 13b. In other words, under normal conditions the VS potential is lower than the VB potential, and when a negative VS overvoltage occurs, the VS potential is higher than the VB potential. Circuit 32 for detecting a negative overvoltage is configured to detect whether the negative VS overvoltage occurs based on the reversal of the order of the potentials at the VS and VB terminals. The circuit 32 for detecting a negative overvoltage detects the occurrence of the negative VS overvoltage and outputs the second mask signal, which is H, shown at time t2 in Fig. 7, to the logic summing element 20 of the level shifter circuit 31. Consequently, the third mask signal is switched from L to H. When the third mask signal, which is H, is input to the STB terminal, the D-interlock circuit 17 is logically locked, and the logic value (the potential) at the HO terminal is fixed. In other words, in the related semiconductor device, the logic value (potential) at the HO terminal is fixed at time t3 in Fig. 4, and in the first preferred embodiment, the logic value (potential) at the HO terminal can be fixed at time t2 in Fig. 4, when the negative VS overvoltage occurs. Therefore, before the negative VS overvoltage has an effect on the main signal (before the main signal switches from H to L at time t2 in Fig. 4), the logic value (potential) at the HO terminal can be fixed, preventing the HO potential from inverting to L at time t2. Furthermore, the third mask signal, which is H, is maintained from time t2 to time t4, and the logic value (potential) at the HO terminal is fixed during this period, so that the output from the HO terminal is stable from time t3 to time t4. In the semiconductor drive device (in the HVIC driver 11) and the semiconductor device according to the first preferred embodiment, as described above, in a case where the circuit 32 detects the occurrence of a negative VS overvoltage, the drive voltage used to drive the P-side SW element 1a is maintained. Therefore, before the occurrence of the negative VS overvoltage has an effect on the main signal, the voltage of the HO terminal used to drive the P-side SW element 1a can be maintained. Consequently, the inversion of the HO potential and the output instability of the HO terminal that occurred in the related semiconductor device can be suppressed.In other words, according to the first preferred embodiment, the adverse effect of the negative VS overvoltage in the always-on level converter circuit can be suppressed by, for example, the D-locking circuit 17. As described above, the circuit 32 for detecting a negative overvoltage compares the VB potential and the VS potential and, based on the result of the comparison, detects whether the negative VS overvoltage occurs, but it is not limited to this. As a configuration of a second preferred embodiment or subsequent embodiments, which will be described next, the circuit 32 for detecting a negative overvoltage can, for example, compare the VS potential and a high-voltage drain potential of transistor 14b (GND potential, a potential at junction 61b) and, based on the result of the comparison, detect whether the negative VS overvoltage occurs. <Zweite bevorzugte Ausführungsform> Fig. 8 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a second preferred embodiment of the present invention. In the second preferred embodiment, the same or similar structural components as those described in the first preferred embodiment are designated with the same reference numerals, and the main differences are described below. A circuit 32 for detecting a negative overvoltage according to the second preferred embodiment is configured to include several Zener diodes 33a, 33b, 33c and 33d (here four), a switching circuit 34, a resistor 35 and a logic inversion element 36. The four Zener diodes 33a to 33d are connected in series between junction 61b and the VS terminal. The potential between Zener diode 33c (first Zener diode) and Zener diode 33d (second Zener diode) is fed into the switching circuit 34. Zener diodes 33a to 33d each have a breakdown voltage of Vz, and in the event of a negative VS overvoltage, the potential between Zener diode 33c and Zener diode 33d is 3xVz (predetermined potential). The switching circuit 34 and the resistor 35 are connected between the VB terminal and the VS terminal. The switching circuit 34 is configured to switch on when the potential between the Zener diode 33c and the Zener diode 33d is 3xVz (predetermined potential). In the configuration described above, in the event of a negative VS overvoltage, the GND potential is considerably larger than the VS potential. Consequently, when the negative VS overvoltage occurs, the voltage Vd between the drain potential of high-voltage transistor 14b and the VS potential is considerably large, and the potential between Zener diode 33c and Zener diode 33d is limited to 3xVz. The switching circuit 34 turns on when the potential between Zener diode 33c and Zener diode 33d is 3xVz (in other words, if the negative VS overvoltage occurs). Then the switching circuit 34 generates an inversion signal of the signal obtained from the voltage distributed by the ratio between the resistor 35 and a turn-on resistor of the switching circuit 34, as a detection signal (second mask signal, which is H), indicating the occurrence of the negative VS overvoltage. In other words, under normal conditions (in a case where the negative VS overvoltage does not occur), the VS potential is approximately equal to the GND potential, so that even at its maximum, the voltage Vd does not normally exceed the voltage between VB and VS. In this case, the switching circuit 34 does not turn on, so no detection signal (second mask signal, which is H) indicating the occurrence of the negative VS overvoltage is output to the STB terminal of the D-interlock circuit 17. On the other hand, if the negative VS overvoltage occurs and the voltage Vd should be 4xVz or greater, the potential between the Zener diode 33c and the Zener diode 33d is 3xVz. In this case, the switching circuit 34 switches on, so that the detection signal (second mask signal, which is H) indicating the occurrence of the negative VS overvoltage is generated, and the generated detection signal is output to the STB terminal of the D-interlock circuit 17. In the semiconductor control device (HVIC driver 11) and the semiconductor device according to the second preferred embodiment as described above, the Zener diodes 33a to 33d are suitably selected and consequently the potential for switching on the switching circuit 34 can easily be set to the desired potential. <Dritte bevorzugte Ausführungsform> Fig. 9 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a third preferred embodiment of the present invention. In the third preferred embodiment, the same or similar structural components as those described in the second preferred embodiment are designated with the same reference numerals, and the main differences are described below. In the third preferred embodiment, an N-type metal oxide semiconductor field-effect transistor (MOSFET) 37 and a resistor 38, which is connected between a gate terminal of the N-type MOSFET 37 and the VS terminal, are used as a switching circuit 34 in Fig. 8. The N-type MOSFET 37 switches on when the potential between Zener diode 33c and Zener diode 33d is 3xVz (in other words, when the negative VS overvoltage occurs). Furthermore, when the N-type MOSFET 37 switches on, it generates, similar to the switching circuit 34 mentioned above, an inversion signal of the voltage distributed by the ratio between resistor 35 and the on-resistance of switching circuit 34, as a detection signal (second mask signal, which is high), indicating that the negative VS overvoltage is present. In the semiconductor driver device (HVIC driver 11) and the semiconductor device according to the third preferred embodiment, as described above, the inversion signal of the signal obtained from the voltage distributed by the ratio between resistor 35 and the on-resistance of the N-type MOSFET 37 can be fed into an inverter element of the next stage as a detection signal indicating that the negative VS overvoltage is occurring. Consequently, stable signal transmission can be achieved, and the circuit size can be compact. Under normal conditions, the N-type MOSFET 37 switches off, thereby reducing power consumption. <Vierte bevorzugte Ausführungsform> Fig. 10 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a fourth preferred embodiment of the present invention. In the fourth preferred embodiment, the same or similar structural components as those described in the second preferred embodiment are designated with the same reference numerals, and the main differences are described below. A circuit 32 for detecting a negative overvoltage according to the fourth preferred embodiment is configured to include a current mirror circuit 39 instead of the switching circuit 34 in Fig. 8. The current mirror circuit 39 is configured to include two N-type MOSFETs 40a and 40b. The N-type MOSFET 40a is connected between the Zener diode 33d and the VS terminal, and the N-type MOSFET 40b is connected between the resistor 35 and the VS terminal. Furthermore, a gate terminal of the N-type MOSFET 40a and a gate terminal of the N-type MOSFET 40b are connected together, and the gate terminals are connected to a junction between the N-type MOSFET 40a and the Zener diode 33d. In the configuration described above, when a negative VS overvoltage occurs, a current flows through the Zener diodes 33a to 33d. Upon detection that current is flowing through these diodes, the current mirror circuit 39 switches on. This current mirror circuit then generates the inverse signal of the voltage distributed by the ratio between resistor 35 and the on-resistance of the switching circuit 34. This signal serves as the detection signal (second mask signal, H), indicating the presence of the negative VS overvoltage. In other words, a circuit for transmitting a current signal to a subsequent stage is established. In the semiconductor driver device (HVIC driver 11) and the semiconductor device according to the fourth preferred embodiment as described above, the circuit 32 for detecting a negative overvoltage is configured to include the current mirror circuit 39, which performs a current mirror operation, and consequently a mirror ratio and the resistor 35 for converting a voltage of the following stage are expediently designed, whereby a desired detection sensitivity can be easily achieved. <Fünfte bevorzugte Ausführungsform> Fig. 11 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a fifth preferred embodiment of the present invention. In the fifth preferred embodiment, the same or similar structural components as those described in the fourth preferred embodiment are designated with the same reference numerals, and the main differences are described below. The semiconductor driver (the HVIC driver 11) and the semiconductor device according to the fifth preferred embodiment are configured to include the current mirror circuit 39 similarly to the fourth preferred embodiment, so that the fifth preferred embodiment can achieve a similar effect to that in the fourth preferred embodiment. Moreover, the current mirror circuit 39 is configured to include two bipolar transistors 41a and 41b instead of two N-type MOSFETs 40a and 40b, and consequently, the effect on the clamping voltage by the Zener diodes 33a to 33d can be uniformly fixed to a forward voltage VF. Therefore, voltage fluctuations in the current can be suppressed. <Sechste bevorzugte Ausführungsform> Fig. 12 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a sixth preferred embodiment of the present invention. In the sixth preferred embodiment, the same or similar structural components as those described in the second preferred embodiment are designated with the same reference numerals, and the main differences are described below. In the sixth preferred embodiment, several Zener diodes 33a to 33d perform the function of diode 15b in Fig. 8, thus eliminating the need for diode 15b. The number of Zener diode stages with a breakdown voltage Vz lower than the clamping voltage on the main signal side is advantageously designed, allowing the clamping voltage on the third mask signal side to be set to a desired voltage. Therefore, the sensitivity of the third mask signal to fluctuations in the VS potential can be improved relative to the sensitivity of the main signal. In other words, the difference in sensitivity between the main signal and the third mask signal can be easily set to a desired voltage, and consequently, stable operation can be expected despite fluctuations in the VS potential. <Siebte bevorzugte Ausführungsform> Fig. 13 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to a seventh preferred embodiment of the present invention. In the seventh preferred embodiment, the same or similar structural components as those described in the sixth preferred embodiment are designated with the same reference numerals, and the main differences are described below. The HVIC driver 11 according to the seventh preferred embodiment is configured to further include a delay circuit 42 in addition to the structural components of the HVIC driver 11, as shown in Fig. 12. The delay circuit 42 delays the main signal, whose level is converted by the converter circuit 31, with respect to the third mask signal, which is used for level conversion of the main signal. Fig. 14 is a timing diagram showing the operation of a semiconductor device according to the seventh preferred embodiment. Upon the occurrence of the negative VS overvoltage, the time at which the main signal, before being input to the delay circuit 42 (namely, the output signal from the logic inversion element 16a), switches from H to L, is approximately equal to the time at which the third mask signal switches from L to H. When the main signal is input to the D terminal of the D-latch circuit 17, it is conceivable that the time at which the main signal switches from H to L may, for some reason, precede the time at which the third mask signal switches from L to H. In this case, the D-latch circuit 17 maintains the main signal, which is affected by the occurrence of the negative VS overvoltage, as an output signal. In the seventh preferred embodiment, the main signal, after being input to the delay circuit 42, is configured to be input to the D-latching circuit 17. Therefore, before the occurrence of the negative VS overvoltage has any effect on the main signal, the logic value (the potential) at the HO terminal can be reliably fixed. In other words, the switching time of the D-latching circuit 17 can be sequentially arranged so that, in the always-on level converter circuit with, for example, the D-latching circuit 17, any adverse effect caused by the negative VS overvoltage can be reliably suppressed. <Achte bevorzugte Ausführungsform> Fig. 15 is a circuit diagram showing part of a configuration of an HVIC driver 11 according to an eighth preferred embodiment of the present invention. In the eighth preferred embodiment, the same or similar structural components as those described in the seventh preferred embodiment are designated with the same reference numerals, and the main differences are described below. In the eighth preferred embodiment, the third mask signal is input into a delay circuit 42. The delay circuit 42 determines whether the negative overvoltage detection circuit 32 detects the occurrence of the negative VS overvoltage, based on the third mask signal and the like. If the delay circuit 42 determines that the occurrence of the negative VS overvoltage has been detected, the delay circuit 42 delays the main signal. In other words, according to the eighth preferred embodiment, the delay circuit 42 delays the main signal only if the negative overvoltage detection circuit 32 detects the occurrence of the negative VS overvoltage. In the semiconductor control device (in the HVIC driver 11) and the semiconductor device according to the eighth preferred embodiment as described above, the delay circuit 42 can be prevented from delaying the output (main signal) under normal conditions (in a case where the negative VS overvoltage does not occur). <Neunte bevorzugte Ausführungsform> Fig. 16 is a circuit diagram showing a configuration of a semiconductor device according to a ninth preferred embodiment. In the ninth preferred embodiment, the same or similar structural components as those described in the first preferred embodiment are designated with the same reference numerals, and the main differences are described below. The semiconductor device shown in Fig. 6 includes the power supply 53, which generates the VB potential (predetermined second potential). In contrast, the semiconductor device according to the ninth preferred embodiment, shown in Fig. 16, is provided with a bootstrap circuit comprising a bootstrap diode 46a and a bootstrap capacitor 46b instead of the power supply 53. An anode of the bootstrap diode 46a is connected to the VCC terminal, to which the power supply 52 (Fig. 1) is connected. A cathode of the bootstrap diode 46a is connected to the VB terminal. The bootstrap capacitor 46b is connected between the VB terminal and the VS terminal. The bootstrap circuit with the configuration described above can generate the power in the bootstrap capacitor 46b equal to that of the power supply 53, based on the power of the power supply 52. ​​In other words, the bootstrap circuit can generate the power to produce the VB potential based on the power of the power supply 52, which is used for the N-side SW element 1b. In the semiconductor device according to the ninth preferred embodiment, as described above, upon detection of the negative VS overvoltage, the VB potential decreases from a VCC potential (potential at the VCC terminal) by the forward voltage VF. Therefore, the order of the potential at the negative VS overvoltage can be determined. Consequently, the detection sensitivity of the negative VS overvoltage can be improved. According to the present invention, within the scope of protection of the invention, the above preferred embodiments can also be combined arbitrarily, or each preferred embodiment can be suitably modified or omitted. Although the invention has been shown and described in detail, the preceding description is explanatory in all aspects and not limiting. Therefore, numerous modifications and alterations can of course be developed without deviating from the scope of protection of the invention.< / operation>

Claims

Semiconductor drive device (11) configured to drive a high-voltage side semiconductor switching element (1a) and a low-voltage side semiconductor switching element (1b) connected in series between a high potential and a low potential, the semiconductor drive device (11) comprising: a negative overvoltage detection circuit (32) that detects whether a negative overvoltage occurs at a junction (1c) between the high-voltage side semiconductor switching element (1a) and the low-voltage side semiconductor switching element (1b); and a level shifter circuit (31) that maintains a drive voltage used when driving the high-voltage side semiconductor switching element (1a) when the negative overvoltage detection circuit (32) detects the occurrence of the negative overvoltage;wherein the level-shifting circuit (31) is configured to maintain the drive voltage in response to a first potential at the junction point (1c), a predetermined second potential, the low potential, and a detection result of the circuit (32) for detecting a negative overvoltage by level-shifting a second signal (main signal) generated on the basis of the first potential, the second potential, and an input signal, wherein the circuit (32) for detecting a negative overvoltage comprises a first Zener diode (33c) and a second Zener diode (33d), and upon occurrence of the negative overvoltage, a potential between the first Zener diode (33c) and the second Zener diode (33d) is a predetermined potential. Semiconductor control device (11) according to claim 1, wherein the circuit (32) for detecting a negative overvoltage further comprises an N-type metal oxide semiconductor field-effect transistor (MOSFET) (37) configured to generate a detection signal (second mask signal) indicating the occurrence of the negative overvoltage if the potential between the first Zener diode (33c) and the second Zener diode (33d) is the predetermined potential. Semiconductor control device (11) according to claim 1, wherein the circuit (32) for detecting a negative overvoltage comprises a current mirror circuit (39) configured to generate a detection signal (second mask signal) when the negative overvoltage occurs, indicating the occurrence of the negative overvoltage. Semiconductor control device (11) according to claim 3, wherein the current mirror circuit (39) comprises two N-type MOSFETs (40a, 40b). Semiconductor control device (11) according to claim 3, wherein the current mirror circuit (39) comprises two bipolar transistors (41a, 41b). Semiconductor control device (11) according to one of claims 1 to 5, wherein the semiconductor control device (11) further comprises a delay circuit (42) which delays the second signal (main signal), the level of which is converted by the level converter circuit (31), with respect to the first signal (third mask signal), which is used for the level conversion of the second signal (main signal). Semiconductor control device (11) according to claim 6, wherein the delay circuit (42) delays the second signal (main signal) when the circuit (32) detects the occurrence of a negative overvoltage. Semiconductor device comprising: a high-voltage side semiconductor switching element (1a) and a low-voltage side semiconductor switching element (1b) connected in series between a high potential and a low potential; and a semiconductor drive device (11) configured to drive the high-voltage side semiconductor switching element (1a) and the low-voltage side semiconductor switching element (1b), wherein the semiconductor drive device (11) comprises: a negative overvoltage detection circuit (32) that detects whether a negative overvoltage occurs at a junction (1c) between the high-voltage side semiconductor switching element (1a) and the low-voltage side semiconductor switching element (1b); and a level shifter circuit (31) that maintains a drive voltage.which is used when driving the semiconductor switching element (1a) on the high-voltage side when the circuit (32) for detecting a negative overvoltage detects the occurrence of the negative overvoltage, and wherein the level-shifting circuit (31) is configured to maintain the drive voltage in response to a first potential at the junction point (1c), a predetermined second potential, the low potential, and a detection result of the circuit (32) for detecting a negative overvoltage by level-shifting a second signal (main signal) generated on the basis of the first potential, the second potential, and an input signal, wherein the circuit (32) for detecting a negative overvoltage comprises a first Zener diode (33c) and a second Zener diode (33d), and upon the occurrence of the negative overvoltage, a potential between the first Zener diode (33c) and the second Zener diode (33d) is a predetermined potential. Semiconductor device according to claim 8, further comprising: a delay circuit (42); and a bootstrap circuit (46a, 46b), wherein the delay circuit (42) delays the second signal (main signal), the level of which is converted by the level converter circuit (31), with respect to the first signal (third mask signal) used for level conversion of the second signal (main signal), and the bootstrap circuit (46a, 46b) is configured to generate power for generating the second potential based on power from a power supply used for the semiconductor switching element (1b) on the low-voltage side.

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