A device and a method for providing oscillator signals, as well as a machine-readable storage medium for its execution and transmitter.

Abstract

A device (100, 150, 300, 400) for providing oscillator signals, comprising: a first digital time converter module (101) configured to generate a first oscillator signal (102) based on a first adapted input signal (103); a second digital time converter module (104) which is configured to be a second to generate oscillator signal (105); a first processing module (106) configured to generate the first adapted input signal (103) of the first digital time converter module (101) by adding noise to a first input signal (107); and a second processing module (109) configured to generate a second adapted input signal (112) by adding noise to a second input signal (111), wherein the second digital time converter module (104) is configured to generate the second oscillator signal (105) based on the second adapted input signal (112), and where the noise added to the first input signal (107) and the noise added to the second input signal (111) are uncorrelated.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the generation of required oscillator signals and in particular to a device and a method for providing oscillator signals. BACKGROUND

[0002] The demand for ever-increasing amounts of data to be transmitted in shorter timeframes is driving higher demands on the transmission signals. Today, transceivers can transmit signals simultaneously at different frequencies. Therefore, various oscillator signals with different frequencies are required. Furthermore, it is desirable to improve the control of noise and interference within the transmission signals in order to adhere to desired limits.

[0003] Publication DE 10 2014 017 296 A1 proposes a direct digital frequency generation using time and amplitude.

[0004] Publication DE 10 2014 014 269 A1 proposes a power-saving technology for digital time converters.

[0005] Publication US 2012 / 0 288 044 A1 proposes phase or frequency synthesis using periodic sigma-delta modulated bit stream techniques. BRIEF DESCRIPTION OF THE FIGURES

[0006] The following are some examples of devices and / or methods, described solely by way of example and with reference to the accompanying figures, in which: Fig. 1a shows a schematic representation of a device for providing oscillator signals; Fig. 1b shows a schematic representation of another device for providing oscillator signals; Fig. 2 shows a schematic representation of a noise shaping module; Fig. Figure 3a shows a schematic representation of a digital-to-time converter module of another device for providing oscillator signals, comprising a coarse time delay module and a fine time delay module. Fig. Figure 3b shows a schematic representation of the operation of a fine time delay module; Fig. Figure 4 shows a schematic representation of a means for providing oscillator signals; Fig. 5 shows a schematic representation of a transmitter module; Fig. 6 shows a block diagram of a mobile component that includes a transmitter module; Fig. Figure 7 shows a flowchart of a procedure for providing oscillator signals. DETAILED DESCRIPTION

[0007] Several embodiments are now described in more detail with reference to the accompanying drawings, in which some embodiments are illustrated. For clarity, the thickness of lines, layers, and / or regions in the figures may be exaggerated.

[0008] While various modifications and alternative forms of further embodiments are possible, examples of these are shown in the drawings and described in detail here. It is understood, however, that the intention is not to limit the embodiments to the specific forms disclosed, but rather that the embodiments should cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Throughout the description of the figures, identical numbers refer to identical or similar elements.

[0009] It is understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as "directly" "connected" or "coupled" to another element, there are no intermediate elements. Other words used to describe the relationship between elements should be interpreted similarly (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0010] The terminology used here is intended only to describe specific embodiments and is not meant to be limiting to further embodiments. According to our usage, the singular forms "ein, eine" and "das, der, die" are also to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "umfassungt," "umfassend," "aufweisen," and / or "aufweisend," as used here, indicate the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0011] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they would normally be understood by an average person skilled in the field to which the examples relate. Furthermore, it is understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning corresponding to their meaning in the context of the relevant technology, and not in an idealized or overly formal sense, unless expressly defined herein.

[0012] The following examples refer to devices (e.g., mobile phone, base station) or components (e.g., transmitter, transceiver) of devices used in wireless or mobile communication systems. A mobile communication system may, for example, correspond to one of the mobile communication systems standardized by the 3rd Generation Partnership Project (3GPP), e.g.Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), High Speed ​​Packet Access (HSPA), Universal Terrestrial Radio Access Network (UTRAN) or Evolved UTRAN (E-UTRAN), Long Term Evolution (LTE) or Advanced LTE (LTE-A), or mobile communication systems with different standards, e.g., Worldwide Interoperability for Microwave Access (WIMAX) IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.16.11, generally any system based on time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), code division multiple access (CDMA), etc. The terms mobile communication system and mobile communication network may be used synonymously.

[0013] The mobile communication system can have multiple transmit points or base station transceivers that are effective in communicating radio signals with a mobile transceiver. In these examples, the mobile communication system can have mobile transceivers, repeater transceivers, and base station transceivers. The repeater transceivers and base station transceivers can consist of one or more central units and one or more remote units.

[0014] A mobile transceiver or mobile device can be a smartphone, mobile phone, end-user equipment (UE), laptop, notebook, personal computer, personal digital assistant (PDA), universal serial bus (USB) stick, tablet computer, car, etc. A mobile transceiver or port can also be referred to as a UE or user according to 3GPP terminology. A base station transceiver can be located in the fixed or stationary part of the network or system. A base station transceiver can be a remote radio head, transmission point, access point, macrocell, small cell, microcell, picocell, femtocell, metrocell, etc. The term small cell can refer to any cell smaller than a macrocell, i.e.,A microcell, picocell, femtocell, or metrocell. Furthermore, a femtocell is considered smaller than a picocell, which is considered smaller than a microcell. A base station transceiver can be a wireless interface of a wired network that enables the transmission and reception of radio signals to a terminal device, a mobile transceiver, or a relay transceiver. Such a radio signal can correspond to radio signals standardized, for example, by 3GPP, or to those generally corresponding to one of the systems listed above. Thus, a base station transceiver can correspond to a NodeB, an eNodeB, a BTS, an access point, etc. A relay transceiver can correspond to an intermediate network node in the communication path between a base station transceiver and a mobile transceiver.A relay station transceiver can forward a signal received from a mobile transceiver to a base station transceiver, or forward signals received from a base station transceiver to the mobile station transceiver.

[0015] The mobile communications system can be cellular. The term cell refers to a coverage area of ​​radio services provided by a transmit point, remote unit, remote head, remote radio head, base station transceiver, repeater transceiver, or NodeB / eNodeB. The terms cell and base station transceiver can be used interchangeably. In some examples, a cell may correspond to a sector. For example, sectors can be achieved using sector antennas, which provide a characteristic for covering an angular section around a base station transceiver or remote unit. In some examples, a base station transceiver or remote unit may operate, for example, three or six cells, covering sectors of 120° (in the case of three cells) or 60° (in the case of six cells), respectively.Similarly, a relay transceiver can establish one or more cells within its coverage area. A mobile transceiver can be registered with or assigned to at least one cell, meaning it can be associated with a cell in such a way that data can be exchanged between the network and the mobile phone within the coverage area of ​​the assigned cell using a dedicated channel, link, or connection. A mobile transceiver can thus register with or be assigned to a relay station or base station transceiver, directly or indirectly, with indirect registration or assignment occurring through one or more relay transceivers.

[0016] When two or more digital-to-time converters (DTCs) operate simultaneously, they can interfere with each other. For example, if two DTCs switch on at the same time, they can each cause a load on the supply voltage (VCC) of one, which affects or influences the voltage supplied to the other DTC. This can cause ripple in the supply voltage (VCC) that can affect one or both digital-to-time converter modules. Similarly, one or both DTCs can suffer from the ripple generated by the other DTC. For example, a reduced supply voltage can be supplied to one or both DTCs, which can impair their operation because it can cause a delay in the DTC output. If such a delay occurs regularly, e.g.,Due to a regular superposition (or collision) of the frequencies generated by two DTCs, this regular timing error can cause disturbances in the output spectrum.

[0017] Fig. Figure 1 shows a schematic representation of a device 100 for providing oscillator signals. The device 100 comprises a first digital time converter module 101 configured to generate a first oscillator signal 102 based on a first adapted input signal 103. The device 100 comprises a second digital time converter module 104 configured to generate a second oscillator signal 105. The device 100 further comprises a first processing module 106 configured to generate the first adapted input signal 103 of the first digital time converter module by adding noise to a first input signal 107.

[0018] Since the first processing module 106 adds noise to the first input signal 107 to generate the first, adjusted input signal 103, a reduction in noise and oscillator signals with a more accurate time delay can be achieved by the two digital time converter modules. Adding noise to the first input signal can lead to a temporary (i.e., time) variation or a temporary deviation of processes (e.g., delay processes) performed by the first digital time converter module 101, which can prevent or reduce interference between the signal provided by the first digital time converter module 101 and the second digital time converter module 104. This can, for example, reduce or minimize interference between the first digital time converter module 101 and the second digital time converter module 104.Furthermore, it can avoid or reduce regularly recurring deviations and thus, for example, prevent or reduce disruptions.

[0019] The first digital time converter module 101 can be configured to provide (or generate) the first oscillator signal 102 at an output interface of the first digital time converter module 101. The provided (or generated) first oscillator signal 102 can have a (first) variable time delay with respect to a reference oscillator signal (e.g., a local oscillator signal with a reference frequency), which is provided, for example, at an input interface of the first digital time converter module 101. The first digital time converter module 101 can apply a (first) variable time delay to the reference oscillator signal using time delay modules of the first digital time converter module 101 to generate the first oscillator signal 102.

[0020] The second digital time converter module 104 can be configured to provide (or generate) a second oscillator signal 105 at an output interface of the second digital time converter module 104. The provided (or generated) second oscillator signal 105 can have a (second) variable time delay with respect to the reference oscillator signal (e.g., the local oscillator signal with the reference frequency), which is provided, for example, at an input interface of the second digital time converter module 104. The second digital time converter module 104 can apply a (second) variable time delay to the reference oscillator signal using time delay modules of the second digital time converter module to generate the second oscillator signal 105.

[0021] A variable time delay can refer to the fact that the provided oscillator signal (e.g., the first oscillator signal and / or the second oscillator signal) is delayed with respect to the reference oscillator signal or with respect to a signal derived from the reference oscillator signal. For example, the provided first oscillator signal 102 may have a (first oscillator) frequency that differs from a frequency of the reference oscillator signal, and the provided second oscillator signal may have a (second oscillator) frequency that differs from a frequency of the reference oscillator signal.

[0022] The first digital time converter module 101 can be configured to receive the first adapted input signal 103, which may be based on the first input signal 107 with added noise. The first input signal 107 can be a digital signal comprising successive control bit sequences for controlling a variable time delay of the first digital time converter module. For example, each control bit sequence can provide (or carry) information to the first digital time converter module 101 about a variable time delay, which is desired in the provided first oscillator signal 102. In addition to (e.g., besides), the variable time delay there can also be a non-variable, i.e., constant, delay. This delay does not produce spurs or other signal degradation but may need to be considered for timing-critical signals, e.g., range signals.

[0023] The input signal can, for example, correspond to a phase signal of a polar representation of a baseband transmit signal.

[0024] The added noise can lead to a deviation, change, or error in at least one bit of the control bit sequences of the first input signal, which, for example, includes information for setting a time delay. For instance, the added noise can affect the conversion of the control bits to a delayed output such that deviations or errors on the order of one or more bits of the control bit sequences can occur. The deviations or errors can be on the order of, for example, one or more least significant bits. Alternatively or additionally, the deviations or errors can be on the order of one or more most significant bits. The digital representation of the adapted input signal 103 can differ from the digital representation of the (initial) input signal 107 by at least an amount corresponding, for example, to one least significant bit (LSB) of the input signal 107.This can affect other bits (e.g., most significant bits), for example due to carry effects.

[0025] At least one bit of the control bit sequence can be modified by a random or pseudorandom number, for example, to add noise. Thus, an initial (desired) variable time delay based on the first input signal 107 can be changed to a modified (desired) variable time delay based on the first, modified input signal 103 due to the added noise.

[0026] For example, noise can be added only to the first input signal 107, resulting in the first, adapted input signal 103 such that a variable time delay is modified only by the first digital time converter module 101 to the adapted, variable time delay based on the added noise. Alternatively, the device can include a second processing module configured to provide a second input signal to the second digital time converter module 104. The second digital time converter module 104 can be configured to provide the second oscillator signal based on the second input signal. The second input signal can, for example, be free of added noise. This can result in, for example, the need for only a single noise generation circuit arrangement and a single processing module 106.Optionally, the second input signal 111 can be provided directly to the second digital time converter module 104 without any intermediate processing modules (e.g., without the second processing module in between).

[0027] Alternatively or optionally, noise can also be added to a second input signal, which can be a digital signal comprising, for example, successive control bit sequences for controlling a variable time delay of the second digital time converter module 104. In other words, noise can be added to input signals (e.g., to each of the first input signal 107 and the second input signal) for both the first digital time converter module 101 and the second digital time converter module 104. In this way, a higher decorrelation of the timings of the first oscillator signal 102 and the second oscillator signal 105 can be achieved, with the same noise level added to each of the input signals. To achieve the same decorrelation by adding noise to only a single input signal, this noise would have to be of a higher order of magnitude, i.e.,With higher noise power, this also causes greater undesirable degradation of the affected signal, e.g., the first oscillator signal 102. By sharing the load across both oscillator signals, less degradation can be achieved for each. With further refinement, the noise can be distributed unevenly between the two (or more) signals, depending on the noise tolerances of the two signals. The noise affecting the signal that can tolerate higher distortion can be selected with a higher order of magnitude or power than the noise added to the other signal. The noise power can be selected to increase with or be proportional to the noise tolerance of the respective signals.

[0028] Fig. Figure 1b shows an example of another device 150 for providing oscillator signals according to an example.

[0029] The further device 150 can include one, more, or all of the features of the device 100. Additionally or optionally, noise can also be added to the second input signal 111 to generate the second, adapted input signal 112. For example, the second processing module 109 can be configured to generate the second, adapted input signal 112 by adding noise to the second input signal 111. The second digital time converter module 104 can be configured to provide the second oscillator signal 105, for example, based on the second, adapted input signal 112.

[0030] The second digital time converter module 104 may be similar or identical in structure and function to the first digital time converter module 101. Furthermore, the second input signal 111 and the second adapted input signal 112 may each have similar functions and characteristics to the first input signal 107 and the first adapted input signal 103. Optionally or alternatively, the implementation of the second digital time converter module 104 may also differ from that of the first digital time converter module 101. Nevertheless, undesirable interference due to regular interference, e.g., due to VCC ripple, may still occur, as this is a common problem regardless of the internal design of the DTC.

[0031] For example, the second digital time converter module 104 can be configured to receive the second, adapted input signal 112, which may be based on the second input signal 111 with added noise. The second input signal 111 can be a digital signal comprising, for example, successive control bit sequences for controlling a variable time delay of the second digital time converter module 104. Each control bit sequence can provide (or carry) information to the second digital time converter module 104 about a variable time delay, which is desired in the provided second oscillator signal 105.

[0032] The added noise can modify at least one bit of the control bit sequences of the second input signal 111, which contains information for setting a time delay. This at least one bit of the control bit sequences can be modified by a random or pseudorandom number, for example, to add the noise. Thus, an initial (desired) variable time delay based on the second input signal 111 can be changed to a modified (desired) variable time delay based on the second, modified input signal 112, which includes the added noise.

[0033] The first processing module 106 can be configured to perform scrambling or encryption of noise, which is added to the first input signal 107 to generate the first, adapted input signal 103. Alternatively, optionally, or additionally, the first processing module 106 can include a noise-shaping module for generating the noise to be added to the first input signal 107. For example, the first processing module 106 can include a noise-shaping module 200 (which may include dithering) for generating the noise to be added to the first input signal 107.

[0034] The second processing module 109 can be configured to perform chopping or encryption of noise, which is added to the second input signal 111 to generate the second, modified input signal 112. Alternatively, optionally, or additionally, the second processing module 109 can include a noise-shaping module for generating the noise to be added to the second input signal 111. For example, the second processing module 109 can include a noise-shaping module 200 for generating the noise to be added to the second input signal 111.

[0035] Encryption and chopping can be used to provide the decorrelation of the two bitstreams. For example, chopping (a nonlinear operation) can invert some bits, while adding noise (a linear operation) can add an error, which can cause, for example, a carry overflow. Some parameters or least significant bits of the noise generator can be chopped or encrypted to produce the two uncorrelated noises to be added to the first input signal 107 and / or the second input signal 111.

[0036] Optionally, it may be possible to chop up parts of the input signal, i.e., some LSBs, to achieve a non-Gaussian distributed noise (in amplitude), such as a boxcar distribution.

[0037] The noise added to the first input signal and the noise added to the second input signal are, for example, uncorrelated. They can be uncorrelated or at least decorrelated. In other words, the noise added to the first input signal and the noise added to the second input signal can each be generated independently and randomly (e.g., they can be different but not interacting), or at least not fully correlated. For example, the second processing module 109 can be configured to perform a different chopping or encrypting of the second input signal 111 to generate uncorrelated noise.

[0038] Alternatively, optionally or additionally, different noise shaping modules can be implemented in the first processing module 106 and the second processing module 109 to generate the uncorrected noise.

[0039] Alternatively, optionally or additionally, identical noise shaping modules can be implemented in the first processing module 106 and the second processing module 109 to generate the uncorrelated noise.

[0040] For both devices 100 and 150, the noise added to the first input signal 107 (and / or the second input signal 111) can modify one or more least significant bits of the control bit sequences (e.g., each of the control bit sequences) of the first input signal 107 (and / or the second input signal 111). The modifications to the corresponding control bit sequences of the first input signal 107 and the second input signal 111 may be uncorrelated. The added noise can typically be on the order of one or more least significant bits of the corresponding control bit sequences.

[0041] The least significant bits can be provided to control a fine time delay module of the first digital time converter module 101. In other words, the added noise can modify at least one bit of the control bit sequences of the first input signal 107 (and / or the second input signal 111), which contains information for setting a fine time delay. The one or more least significant bits of the control bit sequences can be modified by a random number or a pseudorandom number to add the noise. Thus, an initial fine time delay value based on the first input signal 107 can be modified to a customized fine time delay value based on the first customized input signal 103 due to the noise added to the first input signal 107.Similarly, an initial fine time delay value based on the second input signal 111 can be changed to a matched fine time delay value based on the second matched input signal 112 due to the noise added to the second input signal 111.

[0042] The control bit sequence of the first input signal 107 can also include bits (e.g., most significant bits) for controlling a coarse time delay module of the first digital-to-analog converter module 101 and bits (e.g., least significant bits) for controlling a fine time delay module of the first digital-to-analog converter module 101. Similarly, the control bit sequence of the second input signal 111 can include bits (e.g., most significant bits) for controlling a coarse time delay module of the second digital-to-analog converter module 102 and bits (e.g., least significant bits) for controlling a fine time delay module of the second digital-to-analog converter module 102.

[0043] Additionally, optionally, or alternatively, the added noise can lead to a deviation, modification, or error of one or more most significant bits of the control bit sequences. These most significant bits can be provided, for example, to control the coarse time delay module of the first digital time converter module 101. The one or more most significant bits of the control bit sequences can be modified by a random number or a pseudorandom number, for example, to add the noise.

[0044] Optionally or alternatively, the added noise can leave one or more most significant bits of the control bit sequences unchanged (e.g., neglecting occasional carry effects), where the most significant bits contain information, for example, for controlling the coarse time delay module. For example, only the (fine) time delay of the fine time delay modules of the first digital time converter module 101 and the second digital time converter module 104 can be modified by the added noise. Control information for the coarse time delay module can remain unchanged by the added noise. However, due to occasional carry effects (e.g.,Adding a single LSB can lead to a carry effect that can affect the most significant bit (in decimal notation, this corresponds to 1999 + 1 = 2000, in binary notation 1111b + 1b = 10000b). This can sometimes alter the control information for the coarse time delay module. The added noise can be, for example, smaller than the most significant bits.

[0045] Fig. Figure 2 shows a noise shaping module 200 according to an example.

[0046] The noise-shaping module 200 can include a quantization module 223. The noise-shaping module 200 can be configured to receive an input signal 219 (e.g., the first input signal 107 or the second input signal 111). The input signal 219 can be provided to the quantization module 223 and a first signal adder 222. The quantization module 222 can generate a quantization error based on a difference between the input signal 219 and an output signal 229 (e.g., the first adapted input signal 103 or the second adapted input signal 112).

[0047] The output signal 229 can be provided to an output interface of the noise-shaping module 200 and / or received by the first signal adder 222. The first signal adder 222 can calculate a difference between the output signal 229 and the input signal 219, which corresponds to an effective error. The effective error includes a quantization error and a remaining mismatch error and provides an error signal 224 to a feedback filter 225 for noise shaping.

[0048] The noise-shaping feedback filter 225 can perform an operation H(z) to provide a noise-shaped feedback signal 226 to a second signal adder 227. The second signal adder 227 can be configured to calculate a sum and / or difference of the input signal 219 and the feedback signal 226 and to provide a modified input signal 228 to a quantization module 223 and the first signal adder 222 in a second and subsequent iteration steps. The quantization module 223 can generate a quantization error to provide an output signal 229. In the next iteration, the first signal adder 222 provides the newly calculated error signal 224 to the noise-shaping feedback filter 225. The noise-shaping feedback filter 225 can be configured to reduce error contributions within the spectrum caused by quantization in the time domain.

[0049] The noise-shaping module 200 can further include an error generator configured to perform dithering. The dithering can be performed by adding an error contribution (e.g., a dither signal according to a dither algorithm) to the error signal 224 using a third signal adder 261. The dither signal can be a signal with a distribution such as a pseudorandom binary sequence (PRBS) or additive white Gaussian noise (AWGN). The dithering can be applied to the error signal 224, resulting in a modified error signal 224a (epsi). Alternatively, the dithering can be applied to a feedback signal 226 (fb), the input signal 219 (in_f), or the modified input signal 228 (int_f), as indicated by arrows. At any of these points, noise (e.g.,AWGN or another type of noise) is injected and shaped to the desired spectrum via the feedback filter H(z).

[0050] To enhance the smearing effect of the noise shaping module, it may be possible to increase the order of the noise shaper or to try to increase the error contribution within the noise shaper. Implementing dithering can increase the noise floor with little effect on the smearing of the disturbances.

[0051] The first processing module 106 of devices 100, 150 can include a first noise-forming module. The second processing module 109 (of device 150) can include a second noise-forming module. The first noise-forming module (and the second noise-forming module) can be identical noise-forming modules, similar to or identical with noise-forming module 200.

[0052] The first noise shaping module and the second noise shaping module can be configured to generate the uncorrelated noise in the first adapted input signal 103 and the second adapted input signal 112.

[0053] For example, the first noise-forming module can be configured to generate noise based on a first noise sequence (e.g., based on a first dither signal generated according to a first dither sequence or algorithm). The second noise-forming module can be configured to generate (uncorrelated) noise based on a second noise sequence (e.g., based on a second, different dither signal generated according to a second, different dither sequence or algorithm). In other words, the first noise-forming module can be configured to generate noise based on a first dither algorithm. The second noise-forming module can be configured to generate noise based on a second dither algorithm. The first dither algorithm and the second dither algorithm can be different.

[0054] The first and second noise sequences can represent different additive white Gaussian noise (AWGN) or pseudorandom binary sequences (PRBS). The first and second noise sequences can be generated, for example, by the error generator.

[0055] Additionally, alternatively, or optionally, the first and second noise-shaping modules can be configured to generate noise based on different lookup tables or different values ​​within a single lookup table. For example, different lookup tables or different values ​​within a single lookup table can result in different (or uncorrelated) noise sequences being generated by the first and second noise-shaping modules.

[0056] Additionally, alternatively or optionally, the first noise shaping module and the second noise shaping module can be configured to generate noise based on different seed values ​​or different cycle lengths.

[0057] Additionally, alternatively, or optionally, the first noise-shaping module and the second noise-shaping module can each include different feedback filters to generate the uncorrelated noise. For example, the first noise-shaping module (and the second noise-shaping module) can each include a feedback loop. For example, the first dither signal (PRBS and / or AWGN) and the second dither signal (PRBS and / or AWGN) can be added at different positions within the first noise-shaping module and / or the second noise-shaping module (e.g., at different positions in the feedback loop). For example, the first dither signal can be applied to the feedback signal 226 (fb) of the first noise-shaping module, and the second dither signal can be applied to the input signal 219 (in_f) of the second noise-shaping module.

[0058] Dithering can also be implemented for other reasons, such as to combat discretization or nonlinearities, and shared dither modules can be used to generate the uncorrelated dither for the two digital-to-analog converter (DAC) modules. Because the noise added to the input signals of the two DAC modules is uncorrelated, any regularity between them can be broken up or reduced, regardless of, for example, the signals they process. Consequently, encounters between the two DAC modules can be randomly distributed and non-periodic. Such randomly occurring disturbances may then produce no noise (or reduce noise).

[0059] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The two examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g., Fig. 1) or subsequently (e.g. Fig. Examples described in 3-7) will be mentioned.

[0060] Fig. Figure 3a shows an example of a device 300 for providing oscillator signals, which includes a coarse time delay module and a fine time delay module according to an example. The device 300 may additionally or optionally include one or more or all of the features of the device already described with regard to Fig. 1 and Fig. 2 was described.

[0061] The first Digital Time Converter Module 101 (which is similar to the first Digital Time Converter Module 101 from Fig. (1 can be) can include a coarse time delay module 331 configured to generate at least one coarse delay oscillator signal 333 associated with a coarse oscillator frequency.

[0062] The first digital time converter module 101 can further comprise a fine time delay module 332 configured to generate the first oscillator signal 102 having a variable time delay based on at least one coarse delay oscillator signal 333 and a fine time delay.

[0063] The coarse time delay module 331 can be configured to provide or generate the coarse oscillator signal 333 based on the reference oscillator signal 334. For example, the period of the coarse oscillator signal 333 generated by the coarse time delay module 331 can be equal to the period of the reference oscillator signal 334 or exclusively longer (e.g., not shorter than the period of the reference oscillator signal 334). Additionally or optionally, the coarse oscillator frequency can be, for example, a partial harmonic of a frequency of the reference oscillator signal 334.

[0064] The fine time delay module 332 can comprise a plurality of inverter circuits or a digitally controlled edge interpolator (DCEI). For example, the fine time delay module 332 can be controlled by the adapted input signal 103 to provide the first oscillator signal 102, which is set by a fine time delay. For example, the fine time delay can be smaller than a minimum or maximum period of the coarse delay oscillator signal 333, provided by the coarse time delay module 331. For example, the fine time delay module 332 can be configured to generate a fine time delay that is smaller than one period of the reference oscillator signal 334. For example, the fine time delay can be between zero and one period of the reference oscillator signal 334.

[0065] Additionally, optionally or alternatively, one period of the coarse delay oscillator signal 333, generated by the coarse time delay module 331, may exhibit (or have) a coarse time delay based on the added noise that modifies at least one bit (e.g., one or more most significant bits) of a control bit sequence of the first input signal.

[0066] For example, the period of the (adapted) coarse delay oscillator signal exhibiting the coarse time delay (e.g., generated based on the adapted input signal containing one or more most significant bits that are modified based on the added noise) can be greater than the period of the coarse delay oscillator signal without the coarse time delay (e.g., generated based on an adapted input signal containing one or more unchanged most significant bits). The coarse time delay can also increase the period of the (adapted) coarse delay oscillator signal by an integer multiple of the period of a coarse delay oscillator signal that would have been generated based on an adapted input signal containing one or more unchanged most significant bits. This integer can be greater than or equal to 2.

[0067] Additionally, optionally, or alternatively, the first digital time converter module 101 may include one or more mean time delay modules, which may be configured to generate one or more mean delay oscillator signals based on the reference oscillator signal 334. For example, the first digital time converter module 101 may be a multi-stage digital time converter. One period of the mean delay oscillator signal may be a mean time delay. For example, the mean time delay may increase the period of the (adapted) coarse delay oscillator signal by less than one period of a coarse delay oscillator signal that would have been generated based on an adapted input signal having one or more unaltered most significant bits. For example, the mean time delay may be greater than the fine time delay and / or greater than one period of the reference oscillator signal 334.

[0068] For example, one or more medium time delay modules can be connected to the coarse time delay module 331, or can be part of the coarse time delay module 331 and be controlled by one or more most significant bits of the control bit sequences. This can provide a higher resolution, corresponding to the input oscillation from the local oscillator. Optionally or alternatively, one or more medium time delay modules can be connected to the fine time delay module 332, or can be part of the fine time delay module 332, and, for example, be controlled by one or more least significant bits of the control bit sequences. Optionally or alternatively, one or more medium time delay modules can be connected between the coarse time delay module 331 and the fine time delay module 332.

[0069] The first digital time converter module 101 can be configured to provide the first oscillator signal 102, which includes a variable time delay based solely on the fine time delay provided, for example, by the fine time delay module. Additionally, optionally, or alternatively, the first digital time converter module 101 can be configured to provide the first oscillator signal 102, which includes a variable time delay based on the fine time delay and a medium time delay provided, for example, solely by the medium time delay module.Additionally, optionally or alternatively, the first digital time converter module 101 can be configured to provide the first oscillator signal 102, which includes a variable time delay based on the fine time delay, the medium time delay, and a coarse time delay, provided, for example, by the coarse time delay module 331. (For example, it may be possible for a coarse stage to operate at a lower frequency, followed by a fine or medium stage operating at a higher frequency.)

[0070] By shifting (or delaying) the first oscillator signal 102 by a whole step (e.g. by a coarse or medium step), an overlap of the drain at the supply voltage (VCC) can be avoided and the deterioration of the behavior can be prevented.

[0071] The preprocessing block 338 can be configured to generate the desired delay to be introduced (or inserted) into the LO signal to generate the first oscillator signal 102. The desired delay can be generated based on an input signal format that may not directly contain this delay information but may, for example, contain phase information or any information characterizing the desired modulation, in any format. The delay of the coarse time delay module 331 can be parameterized by the most significant bits of the adapted input signal 103 generated by preprocessing block 338, while the delay of the fine time delay module 332 can be parameterized by the least significant bits of the adapted input signal 103 generated by preprocessing block 338.The preprocessing block 338 can thus generate specific input signals 103 for the coarse time delay module 331 and the fine time delay module 332. However, there may not be a preset split according to the bits of the adapted input signal 103; that is, some of the bits can affect both the coarse time delay module 331 and the fine time delay module 332, but usually the most significant or least significant bits primarily affect the coarse or fine time delay modules 331 and 332, respectively.

[0072] While each DTC has several digital stages, the fine-tuning stage operates analogously, for example, by interpolating between two edges at given times. Fine-tuning can be achieved by selecting stronger or weaker drivers triggered by the two adjacent "digital" edges. This concept can be referred to as digitally controlled edge interpolation (DCEI). Different driver strengths can be selected by activating a different number of elementary drivers.

[0073] The driver strength can also depend on the supply voltage (VCC). When triggered, these drivers can also draw current from VCC and cause VCC ripple. If two (or more) digital time converter (DTC) modules operate simultaneously, they can interfere with each other, as they both cause VCC ripple and are themselves affected by the ripple generated by the other DTC. However, the use of multiple DTC modules may be necessary for multiband, carrier aggregation, multistandard, and multi-module devices that incorporate multiple radio frequency (RF) sections, which can be implemented using multiple DTC modules.

[0074] The coarse stage (coarse time delay module 331) can select two edges of a frequency source (e.g., the reference oscillator signal 334) at an approximately desired timing. These selected edges are then used in time instances 1 and 2. Fig. Figure 3b shows that the coarse time delay module 331 can be configured to select the two edges based on control information provided in one or more of the most significant bits of the control bit sequences. For example, the coarse time delay module 331 can be configured to select edges of the reference oscillator signal 334 such that an output oscillator signal 333 can have a period equal to or longer than the period of the reference oscillator signal 334. Additionally or optionally, the coarse time delay module 331 can be configured to select edges of the reference oscillator signal 334 such that the output oscillator signal 333 can have a period exhibiting a coarse oscillator delay or a period with a medium oscillator delay, based on added noise that modifies the most significant bits of the adapted input signal.

[0075] The coarse time delay module 331 can connect these two edges with two sets of inverters 335 and 336 of the fine time delay module 332 (shown in Fig. 3b below). For example, the coarse time delay module 331 can provide a (first) coarse delay oscillator signal associated with the first edge of the first set of inverters 335, and a (second) coarse delay oscillator signal associated with the second edge of the second set of inverters 336. The period of at least one coarse oscillator signal can be the time between the (first) edge of the (first) coarse delay oscillator signal and the (second) edge of the (second) coarse delay oscillator signal.

[0076] One or more additional dithering processes (e.g., similar to the dithering process used with regard to Fig. 2 described), can be used to generate the added noise to introduce the coarse time delay (e.g., at least one step of the coarse stage) or the medium time delay, in addition to the fine tuning by the fine time delay module (e.g., there is a shift of more than the tuning range of the fine stage).

[0077] Fig. Figure 3b shows a schematic representation of an implementation of the operation of a fine-time delay module. In the fine stage (e.g., fine-time delay module 332), a selected number of "upper" inverters at 331 can be switched on at a first time point or time instance (1), and another selected number of inverters at 336 can be switched on at a second time point (2). The slope of the output voltage, measured across capacitor 337, can depend on the number of active inverters (acting as current sources). In this way, the output timing, e.g., the fine time delay when the voltage Vthreshold of the subsequent trigger is reached, can be selected by choosing the appropriate number of inverters at 335 and 336.

[0078] Since the slope depends not only on the number of inverters (shown in the array of curves for different numbers) but also on the voltage at which they are operated, this voltage can be affected if another DTC happens to switch simultaneously, as the same edges were selected in the coarse stage of this digital time converter module. The other DTC can cause a load on VCC, which can also reduce the supply voltage for the first DTC and affect its operation. This can also delay the DTC output. If such delays occur regularly, for example, due to regular beating (or matching) of the frequencies generated by the two digital time converter modules, this regular timing error can, for example, introduce noise into the output spectrum.

[0079] By adding uncorrelated noise to the first input signal 107 and the second input signal 111, dithering can be used to avoid interference due to non-idealities in the circuit design by intentionally generating larger deviations from an ideal signal than necessary. By feeding the error back in a feedback loop to obtain the correct result on average, interference can be avoided, as this also breaks up regularities. Strictly repetitive errors can be avoided in this way (replaced by larger, non-repetitive deviations), thus eliminating interference at the cost of a slightly higher background noise. However, the error may not be apparent at any of the digital-to-time converter modules and therefore cannot be addressed there.

[0080] The various examples described herein can apply to a fine time-delay module (implementing a DCEI) and other DTC implementations except those where a fine stage selects one of a set of edges from a given oscillator. Without a fine time-delay module, the resolution would be limited to the generated set of edges (in the coarse stage). Instead of a DCEI, an array of inverters with adjustable delay can be used (e.g., by adjusting the number of inverters, the inverter supply voltage, or the load experienced by the inverters). The available supply voltage also affects the effective delay in these cases. The examples can refer to a DCEI and an array of inverters used as the delay module. Optionally or alternatively, other adjustable delay means can be used.

[0081] Instead of using two time delay modules, three or more time delay modules can be used (e.g., a coarse time delay module followed by a medium time delay module followed by a fine time delay module). For example, the coarse time delay module can set the delay with a resolution of the reference oscillator signal 334. The coarse (or medium) time delay module can set the delay with a resolution of the reference oscillator signal 334 divided by a small number (e.g., one-quarter), and the fine time delay module can set the delay with a resolution of the reference oscillator signal 334 divided by a larger number (e.g., one-sixteenth). The medium and fine time delay modules can use different implementations (e.g.,The medium time delay module can use a series of inverters, while the fine time delay module can use a DCEI).

[0082] For example, the added noise can be on the order of the resolution of the mean time delay modulus, but does not affect the coarse time delay modulus (apart from possible carry effects, as explained previously). Thus, least significant bits can affect the fine time delay modulus, and most significant bits can affect both the mean and coarse time delay moduli. Consequently, most significant bits can already correspond to a resolution that is less than the period of the reference oscillator signal 334.

[0083] Additionally, alternatively, or optionally, the intermediate time delay modules of different digital-to-analog converter (DAC) modules (e.g., the first DAC module 101 and the second DAC module 104) can use different implementations, thus also decorrelating the time grid as seen through the subsequent fine time delay modules, and thereby reducing the effect of interdependent behavior due to VCC ripple. For example, if an intermediate time delay module has a selectable number of inverters arranged in series, the different modules can use a different number of inverters with different elementary delays to achieve the same overall delay span but with a (at least somewhat) different resolution. This significantly reduces the chances that the two successive time delay modules, for example,are active at exactly the same time.

[0084] Additionally, alternatively, or optionally, the delay range of the fine time delay module can be greater than the resolution of the coarse time delay module (or the medium time delay module if more than two time delay modules are used within a digital time converter module 101). This allows some of the added noise or randomness affecting the coarse time delay module's setting to be compensated for by the fine time delay module. For example, if the delay of the coarse time delay module is reduced by a resolution step of the coarse time delay module compared to the ideal setting, the delay of the fine time delay module can be increased by a similar amount without exceeding the fine time delay module's range.In this way, no error or only a minor error is introduced into the final output signal. Nevertheless, decorrelation can be achieved, for example, in comparison to the timing in a second time converter module 101.

[0085] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The three examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g., Fig. 1 and Fig. 2) or subsequently (e.g. Fig. Examples described in 4-7) will be mentioned.

[0086] Fig. Figure 4 shows a device 400 for providing oscillator signals according to an example.

[0087] The oscillator signal-providing device 400 comprises a first digital time-conversion means 401 configured to generate a first oscillator signal 402 based on a first adapted input signal 403. The oscillator signal-providing device 400 further comprises a second digital time-conversion means 404 configured to generate a second oscillator signal 405. The oscillator signal-providing device 400 further comprises a first processing means for generating adapted input signals 406, configured to generate the first adapted input signal 403 of the first digital time-conversion means 401 by adding noise to a first input signal 407.

[0088] Since the device 400 adds noise to the first input signal 407 to generate the first matched input signal 403, a reduction in interference and more accurate time delay of the oscillator signals by the two digital time converter modules can be achieved. Adding noise to the first input signal can lead to temporal (e.g., time) variation or deviation of processes (e.g., delay processes) performed by the first digital time converter 401, which can prevent or reduce interference between signals provided by the first digital time converter 401 and the second digital time converter 404. This can, for example, reduce or minimize interference between the first digital time converter 401 and the second digital time converter 404.

[0089] For example, the first input signal 407 can be a digital signal comprising successive control bit sequences for controlling a variable time delay of the first digital time conversion device 401.

[0090] For example, one or more least significant bits of the control bit sequences can be changed by a random number or a pseudorandom number to add the noise.

[0091] ZB, the first digital time conversion device 401 can be configured to generate the first oscillator signal 402, and the second digital time conversion device 404 can be configured to generate the second oscillator signal 405, based on the same reference oscillator signal.

[0092] ZB can be configured as a second processing means for generating adapted input signals 409 in order to generate a second adapted input signal 412 by adding noise to a second input signal 411. The second means for digital time conversion 404 can be configured to provide the second oscillator signal 405 based on the second adapted input signal 412.

[0093] For example, the noise added to the first input signal and the noise added to the second input signal may be uncorrelated.

[0094] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The four examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g., Fig. 1 to 3) or subsequently (e.g. Fig. Examples described in 5-7) will be mentioned.

[0095] Fig. Figure 5 shows a transmitter 500 according to an example. The transmitter 500 comprises a first mixer module 551, which is configured to generate a first radio frequency transmit signal 552 by mixing a first amplitude signal 553 with an oscillator signal 102.

[0096] The transmitter 500 comprises a second mixer module 554 configured to generate a second radio frequency transmit signal 555 by mixing a second amplitude signal 556 with a second oscillator signal 105. The transmitter 500 also includes an oscillator signal supply device configured to generate the first oscillator signal 102 and the second oscillator signal 103.

[0097] The device may include one, more, or all of the features already described with respect to the devices for providing oscillator signals according to the preceding figures. For example, the device may include the first digital time converter module 101 and the second digital time converter module 104.

[0098] The transmitter 500 can further include a baseband processor module 520 for generating at least the digital (e.g., baseband) signal to be transmitted and / or for processing a baseband signal. Digitized in-phase (I) and quadrature (Q) signals can be provided, for example, based on the baseband signal.

[0099] The transmitter 500 can, for example, be a polar transmitter. The transmitter 500 can further comprise a polar coordinate provider 559, which can be configured to receive signals in a digital IQ representation (I: in-phase, Q: quadrature) from the baseband processor module 520, and to translate the signal from the IQ representation into polar coordinates, wherein the amplitude or magnitude is described by the digital amplitude signal AM, and the phase is described by the phase signal PM, which is provided by the polar coordinate provider 559 (corresponding to the digital signal).

[0100] The transmitter 500 can further include a power amplifier 557, which is connected to an output of each mixer module 551, 554 via a suitable, optional transmission path (which includes, for example, an amplifier and a matching network) to transmit the amplitude and phase modulated transmit signal 552, 555 to the antenna.

[0101] Other examples may refer to a transmitter, a receiver, or a transceiver comprising the device described above. Additionally, optionally, or alternatively, the transmitter 500 may be part of a radio frequency (RF) transceiver. Although a transmitter (e.g., a polar transmitter) has been described, optionally, additionally, or alternatively, the first digital time converter module 101 and the second digital time converter module 104 of the device may be used to generate, for example, the I and Q signals in an IQ transmitter or the required I and Q signals in a receiver and / or a radio frequency (RF) transceiver.

[0102] The components of the transceiver 500 (e.g., the baseband processor module 520, the polar coordinate provider, the device (100, 150, 300, 400), the first mixer module 551, the second mixer module 554) can, for example, be formed on the same semiconductor chip. The chip can include a chip circuit arrangement for RF generation (e.g., for cellular transmission such as GSM, UMTS, LTE, or others, or for connectivity via Wi-Fi or Bluetooth).

[0103] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The 5 examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g. Fig. 1 to 4) or subsequently (e.g. Fig. Examples described in 6-7) will be mentioned.

[0104] Fig. Figure 6 shows a schematic representation of a mobile device 600. The mobile device comprises a device for providing oscillator signals (e.g., 100, 150, 200, 300) or a means for providing oscillator signals (e.g., 400), which is located in Fig. The mobile device 600, as described in sections 1-5, is implemented in or within a transmitter (e.g., 500). Furthermore, the mobile device 600 includes a baseband processor module 520 for generating at least the digital (e.g., baseband) signal to be transmitted and / or for processing a baseband signal. Additionally, the mobile device 600 includes a power supply unit 630, which supplies power to at least the transmitter 500 and the baseband processor module 520.

[0105] In some examples, the power supply unit 630 may be integrated or implemented at least as part of the variable power supply module described in previous examples.

[0106] Further examples relate to a mobile device (e.g., a mobile phone, tablet, or laptop) that includes a transmitter, a receiver, or a transceiver having the device described above. The mobile device or mobile connection can be used to communicate in a mobile communication system. In some examples, a mobile phone may include a transmitter or a transceiver having a digital-to-analog converter circuit according to the proposed concept or one or more of the examples described above.

[0107] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The six examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g., Fig. 1 to 5) or subsequently (e.g. Fig. 7) described examples are mentioned.

[0108] Fig. Figure 7 shows a method 700 for providing oscillator signals according to an example.

[0109] Method 700 comprises generating (710) a first adapted input signal by a first processing module by adding noise to a first input signal.

[0110] Method 700 comprises generating (720) a first oscillator signal based on a first adapted input signal by a first digital time converter module.

[0111] Method 700 includes generating (730) a second oscillator signal by a second digital time converter module.

[0112] Due to the addition of noise to an initial input signal to generate the first, adapted input signal, a reduction in interference and oscillator signals with a more accurate time delay can be achieved by the two digital time converter modules.

[0113] Method 700 can further include adding noise to modify at least one bit of the control bit sequences of the first input signal, which includes information for setting a fine time delay.

[0114] Method 700 may further include changing one or more least significant bits of the control bit sequences of the input signal by a random number or a pseudorandom number to add the noise.

[0115] Method 700 can further include generating the first oscillator signal and the second oscillator signal based on the same reference oscillator signal.

[0116] Method 700 can further include generating a second, matched input signal by a second processing module by adding noise to a second input signal. Method 700 can further include providing the second oscillator signal based on the second, matched input signal by the second digital time converter module, which may be uncorrelated.

[0117] Further details and aspects will be mentioned in connection with the examples described above or below. The in Fig. The 7 examples shown may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the preceding (e.g. Fig. 1 to 6) or the examples described below.

[0118] Several examples refer to a machine-readable storage medium that contains program code which, when executed, causes a machine to perform procedure 700.

[0119] Several examples refer to a machine-readable storage that includes machine-readable instructions which, when executed, implement the procedure 700 or realize a device 100, 150, 300, 400.

[0120] Several examples refer to a computer program with program code for executing procedure 700 when the computer program is executed on a computer or processor.

[0121] There is a need to provide a concept for generating oscillator signals that suffer from reduced or minimal interference between two adjacent digital-to-analog converter modules. This need can be met by examples such as those described above and below.

[0122] Several examples relate to avoiding interference between two digital-to-analog converter (DAC) modules due to VCC ripple through independent dithering. Several examples relate to combining two dithering stages, which may be intentionally uncorrelated. The two dithering algorithms can be different but do not need to interact. This can, for example, simplify implementations.

[0123] Several examples refer to the use of dithering to smooth out interference caused by recurring errors from repeatedly interfering digital-to-analog converter (DAC) modules. However, this may require detecting this interference (e.g., that both DAC modules have selected the same edge in their coarse steps) to be able to counteract these instances, similar to quantization error. This can necessitate close coupling of the two DAC modules, which can involve high-rate signals, a disadvantage. Either the DAC modules must be placed close to each other, which worsens their interference, or high-rate buses must be laid out across the chip, which consumes area and power and also introduces interference.

[0124] In some examples, blocking capacitors may be implemented to block ripple on VCC. Additionally, independent power sources, such as multiple LDOs, may be provided. However, these can be expensive, both on-chip (capacitors need to be large to provide sufficient capacitance to prevent ripple) and off-chip due to additional pad area and components.

[0125] Aspects and features (e.g., the device for providing oscillator signals, the first digital time converter module, the second digital time converter module, the first processing module, the second processing module, the first input signal, the first adapted input signal, the second input signal, the second adapted input signal, the uncorrelated noise, the coarse time delay module, the fine time delay module, the noise shaping module, the first mixer module, the second mixer module, the baseband processor module) mentioned in connection with one or more specific examples can be combined with one or more of the other examples.

[0126] An oscillator signal can be a signal generated by a circuit arrangement for transmission as a radio frequency (RF) signal. The oscillator signal can be generated at the final RF frequency or at another frequency and subsequently converted to the final transmission frequency, for example, by mixing. The oscillator signal can be modulated in phase, amplitude, or both; at least the phase modulation can be achieved using a digital-to-analog converter (DAC) module.

[0127] The coarse oscillator signal can be a rough intermediate oscillator signal used to derive an oscillator signal. The period of the coarse oscillator signal, or the oscillator signal itself, can indicate the temporal resolution with which the coarse oscillator signal or the oscillator signal is generated; it can also be called the resolution or granularity (e.g., temporal resolution or granularity) of the coarse oscillator signal or the corresponding circuitry that generates it. This accuracy of the coarse or fine oscillator signals can also be characterized by the (coarse or fine) oscillator frequency, which may be related to the inverse of the (coarse or fine) oscillator period. For example,This can be the period or frequency of a reference oscillator signal that is fed to or generated in some components of the (coarse or fine) digital time converter module, but depending on the implementation of the digital time converter, this frequency may only be a characterization of the digital time converter module without being explicitly provided to it.

[0128] The following examples refer to further examples.

[0129] Example 1 is a device for providing oscillator signals, comprising a first digital-to-analog converter module configured to generate a first oscillator signal based on a first, matched input signal. The device further comprises a second digital-to-analog converter module configured to generate a second oscillator signal. The device further comprises a first processing module configured to generate the first, matched input signal of the first digital-to-analog converter module by adding noise to a first input signal.

[0130] In Example 2, the subject of Example 1 may optionally include the first input signal being a digital signal having successive control bit sequences for controlling a variable time delay of the first digital time converter module.

[0131] In Example 3, the subject of Example 2 can optionally include the fact that the added noise modifies at least one bit of the control bit sequences of the first input signal, which includes information for setting a fine time delay.

[0132] In Example 4, the subject of Example 2 or 3 may optionally include the added noise modifying one or more least significant bits of the control bit sequences, the least significant bits being provided to control a fine time delay module of the first digital time converter module.

[0133] In Example 5, the subject of any of Examples 2 to 4 may optionally include the added noise modifying one or more most significant bits of the control bit sequences, the most significant bits being provided to control a crude time delay module of the first digital time converter module.

[0134] In Example 6, the subject matter of any of Examples 2 to 5 may optionally include changing one or more least significant bits of the control bit sequences or one or more most significant bits of the control bit sequences by a random number or a pseudorandom number to add the noise.

[0135] In Example 7, the subject matter of any of Examples 2 to 4 may optionally include that the added noise leaves one or more most significant bits of the control bit sequences unchanged, the most significant bits containing information to control a crude time delay module of the first digital time converter module.

[0136] In Example 8, the subject matter from any of the preceding examples may optionally include the first digital time converter module being configured to generate the first oscillator signal, and the second digital time converter module being configured to generate the second oscillator signal based on an identical reference oscillator signal.

[0137] In Example 9, the subject matter from any of the preceding examples may optionally include that the first processing module has a noise shaping module for generating the noise to be added to the first input signal.

[0138] In Example 10, the subject matter of any of the preceding examples may optionally include that the device further comprises a second processing module configured to generate a second adapted input signal by adding noise to a second input signal, wherein the second digital time converter module is configured to generate the second oscillator signal based on the second adapted input signal.

[0139] In Example 11, the subject of Example 10 may optionally include that the noise added to the first input signal and the noise added to the second input signal are uncorrelated.

[0140] In Example 12, the subject of Example 11 may optionally include the first processing module being configured to perform a chopping or encryption of the first input signal, and the second processing module being configured to perform a different chopping or encryption of the second input signal to generate the uncorrelated noise.

[0141] In Example 13, the subject of Example 11 or 12 may optionally include the first processing module having a first noise-forming module and the second processing module having a second noise-forming module, wherein the first noise-forming module and the second noise-forming module are configured to generate uncorrelated noise in the first adapted input signal and the second adapted input signal.

[0142] In Example 14, the subject of Example 13 can optionally include the first noise shaping module and the second noise shaping module each having a feedback loop.

[0143] In Example 15, the subject of Example 13 or 14 may optionally include the first noise-shaping module being configured to generate noise based on a first noise sequence, and the second noise-shaping module being configured to generate noise based on a second noise sequence, wherein the first noise sequence and the second noise sequence represent different additive white Gaussian noise or pseudorandom binary sequences.

[0144] In Example 16, the subject matter can optionally include from any of Examples 13 to 15 that the first noise shaping module and the second noise shaping module are configured to generate noise based on different lookup tables.

[0145] In Example 17, the subject matter can optionally include, from any of Examples 13 to 16, that the first noise shaping module and the second noise shaping module are configured to generate noise based on different seed values ​​or different cycle lengths.

[0146] In Example 18, the subject of any of Examples 13 to 18 may optionally include the first noise-shaping module being trained to generate noise based on a first dither algorithm, and the second noise-shaping module being trained to generate noise based on a second dither algorithm, wherein the first dither algorithm and the second dither algorithm are different.

[0147] In Example 19, the subject matter of any of Examples 13 to 19 may optionally include the first dither signal and the second dither signal being added to different positions within the first noise shaping module and / or the second noise shaping module.

[0148] In Example 20, the subject matter can optionally include, from any of Examples 13 to 19, that the first noise shaping module and the second noise shaping module are identical noise shaping modules.

[0149] In Example 21, the subject matter of any of Examples 13 to 19 may optionally include the first noise shaping module and the second noise shaping module each comprising different feedback filters to generate the uncorrelated noise.

[0150] In Example 22, the subject matter from any of the preceding examples may optionally include the first digital time converter module comprising a coarse time delay module configured to generate at least one coarse delay oscillator signal associated with a coarse oscillator frequency, and a fine time delay module configured to generate the first oscillator signal having a variable time delay based on the at least one coarse delay oscillator signal and a fine time delay.

[0151] In Example 23, the subject of Example 22 may optionally include the coarse time delay module being configured to provide the at least one coarse delay oscillator signal, wherein one period of the at least one coarse delay oscillator signal has a coarse time delay based on the added noise that modifies at least one bit of a control bit sequence of the first input signal.

[0152] In Example 24, the subject of Example 22 or 23 may optionally include the coarse time delay module being configured to generate at least one coarse oscillator signal based on a reference oscillator signal, wherein the period of the coarse oscillator signal is equal to or exclusively longer than the period of the reference oscillator signal.

[0153] In Example 25, the subject of Example 22 or 23 may optionally include the coarse time delay module being configured to generate at least one coarse oscillator signal based on a reference oscillator signal, wherein the coarse oscillator frequency is a partial harmonic of a frequency of the reference oscillator signal.

[0154] In Example 26, the subject matter of one of Examples 22-25 may optionally include the fine time delay module having a plurality of inverter circuits or a digitally controlled edge interpolator.

[0155] In Example 27, the subject matter may optionally include from any of Examples 22-26 that the fine time delay module is controlled by the adapted input signal to provide the first oscillator signal, which is set by a fine time delay.

[0156] In Example 28, the subject matter may optionally include from any of Examples 22-27 that the fine time delay is smaller than a minimum period of the coarse delay oscillator signal that can be provided by the coarse time delay module.

[0157] In Example 29, the subject can optionally include from any of Examples 22-28 that the fine time delay is between zero and one period of the reference oscillator signal.

[0158] Example 30 is an oscillator signal-providing device comprising a first digital time-conversion means configured to generate a first oscillator signal based on a first matched input signal. The oscillator signal-providing device further comprises a second digital time-conversion means configured to generate a second oscillator signal. The oscillator signal-providing device further comprises a first processing means for generating matched input signals, configured to generate the first matched input signal of the first digital time-conversion means by adding noise to a first input signal.

[0159] In Example 31, the subject of Example 30 may optionally include the first input signal being a digital signal having successive control bit sequences for controlling a variable time delay of the first digital time converter module.

[0160] In Example 32, the subject of Example 30 or 31 may optionally include changing one or more least significant bits of the control bit sequences by a random number or pseudorandom number to add the noise.

[0161] In Example 33, the subject matter of any of Examples 30-32 may optionally include the first digital time conversion means configured to generate the first oscillator signal, and the second digital time conversion means configured to generate the second oscillator signal based on the same reference oscillator signal.

[0162] In Example 34, the subject matter of one of Examples 30-33 may optionally include a second processing means for generating adapted input signals, configured to generate a second adapted input signal by adding noise to a second input signal, wherein the second means is configured for digital time conversion to provide the second oscillator signal based on the second adapted input signal.

[0163] In Example 35, the subject of Example 34 may optionally include that the noise added to the first input signal and the noise added to the second input signal are uncorrelated.

[0164] Example 36 is a transmitter comprising a first mixer module configured to generate a first radio frequency transmit signal by mixing a first amplitude signal with a first oscillator signal. The transmitter further comprises a second mixer module configured to generate a second radio frequency transmit signal by mixing a second amplitude signal with a second oscillator signal. The transmitter further comprises a device for providing oscillator signals according to any one of the preceding claims, configured to generate the first oscillator signal and the second oscillator signal.

[0165] Example 37 is a transmitter, a receiver or a transmit-receiver comprising a device according to any of the preceding examples.

[0166] Example 38 is a mobile device comprising a transmitter, a receiver or a transceiver as defined in Example 37.

[0167] Example 39 is a method for providing oscillator signals, comprising the generation of a first, adapted input signal by a first processing module by adding noise to a first input signal. The method further comprises the generation of a first oscillator signal based on the first, adapted input signal by a first digital-to-time converter module. The method further comprises the generation of a second oscillator signal by a second digital-to-time converter module.

[0168] In Example 40, the subject of Example 39 may optionally include the addition of noise to modify at least one bit of the control bit sequences of the first input signal, which includes information for setting a fine time delay.

[0169] In Example 41, the subject of Example 39 or 40 may optionally include changing one or more least significant bits of control bit sequences of the input signal by a random number or a pseudorandom number to add the noise.

[0170] In Example 42, the subject of any of Examples 39-41 may optionally include generating the first oscillator signal and the second oscillator signal based on the same reference oscillator signal.

[0171] In Example 43, the subject matter may optionally include from any of Examples 39-42 the generation of a second, adapted input signal by a second processing module by adding noise to a second input signal, and the provision of the second oscillator signal by the second digital time converter module based on the second, adapted input signal.

[0172] In Example 44, the subject of Example 43 may optionally include that the noise added to the first input signal and the noise added to the second input signal are uncorrelated.

[0173] Example 45 is a machine-readable storage medium comprising program code which, when executed, causes a machine to perform the procedure according to one of Examples 39-44.

[0174] Example 46 is a machine-readable storage device that includes machine-readable instructions which, when executed, implement a procedure or realize a device according to one of the preceding examples.

[0175] Example 47 is a computer program with program code for performing the procedure of any of Examples 39-44 when the computer program is run on a computer or processor.

[0176] Further embodiments may provide a computer program with program code for performing one of the above methods when the computer program is executed on a computer or processor. A person skilled in the art would readily recognize that steps of various methods described above can be performed by programmed computers. Some embodiments are intended to include program storage devices, such as digital data storage media, that are machine- or computer-readable and encode machine-executable or computer-executable programs of instructions, wherein the instructions perform some or all of the actions of the methods described above. The program storage devices may be, for example, digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media.The exemplary implementations should also cover computers programmed to perform the actions of the procedures described above, or (field) programmable logic arrays ((F)PLA - (Field) Programmable Logic Arrays) or (field) programmable gate arrays ((F)PGA - (Field) Programmable Gate Arrays) programmed to perform the actions of the procedures described above.

[0177] The description and drawings only illustrate the principles of the disclosure. It is therefore understood that the person skilled in the art may derive various arrangements which, although not expressly described or illustrated here, embody the principles of the disclosure and are contained within its meaning and scope. Furthermore, all examples listed here are intended solely for teaching purposes, to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to the advancement of technology, and should be understood as serving without limitation to such specifically listed examples and conditions. Furthermore, all statements made here concerning principles, aspects, and examples of the disclosure, as well as specific embodiments thereof, are intended to encompass their equivalents.

[0178] Functional blocks designated as "means for..." (executing a certain function) are to be understood as comprehensive circuits, each configured to perform a specific function. Therefore, a "means for something" can also be understood as "means configured for or suitable for something." A means configured to perform a certain function does not necessarily mean that such a means will actually perform the function (at a given moment in time).

[0179] The functions of various elements depicted in the figures, including each functional block designated as "means," "means of providing a sensor signal," "means of generating a transmit signal," etc., can be provided by dedicated hardware such as "a signal provider," "a signal processing unit," "a processor," "a controller," etc., as well as by hardware capable of executing software in conjunction with associated software. Furthermore, each instance described herein as "means" could be implemented as or correspond to "one or more modules," "one or more devices," "one or more units," etc. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared.Furthermore, the explicit use of the terms "processor" or "controller" should not be interpreted as referring exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), read-only memory (ROMs) for storing software, random-access memory (RAMs), and non-volatile storage. Other hardware, both conventional and / or custom-designed, may also be included.

[0180] The person skilled in the art should understand that all block diagrams herein represent conceptual views of exemplary circuits embodying the principles of the disclosure. Similarly, it is understood that all flowcharts, process diagrams, state transition diagrams, pseudocode, and the like represent various processes, essentially depicted in a computer-readable medium and thus executed by a computer or processor, irrespective of whether such a computer or processor is explicitly shown.

[0181] Furthermore, the following claims are hereby included in the detailed description, where each claim can stand alone as a separate embodiment. While each claim can stand alone as a separate example, it should be noted that—although a dependent claim may refer in the claims to a particular combination with one or more other claims—other embodiments may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. These combinations are suggested here unless it is stated that a particular combination is not intended. Furthermore, features of a claim are also intended to be included for any other independent claim, even if that claim is not directly dependent on the independent claim.

[0182] It should also be noted that methods disclosed in the description or in the claims may be implemented by a device with means for carrying out each of the respective actions of these methods.

[0183] Furthermore, it is understood that the disclosure of multiple actions or functions revealed in the description or claims may not be interpreted as being in a specific order. The disclosure of multiple actions or functions therefore does not limit them to a specific order, unless these actions or functions are not interchangeable for technical reasons. Furthermore, in some embodiments, a single action may include or be broken down into several sub-actions. Such sub-actions may be included and form part of the disclosure of that single action unless they are expressly excluded.

Claims

[1] A device (100, 150, 300, 400) for providing oscillator signals, comprising: a first digital time converter module (101) configured to generate a first oscillator signal (102) based on a first adapted input signal (103); a second digital time converter module (104) which is configured to be a second to generate oscillator signal (105); a first processing module (106) configured to generate the first adapted input signal (103) of the first digital time converter module (101) by adding noise to a first input signal (107); and a second processing module (109) configured to generate a second adapted input signal (112) by adding noise to a second input signal (111), wherein the second digital time converter module (104) is configured to generate the second oscillator signal (105) based on the second adapted input signal (112), and where the noise added to the first input signal (107) and the noise added to the second input signal (111) are uncorrelated. [2] The device (100, 150, 300, 400) according to claim 1, wherein the first input signal (107) is a digital signal comprising successive control bit sequences for controlling a variable time delay of the first digital time converter module (101). [3] The device (100, 150, 300, 400) according to claim 2, wherein the added noise modifies at least one bit of the control bit sequences of the first input signal (107) which includes information for setting a fine time delay. [4] The device (100, 150, 300, 400) according to one of claims 2 or 3, wherein the added noise modifies one or more least significant bits of the control bit sequences, the least significant bits being provided to control a fine time delay module (332) of the first digital time converter module (101). [5] The device (100, 150, 300, 400) according to one of claims 2-4, wherein the added noise modifies one or more most significant bits of the control bit sequences, the most significant bits being provided to control a coarse time delay module (331) of the first digital time converter module (101). [6] The device (100, 150, 300, 400) according to one of claims 2-5, wherein one or more least significant bits of the control bit sequences or one or more most significant bits of the control bit sequences are modified by a random number or a pseudorandom number to add the noise. [7] The device (100, 150, 300, 400) according to one of claims 2-4, wherein the added noise leaves one or more most significant bits of the control bit sequences unchanged, wherein the most significant bits contain information to control a coarse time delay module (331) of the first digital time converter module (101). [8] The device (100, 150, 300, 400) according to one of the preceding claims, wherein the first digital time converter module (101) is configured to generate the first oscillator signal (102) and the second digital time converter module (104) is configured to generate the second oscillator signal (105) based on an identical reference oscillator signal. [9] The device (100, 150, 300, 400) according to one of the preceding claims, wherein the first processing module (106) comprises a noise shaping module for generating the noise to be added to the first input signal. [10] The device (100, 150, 300, 400) according to claim 1, wherein the first processing module (106) is configured to perform chopping or encrypting of the first input signal (107), and the second processing module (109) is configured to perform different chopping or encrypting of the second input signal (111) to generate the uncorrelated noise. [11] The device (100, 150, 300, 400) according to claim 1 or 10, wherein the first processing module (106) has a first noise shaping module (200) and the second processing module (109) has a second noise shaping module, wherein the first noise shaping module and the second noise shaping module are configured to generate uncorrelated noise in the first adapted input signal and the second adapted input signal. [12] The device (100, 150, 300, 400) according to claim 11, wherein the first noise shaping module (200) and the second noise shaping module each have a feedback loop. [13] The device (100, 150, 300, 400) according to claim 11 or 12, wherein the first noise shaping module (200) is configured to generate noise based on a first noise sequence, and the second noise shaping module is configured to generate noise based on a second noise sequence, wherein the first noise sequence and the second noise sequence represent different additive white Gaussian noise or pseudorandom binary sequences. [14] The device (100, 150, 300, 400) according to one of claims 11-13, wherein the first noise shaping module (200) and the second noise shaping module are configured to generate noise based on different lookup tables. [15] The device (100, 150, 300, 400) according to one of claims 11-14, wherein the first noise shaping module (200) and the second noise shaping module are configured to generate noise based on different seed values ​​or different cycle lengths. [16] The device (100, 150, 300, 400) according to one of claims 11-15, wherein the first noise shaping module (200) is configured to generate noise based on a first dither algorithm, and the second noise shaping module is configured to generate noise based on a second dither algorithm, wherein the first dither algorithm and the second dither algorithm are different. [17] The device (100, 150, 300, 400) according to one of claims 11-16, wherein the first dither signal and the second dither signal are added to different positions within the first noise shaping module and the second noise shaping module. [18] The device (100, 150, 300, 400) according to one of claims 11-17, wherein the first noise shaping module (200) and the second noise shaping module are identical noise shaping modules. [19] The device (100, 150, 300, 400) according to one of claims 11-17, wherein the first noise shaping module (200) and the second noise shaping module each comprise different feedback filters to generate the uncorrelated noise. [20] The device (100, 150, 300, 400) according to one of the preceding claims, the first digital time converter module (101) comprising a coarse time delay module (331) configured to generate at least one coarse delay oscillator signal associated with a coarse oscillator frequency, and a fine time delay module (332) configured to generate the first oscillator signal having a variable time delay based on the at least one coarse delay oscillator signal and a fine time delay. [21] One transmitter (500), comprising: a first mixer module (551) configured to generate a first radio frequency transmit signal (552) by mixing a first amplitude signal (553) with a first oscillator signal (102); a second mixer module (554) configured to provide a second radio frequency to generate a transmit signal (555) by mixing a second amplitude signal (556) with a second oscillator signal (105); and a device (100, 150, 300, 400) for providing oscillator signals according to any one of the preceding claims 1-20, which is configured to generate the first oscillator signal (102) and the second oscillator signal (105). [22] A method (700) for providing oscillator signals, the method comprising: Generating (107) a first adapted input signal by a first processing module by adding noise to a first input signal; Generating (720) a first oscillator signal based on the first adapted input signal by a first digital time converter module, Generating (730) a second oscillator signal by a second digital time converter module; and Generating a second, matched input signal (112) by adding noise to a second input signal (111), wherein the second oscillator signal (105) is generated based on the second, matched input signal (112), and wherein the noise added to the first input signal (107) and the noise added to the second input signal (111) are uncorrelated. [23] A machine-readable storage medium comprising program code which, when executed, causes a machine to perform the method according to claim 22.

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