COMPOUND STRUCTURE AND METHOD FOR ITS PREPARATION

Abstract

Method for producing a connection structure comprising the following steps: producing at least one first hole (112) in a first dielectric layer (110); producing a first barrier layer (120) on side walls and a bottom surface of the first hole (112) and on the surface of the first dielectric layer (110); overfilling the first hole (112) with a first conductive material (130) on the first barrier layer (120), and removing the excess first conductive material (130) and the excess barrier layer outside the first hole (112) to produce a first conductor (132) in the first hole (112) and over the first barrier layer (120);Etching back the first dielectric layer (110) to an etching depth in the range of 2.5 nm to 27.5 nm, such that the first conductor (132) has a part that protrudes from the first dielectric layer (110), wherein, during the etching back of the first dielectric layer (110), the barrier layer (120) is etched such that it is coplanar with the dielectric layer (110) after etching;Forming an etch stop layer (140) on the first dielectric layer (110) and the protruding part of the first conductor (132), wherein the etch stop layer (140) has a raised part (R) covering the protruding part of the first conductor (132), and the raised part (R) has a cover part (142) covering a top surface of the protruding part of the first conductor (132), and at least one spacer part (144) arranged on at least one side wall of the protruding part of the first conductor (132), and wherein the cover part (142) has a thickness (TC) in the range of 5 nm to 50 nm and the spacer part (144) has a thickness (TS) in the range of 15 nm to 70 nm, wherein the thickness (TS) of the spacer part (144) is greater than the thickness (TC) of the cover part (142); forming a second dielectric layer (150) on the etch stop layer (140);Producing at least one second hole (152) through the second dielectric layer (150) and the etch stop layer (140) such that the protruding part of the first conductor (132) is at least partially exposed by the second hole (152); and producing a second conductor (172) in the second hole (152).

Description

BACKGROUND OF THE INVENTIONThe word "connection" in the case of VLSIs (very large-scale integrated circuits) means a metal conductor track which connects the various electronic components. The interconnect metal traces are separated from the substrate by insulating layers except on the contact surface. Since the formation of the integrated circuit (IC) in 1960, aluminum or its alloys have become the most important material for connection metal wirings, and silicon dioxide has become the most important material for insulating layers.Copper-based chips are semiconductor integrated circuits, mostly microprocessors, that use copper for interconnections. Since copper is a better conductor than aluminum, chips using this technology can have smaller metal components and consume less power to conduct electricity through them. Together, these effects result in processors with higher performance.A method for producing a semiconductor device is known from US 2005 / 0 130 367 A1. An apparatus and a method for producing an integrated circuit are known from US 2014 / 0 264 926 A1. A semiconductor device is known from US 2014 / 0 312 508 A1. An integrated circuit structure and a production method are known from US 2005 / 0 224 986 A1.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1 to 13 are sectional views of a connection structure in various stages according to some embodiments of the present invention.Detailed DescriptionThe following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. For example, in the description below, the formation of a first element over or on a second element may have embodiments in which the first and second elements are formed in direct contact, and may also have embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "below," "below," "untere©" / "lower," "above," "obere©" / "upper," and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly.Referring to FIG. 1, a first dielectric layer 110 is formed on a substrate. The first dielectric layer 110 is an interlayer dielectric layer (ILD layer). The first dielectric layer 110 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the first dielectric layer 110 is made of a low-k dielectric material to improve resistive-capacitive (RC) delay. The dielectric constant of the low-k dielectric material is smaller than that of silicon dioxide (SiO 2). One method of reducing the dielectric constant of a dielectric material is to incorporate Kohlenstoff© or fluorine (F) atoms. For example, in SiO 2( k=3.9), the dielectric constant is lowered by incorporating C atoms for forming hydrogenated carbon doped silicon oxide (SiCOH) (k is in the range of 2.7 to 3.3) and incorporating F atoms for forming fluorosilicate glass (FSG) (k is in the range of 3.5 to 3.9). Another method of reducing the dielectric constant of a dielectric material is to incorporate an air gap or pores. Since the dielectric constant of air is 1, the dielectric constant of a dielectric layer can be decreased by increasing the porosity of the dielectric layer. In some embodiments, the low-k dielectric material is, for example, porous silicon oxide (i.e., xerogel or aerogel), nonporous carbon-doped oxide (CDO), black diamond (BD), a benzocyclobutene (BCB)-based polymer, an aromatic thermosetting (hydrocarbon) polymer (ATP), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), a polyarylene ether (PAE), nitrogen-doped diamond-like carbon (DLC), or a combination thereof. The first dielectric layer 110 is formed by, for example, chemical vapor deposition (CVD), spin coating, or a combination thereof. The first dielectric layer 110 has a thickness in the range of about 40 nm (about 400 Å) to about 60 nm (about 600 Å).Referring now to FIG. 2, at least one first hole 112 and at least one second hole 114 are formed in the first dielectric layer 110. The first hole 112 and the second hole 114 are formed by a photolithography and etching process. The photolithography and etching process includes applying a photoresist, exposing, developing, etching, and removing the photoresist. A photoresist is applied to the first dielectric layer 110 by spin coating, for example. The photoresist is then precured to remove excess photoresist solvent. After precure, the photoresist is exposed to a pattern of intense light.The intense light is, for example, g-line light having a wavelength of about 436 nm, i-line light having a wavelength of about 365 nm, krypton fluoride (KrF) excimer laser having a wavelength of about 248 nm, argon fluoride (ArF) excimer laser having a wavelength of about 193 nm, fluoride (F 2)- excimer laser having a wavelength of about 157 nm, or a combination thereof. A space between the last lens of the exposure apparatus and the photoresist surface may be filled during exposure with a liquid medium having a refractive index greater than 1 to improve photolithographic resolution. The exposure causes a chemical change which can dissolve a portion of the photoresist in a photographic developer.Then post-exposure baking (PEB) may be performed before development to help reduce standing wave phenomena caused by the extinction and gain patterns of the incident light. The photographic developer is then applied to the photoresist to remove the portion of the photoresist that is soluble in the photographic developer. The remaining photoresist is then postcured to solidify it.The portions of the first dielectric layer 110 not protected by the remaining photoresist are etched to form the first and second holes 112 and 114. The etching of the first dielectric layer 110 may be performed by dry etching, such as reactive ion etching (RIE), plasma enhanced (PE) etching, or inductively coupled plasma etching (ICP etching). In some embodiments, when the first dielectric layer 110 is silicon oxide, fluorine-based RIE may be used to form the first and second holes 112 and 114. The etching gas used for dry etching the first dielectric layer 110 is, for example, CF 4 / O 2, ClF 3, CCl 3 F 5, SF 4 / O 2 or a combination thereof.After the first and second holes 112 and 114 are formed, the photoresist is removed from the first dielectric layer 110 by, for example, resist removal by plasma exposure, peeling, or a combination thereof. In resist removal by plasma exposure, a plasma source is used to generate a monoatomic reactive species, such as oxygen or fluorine. The reactive species binds with the photoresist to form ash which is removed by a vacuum pump. In the stripping, a photoresist solvent such as acetone or a phenol solvent is used to remove the photoresist from the first dielectric layer 110.Referring now to FIG. 3, a first barrier layer 120 is formed on the sidewalls and bottom surfaces of the first and second holes 112 and 114. In FIG. 3, the first barrier layer 120 is further formed on the top surface of the first dielectric layer 110. The first barrier layer 120 is made of a material that can adhere conductors in the first and second holes 112 and 114 to the first dielectric layer 110 and can stop diffusion of the conductors into the first dielectric layer 110. In some embodiments, when the conductors in the first and second holes 112 and 114 are made of copper (Cu), the first barrier layer 120 is made of, for example, tantalum nitride (TaN), Ta / TaN, Ta, or other transition metal-based materials, or a combination thereof. In some other embodiments, when the conductors in the first and second holes 112 and 114 are aluminum, the first barrier layer 120 is, for example, titanium nitride (TiN), Ti / TiN, Ti, or other transition metal-based materials, or a combination thereof. The first barrier layer 120 is formed by, for example, physical vapor deposition (PVD), ionized physical vapor deposition (IPVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof.Referring now to FIG. 4, a first electrically conductive material 130 overfills the first and second holes 112 and 114. The first electrically conductive material 130 is made of a metal such as copper (Cu), aluminum (A1), tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), tantalum (Ta), or a combination thereof. The first electrically conductive material 130 is formed, for example, by electrochemical deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.Referring now to FIG. 5, the excess first electrically conductive material 130 and the excess first barrier layer 120 outside the first and second holes 112 and 114 are removed by a removal process. In some embodiments, the excess first electrically conductive material 130 and the excess first barrier layer 120 are removed using a chemical mechanical polishing (CMP) process. In some embodiments, when the first electrically conductive material 130 is copper (Cu), the CMP slurry is, for example, a mixture of suspended abrasive particles, an oxidizing agent, and a corrosion inhibitor, and the CMP slurry is acidic. A two-step CMP process may be used to remove the excess first electrically conductive material 130 and the excess first barrier layer 120. In the first step, the abrasive removes the loose first electrically conductive material 130 without interfering with the first barrier layer 120. In the second step, the remaining first electrically conductive material 130 and the remaining first barrier layer 120 are removed using a silicon dioxide abrasive. After the CMP process, a first lower conductor 132 is formed in the first hole 112 and a second lower conductor 134 is formed in the second hole 114.Referring now to FIG. 6, the first dielectric layer 110 is etched back. The first and second lower conductors 132 and 134 have a higher etch resistance to etch back than the first dielectric layer 110. Therefore, the first lower conductor 132 has a part protruding from the top surface of the first dielectric layer 110, and the second lower conductor 134 has a part also protruding from the top surface of the first dielectric layer 110. The etch back of the first dielectric layer 110 may be performed by dry etching, such as reactive ion etching (RIE), plasma enhanced etching (PE etching), or inductively coupled plasma etching (ICP etching). In some embodiments, fluorine-based RIE may be used to etch back the first dielectric layer 110. The etching gas used for etching back the first dielectric layer 110 is, for example, CF 4 / O 2, ClF 3, CCl 3 F 5, SF 4 / O 2 or a combination thereof. In some embodiments, the etch back etch the first dielectric layer 110 to an etch depth in the range of about 2.5 nm (about 25 Å) to about 27.5 nm (about 275 Å).Referring now to FIG. 7, an etch stop layer 140 is formed on the first dielectric layer 110 and the protruding portions of the first and second lower conductors 132 and 134.Referring now to FIG. 8, a second dielectric layer 150 is formed on the etch stop layer 140. The second dielectric layer 150 is also an interlayer dielectric (ILD) layer. The second dielectric layer 150 is made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the second dielectric layer 150 is made of a low-k dielectric material, such as hydrogenated carbon doped silicon oxide (SiCOH), fluorosilicate glass (FSG), porous silicon oxide (i.e., xerogel or aerogel), nonporous carbon doped oxide (CDO), black diamond (BD), a benzocyclobutene (BCB)-based polymer, an aromatic thermosetting (hydrocarbon) polymer (ATP), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), a polyarylene ether (PAE), nitrogen doped diamond-like carbon (DLC), or a combination thereof. The second dielectric layer 150 is formed by, for example, chemical vapor deposition (CVD), spin coating, or a combination thereof. The second dielectric layer 150 has a thickness in the range of about 40 nm (about 400 Å) to about 60 nm (about 600 Å).Referring now to FIG. 9, in the second dielectric layer 150, a third hole 152 is formed by a photolithography and etching process. The photolithography and etching process includes applying a photoresist, exposing, developing, and etching. A photoresist is applied to the second dielectric layer 150 by spin coating, for example. The photoresist is then precured to remove excess photoresist solvent. After precure, the photoresist is exposed to a pattern of intense light.The intense light is, for example, g-line light having a wavelength of about 436 nm, i-line light having a wavelength of about 365 nm, krypton fluoride (KrF) excimer laser having a wavelength of about 248 nm, argon fluoride (ArF) excimer laser having a wavelength of about 193 nm, fluoride (F 2)- excimer laser having a wavelength of about 157 nm, or a combination thereof. A space between the last lens of the exposure apparatus and the photoresist surface may be filled during exposure with a liquid medium having a refractive index greater than 1 to improve photolithographic resolution. The exposure causes a chemical change which can dissolve a portion of the photoresist in a photographic developer.Then post-exposure baking (PEB) may be performed before development to help reduce standing wave phenomena caused by the extinction and gain patterns of the incident light. The photographic developer is then applied to the photoresist to remove the portion of the photoresist that is soluble in the photographic developer. The remaining photoresist 155 is then postcured to solidify it.At least a portion of the second dielectric layer 150 not protected by the remaining photoresist is etched to form the third hole 152. The etching of the second dielectric layer 150 may be performed by dry etching, such as reactive ion etching (RIE), plasma enhanced etching (PE etching), or inductively coupled plasma etching (ICP etching). In some embodiments, when the second dielectric layer 150 is made of silicon oxide, fluorine-based RIE may be used to form the third hole 152, and the etching gas used for dry etching the second dielectric layer 150 is, for example, CF 4 / O 2, ClF 3, CCl 3 F 5, SF 4 / O 2 or a combination thereof.The etch stop layer 140 and the second dielectric layer 150 have different etch resistance characteristics. In some embodiments, the etch stop layer 140 is made of a material having a higher etch resistance to the etchant used to etch the third hole 152 than that of the second dielectric layer 150. Therefore, the etching of the second dielectric layer 150 by the etch stop layer 140 is stopped without overetching the first dielectric layer 110. In some embodiments, when the second dielectric layer 150 is made of silicon oxide, the etch stop layer 140 is made of a carbon-rich material, such as silicon carbon nitride (SiCN). The etch stop layer 140 is formed by plasma enhanced chemical vapor deposition (PECVD), for example.The etch stop layer 140 and the first dielectric layer 110 also have different etch resistance properties. In some embodiments, the etch stop layer 140 has a higher etch resistance to the etchant used to etch the third hole 152 than the first dielectric layer 110. Therefore, even if the etch stop layer 140 is overetched when the second dielectric layer 150 is etched, overetch of the etch stop layer 140 is less than overetch of the first dielectric layer 110 without the etch stop layer 140. In some embodiments, when the first dielectric layer 110 is made of silicon oxide, the etch stop layer 140 is made of a carbon-rich material, such as silicon carbon nitride (SiCN).The etch stop layer 140 has a thickness in the range of about 5 nm (about 50 Å) to about 30 nm (about 300 Å). The etch stop layer 140 has raised portions R covering the protruding portions of the first and second lower conductors 132 and 134, respectively. At least one of the raised portions R has a lid portion 142 and at least one spacer portion 144. The cover part 142 covers the upper side of the protruding part of the first lower conductor 132 and / or the second lower conductor 134. The spacer 144 is arranged on at least one side wall of the protruding part of the first lower conductor 132 and / or of the second lower conductor 134. The spacer 144 is thicker than the cover 142. In some embodiments, the cap portion 142 has a thickness TCin the range of about 5 nm (about 50 Å) to about 50 nm (about 500 Å), and the spacer portion 144 has a thickness TSin the range of about 15 nm (about 150 Å) to about 70 nm (about 700 Å).Referring now to FIG. 10, at least a portion of the etch stop layer 140 exposed by the third hole 152 is etched to form an opening 146. The opening 146 communicates with the third hole 152, and the protruding part of the first lower conductor 132 is at least partially exposed from the opening 146. The etching of the etch stop layer 140 may be performed by dry etching, such as reactive ion etching (RIE), plasma enhanced etching (PE etching), or inductively coupled plasma etching (ICP etching). In some embodiments, when the etch stop layer 140 is made of silicon carbon nitride (SiCN), RIE based on fluorine may be used to form the opening 146, and the etching gas for RIE is, for example, C 2 F 6, CF 4 / O 2, CF 4 / H 2, C 3 F 8 or a combination thereof.Since the spacer 144 is thicker than the cap 142, by etching the etch stop layer 140, the cap 142 may be removed to expose the first lower conductor 132 while leaving at least a portion of the spacer 144 on the first dielectric layer 110. That is, the etching of the opening 146 is stopped before the first dielectric layer 110 is reached, and thereby the first dielectric layer 110 is not exposed from the opening 146. In some embodiments, the opening 146 has a depth D in the range of about 0 nm (about 0 Å) to about 10 nm (about 100 Å).After the opening 146 is formed, the photoresist 155 is removed from the second dielectric layer 150 by, for example, resist removal by plasma exposure, peeling, or a combination thereof. In resist removal by plasma exposure, a plasma source is used to generate a monoatomic reactive species, such as oxygen or fluorine. The reactive species binds to the photoresist 155 to form ash, which is removed by a vacuum pump. In the peeling, a photoresist solvent such as acetone or a phenol solvent is used to remove the photoresist 155 from the second dielectric layer 150.Referring now to FIG. 11, a second barrier layer 160 is formed on the sidewalls of the third hole 152 and on the sidewalls and bottom surface of the opening 146. In FIG. 11, the second barrier layer 160 is further formed on the top surface of the second dielectric layer 150. Because the opening 146 has a small aspect ratio, the second barrier layer 160 can be formed in the opening 146 with at least acceptable step coverage. The second barrier layer 160 is made of a material with which a conductor in the third hole 152 and the opening 146 may be adhered to the second dielectric layer 150 and the etch stop layer 140, and which may stop diffusion of the conductor into the second dielectric layer 150 and the etch stop layer 140. In some embodiments, when the conductor in the third hole 152 and the opening 146 is made of copper (Cu), the second barrier layer 160 is made of, for example, tantalum nitride (TaN), Ta / TaN, Ta, other transition metal-based materials, or a combination thereof. In some other embodiments, if the conductor in the third hole 152 and the opening 146 is aluminum (Al), the second barrier layer 160 is, for example, titanium nitride (TiN), Ti / TiN, Ti, other transition metal-based materials, or a combination thereof. The second barrier layer 160 is formed by, for example, physical vapor deposition (PVD), ionized physical vapor deposition (IPVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof.Referring now to FIG. 12, a second electrically conductive material 170 overfills the third hole 152 and the opening 146. The second electrically conductive material 170 is made of a metal such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), tantalum (Ta), or a combination thereof. The second electrically conductive material 170 is formed, for example, by electrochemical deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.Referring now to FIG. 13, the excess second electrically conductive material 170 and the excess second barrier layer 160 outside the third hole 152 and the opening 146 are removed by a removal process. In some embodiments, the excess second electrically conductive material 170 and the excess second barrier layer 160 are removed using a chemical mechanical polishing (CMP) process. In some embodiments, when the second electrically conductive material 170 is copper (Cu), the CMP slurry is, for example, a mixture of suspended abrasive particles, an oxidizing agent, and a corrosion inhibitor, and the CMP slurry is acidic. A two-step CMP process may be used to remove the excess second electrically conductive material 170 and the excess second barrier layer 160. In the first step, the abrasive removes the loose second electrically conductive material 170 without interfering with the second barrier layer 160. In the second step, the remaining second electrically conductive material 170 and the remaining second barrier layer 160 are removed using a silicon dioxide abrasive. After the CMP process, an upper conductor 172 is formed in the third hole 152 and the opening 146, and the upper conductor 172 is electrically connected to the first lower conductor 132.In some embodiments, the first and second dielectric layers 110 and 150 may be made of substantially the same material, and therefore, the etch selectivity between the first and second dielectric layers 110 and 150 is low. In these embodiments, if an etch stop layer 140 is not formed between the first and second dielectric layers 110 and 150, the first dielectric layer 110 may be overetched during the etching of the second dielectric layer 150 to form at least one high aspect ratio recess in the first dielectric layer 110. Since the aspect ratio of the recess is large, no second barrier layer 160 having an acceptable step coverage can be formed in the recess. Therefore, a retraction cavity may be formed between the upper conductor 172 and the first lower conductor 132 by a subsequent thermal process such as curing.In order to prevent the first dielectric layer 110 from being overetched, the etch stop layer 140 is formed between the first and second dielectric layers 110 and 150. The etch stop layer 140 provides a high etch resistance to the etching of the second dielectric layer 150. Therefore, the etching of the second dielectric layer 150 by the etch stop layer 140 may be stopped without overetching the first dielectric layer 110. Since the first dielectric layer 110 is not overetched to form a high aspect ratio recess, the second barrier layer 160 may be formed with at least acceptable step coverage to adhere the upper conductor 172 to the second dielectric layer 150 and the etch stop layer 140. Therefore, after a subsequent thermal process such as curing, no retracting cavity is formed between the upper conductor 172 and the first lower conductor 132.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A method of manufacturing an interconnect structure, comprising the steps of: forming at least one first hole (112) in a first dielectric layer (110); forming a first barrier layer (120) on sidewalls and a bottom surface of the first hole (112) and on the surface of the first dielectric layer (110); overfilling the first hole (112) with a first conductive material (130) on the first barrier layer (120), and removing the excess first conductive material (130) and the excess barrier layer outside the first hole (112) to form a first conductor (132) in the first hole (112) and over the first barrier layer (120); Etching back the first dielectric layer (110) to an etching depth in the range of 2.5 nm to 27.5 nm so that the first conductor (132) has a part protruding from the first dielectric layer (110), wherein when etching back the first dielectric layer (110), the barrier layer (120) is etched to be coplanar with the dielectric layer (110) after the etching; forming an etch stop layer (140) on the first dielectric layer (110) and the protruding part of the first conductor (132), wherein the etch stop layer (140) has a raised part (R) covering the protruding part of the first conductor (132), and the raised part (R) has a lid part (142) covering an upper surface of the protruding part of the first conductor (132) and at least one spacer part (144), which is arranged on at least one side wall of the protruding part of the first conductor (132), and wherein the cover part (142) has a thickness (TC) in the range from 5 nm to 50 nm and the spacer part (144) has a thickness (TS) in the range from 15 nm to 70 nm, wherein the thickness (TS) of the spacer part (144) is greater than the thickness (TC) of the cover part (142); producing a second dielectric layer (150) on the etch stop layer (140); producing at least one second hole (152) through the second dielectric layer (150) and the etch stop layer (140), such that the protruding part of the first conductor (132) is at least partially exposed from the second hole (152); and producing a second conductor (172) in the second hole (152).The method of claim 1, wherein forming the second hole (152) comprises the steps of: etching a top hole in the second dielectric layer (150); and etching an opening (146) in the etch stop layer (140) such that the protruding portion of the first conductor (132) is at least partially exposed from the opening (146), wherein the opening (146) and the top hole are connected to each other such that the second hole (152) is formed.The method of claim 2, wherein the etch stop layer (140) has a higher etch resistance to an etchant used to etch the top hole in the second dielectric layer (150) than the second dielectric layer (150).The method of claim 2 or 3, wherein the etch stop layer (140) has a higher etch resistance to an etchant used to etch the top hole in the second dielectric layer (150) than the first dielectric layer (110).The method of any of claims 2 to 4, wherein the etching of the opening (146) is stopped before reaching the first dielectric layer (110).The method of any of claims 1 to 5, wherein the etch stop layer (140) is made of a carbon-rich material.An interconnect structure comprising: a first dielectric layer (110) having at least one hole (112) formed therein; a first barrier layer (120) on sidewalls and a bottom surface of the first hole (112), the first barrier layer (120) being coplanar with the first dielectric layer (110); a first conductor (132) located at least partially within the hole (112) of the first dielectric layer (110) and over the first barrier layer (120), the first conductor (132) having a portion protruding from the top surface of the first dielectric layer (110); an etch stop layer (140) disposed on the first dielectric layer (110), the etch stop layer (140) having an opening (146) to at least partially expose the first conductor (132), the first dielectric layer (110) having a top surface facing the etch stop layer (140); a second dielectric layer (150) disposed on the etch stop layer (140) and having at least one hole (152), the hole (152) of the second dielectric layer (150) being in communication with the opening (146) of the etch stop layer (140); a second conductor (172) at least partially located in the hole (152) of the second dielectric layer (150) and electrically connected to the first conductor (132) via the opening (146) in the etch stop layer (140); a third conductor (134) partially located in the first dielectric layer (110), wherein the first dielectric layer (110) has a top surface facing the etch stop layer (140), and the third conductor (134) has a portion protruding from the top surface of the first dielectric layer (110), and the etch stop layer (140) covers the protruding portion of the third conductor (134); and wherein the etch stop layer (140) has a raised portion (R) covering the projecting portion of the third conductor (134), and the raised portion (R) has a lid portion (142) covering an upper surface of the projecting portion of the third conductor (134) and at least one spacer portion (144) disposed on at least one side wall of the projecting portion of the third conductor (134), the lid portion (142) having a thickness (TC) in the range of 5 nm to 50 nm and the spacer portion (144) having a thickness (TS) in the range of 15 nm to 70 nm, the thickness (TS) of the spacer portion (144) being greater than the thickness (TC) of the lid portion (142).The interconnect structure of claim 7, wherein the etch stop layer (140) and the second dielectric layer (150) have different etch resistance properties.The interconnect structure of claim 7 or 8, wherein the etch stop layer (140) and the first dielectric layer (150) have different etch resistance properties.The interconnect structure of any of claims 7 to 9, wherein the etch stop layer (140) is comprised of a carbon-rich material.The interconnect structure of any of claims 7 to 10, wherein the etch stop layer (140) has a portion disposed between the second conductor (172) and the first dielectric layer (110).The interconnect structure of any of claims 7 to 11, wherein the etch stop layer (140) has a thickness in a range from 5 nm to 30 nm.The interconnection structure according to any one of claims 7 to 12, wherein a second barrier layer (160) is disposed on sidewalls of the hole (152) of the second dielectric layer (150) and on the sidewalls and the bottom surface of the opening (146).The interconnect structure of claim 13, wherein the third conductor (172) is made of Cu, and the second barrier layer (160) is made of TaN, Ta / TaN, Ta, or a combination thereof.The interconnect structure of claim 14, wherein the third conductor (172) is made of Al, and the second barrier layer (160) is made of TiN, Ti / TIN, Ti, or a combination thereof.The interconnect structure of any of claims 7 to 15, wherein the first dielectric layer (110) and the second dielectric layer (150) are made of the same material.

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