Method for producing a semiconductor chip and semiconductor chip

Abstract

Method for producing a semiconductor chip (1), comprising the following steps: a) providing a semiconductor layer sequence (10) with a first semiconductor layer (11) and a second semiconductor layer (13), wherein the first semiconductor layer (11) is p-doped and the second semiconductor layer (13) is n-doped or vice versa; b) forming at least one recess (10a) in the semiconductor layer sequence (10) so that side surfaces (11b, 13b) of the first semiconductor layer (11) and the second semiconductor layer (13) are exposed; c) applying an auxiliary layer (20) for electrically contacting the second semiconductor layer (13), wherein the auxiliary layer (20) is in direct contact with the first semiconductor layer (11) and with the second semiconductor layer (13) on the side surfaces (11b, 13b) exposed by the respective recess (10a), wherein the auxiliary layer (20) forms a diode in the reverse direction with respect to the first semiconductor layer (11) during operation of the semiconductor chip (1) and / or a contact resistance between the auxiliary layer (20) and the first semiconductor layer (11) is at least 100 times higher than between the auxiliary layer (20) and the second semiconductor layer (13).

Description

A method for producing a semiconductor chip and a semiconductor chip are specified.The publication US 2013 / 0 306 964 A1 relates to an LED chip having an electrical contact region which is fork-shaped when viewed in cross section.The document U.S. Pat. No. 4,352,187 A discloses a semiconductor laser in which a Schottky diode is formed in places on an electrode layer.One object is to specify a simple method for producing a semiconductor chip and a corresponding semiconductor chip which has a high efficiency during operation.This object is achieved by the method of claim 1 and by the semiconductor chip of claim 2.A method for producing a semiconductor chip is specified. The semiconductor chip can be a semiconductor chip of microelectronics, such as an integrated circuit. In particular, the semiconductor chip can be an optoelectronic semiconductor chip such as a radiation-receiving semiconductor chip or a light-emitting semiconductor chip. For example, the semiconductor chip is a photodiode, a solar cell, a light-emitting diode chip or a laser.A semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer is provided. For example, the first semiconductor layer is formed as a p-type semiconductor region and the second semiconductor layer is formed as an n-type semiconductor region, or vice versa. The semiconductor layer sequence is epitaxially deposited, for example, on a growth substrate. The growth substrate can be formed, for example, with sapphire or silicon.The semiconductor layer sequence can furthermore comprise, in particular, an active region. The active region can be produced between the first and the second semiconductor layer. A function of the semiconductor chips takes place in the active region. For example, the active region can be provided in a finished optoelectronic semiconductor chip for receiving or generating electromagnetic radiation. Furthermore, the semiconductor layer sequence may comprise further semiconductor regions such as buffer regions for crystallographic adaptations, etch stop layers, sacrificial layers, current spreading layers and contact layers. Furthermore, it is possible for the semiconductor layer sequence to have already structured regions and / or metal structures such as a metallic mirror layer, metal grids for current spreading, electrical contacting or current injection or other current spreading layers.For example, the semiconductor layer sequence, in particular the active region, contains a III-V compound semiconductor material. III-V compound semiconductor materials are particularly suitable for generating radiation in the ultraviolet (Al x In y Ga 1-x-y N) via the visible (Al x In y Ga 1-x-y N, in particular for blue to green radiation, or Al x In y Ga 1-x-y P, in particular for yellow to red radiation) to the infrared (Al x InyGa1-x-yAs) spectral range. Here, 0≤x≤1, 0≤y≤1 and x+y≤1, in particular with x≠1, y≠1, x≠0 and / or y≠0, respectively, applies. With III-V compound semiconductor materials, in particular from the above-mentioned material systems, high internal quantum efficiencies can furthermore be achieved during the generation of radiation.At least one recess is formed in the semiconductor layer sequence, so that side surfaces of the first semiconductor layer and of the second semiconductor layer are exposed. In this context, in particular, side surfaces of further semiconductor regions can also be exposed. The respective recess can be formed here, for example, by means of dry- or wet-chemical etching. For example, the respective recess has a circular shape in lateral directions, i.e. parallel or substantially parallel to a main extension of the semiconductor layer sequence. The respective recess can then serve, for example, as a through-connection (so-called "via"). In this case, the semiconductor layer sequence can be completely or else only partially ablated in the region of the recess. Deviating from this or in addition, it is also conceivable for the respective recess to assume a grating structure in lateral directions, as may be the case, for example, for forming a mesa. For this purpose, it is possible in particular to use chlorine-containing plasma.The lateral directions are in particular perpendicular or substantially perpendicular to a growth direction of the semiconductor layer sequence. The side surfaces exposed by the respective recess can enclose a steep angle with the lateral directions, for example greater than 75°. Alternatively, in additional process steps, lacquer can be applied, for example positive lacquer, with the use of which flatter angles, for example between 45% and 75%, can also be achieved. This can simplify subsequent overmolding steps, in particular.The respective recess can extend into the semiconductor layer sequence, for example, as far as a depth of at least 100 nm to at most 2000 nm, or through the latter. A depth of the respective recess is preferably between 300 nm and 1000 nm. A lateral extent of a base surface of the respective recess can be at least 1 μm to at most 100 μm, preferably between 5 μm and 50 μm. In other words, the respective recess can thus be formed many times wider than deep.The side surfaces of the first and second semiconductor layers exposed by the respective recess and optional intermediate layers have an extension toward the bottom surface of the respective recess, which extension is limited by the depth of the respective recess. Thus, an area ratio of the side surfaces of the first and second semiconductor layers exposed by the respective recess and optional intermediate layers to further surfaces exposed by the respective recess and delimiting the respective recess can be less than 1:3, for example less than 1:10, in particular less than 1:100.For the electrical contacting of the second semiconductor layer, an auxiliary layer is applied. After this step, the auxiliary layer is in direct contact with the first semiconductor layer at the side surfaces exposed by the respective recess. In particular, in this context, the exposed side surfaces of the first semiconductor layer and / or of the further semiconductor regions can also be at least partially covered, with the result that the auxiliary layer is in direct contact with a plurality of semiconductor layers or regions of the semiconductor layer sequence after this step. The application of the auxiliary layer can be effected, for example, by sputtering. In this case, the auxiliary layer can be deposited as a closed layer, in particular in the region of the respective recess. A layer thickness of the auxiliary layer is, for example, between at least 5 nm and at most 200 nm. A layer thickness of 10 nm to 50 nm is preferred.The auxiliary layer serves for the electrical contacting of the second semiconductor layer. In other words, during operation of the semiconductor chip, the auxiliary layer has a good electrical conductivity with respect to the second semiconductor layer. A contact resistance between the auxiliary layer and the second semiconductor layer can therefore be, for example, at least 5*10 -6 Ω*cm 2 and at most 1*10 -4 Ω*cm 2. When an operating voltage is applied, a current flow is thus made possible indirectly or directly between the auxiliary layer and the second semiconductor layer.The auxiliary layer further has poor electrical conductivity with respect to the first semiconductor layer. A contact resistance between the auxiliary layer and the first semiconductor layer can thus be higher by several orders of magnitude than in the aforementioned case. For example, the contact resistance is then at least 10 times to 100 times, in particular more than 100 times, preferably more than 1000 times, the above-mentioned upper range limit, i.e. at least more than 1*10 -3 Ω*cm 2. With regard to a functionality of the semiconductor chip, a current flow between the auxiliary layer and the first semiconductor layer is thus substantially prevented.In other words, the auxiliary layer is a contact material which selectively enters into only good electrical contact with the second semiconductor layer. By way of example, on the other hand, during operation of the semiconductor chip, the contact material forms a blocking diode with respect to the first semiconductor layer. Alternatively or additionally, the contact material forms a greatly increased ohmic contact resistance to the first semiconductor layer during operation of the semiconductor chip.According to the method, firstly a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer is provided. Subsequently, at least one recess is formed in the semiconductor layer sequence, so that side surfaces of the first semiconductor layer and of the second semiconductor layer are exposed. Subsequently, an auxiliary layer for electrically contacting the second semiconductor layer is applied. After this step, the auxiliary layer is at least partially in direct contact with the first semiconductor layer and also with the second semiconductor layer on the side surfaces exposed by the respective recess.The side surfaces of the semiconductor layer sequence exposed when the respective recess is formed represent a sensitive region. For example, this region may be susceptible to defects, as a result of which increased leakage currents may occur at the exposed side surfaces, or a failure of the semiconductor chip may be caused. For further processing, it may therefore be necessary to passivated or electrically isolate this region. By applying the auxiliary layer, an extrinsic passivation material can be dispensed with. In particular, subsequent structuring steps can be saved thereby, so that a simple, cost-effective and time-saving production of the semiconductor chip is contributed.The semiconductor layer sequence can in particular have electrical contacts, contact layers or contact layer sequences, via which a respective electrical contacting of the first semiconductor layer or of the second semiconductor layer substantially takes place. For example, in this context, a current spreading layer is arranged within the second semiconductor layer, or on a side of the second semiconductor layer facing away from the first semiconductor layer. Side surfaces of the current spreading layer can be exposed by the respective recess. Alternatively or additionally, the respective recess can extend into the current spreading layer in such a way that a bottom surface of the respective recess is formed by an exposed surface of the current spreading layer. Via the exposed side surfaces and / or surface of the current spreading layer, indirect electrical contacting of the second semiconductor layer by the auxiliary layer can then take place, for example.The electrical contacting of the second semiconductor layer thus takes place from the side of the second semiconductor layer facing the first semiconductor layer. The first semiconductor layer can likewise be electrically contacted from this side, for example via a metallic mirror layer applied on a side of the first semiconductor layer facing away from the second semiconductor layer.The introduction of an additional dielectric between the auxiliary layer and the first semiconductor layer is advantageously only more optional. Anisotropic etching back of the dielectric can therefore also be dispensed with in this context. This simplifies a process flow for producing the semiconductor chip, since both the deposition of the dielectric and its structuring can be omitted, so that a cost-effective production of the semiconductor chip is contributed. Furthermore, an increased reliability of the semiconductor chip and thus an increased yield in the production are made possible. Furthermore, one and the same material advantageously serves for contacting and for insulation, depending on which layer the material adjoins.Furthermore, a semiconductor chip is specified. The semiconductor chip comprises a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer. The semiconductor chip has at least one recess in the semiconductor layer sequence, through which side faces of the first semiconductor layer and of the second semiconductor layer are exposed. The semiconductor chip further comprises an auxiliary layer for electrically contacting the second semiconductor layer. The auxiliary layer is at least partially in direct contact with the first semiconductor layer at the side surfaces exposed by the respective recess.The semiconductor chip is in particular the semiconductor chip produced by means of the method described above, so that all features disclosed for the method are also disclosed for the semiconductor chip and vice versa.The embodiments given below relate both to methods described here and to semiconductor chips described here.In at least one embodiment, the auxiliary layer forms a diode with the first semiconductor layer. In particular, the diode is designed in such a way that it blocks during operation of the semiconductor chip, i.e. when an operating voltage is applied. This advantageously contributes to a high ESD strength of the semiconductor chip. In other words, the diode is connected antiparallel with respect to the first and second semiconductor layers, in particular antiparallel with respect to a pn junction.In at least one further embodiment, the auxiliary layer comprises or consists of a transparent conductive oxide (TCO). Transparent conductive oxides are transparent, conductive materials, generally metal oxides, such as indium tin oxide or zinc oxide, for example.In at least one further embodiment, the auxiliary layer comprises or consists of a metal. For example, this can be aluminum, titanium or rhodium. Advantageously, the auxiliary layer can then form a Schottky diode to form the first semiconductor layer, which is blocking during operation of the semiconductor chip. By way of example, the first semiconductor layer is formed as p-GaN.In at least one further embodiment, the auxiliary layer comprises or consists of an extrinsically doped semiconductor material. For example, this can be doped amorphous silicon, doped zinc oxide or indium tin oxide. Suitable dopants are, for example, aluminum or gallium.In at least one further embodiment, the auxiliary layer comprises or consists of zinc oxide. The semiconductor layer sequence is based on gallium nitride (GaN). Zinc oxide advantageously behaves intrinsically as an n-semiconductor. Surprisingly, it has been found that this enables a selectively good electrical contact with an n-conducting second semiconductor layer based on gallium nitride (for short: n-GaN), and forms a diode which blocks during operation of the semiconductor chip to form a p-conducting first semiconductor layer based on gallium nitride (for short: p-GaN). A contact resistance between the auxiliary layer and the second semiconductor layer can in this case be, for example, at least 5*10 -6 Ω*cm 2 and at most 5*10 -5 Ω*cm 2. A contact resistance between the auxiliary layer and the second semiconductor layer may further be at least 5×10 -5 Ω*cm 2.In at least one further embodiment, the auxiliary layer comprises a gold-germanium alloy. The semiconductor layer sequence is based on aluminum gallium indium phosphide (InGaAlP). Surprisingly, it has been shown, analogously to the preceding embodiment, that the gold-germanium alloy is particularly suitable as selective electrical contact in semiconductor layers based on InGaAlP. Furthermore, such an alloy can be reflective and, with a correspondingly small layer thickness, semitransparent. A contact resistance between the auxiliary layer and the second semiconductor layer may be, for example, at least 1×10 -5 Ω*cm 2 and at most 1×10 -4 Ω*cm 2 in this case. A contact resistance between the auxiliary layer and the second semiconductor layer may further be at least 1×10 -4 Ω*cm 2.In at least one further embodiment, a further mirror layer is applied to a side of the auxiliary layer facing away from the semiconductor layer sequence. The further mirror layer can be, in particular, a metallic mirror layer. For example, the further mirror layer is formed from silver, aluminum, rhodium or gold. A layer thickness of the further mirror layer can be, for example, more than 100 nm. Advantageously, the respective recess can be reflectively mirrored by the further mirror layer.After application to the side surfaces exposed by the respective recess, the auxiliary layer is at least partially in direct contact with the second semiconductor layer. As a result, in particular a contact area between the auxiliary layer and the second semiconductor layer is enlarged, namely around the side surfaces of the second semiconductor layer. In this way, an increase in efficiency of the semiconductor chip can be advantageously achieved. In this context, both a reduction in the threshold voltage and an increase in light by reducing the current density are conceivable (so-called "droop effect").In at least one further embodiment, the auxiliary layer is applied at least partially on a side of the first semiconductor layer facing away from the second semiconductor layer. The auxiliary layer makes direct contact with the first semiconductor layer at least in a region around the respective recess. As a result, in particular a contact area between the auxiliary layer and the first semiconductor layer is enlarged. In an advantageous manner, a further increase in the ESD strength of the semiconductor chip can thus be achieved.In at least one further embodiment, before the respective recess is formed in the semiconductor layer sequence, a metallic mirror layer is applied to the side of the first semiconductor layer facing away from the second semiconductor layer. The metallic mirror layer has an opening toward the semiconductor layer sequence in each case corresponding to a region of the respective recess. A passivation layer is applied to a side of the metallic mirror layer facing away from the semiconductor layer sequence.In this context, the metallic mirror layer is formed, for example, only outside a first lateral region around the respective recess, i.e., at a distance from the latter. For example, the passivation layer is removed in a second lateral region around the respective recess before the step or in the step of forming the respective recess. For example, fluorine-containing plasma can be used. The second lateral region is, for example, smaller than the first lateral region or is retracted with respect to the respective recess in such a way that a side surface of the metallic mirror layer is completely covered by the passivation layer even after the step of forming the respective recess, such that a short circuit between the subsequently applied auxiliary layer and the metallic mirror layer can be avoided. For example, a lateral distance between the metallic mirror layer and the subsequently applied auxiliary layer is between at least 100 nm and at most 5 μm, in particular less than 10 μm.In at least one further embodiment, the passivation layer is ablated in a lateral region around the respective recess.For example, a wet chemical etching medium is used for this purpose. The lateral region around the respective recess, in which the passivation layer is ablated, is also referred to below as a third lateral region. In particular, the second lateral region comprises the third lateral region, which in turn comprises the first lateral region. In other words, a side surface of the metallic mirror layer can thus also be completely covered by the passivation layer after this step. In particular, the side of the first semiconductor layer facing away from the second semiconductor layer is exposed around the respective recess at least between the first and the third region, so that the subsequently applied auxiliary layer has an enlarged contact surface with respect to the first semiconductor layer. This advantageously contributes to a particularly high ESD strength of the semiconductor chip. A lateral extent by which the passivation layer is retracted is, for example, between at least 500 nm and at most 5000 nm.In at least one further embodiment, before the application of the auxiliary layer, a mirror protection layer is applied on the side of the first semiconductor layer facing away from the second semiconductor layer. The mirror protection layer completely covers side surfaces of the metallic mirror layer facing the respective recess.In particular, the mirror protection layer can also partially or completely cover a side surface of the passivation layer facing the respective recess. The mirror protection layer contributes in particular to the fact that the metallic mirror layer is protected in the step of forming the respective recess, for example in the case of semiconductor etching from etching media such as chlorine-containing plasma. The arrangement of the mirror protection layer on the side surfaces of the metallic mirror layer can be effected, for example, in a self-aligning manner. Such a self-aligningly applied mirror protection layer is described, for example, in DE 10 2012 107 921 A1.In at least one further embodiment, in at least one of the steps of forming the respective recess, applying the auxiliary layer or an intermediate step thereof, a modified region of the semiconductor layer sequence is formed around the exposed side surfaces of the first semiconductor layer and of the second semiconductor layer. The modified region affects electrical conductivity between the auxiliary layer and that of the first semiconductor layer.The modified region is in particular a surface modification, that is to say a modification which relates only to an extremely small proportion of the semiconductor layer sequence with respect to its main direction of extent. The modification can be, for example, a reaction which takes place by supplying a gas during and / or between and / or after one of the aforementioned steps. For example, in a process step after the semiconductor etching, a gas such as oxygen is supplied, so that the GaN semiconductor material is exposed to 2- plasma at its surface O. In this region, the semiconductor material, in particular a p-type region, can be partially damaged, destroyed or deactivated, for example by oxidation, such that, for example, a breakdown voltage and / or a threshold voltage is raised toward the subsequently applied auxiliary layer. Alternatively, for example, a use of fluorine or hydrogen is conceivable, so that the surface is exposed to F plasma or H plasma. Furthermore, the modification can also be effected by mechanical action, for example by argon sputtering.The modification relates in particular to both the first semiconductor layer and the second semiconductor layer. Advantageously, the modification further restricts an electrical conductivity between the auxiliary layer and the sensitive first semiconductor layer, while the substantially insensitive second semiconductor layer experiences virtually no impairment of the electrical conductivity. Such a method step can be carried out with particularly low outlay.The modified region can extend between at least 1 nm and at most 100 nm deep into the semiconductor layer sequence, for example between at least 10 nm and at most 50 nm deep, in particular between at least 10 nm and at most 20 nm deep. A volume proportion of the modified region with respect to the semiconductor layer sequence is thus negligible, and in particular substantially less than 1%, for example in the range of 0.1%.In at least one further embodiment, the semiconductor layer sequence is redoped in the region of the exposed side surfaces of the first semiconductor layer and of the second semiconductor layer. For example, constituents of the subsequently applied auxiliary layer which at least partially covers the exposed side surfaces of the semiconductor layer sequence can diffuse into the adjacent semiconductor regions, as a result of which their semiconductor properties can be greatly changed, in particular with regard to respective transition resistances. For such a redoping, the aforementioned gold-germanium alloy is particularly suitable as the material of the auxiliary layer, for example.In at least one further embodiment, the modified region of the semiconductor layer sequence is at least partially ablated. For example, the modified region is at least partially removed by a selective wet chemical etching, for example by means of hot phosphoric acid (H 3 PO 4) or potassium hydroxide (KOH). This advantageously contributes to a high ESD strength of the semiconductor chip.In at least one further embodiment, before the formation of the respective recess, in particular before applying the metallic mirror layer, a contact layer is applied on the side of the first semiconductor layer facing away from the second semiconductor layer. The contact layer serves, for example, for current expansion. This is advantageous in particular if a dielectric mirror is subsequently applied in front of the metallic mirror layer. The contact layer is, for example, a transparent conductive oxide (TCO).In at least one further embodiment, the contact layer applied before the formation of the respective recess on the side of the first semiconductor layer facing away from the second semiconductor layer is completely removed in a lateral fourth region around the respective recess. For example, after the application of the auxiliary layer, the contact layer in this region is for this purpose ablated with a selective wet chemical etching step in such a way that an edge of the contact layer facing the respective recess is pulled behind a side surface of the passivation layer facing the recess. The edge of the contact layer is advantageously covered by the passivation layer in such a way that short circuits with the auxiliary layer can be avoided.In at least one further embodiment, an active region in the semiconductor layer sequence is penetrated in the step of forming the respective recess. The active region is designed in particular for receiving or generating electromagnetic radiation. The active region can be, for example, a radiation-generating pn junction or single- or multiple-quantum structure. Further, in this step, side surfaces of the active region are exposed. After application to the side surfaces exposed by the respective recess, the auxiliary layer is at least partially in direct contact with the active region.In at least one further embodiment, in the step of forming the respective recess, a semiconductor buffer region is exposed on a side of the first semiconductor layer facing away from the metallic mirror layer. After the application, the auxiliary layer is at least partially in direct contact with the semiconductor buffer region.The semiconductor buffer region can in this case in particular have the aforementioned electrical contacts, contact layers or contact layer sequences, via which the respective electrical contacting of the second semiconductor layer takes place. For example, the semiconductor buffer region comprises a current spreading layer, the side surfaces and / or surface of which are exposed by the respective recess, so that indirect electrical contacting of the second semiconductor layer by the auxiliary layer is made possible.In particular, in the step of forming the respective recess, a current spreading layer is exposed on a side of the first semiconductor layer facing away from the metallic mirror layer, so that the auxiliary layer is at least partially in direct contact with the current spreading layer after the application. The above-mentioned contact resistance between the auxiliary layer and the second semiconductor layer can be produced in particular by the contacting via the current spreading layer.In at least one further embodiment, the semiconductor chip is embodied as an optoelectronic semiconductor chip. The optoelectronic semiconductor chip can be, for example, a radiation-receiving semiconductor chip such as a photodiode or a solar cell. In particular, the optoelectronic semiconductor chip is a light-emitting semiconductor chip such as a light-emitting diode chip.Further features, configurations and functionalities emerge from the following description of the exemplary embodiments in conjunction with the figures.The following are shown: FIGS. 1 ato 1 f show an exemplary embodiment of a method for producing a semiconductor chip on the basis of intermediate steps, each of which is illustrated in schematic sectional view; FIG. 2 shows a first section of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view; FIGS. 3 ato 3 f show a first to sixth exemplary embodiment of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view; FIG. 3 g shows an example of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view, illustrating the invention; FIG. 4 shows a second section of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view; FIG. 5 shows an eighth exemplary embodiment of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view; and FIG. 6 shows a ninth exemplary embodiment of a further semiconductor chip in schematic sectional view.Identical, similar or identically acting elements are provided with the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures with respect to one another are not to be considered as true to scale. Rather, individual elements may be represented with exaggerated size for better clarity and / or for better understanding. The figures show in particular in each case sections of a part of a semiconductor chip to be produced. The cut-outs can be continued respectively on the right and left sides of the sectional representation, as is indicated by dash-dot lines.In conjunction with the schematic sectional representations of FIGS. 1 ato 1 f, an exemplary embodiment of a method described here for producing a semiconductor chip is explained in more detail. The semiconductor chip described here is in particular an optoelectronic semiconductor chip such as an LED chip, for example an InGaN LED chip. In other exemplary embodiments, the semiconductor chip can also be, for example, an InGaAlP LED chip.FIG. 1 ashows a first method step in which a semiconductor buffer region 15 is deposited on an upper side of a growth substrate 60. For example, the growth substrate 60 is a sapphire substrate or a silicon substrate, onto which a semiconductor layer sequence 10 can subsequently be deposited (compare FIG. 1 b ). The semiconductor layer sequence 10 is based, for example, on a nitride compound semiconductor material. For example, the semiconductor buffer region 15 is a layer formed with GaN.Subsequently, FIG. 1 b, a first semiconductor layer 11, an active region 12 and a second semiconductor layer 13 are epitaxially deposited. The layers are, for example, likewise layers formed with GaN. In particular, the first semiconductor layer 11 is a p-doped region and the second semiconductor layer 13 is an n-doped region. If the semiconductor chip is, for example, a radiation-generating semiconductor chip, electromagnetic radiation is generated in the active region 12 in the finished semiconductor chip 1 (cf. FIG. 2 ).The semiconductor buffer region 15 can have a current spreading layer 16 (cf. FIG. 1 a ) which extends, for example, in a planar manner through the semiconductor buffer region 15. For the sake of clarity, the current spreading layer 16 is only shown in FIGS. 1 aand 1 e.Subsequently, FIG. 1 c, the structured arrangement of a metallic mirror layer 30 takes place on the upper side of the semiconductor layer sequence 10 facing away from the growth substrate 60. For example, the metallic mirror layer is first applied by vapor deposition or sputtering over the surface and then structured, for example with the aid of a photostructureable protective layer and exposure.After this step, the metallic mirror layer 30 is structured in particular such that it is completely open in the lateral direction. In other words, the metallic mirror layer 30 has at least one opening 30 a.Subsequently, a passivation layer 40 is applied to a side of the metallic mirror layer 30 facing away from the semiconductor layer sequence 10. The passivation layer 40 is, for example, a layer comprising silicon dioxide or silicon nitride, which can have a thickness of at least 50 nm and at most 1000 nm, in particular between 100 nm and 500 nm, for example.As indicated in FIG. 1 c, the passivation layer 40 can extend over the surface of the metallic mirror layer 30. In the region of the respective opening 30 a, the passivation layer 40 may furthermore be in direct contact with the semiconductor layer sequence 10. In particular, a side surface 30 bof the metallic mirror layer 30 exposed by the respective opening 30 ais covered by the passivation layer 40.Subsequently, FIG. 1 d, corresponding to the respective opening 30 ain the metallic mirror layer 30, openings 40 aare produced in the passivation layer 40, for example using a photomask and fluorine-containing plasma. The respective opening 40 ain the passivation layer 40 is advantageously arranged in such a way that the side surface 30 bof the metallic mirror layer 30 is still covered by the passivation layer 40.Subsequently, FIG. 1 e, a dry etching step is carried out, for example using chlorine plasma, in which the material of the semiconductor layer sequence 10 is at least partially removed, so that a recess 10 ais formed in the semiconductor layer sequence 10. In the region of the recess 10 a, the side surfaces 11 b, 12 b, 13 bof the first semiconductor layer 11, of the active region 12 and of the second semiconductor layer 13 are each exposed. Furthermore, it is conceivable that a side surface 15 bof the semiconductor buffer region 15 is exposed by the recess 10 a. In other words, the recess 10 aextends in the vertical direction as far as into the semiconductor buffer region 15, in particular as far as the current spreading layer 16.The side surface 30 bof the metallic mirror layer 30, on the other hand, may be further covered by the passivation layer 40. The recess 10 acan be, for example, a circular recess or a grid structure. The semiconductor layer sequence 10 can have a steep, exposed edge which, for example, has an angle of over 75° with respect to the growth substrate 60.In a further method step, which is explained in connection with FIG. 1 f, an auxiliary layer 20 is subsequently applied to the exposed semiconductor layer sequence 10, for example by homogeneous sputtering. For example, the auxiliary layer 20 is a zinc oxide layer. The auxiliary layer 20 can have a thickness of at least 5 nm and at most 50 nm.Thus, between the method steps illustrated in FIGS. 1 eand 1 f, in particular no intermediate step takes place in which a dielectric, such as TEOS-SiO 2, is deposited and anisotropically etched back.In other words, the auxiliary layer 20 is applied directly to the semiconductor layer sequence 10, so that it is at least in direct contact with the first semiconductor layer 11 via the side surface 11 b.The auxiliary layer constitutes in particular a contact material which selectively makes good contact only with the n-GaN or forms a blocking diode or a high contact resistance to the p-GaN when the semiconductor chip is operated. Zinc oxide is particularly well suited in this case, since it already behaves intrinsically as an n-semiconductor. Alternatively, an extrinsically doped semiconductor material such as doped amorphous silicon, zinc oxide or indium tin oxide doped with, for example, aluminum or gallium, can also be used. Furthermore, metals such as aluminum or rhodium, which form a blocking Schottky diode with the p-GaN, can also be used. The auxiliary layer 20 can also consist of several of the materials mentioned or comprise these, for example in the form of a contact stack.Advantageously, an increase in efficiency can be achieved by the auxiliary layer 20, since a contact area with the second semiconductor layer 13 around the side surface 13 bis increased, so that the threshold voltage can be lowered or the current density can be lowered. By omitting the additional dielectric, a simplified process flow is made possible, so that the semiconductor chip can be produced cost-effectively.In subsequent method steps, a further mirror layer 25 (compare FIG. 5 ) can be applied to a side of the auxiliary layer 20 facing away from the growth substrate 60, such that the respective recess 10 ais reflectively mirrored. The mirror layer can be, in particular, a metallic mirror layer made of silver, aluminum, rhodium or gold. The mirror layer can have a thickness of at least 100 nm, for example.Furthermore, in subsequent method steps, for example, an electrically conductive material 70 may be filled into the opening 23, which electrically contacts the semiconductor material of the semiconductor buffer region 15 and / or the auxiliary layer 20. Furthermore, a carrier 80 can be applied and the growth substrate 60 removed, wherein the upper side of the semiconductor buffer region 15 facing away from the carrier 80 can be roughened, see FIG. 2.The first section of the finished semiconductor chip 1 illustrated in FIG. 2 shows, in particular, a through-connection of the second semiconductor layer 13 via the auxiliary layer 20 from a side facing the first semiconductor layer 11, in which the recess 10 acan be of circular configuration. Contacting of the first semiconductor layer 11 is not shown in more detail here.FIGS. 3a to 3g show a first to seventh exemplary embodiment of a semiconductor chip produced according to FIGS. 1a to 1f in each case in schematic sectional view.In the semiconductor chip according to the first exemplary embodiment (FIG. 3 a), the auxiliary layer 20 is in direct contact with the first semiconductor layer 11, the active region 12 and the second semiconductor layer 13 via the respective side surfaces 11 b, 12 b, 13 b.Compared to a GaN semiconductor layer sequence which is contacted with conventional contact material, i.e. for example by silver or platinum contact material (stack) from a p-conducting region and by zinc oxide from an n-conducting region, a same semiconductor layer sequence which is contacted on both sides by zinc oxide has greatly changed characteristics. If these semiconductor layer sequences are, for example, a GaN LED having a lateral area of extent of 1000×10000 μm 2, which are each contacted in a planar manner, then an operating current in the case of conventional contact material can be, for example, between 35 mA and 1750 mA, whereas only an operating current of less than 1 mA to 10 mA occurs in the case of contact on both sides by zinc oxide. In the first case, a nominal threshold voltage is between 2.8 V and 3.3 V; in the second case, on the other hand, the nominal threshold voltage is approximately 0.5 V to 1.0 V higher, for example between 3.5 V and 4.0 V.In other words, the required operating (duty) voltage drastically increases. At operating (operating) voltages of 2.7 V and 3.5 V, as are customary in the first case, therefore, only a current which is substantially smaller flows in the second case.Since, in addition, a ratio of contact areas to the auxiliary layer 20 between the first and second semiconductor layers 11, 13 and further areas exposed by the respective recess, for example the current spreading layer 16, is at least less than 1:3, as shown in the general part of the description, a current flow between the auxiliary layer 20 and the first semiconductor layer is further reduced and in particular negligible in the operating direction. In particular, a large ratio of a part of the current spreading layer 16 forming the bottom surface of the respective recess 10a together with a side surface of the current spreading layer 16 exposed by the respective recess 10a to the exposed side surfaces 11b, 12b is advantageous.The second exemplary embodiment (FIG. 3 b) differs from the first exemplary embodiment in that an additional retraction of the passivation layer 40 is carried out after the semiconductor etching, for example using a wet-chemical etching medium. Thus, a part 11 dof a surface of the first semiconductor layer 11 is also exposed. Advantageously, a larger p-GaN area is thus available for forming a diode with opposite polarity to the semiconductor chip, so that an ESD stability of the semiconductor chip is contributed.The third exemplary embodiment (FIG. 3 c ) differs from the preceding exemplary embodiments in that after and / or during the semiconductor etching a surface modification of the semiconductor layer sequence 10 is carried out, which affects both p-GaN and n-GaN. In particular, this can also relate to a pn junction with the active region 12. As illustrated in FIG. 3 c, a modified region 10 cis thereby produced at the side surfaces 11 b, 12 b, 13 bof the semiconductor layer sequence 10, for example by supplying oxygen, fluorine or hydrogen (O 2- plasma, F plasma or H plasma), or by sputtering argon.The fourth exemplary embodiment (FIG. 3 d) differs from the third exemplary embodiment in that the modified region 10 c(cf. FIG. 3 c) is partially or completely removed before deposition of the auxiliary layer 20, for example by a selective wet chemical etching, for example by means of hot H 3 PO 4 or KOH. Advantageously, this contributes to the ESD stability of the semiconductor chip. For example, the subsequently applied auxiliary layer 20 extends into the remote region 10c. In particular, this may be completely filled by material 20 cof the auxiliary layer 20.The fifth exemplary embodiment (FIG. 3 e) differs from the preceding exemplary embodiments in that a thin current spreading layer 90 is arranged between the first semiconductor layer 11 and the passivation layer 40. For example, the current spreading layer 90 can also be a layer stack which is deposited in a plurality of coating processes. The current spreading layer 90 is applied in particular in a planar manner to the semiconductor layer sequence 10, for example directly on the first semiconductor layer 11.The current spreading layer 90 can be embodied in particular as transparent. By way of example, it is formed from a transparent conductive oxide such as indium tin oxide. The current spreading layer is particularly advantageous if a dielectric mirror is to be implemented in front of the metallic mirror layer.In a subsequent step, for example after the semiconductor etching, an edge of the current spreading layer 90 facing the recess 10 acan be drawn in the lateral direction behind an edge of the passivation layer 40 facing the recess 10 a, for example by approximately 1 μm in the lateral direction. For example, a selective wet chemical etching step is used for this purpose, in which material 91 of current spreading layer 90 is completely removed. Short circuits with the auxiliary layer 20 can thus be advantageously avoided.The sixth exemplary embodiment (FIG. 3 f) differs from the preceding exemplary embodiments in that the metallic mirror layer 30 is bounded by a mirror protection layer 50 toward the recess 10 a. The mirror protection layer 50 can be applied, for example, in a self-aligning manner, as already mentioned in the general description section. In this connection, it is not necessary for the passivation layer 40 to cover the side surface 30 b(cf. FIG. 1 d) of the metallic mirror layer 30, but rather the opening 40 ain the passivation layer 40 can extend as far as the side surface 30 b.As illustrated in FIG. 3 f, very small lateral protrusions of the active region 12 over the metallic mirror layer 30 can thus be achieved. In this way, a region of the active region that cannot be used for generating radiation or detecting radiation is kept very small.In this context, the metallic mirror layer 30 can cover up to 90% of an area of the active region 12.The illustrative example (FIG. 3 g) differs from the preceding exemplary embodiments in that, before the application of the auxiliary layer 20, a protective layer 51 is applied to the side surfaces 11 b, 12 b, 13 bof the semiconductor layer sequence 10, such that these are covered at least in places. For example, conformal deposition is used here. The protective layer 51 comprises as material, for example, oxides or nitrides such as silicon dioxide, Si 3 N 4 and / or Al 2 O 3 or a material stack thereof. In a subsequent method step, a directed etching back of the protective layer 51 takes place, so that at least the side surface 11 bof the first semiconductor layer 11 is exposed. Measurements have shown that a semiconductor chip produced in this way is surprisingly equivalent in terms of low-current behavior, high-current behavior and breakdown behavior in reverse loading to a semiconductor chip whose protective layer 51 has not been etched back or has been etched back only slightly, such that its side surfaces 11 b, 12 b, 13 bof the semiconductor layer sequence 10 are still covered by the protective layer 51.The second section of the semiconductor chip illustrated in FIG. 4 shows the passivation layer 40 laterally indented in conjunction with the second exemplary embodiment (cf. FIG. 3 b ). As is further illustrated in FIG. 4, the section of the first semiconductor layer 11 in direct contact with the auxiliary layer 20 is at a lateral distance from the metallic mirror layer 30, so that short circuits can be avoided. In this exemplary embodiment, the auxiliary layer 20 is arranged overlapping with respect to the metallic mirror layer 30 and is separated from the latter by the passivation layer 40. In particular, at least the part 11 dof the first semiconductor layer 11 (compare FIG. 3 b ) and the side surfaces 11 band 12 bare securely covered by the auxiliary layer 20. A lateral overlap region of the auxiliary layer 20 with the metallic mirror layer 30 can optionally be dispensed with.FIG. 5 shows an eighth exemplary embodiment of the semiconductor chip produced according to FIGS. 1 ato 1 fin schematic sectional view. The section shown corresponds to the section shown in FIG. 2, but the semiconductor chip 1 additionally has a further mirror layer 25 here, which reflectively mirrors the respective recess 10 a. Advantageously, the further mirror layer 25 extends in the lateral direction at least as far as the metallic mirror layer 30, so that a complete mirror coating can be achieved in the region of the respective recess 10 a. In this context, it is also conceivable for the two mirror layers 25, 30 to be arranged overlapping in the lateral direction.A ninth exemplary embodiment of a further semiconductor chip 2 is shown in FIG. 6 in a section in schematic sectional view. The cutout corresponds substantially to that of FIGS. 2 and 5, but here at least one recess 10 eis introduced into the semiconductor layer sequence 10 from a side of the second semiconductor layer 13 facing away from the second semiconductor layer 11. In this exemplary embodiment, this is in particular a completely etched-through semiconductor stack, in which the respective recess 10 eextends completely through the semiconductor buffer region 15 as far as the conductive layer 70. The side surfaces exposed by the respective recess 10 eare covered by the auxiliary layer 20 analogously to the preceding exemplary embodiments. The respective recess 10 emay also be referred to as an n-side via, and the respective recess 10 a(cf. FIGS. 1-5 ) as a p-side via.

Claims

Method for producing a semiconductor chip (1), comprising the following steps: a) providing a semiconductor layer sequence (10) having a first semiconductor layer (11) and a second semiconductor layer (13), wherein the first semiconductor layer (11) is p-doped and the second semiconductor layer (13) is n-doped or vice versa; b) forming at least one recess (10a) in the semiconductor layer sequence (10), such that side faces (11b, 13b) of the first semiconductor layer (11) and of the second semiconductor layer (13) are exposed; c) applying an auxiliary layer (20) for electrically contacting the second semiconductor layer (13), wherein the auxiliary layer (20) is in direct contact with the first semiconductor layer (11) and with the second semiconductor layer (13) on the side surfaces (11b, 13b) exposed by the respective recess (10a), wherein the auxiliary layer (20) forms a diode in the reverse direction to the first semiconductor layer (11) during operation of the semiconductor chip (1) and / or a contact resistance between the auxiliary layer (20) and the first semiconductor layer (11) is at least 100 times higher than between the auxiliary layer (20) and the second semiconductor layer (13).Semiconductor chip (1), comprising - a semiconductor layer sequence (10) having a first semiconductor layer (11) and a second semiconductor layer (13), wherein the first semiconductor layer (11) is p-doped and the second semiconductor layer (13) is n-doped or vice versa; - at least one recess (10a) in the semiconductor layer sequence (10), through which side faces (11b, 13b) of the first semiconductor layer (11) and of the second semiconductor layer (13) are exposed; an auxiliary layer (20) for electrically contacting the second semiconductor layer (13), wherein the auxiliary layer (20) is in direct contact with the first semiconductor layer (11) and with the second semiconductor layer (13) at the side surfaces (11b, 13b) exposed by the respective recess (10a), wherein the auxiliary layer (20) forms a diode in the reverse direction to the first semiconductor layer (11) during operation of the semiconductor chip (1) and / or a contact resistance between the auxiliary layer (20) and the first semiconductor layer (11) is at least 100 times higher than between the auxiliary layer (20) and the second semiconductor layer (13).Semiconductor chip (1) according to Claim 2, in which the auxiliary layer (20) contains or consists of one of the following materials: - transparent conductive oxide, - metal.Semiconductor chip (1) according to either of Claims 2 and 3, in which the auxiliary layer (20) comprises zinc oxide or consists thereof, and the semiconductor layer sequence (10) is based on GaN.Semiconductor chip (1) according to either of Claims 2 and 3, in which the auxiliary layer (20) comprises or consists of a gold-germanium alloy, and the semiconductor layer sequence (10) is based on InGaAlP.Method according to Claim 1, in which the auxiliary layer (20) is applied at least partially on a side of the first semiconductor layer (11) facing away from the second semiconductor layer (13) and makes direct contact with the latter at least in a region around the respective recess (10a).Method according to either of Claims 1 and 6, in which, before step b), - a metallic mirror layer (30) is applied to that side of the first semiconductor layer (11) which is remote from the second semiconductor layer (13) and which, corresponding to a region of the respective recess (10a), in each case has an opening (30a) towards the semiconductor layer sequence (10), and - a passivation layer (40) is applied to that side of the metallic mirror layer (30) which is remote from the semiconductor layer sequence (10).Method according to Claim 7, in which the passivation layer (40) is ablated in a lateral region around the respective recess (10a).Method according to one of the preceding claims 7 or 8, in which before step c) a mirror protection layer (50) is applied to the side of the first semiconductor layer (11) facing away from the second semiconductor layer (13), wherein the mirror protection layer (50) completely covers side surfaces (30b) of the metallic mirror layer (30) facing the respective recess (10a).Method according to one of Claims 1 or 6 to 9, in which, in at least one of the steps b), c) or an intermediate step thereof, a modified region (10c) of the semiconductor layer sequence (10) is formed around the exposed side faces (11b, 13b) of the first semiconductor layer (11) and of the second semiconductor layer (13), which region impairs an electrical conductivity between the auxiliary layer (20) and that of the first semiconductor layer (11).Method according to Claim 10, in which the modified region (10c) of the semiconductor layer sequence (10) is at least partially ablated.Method according to one of Claims 1 or 6 to 11, in which - in step b) an active region (12) for generating electromagnetic radiation in the semiconductor layer sequence (10) is penetrated and side faces (12b) of the active region (12) are exposed, and - after step c) the auxiliary layer (20) is at least partially in direct contact with the active region (12) at the side faces (12b) exposed by the recess (10a).Method according to one of Claims 7 to 9, in which, in step b), a semiconductor buffer region (15) is exposed on a side of the first semiconductor layer (11) facing away from the metallic mirror layer (30), and - the auxiliary layer (20), after step c), is at least partially in direct contact with the semiconductor buffer region (15).Semiconductor chip (1) according to one of Claims 2 to 5, which is designed as an optoelectronic semiconductor chip.

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