Device and method for clock generation

Abstract

Device comprising the following: a dithering circuit configured to repeatedly switch between a first value and a second value to generate a tuning word, wherein the dithering circuit is configured to switch with a first clock frequency of a first clock signal, the first clock signal being generated by a clock and data recovery (CDR) system; an accumulator configured to add the tuning word and a previous accumulator output value to generate a new accumulator output value at a second clock frequency of a second clock signal, the second clock signal being generated by a crystal oscillator; and at least one logic circuit designed to generate multiple clock signals, each based on several different bit values ​​of the new accumulator output value.

Description

GENERAL STATE OF THE TECHNOLOGY INVENTIONAL FIELD

[0001] The invention relates generally to electronics, in particular for clock generation. Description of the related technique

[0002] Electronic systems, such as transceivers and receivers, may have a system clock signal based on a quartz crystal with a fixed frequency, but they can also use multiple clock signals of different frequencies. Because transceivers perform functions such as clock and data recovery (CDR), clock signals at multiples of the data rate can still provide diversity and data rate compatibility for further processing within such an electronic system.

[0003] US 2011 / 0299585A1 discloses a receiving device comprising an equalizer circuit, a clock and data recovery circuit, a counting circuit representing a sample result of an input signal supplied to the equalizer circuit, a coefficient changing circuit to adjust the coefficients of the equalizer circuit, a peak detection circuit to identify a peak in the number of occurrences of the sample result at different coefficients, and a coefficient setting circuit that selects the coefficients of the equalizer circuit as they are set when the peak value occurs.

[0004] It is an object of the present invention to demonstrate an improved device and a corresponding improved method for clock and data recovery. BRIEF DESCRIPTION OF THE INVENTION

[0005] One embodiment includes a device comprising: a dithering circuit configured to repeatedly switch between a first value and a second value to generate a tuning word, wherein the dithering circuit is configured to switch at a first clock frequency of a first clock signal, the first clock signal being generated by a clock and data recovery system (CDR system), and an accumulator configured to add the tuning word and a previous accumulator output value to generate a new accumulator output value at a second clock frequency of a second clock signal, the second clock signal being generated by a crystal oscillator.

[0006] Another embodiment includes a clock generation method comprising the following steps: generating a first clock signal, receiving a second clock signal, repeatedly switching between a first value and a second value to generate a tuning word, the switching occurring at a first clock frequency of the first clock signal, and adding the tuning word and a previous accumulator output value to generate a new accumulator output value at a second clock frequency of the second clock signal.

[0007] Another embodiment includes a clock generation device, wherein the device comprises: a means for generating a first clock signal, a means for repeatedly switching between a first value and a second value to generate a tuning word, the switching occurring at a first clock frequency of the first clock signal, and a means for adding the tuning word and a previous accumulator output value to generate a new accumulator output value at a second clock frequency of the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These drawings and the accompanying description are provided here to illustrate embodiments of the invention and are not intended to be limiting. Fig. Figure 1A is a schematic block diagram illustrating an exemplary clock and data recovery (CDR) system including an exemplary clock generation system according to one embodiment. Fig. Figure 1B is a schematic block diagram illustrating a transceiver system including another exemplary clock generation system according to one embodiment. Fig. 1C is a schematic block diagram showing the exemplary clock generation system. Fig. 1A illustrates. Fig. Figure 2 is a schematic block diagram illustrating part of an exemplary clock generation system according to one embodiment. Fig. Figure 3 is a schematic block diagram illustrating another part of an exemplary clock generation system according to one embodiment. Fig. Figure 4A is a schematic block diagram illustrating an implementation example of a clock generation system according to one embodiment. Fig. Figure 4B is a schematic block diagram illustrating an implementation example of a clock generation system according to another embodiment. Fig. Figure 4C is a schematic block diagram illustrating an implementation example of a clock generation system according to another embodiment. Fig. Figure 5 is a timing diagram illustrating an exemplary clock generation according to one embodiment. Fig. Figure 6 is a curve illustrating the performance of an exemplary clock generation system according to one embodiment. Fig. Figure 7 is a curve illustrating the frequency ranges generated by an exemplary clock generation system according to one embodiment. DETAILED DESCRIPTION

[0009] Various aspects of the novel systems, devices, and methods are described in more detail below with reference to the accompanying drawings. This disclosure, however, can be implemented in many different forms and should not be interpreted as being limited to any particular structure or function presented in this entire disclosure. Rather, these aspects are provided in such a way as to ensure that this disclosure is accurate and complete, and that it fully conveys to those skilled in the art the scope of protection of the disclosure. Based on the teachings herein, a person skilled in the art should understand that the scope of protection of the disclosure is intended to cover all aspects of the novel systems, devices, and methods disclosed herein, regardless of whether they are implemented independently or in combination with any other aspect.For example, a device may be implemented or a method carried out using any number of the aspects set forth herein. Additionally, the scope of protection shall cover such a device or method as is carried out using a different structure, a different functionality, or a structure and functionality in addition to or different from the various aspects set forth herein. It is understood that any aspect disclosed herein may be implemented by one or more elements of a claim.

[0010] Although specific aspects are described here, many variations and permutations of these aspects are within the scope of the disclosure. While some uses and advantages of the preferred aspects are mentioned, the scope is not intended to be limited to these specific uses, applications, or objectives. Rather, aspects of the disclosure are intended to be generally applicable to various wired and wireless technologies, system configurations, networks (including optical networks), hard disks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings merely illustrate the disclosure, rather than limiting it, with the scope of the disclosure being defined by the attached claims and equivalents thereto.

[0011] A clock and data recovery (CDR) system transmits data without a separate clock signal. Instead, the clock signal is embedded in the data stream, and the CDR recovers the clock signal when receiving data. By accumulating a fluctuating tuning counter value with an oversampling data rate, multiple one-bit signals can be generated at multiples of the recovered data rate and precisely synchronized with the data stream, while utilizing the full range of the accumulator. These multiple clock signals can be used in different modules within the CDR system and in other modules of a transceiver system that incorporates the CDR system.

[0012] With reference to Fig. 1A: A schematic block diagram illustrating an exemplary clock and data recovery (CDR) system, including an exemplary clock generation system, is described below. The illustrated system 100 includes a CDR module 110, a data rate correction module 112, a non-integer data rate support module 114, and a clock generation system 150. The clock generation system 150 may include a CDR clock enable generator 106 and a clock gate cell 108. The system 100 can be implemented within systems, such as a network device, to capture and track a data stream modulated by one of several modulation schemes. Exemplary modulation schemes include 2-FSK or binary FSK, 3-FSK or ternary FSK, and 4-FSK, depending on the number of digital levels represented in discrete frequencies.System 100 can also include a system clock signal, master clk, which is based, for example, on the frequency of a crystal oscillator that provides clock signals for the CDR clock enable generator 106 and the clock gate cell 108. In some embodiments, other circuits, such as oversampling filters, demodulators, or serializers, can be used instead of the CDR module 110, as also described below. Fig. 1B is described.

[0013] The CDR module 110 performs clock and data recovery. Among other things, the CDR module 110 can receive the signal xN dr_clk generated by the clock generation system 150. In some embodiments, the CDR module 110 can be configured to receive multiple xN dr_clk signals at different frequencies, such as data rates x32, x64, etc. The CDR module 110 can include various internal modules for clock and data recovery. The CDR module 110 can incorporate a numerically controlled CDR oscillator (NCO) that performs clock recovery. The CDR NCO can, among other things, receive a data sequence and generate a signal rx_clk and a signal rx_data, which are the output signals of the CDR module 110. The signal rx_clk is a recovered clock signal, synchronous with the data sequence, and the signal rx_data is a recovered data signal based on the data sequence.The signal rx_clk can be generated by creating a clock signal with a 50% duty cycle, based on an internal count value of the CDR-NCO. For example, the signal rx_clk can be set low for the first half of the CDR-NCO counter period and high for the second half of the CDR-NCO counter period.

[0014] The CDR module 110 can further include additional modules, such as phase detection and reset modules, PLL filters, and / or modular signal acquisition and detection modules, which operate in conjunction with the CDR-NCO. For example, the CDR module 110 can output a reset_nco signal and an msr_phi signal, as required by the phase detection and reset modules. In some embodiments, the internal counter of the CDR-NCO of the CDR module 110 can be programmed, reset, and / or adjusted as the CDR module 110 itself, and the additional modules discussed above operate in conjunction with the data rate correction module 112 and the non-integer data rate support module 114, the features of which are described in more detail below.

[0015] The Data Rate Correction Module 112 can adjust a programmed data rate to match an incoming data rate. The Data Rate Correction Module 112 receives, among other things, a phase signal, gain parameters such as k1 and kT, and a data rate signal, as shown in Fig. Figure 1A illustrates this. In some embodiments, the data rate correction module 112 may include an accumulator, a proportional controller, and an integral controller. The accumulator receives the phase signal msr_phi and accumulates it to generate an error signal. The error signal then passes through a proportional-integral (PI) controller to generate a data rate correction value, where the proportional and integral controllers have gain parameters of ki and kt, respectively. The data rate correction value is added to the data rate signal to generate a data rate corrected signal, which is an output signal of the data rate correction module 112.In one embodiment, the data rate correction module 112 can also include a scaling block to generate a scaling value to be added to the main data rate register to obtain a corrected data rate value, and the data rate adjustment and data rate signals can be summed to generate the data rate corrected signal to be output by the data rate correction module 112.

[0016] The non-integer data rate support module 114 can provide support for data rates that differ from the programmed data rate by a non-integer fraction. In one embodiment, the non-integer data rate support module 114 can include, among other things, programmable counter and denominator registers and an accumulator that accumulates a counter value. The non-integer data rate support module 114 can enable a CDR circuit designed to use a set unit step to approximate a target data rate that is not an integer multiple of the unit step, rather than allowing the system to accumulate non-integer data rate errors over time.The counter register can be set to the counter of the non-integer difference between the actual data rate and the programmable CDR data rate, allowing the adjusted data rate to switch or dither between the programmed data rate and another value, such as the programmed data rate increased by a unit step. For example, the CDR system might be designed to use the unit step of 100 bits / s, and the target data rate might be 32768 bits / s. Without the non-integer data rate support module, the CDR system would have to be programmed to use either 32700 bits / s or 32800 bits / s to approximate 32768 bits / s. Instead, the counter register can be set to 68, and the denominator can be set to 100 in this example. The counter value accumulates over time, and the accumulated counter value exceeding the denominator value is calculated.Each time the accumulated counter value exceeds the denominator value, the adjusted data rate is set to the programmed data rate increased by one unit step. In the example above, the data rate will be 32800 bits / s for 68% of the time and 32700 bits / s for 32% of the time; thus, it approaches 32768 bits / s very closely. The description above regarding support module 114 for non-integer data rates is merely one embodiment of switching or fluctuating between two data rates to achieve a non-integer data rate. The number of bits may, for example, differ from that in the example above; the two data rates may, for example, differ by more than one unit step; and the fluctuation may, for example, occur in the opposite direction.

[0017] The clock generation system 150 can generate a clock signal at N times the data rate. The clock generation system 150 can receive the data rate signal, which can be a data rate corrected by the data rate correction module 112 or a data rate adapted for non-integer data rates by the support module 114. The clock generation system 150 can also receive a scaling factor from a processor (not shown) to multiply the data rate signal and generate an effective data rate signal to be input into the CDR clock enable generator 106. In some implementations, a dedicated hardware block can perform the calculation instead of the processor. In some embodiments, the clock generation system 150 may not be configured to scale the incoming data rate; in this case, the effective data rate signal would be the same as the data rate signal.The clock generation system 150 can output the signal xN dr_clk to the CDR module 110. The signal xN dr_clk is a clock signal with N times the effective data rate. In alternative embodiments, the CDR clock enable generators 106 and the clock gate cells 108 can be configured to generate multiple signals xN dr_clk of different multiples of the effective data rate, such as x16, x32, x64, etc. Further details of the clock generation system 150 are described in conjunction with [reference missing]. Fig. 1C described below.

[0018] With reference to Fig. 1B: A schematic block diagram illustrating a transceiver system including another exemplary clock generation system is described below. The illustrated transceiver system 130 includes an oversampling clock generation system 132, a clock and data recovery system 136, a transmitter subsystem 134, and a receiver subsystem 138. The oversampling clock generation system 132 can be implemented essentially similarly to the clock generation system 150 ( Fig. 1A, Fig. 1C) can be implemented so that several of the signals xN dr_clk ( Fig. 1A) generated with different multiples of the data rate or the effective data rate. The oversampling clock generation system 132 can output multiple clock signals with multiples of the data rate (or the effective data rate) to the clock and data recovery system 136, such as "data rate x2", "data rate x4", ... "data rate x2048", as in Fig. Figure 1B illustrates this. In some embodiments, the clock and data recovery system can consist of 136 modules, such as the CDR module 110 ( Fig. 1A), the data rate correction module 112 ( Fig. 1A), the support module 114 for non-integer data rates ( Fig. 1A) and others, in connection with Fig. 1A discussed modules are included.

[0019] The transmitter subsystem 134 can receive a transmit data clock signal from the clock and data recovery system 136 and the multiple clock signals from the oversampling clock generation system 132. The transmitter subsystem 134 can be configured to receive signals with a transmitting antenna, as shown in Fig. Figure 1B illustrates how to send. Alternatively, the transmission channel can be a wire or an optical fiber.

[0020] The receiver subsystem 138 can receive a receive data clock signal from the clock and data recovery system 136 and the multiple clock signals from the oversampling clock generation system 132. The receiver subsystem 138 can be configured to receive signals, for example, with a receiving antenna, as in Fig. 1B is illustrated, or can be received via a wired or optical connection. The illustrated system 130 can have the advantage of having multiple clock signals generated by the clock and data recovery system 136, which are available to both the transmitter subsystem 134 and the receiver subsystem 138, which use the clocked design disclosed herein. Furthermore, the multiple clock signals generated by the clock and data recovery system 136 can be used in other circuits, such as oversampling filters, demodulators, and serializers.

[0021] With reference to Fig. 1C: A schematic block diagram is described below, illustrating the exemplary clock generation system 150. Fig. Figure 1A illustrates this. The clock generation system 150 can receive a scaling factor of 152 from a processor (not shown) and a data rate of 154, as shown in Fig. Figure 1A illustrates this. In some implementations, a dedicated hardware block can be used instead of the processor. An effective data rate 156 is generated by multiplying the data rate 154 by the scaling factor 152. In some embodiments, the value of the scaling factor 152 can be one, or the illustrated system 150 can omit the scaling features, and the data rate 154 and the effective data rate 156 can be the same. The CDR clock enable generator 106 can receive the effective data rate 156, an accumulator maximum count signal 158 (accum_max_count), and a clock signal 162. The clock enable generator 106 can output a signal 164 indicating that N times the data rate is required (xN dr_clk_req) to the clock gate cell 108. Clock gate cell 108 can also receive a reset signal 168 and the clock signal 162. The reset signal 168 can asynchronously reset the flip-flops of clock gate cell 108.The clock gate cell can generate the signal xN dr_clk 170, which is output by the clock generation system 150, as also shown in . Fig. 1A is illustrated.

[0022] The scaling factor 152 can be used to adjust the data rate 154 to produce the effective data rate 156. The scaling factor 152 can be determined by the processor based in part on the system crystal frequency, the accumulator maximum count signal 158, and the programmability of the accumulator maximum count signal 158. For example, a 26 MHz crystal and an 18-bit accumulator can be used in one implementation, and the accumulator maximum count signal 158, which can act as a module for division, can be set to 260,000 in the implementation. In this example, a 52 MHz crystal can be used instead of the 26 MHz crystal, with the scaling factor 152 set to, for example, 1 / 2, without any further change in the bit selection.The scaling factor of 152 can provide diversity in the input crystal frequency because it can be used to adjust the data rate based on the crystal frequency. For example, an accumulator width increment of 1 at 26 MHz in this example can result in a data rate of 100 bits per second (bit / s). In some embodiments, the application of the scaling factor of 152 can be accomplished using shift registers.

[0023] The CDR clock enable generator 106 can be implemented in various ways, which are described below in conjunction with the Fig. 2 and Fig. Include the 3 described features. Implementation examples for the CDR clock release generator 106 are further detailed below. Fig. 4A - 4C illustrates this. In some embodiments, the CDR clock enable generator 106 can output multiple signals 164 xN dr_clk_req, so that the clock generation system 150 can output multiple clock signals xN dr_clk to other modules, such as those associated with the Fig. Modules 1A - 1B illustrated and discussed. Details of specific implementations of the CDR clock enable generator 106 are given below in conjunction with the Fig. 2 - 4C discussed. In some embodiments, the several, in conjunction with the Fig. The features described below (2 - 4C) are combined to implement the CDR clock enable generator 106.

[0024] The clock gate cell 108 can be configured to enable or disable multiple clock signals generated by the CDR clock enable generator 106, for example to reduce power consumption. The clock gate cell 108 can receive multiple signals xN dr_clk_req 164 and enable or disable each of the signals xN dr_clk_req 164, as required by the systems 100 ( Fig. 1A) and 130 ( Fig. 1B) is required, which incorporates the clock generation features disclosed here.

[0025] With reference to Fig. 2: A schematic block diagram illustrating part of an exemplary clock generation system is described below. The illustrated system 200 can be part of an implementation example for the CDR clock enable generator 106 ( Fig. 1A, Fig. 1C). The illustrated System 200 contains a multiplexer 202, a tuning adder stage 204, an accumulator adder stage 206, and a data rate accumulator register 208. The System 200 receives a data rate or effective data rate signal, as in conjunction with the Fig. 1A and Fig. As described in 1C, the data rate or effective data rate signal is modified by dithering to generate a tuning word, and the tuning word is accumulated to generate an accumulator output signal. In an embodiment as described in Fig. As illustrated in Figure 2, the System 200 can include a 16-bit data rate input signal and an 18-bit accumulator output signal, and in other embodiments, the data rate input signal and the accumulator output signal can each have a different number of bits than those shown in Figure 2. Fig. The two illustrated examples show that the number of bits can vary over a wide range.

[0026] The illustrated System 200 implements an accumulator with the accumulator adding stage 206 and the data rate accumulator register 208. The data rate accumulator register 208 also accepts a system clock signal, which can, for example, be at the system crystal frequency. Because the data rate accumulator register 208 accumulates the input data rate value with each cycle of the clock signal, each bit value of the output signal of the data rate accumulator register 208 can have a frequency multiple of the input data rate value. For example, if the input clock for the data rate accumulator register 208 is 26 MHz and the data rate is 100 bits / s, the accumulator output signal will accumulate bits at a rate of 26 MHz / 100 bits / s, which can generate count values ​​of up to 260,000 per bit, assuming that the register has a sufficient number of bits.Therefore, a maximum count value or module can be determined based on the input clock and the data rate. In the example above, the module can be set to 260,000. If, for example, the data rate accumulator register 208 has 18 bits, the data rate accumulator register 208 can hold the maximum count value of 2. 18 exhibit -1, which is 262,143. In some embodiments, the maximum countable register value of the data rate accumulator register 208 can be a constant multiple of the module, because the module can be a power of two (minus one). One implementation of such embodiments is further described below in connection with Fig. 4C is discussed. In other embodiments, the maximum countable register value of the data rate accumulator register 208 may not be a constant multiple of the count values ​​generated based on the data rate and the clock frequency; in this case, a dithering circuit and / or a count reset circuit can be implemented. The count reset circuit is used in conjunction with the Fig. 4A - 4B described below. The dithering circuit, as described in Fig. 2, which is illustrated, is described below.

[0027] The illustrated System 200 implements the dithering circuit with the multiplexer 202 and the tuning adder stage 204. The multiplexer 202 can select one of two values, such as K and 0, as shown in Fig. Figure 2 illustrates this. The value of K can be determined by the number of bits that the accumulator register 208 has and the system crystal frequency CLK. For example, an implementation example for System 200 might have the data rate accumulator register 208 with 18 bits, the system crystal frequency of 26 MHz, and the data rate of 100 bits per second (bit / s). As in the previously discussed example, the counter can count upwards to 260,000, one bit at a time, even though the data rate accumulator register 208 has 18 bits that can count upwards to 262,143. If the module (e.g., 260,000) uses only a portion of the number scheme, which ranges from 0 to 2, the counter will be able to count upwards by one bit at a time. NSince -1 (e.g., 262,143) may suffice, it can be advantageous to distribute the accumulator numbers for oversampling clock generation across the entire range of the number scheme. To bring the count value per bit or module (e.g., 260,000) as close as possible to the maximum countable register value (e.g., 262,143), an adjustment value K can be added to the data rate in the tuning adder stage 204. The adjustment value K can be added to the data rate multiplied by N (data rate x N) because the multiplexer 202 receives the clock signal data rate x N and oscillates between K and 0. In this example, the adjustment value K can be 66, and the signal data rate x N can be at data rate x 32; in this case, the counter can count upwards to 260,000 + 66 × 32 = 262,112, which is close to 262,143.Because the difference between the module and the maximum countable register value is reduced, the entire range of the data rate accumulator register 208 can be used, for example, with a minimal error in the output clock signals. In other embodiments, a different adjustment value K and / or a different multiple N of the data rate can be used to further reduce the difference. In other embodiments, the counter reset circuit, which is used in conjunction with the... Fig. 4A - 4B, as described below, can be used instead of or in conjunction with the dithering circuit.

[0028] With reference to Fig. 3: A schematic block diagram illustrating another part of an exemplary clock generation system is described below. The illustrated system 300 can be part of an implementation example for the CDR clock enable generator 106 ( Fig. 1A, Fig. 1C). In one embodiment, the system 300 can be, as in Fig. Figure 3 illustrates an 18-bit accumulator with 18 registers for 18 bits, designated accordingly from 0 to 17. In another embodiment, an accumulator of System 300 can have a different number of bits than shown. Fig. 3 is illustrated. The part of the in Fig. The exemplary clock generation system illustrated in Figure 3 can include multiple one-bit registers and one or more logic circuits to generate one or more output clocks. Specifically, the illustrated system 300 includes 18 one-bit registers and three logic circuits, each containing an inverter and an AND gate. The three logic circuits can function as edge detectors. In other embodiments, the number of one-bit registers and the number of logic circuits can differ. In other embodiments, the logic circuits or edge detectors can be implemented with circuit elements other than an inverter or an AND gate. The system 300 then outputs one or more clock signals, such as clock signals 302, 304, and 306, via one or more corresponding registers.

[0029] For better illustration, the System 300 shows the output clock signals 302, 304, and 306, and the System 300 can have a larger or smaller number of output clock signals. Clock signal 302, for example, is based on the current and previous values ​​of the 13th bit (of the least significant bit, or LSB) of an 18-bit register, such as the data rate accumulator register 208 ( Fig. 2), generated. The 13th bit (of the LSB) of the 18-bit register oscillates between 0 and 1 at a rate 32 times the data rate, because 2 (18-13) = 2 5 = 32. Similarly, the clock signal 304 is generated, for example, based on the current and previous values ​​of the 12th bit (of the LSB) of the 18-bit register. Therefore, the output clock signal 304 has 64 times the data rate because 2 (18-12) = 2 6= 64. Likewise, the clock signal 306 has 128 times the data rate, and if more logic circuits are added to more bits of the accumulator, the system 300 can theoretically use the clock signal at up to 2 n -fold of the data rate, where n is the number of bits in the accumulator register minus one (e.g., 17 for an 18-bit register). In embodiments that utilize the full range of the maximum countable accumulator register value (e.g., 262,143 in the example mentioned above), all clocks based on the LSB to the most significant bit (MSB) can be generated exactly. In embodiments that do not utilize the full range of the maximum countable accumulator register value, output clocks up to a certain multiple of the data rate can be generated using the System 300 in conjunction with, for example, the following: Fig. The dithering circuit described above can be generated exactly as described above.

[0030] The Fig. Figures 4A-4C illustrate various implementation examples for the clock generation system described here. Although the examples in the Fig. While the systems illustrated in 4A - 4C contain specific bit counts for certain signals, the clock generation system described here can, in other embodiments, use signals with bit counts that differ from those shown in the Fig. 4A - 4C illustrated the differences, which can be implemented. In one embodiment, the differences shown in the Fig. 4A - 4C illustrated systems with a constant modulus (e.g. 260,000) and a scalable clock input signal (e.g. by a factor of 1 / f). xtal ) implement. In another embodiment, the in the Fig. The embodiments illustrated in Figures 4A-4C implement a programmable module and a scalable clock input signal; in this case, a maximum accumulator count (accum_max_count) can be programmable. In another embodiment, the elements shown in the Fig. 4A - 4C illustrated systems implementing a programmable module and a constant clock input signal.

[0031] With reference to Fig. 4A: A schematic block diagram illustrating an implementation example for a clock generation system is described below. A clock enable generation system 106a can be an implementation example for the CDR clock enable generator 106 from the Fig. 1A, Fig. It should be 1C. Fig. 4A contains the clock release generation system 106a and a data rate correction / support module 404. The data rate correction / support module 404 can provide one or more of the features of the data rate correction module 112 ( Fig. 1) and the support module 114 for non-integer data rates discussed above ( Fig. 1) included. The in Fig. The system illustrated in 4A also includes scaling an input clock signal (input clk) by a factor of 1 / f. xtal, which generates an effective data rate signal based on the data rate signal from the data rate correction / support module 404. This factor can be determined similarly to how the scaling factor is determined, as described in conjunction with Fig. 1 is discussed. The clock release generation system 106a contains a counter reset circuit 402 and the accumulator and logic features that, in conjunction with the Fig. 2 - 3 will be discussed above.

[0032] The 402 counter reset circuit can have a constant module or a maximum accumulator count (accum_max_count). The 402 counter reset circuit can also include a comparator and a multiplexer, as shown in Fig. Figure 4A illustrates how to determine whether the accumulated data rate count is greater than the constant module. If the counter reset circuit 402 determines that the accumulator count is greater than the constant module, it can reset the accumulator count to zero. For example, if the data rate is 100 bits / s and the system crystal frequency is 26 MHz, the constant module can be selected from 260,000. Assuming that the accumulator in the clock enable generation system 106a has a sufficient number of bits (e.g., at least 18 bits), the counter reset circuit 402 can be configured to reset the accumulator counter to zero after the count reaches 260,000. Therefore, the circuit shown in Figure 4A illustrates how to use the accumulator to determine whether the accumulated data rate count is greater than the constant module. Fig. 4A illustrated how to implement a constant module and a scalable clock input signal in the system.

[0033] With reference to Fig. 4B: A schematic block diagram illustrating another implementation example for a clock generation system is described below. The one in Fig. The system illustrated in 4B includes the clock release generation system 106a and the data rate correction / support module 404, which, in conjunction with Fig. 4A will be discussed above. Unlike the one in Fig. 4A illustrated system takes the clock release generation system 106a from Fig. 4B receives the data rate signal from the data rate correction / support module 404 without scaling the data rate. Therefore, this can be in Fig. Figure 4B illustrated how to implement a programmable module with a constant clock input signal.

[0034] With reference to Fig. 4C: A schematic block diagram illustrating another implementation example for a clock generation system is described below. A clock enable generation system 106b can be another implementation example for the CDR clock enable generator 106 from the Fig. 1A, Fig. It should be 1C. Fig. 4C includes the Clock Release Generation System 106b and the Data Rate Correction / Support Module 404, which are described above in conjunction with the Fig. 4A - 4B will be discussed. The clock release generation system 106b also includes the accumulator and logic features, which are discussed above in conjunction with the Fig. 2-3 will be discussed. The clock enable generation system 106b can implement a programmable module that is a power of two, and the clock enable generation system 106b can be implemented without the counter reset circuit 402. If the module is a power of two, the registers in the clock enable generation system 106b would reset when the counter accumulates and reaches its maximum, and a reset circuit might not be necessary.

[0035] With reference to Fig. 5: A schematic timing diagram illustrating an example of clock generation is described below. The illustrated diagram shows an implementation example of the revelation here with a CDR-NCO, similar to the one in conjunction with Fig. 1A discussed a device that runs at 32 times the data rate and an accumulator that adds the data rate at 26 MHz. In this example, as shown in the line labeled "Data Rate", the Fig. The time period shown in Figure 5 represents a one-bit period of the data signal, and during this period, the disclosed clock generation system accumulates to approximately 262,000. Based on different bits of the accumulator, as discussed above, multiple clock signals of multiples of the data rate can be generated. In this example, a clock signal with 32 times the data rate, referred to as "DR × 32", can be generated based on the 13th bit of an 18-bit register. Likewise, clock signals at other multiples of the data rate can be generated based on different bits of the accumulator, as shown in Figure 5. Fig. 5 is shown.

[0036] With reference to Fig. 6: A curve illustrating the performance of an exemplary clock generation system is described below. The curve has an input crystal frequency in the range of 25 MHz to 55 MHz on the horizontal or x-axis and multiples of the data rate frequencies in megabits per second (Mbit / s) on the vertical or y-axis. The curve illustrates the generation of multiple clock signals, as disclosed here, based on a data rate of 0.1 Mbit / s. Based on a data rate of 0.1 Mbit / s, clock signals of 3.2 Mbit / s (32 times the data rate), 1.6 Mbit / s (16 times the data rate), 0.8 Mbit / s (8 times the data rate), 0.4 Mbit / s (4 times the data rate), and 0.2 Mbit / s (2 times the data rate) can be generated using a range of input crystal frequencies. Certain combinations of crystal frequencies and data rates can produce more or less exact multiples of the data rates, as shown in the line "32 × data rate" in Fig. Figure 6 is shown because clock generation can involve discarding non-integer bits when the data rate is divided by the crystal frequency. The accuracy of the data rate multiples can be improved, for example, by adding more resolution to the non-integer bits.

[0037] With reference to Fig. 7: A curve illustrating the frequency ranges generated by an example clock generation system is described below. The curve in Fig. Figure 7 illustrates a maximum frequency that can be generated with respect to an input clock frequency. Fs in Fig. 7 is an input frequency sampling rate, which could be, for example, a crystal frequency, such as 26 MHz in the examples discussed above. The x-axis of the curve in Fig. Figure 7 shows various oversampling factors (OS) that can be used, for example, in a system implementing clock and data recovery. The y-axis of the curve in Fig. Figure 7 shows the maximum range of data rates in bits / s at which an exact oversampling clock can be generated based on the clock generation system revealed here. As in Fig. As illustrated in Figure 7, for a given OS and Fs, a data range extending up to Fs / (2×OS) can be used to generate an oversampling clock without compromising the accuracy as disclosed herein. For example, if Fs is 26 MHz and clock and data recovery are performed at 32 times the data rate (i.e., an OS of 32), the maximum data rate for generating an exact oversampling clock is 406.25 kHz.

[0038] The preceding description and the claims may refer to elements or features that are "connected" or "coupled" to one another. Unless expressly stated otherwise, "connected," as used herein, means that one element / feature is directly or indirectly connected to another element / feature, but not necessarily mechanically. Unless expressly stated otherwise, "coupled" likewise means that one element / feature is directly or indirectly coupled to another element / feature, but not necessarily mechanically. Thus, although the various circuit diagrams shown in the figures represent exemplary arrangements of elements and components, additional, intermediate elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the circuits shown is not adversely affected).

[0039] As used here, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculating, computing, processing, deducing, investigating, looking up (e.g., looking up in a table, database, or other data structure), ascertaining, and the like. It can also include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and the like. "Determine" can also include solving, selecting, choosing, ascertaining, and the like. Furthermore, "channel width," as used herein, can in certain aspects encompass or be described as bandwidth.

[0040] The various operations of the procedures described above can be performed by any suitable means capable of carrying out the operations, such as various hardware and / or software components, circuits, and / or modules. In general, any operations illustrated in the figures can be performed by appropriate functional means capable of carrying out the operations.

[0041] The various illustrative logic blocks, modules, and circuits described in connection with this disclosure can be implemented or realized using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate array or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computer devices, e.g.,a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0042] The methods disclosed herein comprise one or more steps or actions to achieve the described process. The process steps and / or actions can be interchanged without deviating from the scope of protection of the claims. In other words, unless a specific sequence of steps or actions is specified, the sequence and / or the use of specific steps and / or actions can be modified without deviating from the scope of protection of the claims. Applications

[0043] Furthermore, the disclosed methods, systems, and / or devices can be implemented in various electronic devices. Examples of electronic devices include, but are not limited to, consumer electronics products, components of consumer electronics products, electronic testing equipment, etc. Examples of electronic devices may also include memory chips, memory modules, optical network or other communication network circuits, and hard disk drive circuits.Consumer electronics and household appliances may include, but are not limited to, the following: wireless equipment, mobile phones, cellular base stations, telephones, televisions, computer monitors, computers, laptops, personal digital assistants (PDAs), microwave ovens, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, video recorders, MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer-dryers, copiers, fax machines, scanners, multifunctional peripherals, wristwatches, watches, etc. Electronic equipment may also include unfinished products.

[0044] It is understood that the implementation methods are not limited to the exact arrangement and components described above. Various modifications, changes, and variants can be made to the arrangement, operation, and details of the methods and devices described above without deviating from the scope of protection afforded by the implementation methods.

[0045] Although this invention has been described in terms of certain embodiments, other embodiments that would be apparent to a person skilled in the art, including embodiments that do not provide all of the features and advantages set forth herein, also fall within the scope of protection of this invention. Furthermore, the various embodiments described above can be combined to provide further embodiments. Additionally, certain features shown in connection with one embodiment can also be incorporated into other embodiments.

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