DC-DC buck converters protected against short circuits

Abstract

Buck converter, which is capable of self-protection of the buck converter against a short circuit or overload at the output of the buck converter by means of a self-protection loop, of managing a recovery from a short circuit or overload condition of the buck converter and for an intrinsic soft start that prevents excessive inrush currents, which includes the following: an output stage comprising a high-side switch and a low-side switch, both connected in series, the output stage being configured to be connected to a coil having a first terminal at a node between the high-side switch and the low-side switch; a minTon unit configured to define a minimum on-time of the high switch; a minToff time unit configured to limit a maximum switching frequency of the buck converter; a circuit arrangement configured to detect a short circuit or overload condition of the buck converter, wherein the overload condition includes reaching a current limit of a current through the coil; a current coil low-crossing detector configured to detect when the current through the coil reaches a defined low-crossing value, which may be zero, and configured to output a corresponding signal; and a control logic configured to perform a short-circuit self-protection loop by enabling and managing a recovery from the short-circuit or overload condition of the buck converter, wherein the circuit arrangement configured to detect a short circuit or overload condition of the buck converter includes a high-side switch current sensing unit and a first comparator configured to compare the result of the high-side current sensing with a reference current.

Description

(1) Technical field

[0001] This disclosure relates generally to electronic circuits and, more particularly, to new short-circuit self-protection methods and circuits for buck converters and boost converters that are self-protected against short circuits. (2) Background

[0002] There is a growing demand for switching converters such as buck converters. A very important feature of buck converters is the ability to withstand an output short circuit. US 8 710 810 B1 describes a regulated power supply system using multiphase DC-DC converters with dynamic phase rejection, featuring fast turn-on, slow turn-off, early turn-on, and both load voltage and drive transistor feedback to pulse width modulators. DE 10 2011 088 654 A1 describes a method for controlling a switching converter, whereby the switching converter is configured to convert an input voltage into an output voltage that is supplied to a load according to a switching signal.

[0003] Currently, most of the commercial or known solutions to protect a buck converter from damage to a short-circuit relay are based on the following: - external components; - Cycle-to-cycle current limiting; - Frequency return technology; - Hiccup mode;

[0004] It is obvious that the use of external components is expensive and does not contribute to the robustness of the converter itself.

[0005] Cycle-to-cycle current limiting and frequency flyback techniques, as outlined later, require complex design effort and, if not carefully designed, do not always guarantee reliable short-circuit protection.

[0006] In the above protection, the control loop must also be carefully checked to avoid instability problems.

[0007] Hiccup mode instead generates a tremendous influx of current on each cycle and can therefore cause problems at the system level.

[0008] All these techniques rely on the designer's ability to identify the worst-case condition and define the trade-off between frequency, stability, duty cycle, minimum off-time, minimum on-time, inductor and capacitance parameters.

[0009] It is a challenge for designers of buck converters or boost converters to overcome the disadvantages mentioned above. SUMMARY

[0010] A primary object of the present disclosure is to achieve self-protection against a short circuit present at a buck converter output or a boost converter output, as well as intrinsic circuitry for soft start or inrush current limiting, respectively.

[0011] Another object of the present disclosure is to achieve a simple implementation of self-protection against a short circuit present at a buck converter output or a boost converter output.

[0012] Another object of the present disclosure is to achieve self-protection against a short circuit applied to a buck converter output or a boost converter output that is independent of frequency, minimum turn-on time, minimum turn-off time, duty cycle, inductor and capacitance parameters.

[0013] Another object of the present disclosure is to achieve robust and stable self-protection against a short circuit applied to a buck converter output or a boost converter output.

[0014] Furthermore, it is an object of the present disclosure to achieve self-protection against a short circuit present at a buck converter output or a boost converter output, which can be applied to basically all modulation loops, including CCM PFM.

[0015] Moreover, it is an object of the present disclosure to achieve a robust and stable self-protection against a short circuit applied to a buck converter output or a boost converter output that does not generate inrush current problems.

[0016] According to the objectives of this disclosure, a buck converter is proposed that is capable of self-protection against a short circuit at the output of the buck converter and of an intrinsic soft start that prevents excessive inrush currents. The disclosed buck converter first comprises: an output stage having a high-side switch and a low-side switch, both connected in series, wherein the output stage is connectable to an inductor having a first terminal at a node between the high-side switch and the low-side switch; a minTon time unit that defines a minimum on-time of the high-side switch; and a minToff time unit configured to limit a maximum switching frequency of the buck converter.Furthermore, the buck converter comprises circuitry configured to detect a short circuit or overload condition of the buck converter, wherein the overload condition comprises reaching a current limit of a current through the coil, a current coil low crossing detector capable of detecting when the current through the coil reaches a defined low crossing value, which may be zero, and outputting a corresponding signal, and control logic configured to perform a self-protection loop by activating and managing recovery from a short circuit or overload condition of the buck converter.

[0017] According to the objects of the disclosure, a method for self-protection of a buck converter against a short circuit at the output of the buck converter and for an intrinsic soft start that prevents excessive inrush currents is proposed.The disclosed method comprises the steps of: (1) providing a buck converter having an inductor and an output stage having a high-side switch and a low-side switch, (2) checking, by appropriate circuitry, whether a short circuit or overload condition exists at the output of the buck converter, and if so, going to step (3), otherwise repeating step (2), and (3) ensuring that the output stage remains in the tri-state condition once the inductor current reaches zero until an internal controller instructs the current to flow in a same direction as the current limit that was previously triggered, and restoring normal operation of the buck converter and going back to step (2). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which form an integral part of this description, show: Fig. Figure 1 shows a block diagram of a buck converter using a DCM and PFM operating mode protected against short circuit. Fig. 2 shows a time diagram of the output voltage V OUT , the reference voltage V REF , the coil current I L , and the load current I LOAD of the buck converter of Fig. 1. Fig. Figure 3 shows a block diagram of a buck converter without short circuit protection known to the inventor using the CCM and PFM modes of operation. Fig. 4 shows a time diagram of the output voltage V OUT , the reference voltage V REF , the coil current I L and the load current I LOAD of the buck converter of Fig. 3. Fig. Figure 5 shows a general PWM controlled buck converter characterized by a minimal turn-on time. Fig. Figure 6 shows a short circuit condition for an unprotected buck converter in DCM PFM. Fig. Figure 7 shows the case of a short circuit to ground applied to VOUT (forced zero voltage between VOUT and ground VOUT = 0 V) ​​of a buck converter in CCM PFM. Fig. Figure 8 shows the case of a short circuit, which occurs when the short circuit is present while VOUT is below VREF, of a buck converter in CCM PFM. Fig. Figure 9 shows the coil current and output voltage waveforms for a PWM buck converter shorted to ground. Fig. 10a shows waveforms of the coil current I L for a buck converter in CCM with short circuit protection and VOUT shorted to ground. Fig. Figure 10b shows the waveforms of Fig. 10a zoomed in. Fig. 11 represents a first implementation of short-circuit self-protection in CCM PFM. Fig. 12 represents a second implementation of short-circuit self-protection in CCM PFM. Fig. Figure 13 shows waveforms of the coil current, Vout, the CLK pulses, the HIGH_Z signal and the CLK_LIMIT signal in the case of a ground-shorted output VOUT=0 in a CCM-PWM operation. Fig. Figure 14 shows a short-circuit protection circuit implementation in PWM for VSHORT <= VREF. Fig. 15 shows a short circuit protection circuit implementation in PWM for any VSHORT. Fig. Figure 16 shows a PWM start of a buck converter with a large capacitance at the output. Fig. Figure 17 shows a flowchart of a method for self-protection of a buck converter against a short circuit at the output of the buck converter and for an intrinsic soft start that prevents excessive inrush currents. DETAILED DESCRIPTION

[0019] This disclosure is about a new self-protection method and short-circuit protection circuit for buck and boost converters and their implementation in particular for two of the most common modulations: pulse frequency modulation (PFM) and pulse width modulation (PWM).

[0020] Disclosed are embodiments of methods and circuits for achieving self-protection against a short circuit present at a buck converter output or a boost converter output, as well as having an intrinsic soft start circuit arrangement for a soft start or an inrush current limit, wherein the converter operates using various modulation feedback loops such as CCM, PFM or PWM. Description of discontinuous conduction mode (DCM) and PFM

[0021] Fig. 1 shows a block diagram of a buck converter with short circuit protection known to the inventor using DCM and PFM operating modes. Fig. 2 shows a time diagram of the output voltage V OUT , the reference voltage V REF 23, the coil current I L and the load current I LOAD The currents and voltages in Fig. 2 correspond to the Fig. 1 shown buck converter. Fig. 2 shows the coil current I L 20, the load current I LOAD 21, a programmed current peak PCP 24 of the coil current I L , the output voltage V OUT 22 and the reference voltage V REF 23.

[0022] As in Fig. 1 and in Fig. 2, starting with a high impedance (Hi-Z) condition of the output stage at time t1, when the output voltage V OUT below the reference voltage V REF, the undervoltage comparator UVC 7 is triggered and the flip-flop 9 is set. Consequently, the high side in the output stage 1 is activated, as well as the high side current detection HCS 2 and the overcurrent comparator OCC 12, which is masked out for a minimum on-time (minTon) 11. During this phase, the high side current (i.e. also the current I L in coil 4) is sampled by HCS 2 and converted into an internal amplified copy, which is compared with a function of an internal reference (IREF) of the programmed current peak PCP 24, as shown in Fig. 2. The high-side current sense (HCS) 2 includes the internal amplified replica. Once the current in the coil reaches the programmed current peak (PCP) 24, the OCC 12 triggers and resets the flip-flop 9. From this point, the low-side output is enabled, as well as the low-side current sense (LSCS) 3 and the zero-crossing current comparator (ZCCC) 10. The current in the coil decreases, and once it reaches zero, the ZCCC 10 triggers, putting the output stage into high-impedance (High-Z) mode. Due to the AND logic block 8, only at this point, when VOUT is still below the reference voltage VREF, can the loop restart.

[0023] Blocks 13 and 5 are a general logic inverter gate and a buck converter output capacitor, respectively. Description of PFM function in continuous conduction mode (CCM)

[0024] Fig. Figure 3 shows a block diagram of a buck converter without short circuit protection known to the inventor using CCM and PFM modes of operation. Fig. 4 shows a time diagram of the output voltage V OUT , the reference voltage V REF , the coil current I L and the load current I LOAD of the buck converter of Fig. 3. As in Fig. As shown in Figure 4, starting from a Hi-Z output stage condition, when VOUT 41 falls below the reference voltage VREF 40, the undervoltage comparator (UVC) 7 triggers and the flip-flop 9 is set. Consequently, the high side of the output stage 1 is activated, as well as the high side current sense (HSCS) 2 and the OCC 12, which is gated for a minimum on-time (minTon) 11. During this phase, the high side current (i.e., also the current in coil 4) is sensed and converted into an internal amplified replica, which is compared with a function of an internal reference IREF_MAX of the programmed current peak. Once the current in the coil reaches the programmed current peak, the OCC 12 triggers and resets the flip-flop 9. From this point on, the low side of the output stage 1 is activated, as are the low side current sense (LSCS) 3 and the ZCCC 10.The current in the coil decreases, and this time (unlike DCM PFM), after a minimum Toff time specified by block 14, if the VOUT voltage is still below the reference voltage VREF (since AND gate 9 is no longer gated by the minToff time), the loop can restart. In any case, when the current in the coil reaches zero, the ZCCC 10 triggers, driving output stage 1 to high-Z (high impedance).

[0025] Furthermore, the circuit of Fig. 3 an inverter gate 13 and the buck converter output capacitance 5. PULSE WIDTH MODULATION (PWM) FUNCTIONAL DESCRIPTION

[0026] PWM (Pulse Width Modulation) is the most common modulation used by DC-to-DC converters.

[0027] There are too many possible implementations of a PWM control loop and for this reason they will not be described in detail. However, for reference, Fig. 5 is a general-purpose PWM-controlled buck converter characterized by a minimum turn-on time (minTon). Clock 8 periodically sets flip-flop 10, while the PWM loop controls the on / off switching time based on feedback from the actual output voltage VOUT, reference voltage VREF (ideal output voltage), HSCS 2 and LSCS 3, and minTon unit 9. The minimum Ton period is a value that can be defined in minTon unit 9.

[0028] Blocks 4 and 5 are the buck converter inductor and the buck converter output capacitance, respectively. Block 11 is a general logic inverter. SHORT-CIRCUIT BEHAVIOUR FOR AN UNPROTECTED BUCK CONVERTER IN DCM / PFM

[0029] In case of a short circuit on the buck converter output voltage, if the voltage applied to VOUT is above the target voltage (VOUT >= VREF), the buck converter remains under the tri-state condition.

[0030] Fig. Figure 6 shows a short-circuit condition for an unprotected buck converter in DCM PFM, i.e., a short circuit to ground applied to VOUT (forced zero voltage between VOUT and ground, VOUT = 0 V). If, instead, the short circuit applied to VOUT is below the reference voltage VREF (VOUT < VREF), the buck converter attempts to deliver as much current as it can. Fortunately, in DCM PFM, even in the case of a short circuit, the maximum deliverable current is limited by the intrinsic control loop to a maximum of half the programmed peak current. SHORT-CIRCUIT BEHAVIOUR FOR AN UNPROTECTED BUCK CONVERTER IN CCM / PFM

[0031] In the event of a short circuit at the buck converter output voltage, if the voltage short circuit present at VOUT is above the target voltage (VOUT >= VREF), the buck converter remains in the tri-state state. If, instead, the short circuit present at VOUT is below the reference voltage VREF (VOUT < VREF), the buck converter attempts to deliver as much current as it can. This time, in CCM PFM, the maximum deliverable current is well above the programmed peak current due to the constraints of minToff and minTon.

[0032] In fact, the maximum switching frequency is limited not only by the minToff time, but also by the minTon time, which is intrinsically based on the design. When the high side of the output stage is turned on, the current comparator should actually start operating. To prevent it from triggering for the initial inrush current, a blanking time must be implemented. This is the minTon time. It may happen that, due to design limitations, minTon and minToff cannot be correlated and are thus selected independently. In this case, there is no guarantee that the buck converter will operate correctly during a short circuit. Due to these limitations, the current in the inductor continues to increase until a new steady state is reached. Unfortunately, this new steady state may require the inductor current to exceed the maximum allowable current, eventually destroying the inductor.

[0033] Fig. Figure 7 shows the case of a short circuit to ground applied to VOUT (forced zero voltage between VOUT and ground; VOUT = 0 V).

[0034] Fig. Figure 8 shows the case of an applied short circuit when the short circuit is present while VOUT is below VREF. In this case, the buck converter turns on the high side. Once the programmed current limit is reached, the low side is turned on, but after the minToff period, VOUT is still below VREF, so the buck converter has no choice but to turn on the high side again for at least a minTon period, even if the current in the coil is above the current limit. With an applied short circuit, the buck converter in CCM PFM can only operate with minTon and minToff, and for the reason explained above, the current in the coil may not be limited correctly, and the coil may eventually be destroyed. Short-circuit behavior for a PWM buck converter protected by cycle-to-cycle current limiting.

[0035] Fig. Figure 9 shows the coil current and output voltage waveforms for a buck converter shorted to ground in PWM.

[0036] For simplicity, the case of a short circuit at the buck converter output voltage is considered when the short circuit voltage applied to VOUT is below the target voltage (VOUT < VREF). The case of a buck converter characterized by positive cycle-to-cycle current limiting and a period of minimum turn-on time minTon is also considered.

[0037] In this case, as in the case of CCM PFM, even though the current limit is triggered, the buck converter must remain on for at least one minTon period. Therefore, the coil current increases until a new steady state is reached. Although the current limit is set to approximately 600 mA, steady state can only be reached at 2 A coil current due to the minTon setting.

[0038] Implementations of short-circuit self-protection in CCM-PFM modulation mode: New short-circuit self-protection procedure

[0039] To limit the current in the coil in case of a short circuit (and also at start, as in Fig. 16), a new method is disclosed:

[0040] The basic idea for this short circuit self-protection can be divided into 3 steps: 1. A circuit must detect the short circuit / overload condition. 2. When a short circuit is detected, the current in the coil must be limited at its peak value, and once this limitation is triggered, the current must be inverted as soon as possible until it is low enough (or high enough for negative currents) so that the limit is not exceeded during the next forced on-time. This can apply to either the on-time of the high-side switch or the on-time of the low-side switch (usually t off called). 3. Once the current reaches zero or a value close to zero, the output stage must remain in the tri-state state until the internal control commands the current to flow in the same direction as the current limit that was previously triggered. At this point, normal operation can be restored. (If the short circuit is still detected, steps 2 and 3 are repeated.) Implementations of short-circuit self-protection in CCM PFM

[0041] To detect the short circuit / overload condition, 2 possible solutions are revealed: 1) Use of an additional overcurrent comparator output (OCC output) with the option in combination with the minTon period unit (Ton); (1st implementation), as in Fig. 11 shown. 2) Use of the minTon time unit in combination with the OCC output (2nd implementation), as in Fig. 12 shown.

[0042] With reference to Fig. 11, in the 1st implementation, if a short circuit exists that forces VOUT < VREF, which is detected by the undervoltage comparator (UVC) 7, first the high-side current sensing unit 2 triggers the primary current limiting comparator OCC 12, then after the first minimum high switch on time, as defined in the minTon unit 11, the second OCC 15 can be selectively triggered by the minTon unit 11, and since the buck converter is not in high-Z (tri-state, HIGH_Z low), the CLK_LIMT signal is set to 0 by the flip-flop 16. At this point, due to the AND gate 8, the current in the coil is forced to decrease until it reaches the low pass-through value Izero_ref, as input to the ZCCC unit 10. The low pass value IZERO_ref can be zero or close to zero.The moment the current in the coil reaches Izero_ref, the HIGH_Z signal goes high, setting the buck converter to high-Z. Since flip-flop 16 is reset and the CLK_LIMIT signal is again 1, AND 8 is no longer gated, and the buck converter can resume normal operation. If the short circuit is not removed, the short-circuit self-protection loop repeats.

[0043] It should be noted that the minimum Toff time and the minimum Ton time may be different.

[0044] In the Fig. In the second implementation shown in Figure 12, when a short circuit occurs forcing VOUT < VREF, the current first triggers the current limit comparator OCC 12, then immediately after the following minimum turn-on time (minTon) of the high switch, since the OCC 12 is still high and the buck converter is not in high-Z (tri-state, HIGH_Z low), the signal CLK_LIMT is set to 0 by flip-flops 15 and 16. At this point, due to the AND gate 8, the current in the coil is forced to decrease until it reaches the low pass value Izero_ref. The moment it reaches Izero_ref, the HIGH_Z signal is switched high, the buck converter is set to high-Z, and since flip-flop 16 is reset and the CLK_LIMIT signal is again 1, the AND gate 8 is no longer gated and the buck converter can restore normal operation.If the short circuit is not removed, the short circuit self-protection loop is repeated.

[0045] The minToff time of block 14 defines the maximum switching frequency and therefore prevents the buck converter from going to a duty cycle of 100%.

[0046] Fig. 10a shows waveforms of the coil current I L for a buck converter in CCM with short-circuit protection and VOUT shorted to ground and Fig. Figure 10b shows the waveforms of Fig. 10a zoomed in. Fig. 10b shows the programmed current limit 100 and the minimum ton period 101. IMPLEMENTATIONS OF SHORT-CIRCUIT SELF-PROTECTION IN PWM

[0047] In Fig. 14 and Fig. 15 shows two implementations for short-circuit self-protection in PWM.

[0048] In particular, Fig. 14 the implementation for short-circuit protection only for VOUT > VREF. In Fig. 15, the implementation is complete to provide short circuit protection for any value of short circuit at VOUT. Implementations of short-circuit self-protection in PWM for VSHORT <= VREF

[0049] Fig. Figure 14 shows a short-circuit protection circuit implementation in PWM for VSHORT <= VREF. Compared to PWM without protection in Fig. 5 the following elements were Fig. 14 added: - ZCCC (Current Coil Low Crossover Detector) 12 (switched high when the current in the coil reaches a defined value Izero_ref, it is latched once triggered and is reset to low by the output of inverter 13 HIGH_Z = 0 if reset = 0); - Inverter gate 13; - AND gate 14; - OCC (overcurrent comparator) 15; - edge-triggered D-type flip-flop with positive logic reset 16; - edge-triggered D-type flip-flop with negative logic reset 17; - AND gate 18; and - OR gate with one input active low 19;

[0050] In case of a short circuit applied to VOUT forcing VOUT < VREF when the current exceeds the programmed current limit (function of IREF), the output of the OCC 15 forces the net CLK LIMIT low.

[0051] Consequently, the CLK signal is gated 18, and the low side of the output stage is activated (reset is forced on flip-flop 10 by OR gate 19). At the same time, ZCCC 12 is activated. As soon as the current in the coil reaches zero (or Izero_ref), ZCCC 12 triggers, the HIGH_Z signal is high, and the output stage is forced into the tri-state condition. Since HIGH_Z is high, the output of flip-flop 16 is high, and on the rising edge of the next CLK, the CLK_LIMIT signal is forced high, flip-flop 10 is set, and the output is no longer in the tri-state condition because the output of AND gate 14 is forced low.

[0052] The normal PMW loop can now take over, or if the short circuit is still present, it will be detected again and the loop described above will be repeated.

[0053] Fig. Figure 13 shows waveforms of the coil current, Vout, the CLK pulses, the HIGH_Z signal and the CLK_LIMIT signal in the case of a ground-shorted output VOUT = 0 in a CCM-PWM operation. Implementation of a complete short-circuit self-protection in PWM (any VSHORT)

[0054] Fig. Figure 15 shows a short-circuit protection circuit implementation in PWM for any VSHORT. Compared to PWM without protection in Fig. 14 the following elements were Fig. 15 added: - (20) AND gate 20; - (21) OR gate with one input active low 21; - (22) OCC (overcurrent comparator) 22; - (23) edge-triggered flip-flop D-type with positive logic reset 23; and - (24) edge-triggered D-type flip-flop with negative logic reset 24.

[0055] The Fig. 14 shown inverter gate 13 has now been converted into a NAND gate 130 in Fig. 15 changed.

[0056] The case of a short circuit applied to VOUT forcing VOUT < VREF has already been outlined above.

[0057] In case of short circuit VOUT > VREF, when the current exceeds the programmed negative current limit (function of IREF_N), the output of the OCC 22 forces the net RST_LIMIT to low.

[0058] Consequently, the RST signal is gated 20, and the low side of the output stage is activated (reset is forced on flip-flop 10 by OR gate 21). While the low output side is activated, the high side is deactivated.

[0059] At the same time, the ZCCC 12 is activated. As soon as the current in the coil reaches Izero_ref, the ZCCC 12 triggers, the HIGH_Z signal goes high, and the output stage is forced into the tri-state state. Because HIGH_Z is high, the output of flip-flop 22 is high. On the rising edge of the next RST, the RST_LIMIT signal is forced high, flip-flop 10 is reset, and the output is no longer in the tri-state state because the output of AND gate 14 is forced low.

[0060] The normal PWM loop can now take over, or, if the short circuit is still present, it is detected again and the loop described above is repeated. In this case, the ZCCC 12 must be able to detect the coil current continuity in both the high-side switch and the low-side switch.

[0061] It should be noted that the short-circuit self-protection implementation disclosed in the document is also an intrinsic soft start implementation. All implementations disclosed above also operate as intrinsic start circuitry. Fig. Figure 16 shows a PWM start of a buck converter with a large capacitance at the output.

[0062] Furthermore, it should be noted that a short circuit to ground in a buck converter is similar to a short circuit at the output of a boost converter to a supply voltage of a boost converter. Therefore, the methods disclosed above for buck converters can also be applied to boost converters.

[0063] Fig.Figure 17 shows a flowchart of a method for self-protecting a buck converter against a short circuit at the buck converter output and for an intrinsic soft start that prevents excessive inrush currents. A first step 170 represents the provision of a buck converter with an inductor and an output stage with a high-side switch and a low-side switch. The next step 171 represents checking whether a short circuit or overload condition exists at the buck converter output by appropriate circuitry, and if so, going to step 172; otherwise, repeating step 171.Step 172 describes limiting a current through the coil at its peak value, and once this limit is triggered, inverting the current as soon as possible until it is low enough in absolute value not to exceed this limit during a next forced on-time period, where the on-time applies to either the high-side or the low-side switch, and the final step 173 represents ensuring that the output stage remains in the tri-state condition once the coil current reaches zero until an internal controller instructs the current to flow in a same direction as the current limit that was previously triggered, restoring normal operation of the buck converter and returning to step 171.

Claims

[1] Buck converter capable of self-protecting the buck converter against a short-circuit or overload at the output of the buck converter by means of a self-protection loop, managing recovery from a short-circuit or overload condition of the buck converter, and providing an intrinsic soft start preventing excessive inrush currents, comprising: an output stage having a high-side switch and a low-side switch, both connected in series, the output stage being configured to be connected to an inductor having a first terminal at a node between the high-side switch and the low-side switch; a minTon unit configured to define a minimum on-time of the high switch; a minToff time unit configured to limit a maximum switching frequency of the buck converter; a circuit arrangement configured to detect a short circuit or an overload condition of the buck converter, wherein the overload condition comprises reaching a current limit of a current through the coil; a current coil low-crossing detector configured to detect when the current through the coil reaches a defined low crossover value, which may be zero, and configured to output a corresponding signal; and a control logic configured to perform a short-circuit self-protection loop by activating and managing recovery from the short-circuit or overload condition of the buck converter, wherein the circuitry configured to detect a short circuit or overload condition of the buck converter comprises a high-side switch current sensing unit and a first comparator configured to compare the result of the high-side current sensing with a reference current. [2] The buck converter of claim 1, wherein the buck converter is operated in pulse frequency modulation (PFM) with continuous line modulation (CCM), wherein the control logic is configured to perform a short-circuit self-protection loop, and wherein, when the circuitry configured to detect a short-circuit or overload condition of the buck converter signals a short-circuit, a second comparator configured to compare the result of the high-side current detection with a reference current is triggered and then initiates a CLK_LIMIT signal being set low while putting the buck converter into a low-impedance mode and, at the same time, forcing the current through the coil to decrease until it reaches the low pass-through value, and at the moment the coil current reaches the low pass-through value,the buck converter is put back into high impedance mode, the CLK_LIMIT signal is set high and the buck converter can restore normal operation, and if the short circuit is not removed, the short circuit self-protection loop is repeated. [3] The buck converter of claim 2, wherein the second comparator is configured to compare the result of the high side current detection with the reference current triggered by the minTon unit. [4] The buck converter of claim 3, wherein a flip-flop initiated by the second comparator sets the CLK_LIMIT signal low when a short circuit has been detected and the buck converter is in low impedance mode, and the flip-flop sets the CLK_LIMIT signal, initiated by the second comparator, high the moment the inductor current reaches the low pass-through value and the buck converter is in high impedance mode. [5] The buck converter according to claim 1, wherein the buck converter is set to a low impedance mode in the event of a short circuit by a current sensing device flowing through the low-side switch and a comparator configured to compare the result of the low-side current sensing with a reference current representing the low pass-through current value, the output of the comparator being connected to the output stage and setting the impedance mode of the buck converter, the comparator setting the impedance mode to high when the sensed low-side current is equal to the low pass-through current value. [6] A buck converter according to claim 5, wherein the reference current representing the low pass current value has a value of zero or close to zero. [7] A buck converter according to claim 1, wherein the buck converter is configured to operate in pulse frequency modulation (PFM) with continuous line modulation (CCM), wherein the control logic is configured to perform a short-circuit self-protection loop, and wherein, when the circuitry configured to detect a short-circuit or an overload condition of the buck converter signals a short-circuit, two flip-flops are triggered after a defined minimum high switch off time and then a CLK_LIMIT signal is set low while the buck converter is set to a low-impedance mode, and at the same time the current through the coil is forced to decrease until it reaches the low-pass value, and at the moment the current reaches the low-pass value, the buck converter is set back to the high-impedance mode,the CLK_LIMIT signal is set high and the buck converter can restore normal operation, and if the short circuit is not removed, the short-circuit self-protection loop is repeated. [8] The buck converter of claim 7, wherein the circuitry configured to trigger a signal in the event of a short circuit or an overload condition comprises a first flip-flop and a second flip-flop, the first flip-flop receiving a signal indicative of a short circuit condition from the circuitry configured to detect a short circuit or an overload condition of the buck converter and triggering the second flip-flop to set the CLK_LIMIT signal low when a short circuit has been detected and the buck converter is in the low impedance mode, and the second flip-flop setting the CLK_LIMIT signal high the moment the inductor current reaches the low pass-through value and the buck converter is in the high impedance mode. [9] The buck converter according to claim 7, wherein the buck converter is set to a low impedance mode in the event of a short circuit by a current sensing device that detects the current flowing through the low-side switch and a comparator configured to compare the result of the low-side current detection with a reference current representing the low-side pass-through value, the output of the comparator being connected to the output stage and setting the impedance mode of the buck converter, the comparator setting the impedance mode to high when the detected low-side current is equal to the low-side pass-through value. [10] The buck converter of claim 1, wherein the buck converter is configured to operate in pulse width modulation (PWM), wherein the control logic is configured to perform a short-circuit self-protection loop, and wherein, when the circuitry configured to detect a short-circuit or overload condition of the buck converter signals a short-circuit, a signal CLK_LIMIT is set low, a clock signal CLK is gated by a logical AND gate, the low side of the output stage is activated and, at the same time, the current through the coil is forced to decrease until it reaches the low pass-through value, and the moment the current reaches the low pass-through value, the buck converter is put back into the high-impedance mode,the output stage is forced into triple-state mode and on a rising edge of a next clock pulse CLK, the CLK_LIMIT signal is set high, the output stage is no longer in triple-state mode and the buck converter can restore normal operation, and if the short circuit is not removed, the short-circuit self-protection loop is repeated. [11] A method for self-protecting a buck converter against a short circuit at the output of the buck converter and for an intrinsic soft start preventing excessive inrush currents, comprising the steps of: (1) Providing a buck converter having an inductor and an output stage having a high side switch and a low side switch; (2) Check whether a short circuit or overload condition exists at the output of the buck converter by detecting an overcurrent of the high side switch, and if so, go to step (3), otherwise repeat step (2); and (3) Ensure that the output stage remains in the triple state once the coil current reaches zero until the current is directed to flow in a same direction of the current that was previously triggered, and restore the normal operation of the buck converter in the previous modulation mode and return to step (2). [12] The method of claim 11, wherein the method is applicable to PFM and PWM modulation. [13] Method according to claim 11, wherein the method is also applicable to boost converters against short circuits between a boosted voltage and a supply voltage.

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