ELECTRONICS MODULE AND METHOD FOR MANUFACTURING AN ELECTRONICS MODULE

Abstract

Electronic module (200), comprising: a carrier (240), a layer of solder (230) arranged on the support (240), a semiconductor substrate (110) arranged on the carrier (240), and a metal stack (120') arranged between the support (240) and the semiconductor substrate (110), wherein the metal stack (120') has a first layer (126) which has NiSi, wherein intermetallic phases are formed between the first layer (126) and the solder layer (230), wherein the metal stack (120') completely covers a first surface (110A) of the semiconductor substrate (110), and wherein the metal stack (120') contains N impurities in the form of NiN and / or SiN.

Description

TECHNICAL AREA

[0001] The invention relates to an electronic module and a method for manufacturing such an electronic module. STATE OF THE ART

[0002] Manufacturers of electronic devices are constantly striving to increase the performance of their products while simultaneously reducing manufacturing costs. One cost-intensive area in the manufacture of electronic devices or electronic modules is the creation of metal stacks arranged on the surface of a semiconductor substrate. Backside metallization (BSM) can be an example of such a metal stack. Such metal stacks may include a first layer that reacts when the semiconductor substrate is soldered to a substrate with a solder layer. Improvements to such metal stacks, for example, improvements in the first layer, as well as improved soldering techniques, can help to reduce manufacturing costs, improve the reliability of solder joints, and reduce wafer and chip bending. For these and other reasons, the present invention is required.US Patent 2006 / 0202352A1 discloses an electronic module comprising a carrier, a solder ball mounted on the carrier, and a semiconductor substrate mounted on the carrier. An underbump metallization, comprising a NiSi layer, is arranged between the solder ball and the semiconductor substrate. Intermetallic phases can form between the NiSi layer and the solder ball. Further electronic modules are disclosed in US Patent 2008 / 0203571A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The accompanying drawings are provided to further enhance understanding of embodiments and are integrated into, and form part of, this description. The drawings illustrate embodiments and, together with the description, serve to explain the principles of these embodiments. Other embodiments and many of the intended advantages of embodiments will become readily apparent when they are better understood by reference to the detailed description that follows. The elements in the drawings are not necessarily to scale relative to one another. Identical reference numerals denote corresponding similar parts. Fig. Figure 1 schematically shows a cross-sectional view of an example of an electronic device. Fig. Figure 2 schematically shows a cross-sectional view of an example of an electronic module. Fig. Figure 3 shows a flowchart of a process for manufacturing an electronic device. Fig. Figure 4 shows a flowchart of a process for manufacturing an electronic module. DETAILED DESCRIPTION

[0004] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. However, it may be apparent to those skilled in the art that one or more aspects of the embodiments can be implemented with a lesser degree of these specific details. In other cases, known structures and elements are shown schematically to facilitate the description of one or more aspects of the embodiments. In this respect, directional terminology such as "top," "bottom," "left," "right," "upper," "lower," etc., is used with reference to the orientation of the figure(s) being described.Since components of embodiments can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way restrictive. It is understood that other embodiments can be used and structural or logical modifications can be made without deviating from the scope of protection of the present invention.

[0005] While a particular feature or aspect of an embodiment may be disclosed with reference to only one of several implementations, such a feature or aspect may additionally be combined with one or more other features or aspects of the other implementations if this is desirable and advantageous for any given or specific application, unless specifically stated otherwise or technically restricted. The terms "coupled" and "linked" may be used together with their derivatives.It is understood that these expressions can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact or not in direct contact with each other; intervening elements or layers may be provided between the “bonded”, “attached” or “connected” elements.

[0006] The semiconductor substrates or semiconductor chips described below can be of various types and can be manufactured using different technologies. The embodiments of an electronic device and an electronic module, and of a method for manufacturing an electronic device and an electronic module, can utilize various types of semiconductor chips or circuits contained within the semiconductor chips, including AC-DC or DC-DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (junction-gate field-effect transistors), power bipolar transistors, integrated logic circuits, analog integrated circuits, integrated mixed-signal circuits, sensor circuits, MEMS (microelectromechanical systems), integrated power circuits, chips with integrated passive elements, etc.The embodiments can also utilize semiconductor chips comprising MOS transistor structures or vertical transistor structures, such as IGBT (insulated-gate bipolar transistor) structures, diodes, or, more generally, transistor structures, in which at least one electrical contact point is located on a first main face of the semiconductor chip and at least one other electrical contact point is located on a second main face of the semiconductor chip opposite the first main face. Furthermore, the embodiments of insulating materials can be used, for example, to provide insulating layers in various types of packages and insulation for electrical circuits and components, and / or to provide insulating layers in various types of semiconductor chips or circuits contained within semiconductor chips, including the semiconductor chips and circuits mentioned above.

[0007] The semiconductor substrates or semiconductor chips considered here can be thin. These substrates or chips can be made from specific semiconductor materials, such as Si, SiC, SiGe, GaAs, GaN, or from any other semiconductor material, and can furthermore contain one or more inorganic or organic materials that are not semiconductors, such as insulators, plastics, or metals.

[0008] The semiconductor substrates or chips may have contact points (or electrodes) that allow electrical contact with the integrated circuits embedded within them. The electrodes may be located on one main face of the semiconductor substrate or chip, or on both main faces. They may comprise one or more electrode metal layers deposited onto the semiconductor material. The electrode metal layers can be manufactured with any desired geometric shape and material composition. For example, they may comprise or be made from a material selected from the group consisting of Cu, Ni, NiSn, Au, Ag, Pt, and Pd, an alloy of one or more of these metals, an electrically conductive organic material, or an electrically conductive semiconductor material.

[0009] The semiconductor substrates or chips can be bonded to a substrate. The substrate can be a (permanent) device carrier used for encapsulation. The substrate can comprise or consist of any type of material, such as ceramic or metal, copper or copper alloy, or iron-nickel alloy. The substrate can be a power electronics substrate, a conductor frame, a DCB (Direct Copper Bond), DAB (Direct Aluminum Bond), or AMB (Active Metal Braze) type substrate, an IMS (Insulated Metal Substrate), or a PCB (Printed Circuit Board). The substrate can be mechanically and electrically connected to a contact element of the semiconductor substrates or chips. The semiconductor substrates or chips can be connected to the substrate by soldering, for example, by reflow soldering and / or vacuum soldering and / or diffusion soldering.When diffusion soldering is used as the joining technology between semiconductor substrates or chips and the support, solder materials can be employed that, due to interfacial diffusion processes after soldering, result in intermetallic phases at the interface between the semiconductor and the support. A soft solder material, or specifically a solder material capable of forming diffusion solder bonds, can be used. For example, a solder material comprising one or more metals selected from the group consisting of Sn, SnAg, SnAu, SnCu, In, InAg, InCu, and InAu. The solder material can contain Pb, or a Pb-free solder material can be used.

[0010] The electronic modules can include an encapsulation material that covers the semiconductor chip(s). The encapsulation material can be electrically insulating. It can be any suitable plastic or polymer material, such as a silicone gel, a thermoset, thermoplastic, or heat-curing material, or a laminate (prepreg), and may contain fillers. Various techniques can be used to encapsulate the semiconductor chip(s) with the encapsulation material, such as compression molding, injection molding, powder casting, liquid casting, or lamination. Heat and / or pressure can be used to apply the encapsulation material.

[0011] In several embodiments, layers or stacks of layers are applied to one another, or materials are applied or deposited onto layers. It is understood that terms such as "applied" or "deposited" are intended to cover virtually all types and techniques of layer application. In particular, they are intended to cover techniques in which layers are applied all at once as a whole, such as lamination techniques, as well as techniques in which layers are deposited sequentially, such as sputtering, plating, casting, CVD, etc.

[0012] The following are examples of an electronic device comprising a metal stack arranged on a semiconductor substrate or a semiconductor chip. The metal stack can be arranged on the back side of the semiconductor substrate. The metal stack can be arranged on a chip pad of the semiconductor substrate and can be configured to provide an electrical connection between the chip pad and a substrate to which the semiconductor substrate is attached. The metal stack can comprise a single metal layer or multiple metal layers, for example, two layers, three layers, four layers, or more than four layers. The metal stack can be of any suitable size or shape. The metal stack can completely cover a surface of the semiconductor substrate or can only partially cover the surface.

[0013] The metal stack can include a first layer designed to act as a reactant for solder deposition during soldering. This first layer can be a nickel-silicon (NiSi) compound. NiSi can exhibit superior properties as a first layer compared to other materials such as pure nickel or nickel-vanadium (NiV) alloys. For example, NiSi reacts more slowly with tin (Sn) during soldering compared to Ni or NiV. In particular, approximately twice as much NiV as NiSi can be consumed when the same soldering process is performed. Therefore, a thinner layer or layers of NiSi can be used in a metal stack compared to NiV.This can reduce the manufacturing time and cost of the metal stack and can also minimize wafer bending or chip bending caused by the difference in the coefficients of thermal expansion (CTE) of the semiconductor substrate and the metal stack.

[0014] The first layer can be produced using various deposition techniques known in engineering. For example, the first layer can be produced using magnetron sputtering. Unlike pure Ni, NiSi is not ferromagnetic and therefore does not interfere with the magnetron of a deposition chamber.

[0015] Magnetron sputtering can be performed in the presence of a process gas. The process gas can comprise a noble gas, for example, Ar, Xe, Kr, or Ne. According to one aspect of the invention, the process gas comprises N (nitrogen). The process gas can, for example, contain N in an amount of approximately 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or even more than 80%. The remainder of the process gas can consist of Ar. The presence of N in the process gas during magnetron sputtering causes the integration of N impurities into the metal stack. N impurities are integrated into the first layer. N is integrated into the first layer along with NiSi, so that NiN and / or SiN are formed in the first layer. N can have a positive effect on the performance of the metal stack, for example, the quality of a brazed joint between the metal stack and a substrate.

[0016] Fig. Figure 1 shows an example of an electronic device 100. The electronic device 100 comprises a semiconductor substrate 110 and a metal stack 120 arranged on a first surface 110A of the semiconductor substrate. The semiconductor substrate 110 can comprise a semiconductor wafer or a single semiconductor chip. The first surface 110A can be a back side of the semiconductor substrate 110. The semiconductor substrate can include a chip pad (not shown) arranged on the first surface 110A, and the metal stack 120 can be arranged on the chip pad and electrically connected to it.

[0017] The metal stack 120 can completely cover the first surface 110A or can only partially cover the first surface 110A, as shown in Fig. Figure 1 shows that the metal stack 120 can have any suitable shape and any suitable lateral or vertical dimension with respect to the first surface 110A. The metal stack 120 can be structured or unstructured. The metal stack 120 can include N impurities as described above.

[0018] The metal stack 120 can comprise a first layer 126, wherein the first layer 126 comprises or consists of NiSi. The first layer 126 can have any suitable thickness, depending on the specific requirements for the first layer 126, the thickness being measured along a direction perpendicular to the first surface 110A. The first layer 126 can have a thickness in the range of 50 nm to 2000 nm, in particular 100 nm to 1000 nm, more precisely 200 nm to 600 nm, and even more precisely 400 nm to 500 nm. The thickness of the first layer 126 can also be approximately 300 nm or exactly 300 nm.

[0019] The first layer 126 can comprise an amount of Si in the range of 2 wt.% to 50 wt.%, in particular 2 wt.% to 20 wt.%, more precisely 3 wt.% to 10 wt.%, more precisely 4 wt.% to 5 wt.% and even more precisely about 4.5 wt.% or exactly 4.5 wt.% of the total amount of material of the first layer 126.

[0020] The metal stack 120 can comprise additional layers besides the first layer 126. For example, the metal stack can include a third layer 128 arranged on top of the first layer 126. The third layer 128 can be designed to protect the first layer 126 from corrosion. The third layer 128 can comprise or consist of any suitable material or material composition. For example, the third layer 128 can comprise or consist of one or more of Ag, Pt, Pd, and Au. The third layer 128 can have any suitable thickness and can, for example, have a thickness in the range of 50 nm to 2000 nm, in particular 100 nm to 1000 nm, more precisely 150 nm to 500 nm, and even more precisely 200 nm to 300 nm. The thickness of the third layer 128 can also be approximately 200 nm or exactly 200 nm.

[0021] The metal stack 120 can comprise a second layer 124, the second layer 124 being arranged between the first layer 126 and the semiconductor substrate 110. The second layer 124 can act as a barrier layer and prevent the diffusion of impurities into the semiconductor substrate 110. The second layer 124 can have any suitable thickness, for example, a thickness of approximately or exactly 200 nm. The second layer 124 can comprise any suitable material and can, for example, include or consist of one or more of Ti, WTi, Ta, or an alloy comprising at least one of these materials.

[0022] The metal stack 120 can comprise a fourth layer 122 arranged between the first layer 126 and the semiconductor substrate 110. If the metal stack 120 comprises a second layer 124, the fourth layer 122 is arranged between the second layer 124 and the semiconductor substrate 110. The fourth layer 122 can have any suitable thickness, for example, a thickness in the range of 50 nm to 2000 nm, in particular 100 nm to 1000 nm, more precisely 200 nm to 600 nm, and even more precisely, in particular, 300 nm to 500 nm. The thickness of the fourth layer 122 can also be approximately or exactly 400 nm. The fourth layer 122 can comprise any suitable material and can, for example, comprise or consist of Al and / or Ti.

[0023] Fig. Figure 2 shows an example of an electronic module 200. The electronic module 200 comprises an electronic device 100 (which includes a semiconductor substrate 110 and a metal stack 120') and a carrier 240 to which the electronic device 100 is attached. The electronic module 200 may further comprise an encapsulation body 250 that encapsulates the semiconductor substrate 110.

[0024] The electronic module 200 further comprises a solder layer 230, which is arranged on the carrier 240 and soldered to the metal stack 120'. The solder layer 230 can, for example, comprise SnAg or Sn.

[0025] The metal stack 120' of the electronic module 200 can be combined with the metal stack 120 of the electronic device 100. Fig. 1. The first layer 126 may be identical, except for changes introduced by soldering the electronic device 100 to the solder layer 230. According to an example of an electronic module 200, the first layer 126 may be thinner after soldering than before soldering. For example, the first layer 126 may be one-quarter thinner, one-half thinner, three-quarters thinner, or there may even be no first layer present in the metal stack 120' after soldering. The first layer 126 may also be almost completely consumed by the soldering process, except for some spots 232 comprising NiSi that remain in the metal stack 120' after soldering. The spots 232 may be located at an interface between the first layer 126 and the solder layer 230. The spots 232 may contain a higher concentration of Si than the first precursor layer 126 because Ni may be "pulled out" during soldering.For example, if the first layer 126 contained 4.5% Si, the spots 232 may contain about four times more Si, or in other words, about 20% Si.

[0026] According to an example of an electronic module 200, the metal stack 120' between the first layer 126 and the solder layer 230 can comprise intermetallic phases formed.

[0027] In the electronic device 200, the metal stack 120' contains N impurities. N can improve the quality of the solder joint formed between the metal stack 120' and the solder layer 230. For example, if the first layer 126 is completely consumed by the soldering process, the electronic module 200 does not exhibit delamination problems, as the metal stack 120' delaminates from the solder layer 230, because N in the metal stack 120' can counteract the delamination. If the metal stack 120' contains the spots 232, the spots 232 can, for example, contain NiN and / or SiN.

[0028] The semiconductor substrate 110 of the electronic module 200 can comprise a first electrode on the first surface 110A and a second electrode on the second surface 110B opposite the first surface 110A. The electronic module 200 can be configured for an electric current to flow vertically from the second electrode to the first electrode and further through the metal stack 120' to the support 240.

[0029] The in Fig. Figure 2 shows electronic module 200, which includes only a semiconductor substrate 110, a metal stack 120, and a support 240. Other examples of electronic module 200 may, of course, include additional components, such as additional semiconductor substrates, additional metal stacks, additional supports, or other suitable additional components. These additional components can be described with reference to the information in Figure 2. Fig. The two components shown can be arranged side by side and / or stacked vertically.

[0030] Fig. Figure 3 shows a method 300 for manufacturing an electronic device such as the electronic device 100 of Fig. 1. Method 300 comprises a first process step 301, wherein the first process step 301 comprises providing a semiconductor substrate such as semiconductor substrate 110. Method 300 further comprises a second process step 302, wherein the second process step 302 comprises arranging a metal stack such as metal stack 120 on the semiconductor substrate.

[0031] The arrangement of the metal stack 120 in the second process step 302 can include sputtering a first layer onto the semiconductor substrate. Sputtering can be performed in the presence of a process gas comprising N as described above.

[0032] The arrangement of the metal stack 120 in the second process step 302 can further include the integration of N impurities into the metal stack 120 as described above.

[0033] Fig. Figure 4 shows a method 400 for manufacturing an electronic module such as the electronic module 200 of Fig. 2. Method 400 comprises a first process step 401, wherein the first process step 401 comprises providing a semiconductor substrate and a support. Method 400 comprises a second process step 402, wherein the second process step 402 comprises arranging a metal stack on the semiconductor substrate. Method 400 comprises a third process step 403, wherein the third process step 403 comprises arranging a solder layer on the support. Method 400 comprises a fourth process step 404, wherein the fourth process step 404 comprises soldering the semiconductor substrate onto the support.

Claims

[1] Electronic module (200), comprising: a carrier (240), a layer of solder (230) arranged on the support (240), a semiconductor substrate (110) arranged on the carrier (240), and a metal stack (120') arranged between the support (240) and the semiconductor substrate (110), wherein the metal stack (120') has a first layer (126) which has NiSi, wherein intermetallic phases are formed between the first layer (126) and the solder layer (230), wherein the metal stack (120') completely covers a first surface (110A) of the semiconductor substrate (110), and wherein the metal stack (120') contains N impurities in the form of NiN and / or SiN. [2] Electronic module (200) according to claim 1, wherein the carrier (240) comprises a power electronics substrate, a conductor frame, a DCB, a DAB, an AMB, an IMS or a PCB. [3] Electronic module (200) according to claim 1 or 2, wherein the carrier (240) comprises or consists of one or more copper, a copper alloy and an iron-nickel alloy. [4] Electronic module (200) according to one of the preceding claims, further comprising an encapsulation body (250) encapsulating the semiconductor substrate (110). [5] Electronic module (200) according to one of the preceding claims, wherein the metal stack (120') comprises a second layer (124) arranged between the semiconductor substrate (110) and the support (240), comprising Ti, WTi or Ta. [6] Electronic module (200) according to one of the preceding claims, wherein the metal stack (120') comprises a fourth layer (122) arranged between the semiconductor substrate (110) and the support (240), comprising Al and / or Ti. [7] Electronic module (200) according to one of the preceding claims, wherein the solder layer (230) comprises Sn or SnAg. [8] Method (400) for manufacturing an electronic module, comprising: Providing (401) a carrier and a semiconductor substrate, Arranging (402) a metal stack on the semiconductor substrate such that the metal stack completely covers a first surface of the semiconductor substrate, wherein the metal stack has a first layer which has NiSi, Arranging (403) a diffusion bond layer between the metal stack and the support, and Diffusion soldering (404) of the semiconductor substrate onto the support, wherein intermetallic phases are formed between the first layer and the diffusion solder layer by the diffusion soldering (404), and wherein the metal stack has N impurities in the form of NiN and / or SiN. [9] Method according to claim 8, wherein the carrier comprises a power electronics substrate, a conductor frame, a DCB, a DAB, an AMB, an IMS or a PCB. [10] Method according to claim 8 or 9, wherein the carrier comprises or consists of one or more of copper, a copper alloy and an iron-nickel alloy. [11] Method according to any one of claims 8 to 10, wherein the diffusion solder layer comprises Sn or SnAg.

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