Level conversion device and method

Abstract

Device comprising: a level converter (140) comprising a first current limiter (141), wherein the level converter (140) is configured to generate a first output signal (VO1) at a first terminal of the first current limiter (141) and to generate a second output signal (VO2) at a second terminal of the first current limiter (141) according to a first input signal (VIN); and a selector (160) configured to selectively send one of the first output signal (VO1) and the second output signal (VO2) according to the first input signal (VIN).

Description

BACKGROUND

[0001] With the rapid development of manufacturing process technology, low-power designs are widely used in many applications. For example, level shifters are commonly used as voltage signal interfaces between various circuits operating at different operating voltages. When operating at a lower operating voltage, such as a sub-threshold voltage, the level shifters fail due to leakage currents.

[0002] US 5 378 932 A discloses a level shift circuit comprising first and second voltage terminals, first and second input terminals, an output terminal, a level converter circuit, and an output circuit. The level converter comprises first, second, and third nodes, first, second, third, and fourth transistors, and a resistive element. The first transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the first node, and a control electrode connected to the first input terminal. The second transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the second node, and a control electrode connected to the second input terminal.The third transistor has a first electrode connected to the second voltage level, a second electrode connected to the first node, and a control electrode connected to the second node. The resistive element is connected between the second and third nodes. The fourth transistor has a first electrode connected to the second voltage level, a second electrode connected to the third node, and a control electrode connected to the first node. The output circuit includes fifth and sixth transistors. The fifth transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the output terminal, and a control electrode connected to the second node.The sixth transistor has a first electrode connected to the second voltage terminal, a second electrode connected to the output terminal, and a control electrode connected to the third node.

[0003] JP 2011-172065 A addresses the problem of how to provide a level conversion circuit that constantly outputs an output signal with a suitable amplitude despite the range in which the voltage levels of the first and second input signals change.As a solution, the level conversion circuit includes a first differential amplifier section having N-type transistors as an input differential pair and receiving first and second input signals II input from the outside at the gates of the N-type transistors, a second differential amplifier section having P-type transistors as an input differential pair and receiving the first and second input signals II at the gates of the P-type transistors, an input determiner that determines whether each voltage level of the first and second input signals is higher than a reference potential by comparing the voltage levels of the first and second input signals with the predetermined reference potential, and an output selector that selects an output of the first or second differential amplifier in response to the result determined by the input determiner.

[0004] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a schematic diagram of an apparatus according to various embodiments of the present disclosure; Fig. 2 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. 3 is a flow chart of operations of the device in Fig. 2, when the input signal VIN has a logic value of 1, according to various embodiments of the present disclosure; Fig. 4 is a flow chart of operations of the device in Fig. 2, when the input signal VIN has a logic value of 0, according to various embodiments of the present disclosure; Fig. 5 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. 6 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. Figure 7 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. Figure 8 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. 9 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure; Fig. 10 is a circuit diagram of the device in Fig. 1 according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The following disclosure contemplates many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the sake of simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0007] The terms used in this specification generally have their customary meanings in the field and in the specific context in which each term is used. The use of examples in this specification, including examples of any terms discussed herein, is for illustrative purposes only and in no way limits the scope and meaning of the disclosure or any discussed term. Likewise, the present disclosure is not limited to the various embodiments recited in this specification.

[0008] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. The terms are used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" encompasses any combination of one or more of the related listed items.

[0009] Fig. Figure 1 is a schematic diagram of a device 100 according to various embodiments of the present disclosure. In some embodiments, the device 100 is implemented in or as a level shifter.

[0010] As illustrated in Fig. 1, the device 100 includes an input signal generator 120, a level shifter 140, a selector 160, and an output stage 180. For illustration, the input signal generator 120 includes an inverter 120A. The input signal generator 120 is configured to input an input signal VIN and further output an input signal VINB through the inverter 120A in response to the input signal VIN. In other words, in some embodiments, the input signal VIN is an inverse of the input signal VINB. In some embodiments, the input signal VINB is a phase shift of the input signal VIN. In some embodiments, the input signal VINB is generated by a logical or arithmetic operation of the input signal VIN.

[0011] Level converter 140 is configured to adjust the voltage level of the input signal VIN to generate an output signal VO1 and an output signal VO2. For illustration, the maximum voltage level of the input signal VIN is set to a voltage VDDI. Level converter 140 can adjust the maximum voltage of the input signal VIN from the voltage VDDI to a voltage VDDO, where the voltage VDDO differs from the voltage VDDI.

[0012] Selector 160 is configured to send one of the output signal VO1 and the output signal VO2 to output stage 180 according to input signals VIN and VINB. Output stage 180 is configured to adjust the voltage swing of one of the output signal VO1 and the output signal VO2 sent from selector 160 to generate an output signal VO4. In some embodiments, output stage 180 includes one or more buffers that pull the voltage swing of one of the output signals VO1 and VO2 to a full range to generate output signal VO4. The drive capability of device 100 is effectively increased by output stage 180. To illustrate, the full range of the voltage swing is configured from a voltage VSS, which is, for example, a ground voltage, to a voltage VDDO, which is, for example, an operating voltage.

[0013] In some embodiments, input signal generator 120 operates at voltage VDDI, while level shifter 140, selector 160, and output stage 180 operate at voltage VDDO. In some embodiments, voltage VDDI is less than or equal to voltage VDDO. For example, voltage VDDI ranges from about 0.2 volts to about 1.2 volts, and voltage VDDO ranges from about 1.2 volts. Alternatively, in some other embodiments, voltage VDDI is greater than or equal to voltage VDDO. For example, voltage VDDI is about 1.2 volts, and voltage VDDO ranges from about 0.2 volts to about 1.2 volts. In other words, in some embodiments, level shifter 140 can pull up the voltage level of input signal VIN to a higher voltage. Alternatively, in some embodiments, level shifter 140 can pull down the voltage level of input signal VIN to a lower voltage.

[0014] The arrangements of the VDDI and VDDO voltages are illustrative. Various arrangements of the VDDI and VDDO voltages are within the contemplated scope of the present disclosure.

[0015] It will now Fig. 2 is referred to. Fig. 2 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0016] In some embodiments, level shifter 140 includes switches M1-M4 and current limiters 141 and 142. Level shifter 140 generates output signal VO1 at a first terminal of current limiter 141 and generates output signal VO2 at a second terminal of current limiter 141.

[0017] To illustrate, a first terminal of switch M1 is configured to receive the voltage VDDO, a second terminal of switch M1 is coupled to the first terminal of current limiter 141, and a control terminal of switch M1 is coupled to a second terminal of current limiter 142 and receives a control signal VC. A first terminal of switch M2 is coupled to the second terminal of current limiter 141, a second terminal of switch M2 is configured to receive the voltage VSS, and a control terminal of switch M2 is configured to receive the input signal VIN. A first terminal of switch M3 is configured to receive the voltage VDDO, a second terminal of switch M3 is coupled to a first terminal of current limiter 142, and a control terminal of switch M3 is coupled to the second terminal of current limiter 141 to receive the output signal VO2.A first terminal of switch M4 is coupled to the second terminal of current limiter 142, a second terminal of switch M4 is configured to receive voltage VSS, and a control terminal of switch M4 is configured to receive input signal VINB. In some embodiments, voltage VSS is lower than voltage VDDO.

[0018] In some embodiments, switches M1 and M3 operate as pull-up units of level shifter 140. To illustrate, when switch M1 is turned on by control signal VC, the voltage level of the first terminal of current limiter 141 is pulled up by switch M1 to voltage VDDO. Therefore, the first terminal of current limiter 141 generates output signal VO1 corresponding to the pulled-up voltage level. When switch M3 is turned on by output signal VO2, the voltage level of the first terminal of current limiter 142 is pulled up by switch M3 to voltage VDDO.

[0019] Switches M2 and M4, like switches M1 and M3, function as pull-down units of level converter 140. To illustrate, when switch M2 is turned on by the input signal VIN, the voltage level of the second terminal of current limiter 141 is pulled down by switch M2 to the voltage VSS. When switch M4 is turned on by the input signal VINB, the voltage level of the second terminal of current limiter 142 is pulled down to the voltage VSS. Therefore, the second terminal of current limiter 142 generates the control signal VCC corresponding to the pulled-down voltage level.

[0020] With the arrangements for the switches M1-M4, a self-control mechanism is implemented in the level converter 140. Detailed operations are described below with reference to Fig. 3 and Fig. 4 described.

[0021] In some methods, when the input signal VIN, without using current limiters 141 and 142, is a lower-limit voltage with, for example, a voltage level of approximately 0.2 volts, switch M1 and switch M2 are turned on simultaneously. Under such a condition, if a current IM1 flowing from switch M1 to switch M2 is greater than a current IM2 flowing through switch M2, the pull-down operation of switch M2 fails. Effectively, the operations of level shifter 140 fail. Due to the foregoing, the device in these methods cannot be operated with a lower-limit voltage.

[0022] Compared to the above-mentioned methods, in some embodiments, the current limiter 141 is used to reduce the current IM1 flowing from switch M1 to switch M2, and the current limiter 142 is used to reduce a current IM3 flowing from switch M3 to switch M4. In other words, the current limiter 141 is configured to generate a voltage drop between switches M1 and M2, wherein the voltage drop is sufficient to reduce the current IM1. The current limiter 142 is configured to generate a voltage drop between switches M3 and M4, wherein the voltage drop is sufficient to reduce the current IM3. With such arrangements, the switch M2 can pull the voltage level of the second terminal of the current limiter 141 down to the voltage VSS when the input signal VIN is a low voltage, for example, a lower-limit voltage.

[0023] In some embodiments, the current limiter 141 and the current limiter 142 are resistive devices. In various embodiments, the current limiter 141 and the current limiter 142 are diodes. In further embodiments, the diodes for implementing the current limiter 141 and the current limiter 142 are formed with different types of transistors. To illustrate how in Fig. As shown in Figure 2, the current limiter 141 includes a diode-connected metal-oxide-silicon field-effect transistor (MOSFET) M5, and the current limiter 142 includes a diode-connected MOSFET M6. The diode-connected MOSFET M5 effectively provides the voltage drop, i.e., the threshold voltage of the diode-connected MOSFET M5, between the switches M1 and M2. The diode-connected MOSFET M6 also provides a voltage drop, i.e., the threshold voltage of the diode-connected MOSFET M6, between the switches M3 and M4. As a result, the current IM1 flowing to the switch M2 and the current IM3 flowing to the switch M4 are reduced.

[0024] The configurations of current limiters 141 and 142 are illustrative. Various configurations of current limiters 141 and 142 are within the contemplated scope of the present disclosure.

[0025] With continued reference to Fig. 2, in some embodiments, selector 160 includes switches M7 and M8. Switch M7 is coupled between the first terminal of current limiter 141 and output stage 180. Switch M7 is configured to be turned on according to input signal VIN to send output signal VO1 from the first terminal of current limiter 141 to output stage 180. Switch M8 is coupled between the second terminal of current limiter 141 and output stage 180. Switch M8 is configured to be turned on according to input signal VIN to send output signal VO2 from the second terminal of current limiter 141 to output stage 180.

[0026] It will now be available on both Fig. 2 as well as Fig. 3 referred to. Fig. 3 is a flowchart 300 of operations of the device 100 in Fig. 2 according to various embodiments of the present disclosure when the input signal VIN has a logic value of 1.

[0027] The input signal VIN can have a logical value of 1 or 0 in various embodiments. As in Fig. 3, operations of the device 100 are shown in Fig. 2 with respect to the input signal VIN with a logical value of 1.

[0028] In step S310, switch M2 is turned on by the input signal VIN. In step S320, the voltage level of the second terminal of MOSFET M5 is pulled down to the voltage VSS. Therefore, the output signal VO2 is generated, which corresponds to the pulled-down voltage level of the second terminal of MOSFET M5. In step S330, switch M8 is turned on by the input signal VIN to send the output signal VO2 to the output stage 180. In step S340, the output stage 180 outputs the output signal VO4 in response to the output signal VO2.

[0029] In some embodiments, the voltage swing of the input signals VIN and VINB ranges from the voltage VSS to the voltage VDDI, where the voltage VSS corresponds to the logic value 0 and the voltage VDDI corresponds to the logic value 1. To illustrate how in Fig. As shown in Figure 2, when the input signal VIN has a logic value of 1, the input signal VINB has a logic value of 0. The switch M2 is thus turned on by the input signal VIN. Therefore, the voltage level of the second terminal of the MOSFET M5 is pulled down to the voltage VSS to generate the output signal VO2 with the level of the voltage VSS. The voltage level of the first terminal of the MOSFET M5 then passes through the diode-connected MOSFET M5 to the voltage VSS+VTH5, where VTH5 is a threshold voltage of the MOSFET M5. Furthermore, the switch M8 is turned on by the input signal VIN to send the output signal VO2 to the output stage 180. The output stage 180 generates the output signal VO4 with a logic value of 1 in accordance with the output signal VO2.

[0030] As described above, in the operations S310-S340 shown above, the diode-connected MOSFET M5 provides a voltage drop, i.e., the threshold voltage of the MOSFET M5, between the switches M1 and M2. In other words, the diode-connected MOSFET M5 effectively acts as a resistive device between the switches M1 and M2 to provide resistance to reduce the current flowing from the switch M5 to the switch M2, compared to methods that do not use a current limiter. With such arrangements, the current IM1 flowing from the switch M1 to the switch M2 is reduced. As a result, the pull-down operation of the switch M2 can be performed with a lower threshold voltage.

[0031] It will now be available on both Fig. 2 as well as Fig. 4 referred to. Fig. 4 is a flowchart 400 of operations of the device 100 in Fig. 2 according to various embodiments of the present disclosure when the input signal VIN has a logic value 0.

[0032] Alternatively, as in Fig. 4, operations of the device 100 are shown in Fig. 2 when the input signal VIN has the logic value 0. In step S410, switch M2 is turned off by the input signal VIN. In step S420, switch M4 is turned on by the input signal VINB. In step S430, the voltage level of the second terminal of MOSFET M6 is pulled up to the voltage VSS to generate the control signal VC. In step S440, switch M1 is turned on by the control signal VC. In step S450, the voltage level of the first terminal of MOSFET M5 is pulled up to the voltage VDDO. Therefore, the output signal VO1 is generated, which corresponds to the pulled-up voltage level of the second terminal of MOSFET M5. In step S460, switch M7 is turned on by the input signal VIN to send the output signal VO1 to the output stage 180. In operation S470, the output stage 180 outputs the output signal VO4 in response to the output signal VO1.

[0033] To illustrate how Fig. As shown in Figure 2, when the input signal VIN has a logic value of 0, the input signal VINB correspondingly has a logic value of 1. Thus, switch M2 is turned off by the input signal VIN. Switch M4 is turned on by the input signal VINB to send the voltage VSS to the second terminal of MOSFET M6. Therefore, the voltage level of the second terminal of MOSFET M6 is pulled down to the voltage VSS to generate the control signal VC. Switch M1 is turned on by the control signal VC. Therefore, the voltage level of the first terminal of MOSFET M5 is pulled up to the voltage VDDO to generate the output signal VO1, which has the level of the voltage VDDO. The voltage level of the second terminal of MOSFET M5 then goes to the voltage VDDO-VTH5. Switch M7 is also turned on by the input signal VIN to send the output signal VO1 to the output stage 180.As a result, the output stage 180 generates the output signal VO4 with the logic value 0 corresponding to the output signal VO2.

[0034] It should be noted that in the above-described operations S410-S470, the diode-connected MOSFET M6 provides a voltage drop, i.e., a threshold voltage of the MOSFET M6, between the switches M3 and M4. In other words, the diode-connected MOSFET M6 effectively acts as a resistive device between the switches M3 and M4 to provide resistance to reduce the current flowing from the switch M6 to the switch M2. With such arrangements, the current IM3 flowing from the switch M3 to the switch M4 is reduced. As a result, the pull-down operation of the switch M4 can be performed with a lower threshold voltage.

[0035] In some embodiments, the steps shown in flowchart 300 in Fig. 3 shown operations and the flow chart 400 in Fig. 4 are implemented as level conversion procedures.

[0036] It will now Fig. 5 is referred to. Fig. 5 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0037] Compared with the device 100 in Fig. 2 are equal elements in Fig. 5 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 5, the input signal generator 120 of the device 100 further includes a NAND gate 120B. An output terminal of the NAND gate 120B is coupled to an input terminal of the inverter 120A. In some embodiments, the NAND gate 120B operates as an enable unit of the input signal generator 120. To illustrate, the NAND gate 120B is configured to receive an initial input signal IN and an enable signal EN and to output the input signal VINB to the inverter 120A according to the initial input signal IN and the enable signal EN. The inverter 120A is further configured to output the input signal VIN according to the input signal VINB.

[0038] When the initial input signal IN and the enable signal EN both have a logic value of 1, the input signal VINB has a logic value of 0. Therefore, the input signal VIN has a logic value of 1. With such arrangements, the level converter 140 can perform the level shifting for the input signal VIN as discussed above when the enable signal EN has a logic value of 1.

[0039] When the initial input signal IN has a logic value of 1 and the enable signal has a logic value of 0, the device 100 is disabled. Under this condition, the NAND gate 120B outputs the input signal VINB with a logic value of 1. The inverter 120A then outputs the input signal VIN with a logic value of 0. Therefore, the switch M7 is turned on by the input signal VIN to output the output signal VO1 with a logic value of 1 to the output stage 180, as described above. Fig. 4. As a result, the output stage 180 receives the output signal VO1 with the logic value 1 and outputs the output signal VO4 with the logic value 0. In other words, when the device 100 is disabled, the device 100 continues to output the output signal VO4 with the logic value 0 instead of outputting a float voltage.

[0040] In some embodiments, NAND gate 120B and inverter 120A operate at voltage VDDI. In other words, both the maximum voltage level of the input signals VIN and VINB and the maximum voltage level of the enable signal EN are set to voltage VDDI.

[0041] It will now Fig. 6 is referred to. Fig. 6 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0042] Compared with the device 100 in Fig. 2 are equal elements in Fig. 6 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 6, the input signal generator 120 of the device 100 further includes a NOR gate 120C. An output terminal of the NOR gate 120C is coupled to an input terminal of the inverter 120A. In some embodiments, the NOR gate 120C operates as an enable unit of the input signal generator 120. By way of illustration, the NOR gate 120C is configured to receive the initial input signal IN and an enable signal ENB and, accordingly, to output the input signal VINB to the inverter 120A. The inverter 120A is configured to output the input signal VIN according to the input signal VINB. In some embodiments, the NOR gate 120C and the inverter 120A operate at the voltage VDDI.

[0043] Furthermore, compared with the device 100 in Fig. 5, in some embodiments described in Fig. 6, the device 100 is enabled when the enable signal ENB has the logic value 0. When the enable signal ENB has the logic value 1, the NOR gate 120C outputs the input signal VINB with the logic value 0. The inverter 120A thus generates the input signal VIN with the logic value 1. As a result, the output stage 180 outputs the output signal VO4 with the logic value 1. In other words, when the device 100 is disabled, the device 100 continues to output the output signal VO4 with the logic value 1 instead of outputting a maintenance voltage.

[0044] The arrangements of the input signal generator 120 in Fig. 5-6 are illustrative. Various arrangements of the tightness level 120 are within the contemplated scope of the present disclosure.

[0045] It will now Fig. 7 is referred to. Fig. 7 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0046] Compared with the device 100 in Fig. 2 are equal elements in Fig. 7 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 7, the level converter 140 further includes a switch M9. A first terminal of the switch M9 is coupled to the second terminals of the switches M2 and M4, a second terminal of the switch M9 is configured to receive the voltage VSS, and a control terminal of the switch M9 is configured to receive the enable signal EN. The switch M9 is configured to be turned on according to the enable signal EN, thereby enabling the switches M1-M6. In other words, in some embodiments, the switch M9 functions as an enable unit of the level converter 140.

[0047] Furthermore, compared with Fig. 2, in some embodiments, includes Fig. 7, the output stage 180 of the device 100 includes a buffer 182, a control circuit 184, and a buffer 186. An input terminal of the buffer 182 is coupled to the selector 160 for receiving one of the output signal VO1 and the output signal VO2. The buffer 182 then outputs an output signal VO3 according to one of the output signal VO1 and the output signal VO2. The control circuit 184 is coupled between the buffers 182 and 186. The control circuit 184 is configured to output a buffer signal VB according to the output signal VO3 and the enable signal EN. The buffer 186 is configured to output the output signal VO4 according to the buffer signal VB. In some embodiments, the control circuit 184 includes a NAND gate 184A. To illustrate, as in Fig. As shown in Figure 7, when the enable signal EN has a logical value of 1, switch M9 is turned on to enable switches M1-M6. Under this condition, the logical value of the buffer signal VB is determined by the output signal VO3, as shown above. Fig. 3-4. When the output signal VO3 has a logic value of 1, the buffer signal VB has a logic value of 0. However, when the output signal VO3 has a logic value of 0, the buffer signal VB has a logic value of 1. When the enable signal has a logic value of 0, switch M9 is turned off and switches M1-M6 are also turned off. The level shifter 140 is effectively disabled. Under this condition, the NAND gate 184A outputs the buffer signal VB with a logic value of 1. As a result, therefore, the buffer 186 outputs the output level with a logic value of 0. With such arrangements, when the level shifter 140 is disabled, the device 100 continues to output the output signal VO4 with a value of 0 instead of outputting a sustain voltage.

[0048] In some embodiments, switch M9 and output stage 180 operate at voltage VDDO. In other words, the maximum voltage level of enable signal EN is set to voltage VDDO.

[0049] It will now Fig. 8 is referred to. Fig. Figure 8 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0050] Compared with the device 100 in Fig. 7 are equal elements in Fig. 8 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 8, switch M10 of device 100 is coupled to switches M1 and M3. In some embodiments, the first terminal of switch M10 is coupled to both first terminals of switches M1 and M3, and the control terminal of switch M10 is configured to receive the enable signal ENB. Switch M10 is configured to be turned on in accordance with the enable signal ENB to enable switches M1-M6. In some embodiments, the enable signal ENB is an inverse of the enable signal EN. To illustrate, when the enable signal EN has a value of 1, the enable signal ENB has a value of 0. Under this condition, switch M10 is turned on to enable switches M1-M6. The logical value of the buffer signal VB is determined according to one of the output signal VO1 and the output signal VO2 sent from the level shifter 140.However, if the enable signal EN has a logic value of 0, the enable signal ENB has a logic value of 1. Under this condition, switch M9 is turned off. Level converter 140 is effectively disabled. As a result, NAND gate 184A outputs buffer signal VB with a logic value of 1, and buffer 183 continues to output signal VO4 with a logic value of 0.

[0051] It will now Fig. 9 is referred to. Fig. 9 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0052] Compared with the device 100 in Fig. 7 are equal elements in Fig. 9 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 9, control circuit 184 is coupled to an output terminal of selector 160 and buffer 182. Control circuit 184 is configured to send voltage VDDO to buffer 182 in accordance with enable signal EN. Buffer 182 is configured to receive one of output signals VO1 and VO2 and voltage VDDO and, accordingly, to output output signal VO3. Buffer 186 is coupled to buffer 182 for receiving output signal VO3 and outputting output signal VO4 in response to output signal VO3.

[0053] In some embodiments, the control circuit 184 includes a switch M11. A first terminal of the switch M11 is configured to receive the voltage VDDO, a second terminal of the switch M11 is coupled to the selector 160 for receiving one of the output signals VO1 and VO2, and a control terminal of the switch M11 is configured to receive the enable signal EN. To illustrate, when the enable signal has the logic value 1, the switch M9 is turned on and the switch M11 is turned off. Therefore, the switches M1-M6 are enabled. As a result, the logic value of the output signal VO4 is determined according to the input signal VIN, as described above in Fig. 3-4. However, when the enable signal EN has a logic value of 0, switch M9 is turned off to disable switches M1-M6. Under this condition, switch M11 is turned on by the enable signal EN to send the voltage VDDO to buffer 182. Buffer 182 effectively receives a signal with a logic value of 1. As a result, buffer 184 outputs the output signal VO4 with a logic value of 1. With such arrangements, when level shifter 140 is disabled, device 100 continues to output the output signal VO4 with a logic value of 1 instead of outputting a maintenance voltage.

[0054] It will now Fig. 10 referred to. Fig. 10 is a circuit diagram of the device 100 in Fig. 1 according to various embodiments of the present disclosure.

[0055] Compared with the device 100 in Fig. 8 and Fig. 9 are equal elements in Fig. 10 are provided with the same reference numerals for ease of understanding. In some embodiments shown in Fig. 10, the control circuit 184 is coupled to an output terminal of the selector 160 and the buffer 182. The arrangement of the control circuit 184 in Fig. 10 is the same as the arrangement of the control circuit 184 in Fig. 9. Therefore, the corresponding descriptions are not repeated here.

[0056] To illustrate how Fig. As shown in Figure 10, when the enable signal EN has the logical value 1, the enable signal ENB has the logical value 0. Therefore, the switch M10 is turned on by the enable signal ENB, and the switch M11 is turned off by the enable signal EN. As a result, the switches M1-M6 are enabled, and the logical value of the output signal VO4 is determined according to the input signal VIN, as described above. Fig.3-4. However, when the enable signal EN has a logic value of 0, the enable signal ENB has a logic value of 1. Therefore, switch M10 is turned off by the enable signal ENB to lock switches M1-M6, and switch M11 is turned on by the enable signal EN to send the voltage VDDO to buffer 182. As a result, buffer 186 outputs the output signal VO4 with a logic value of 1.

[0057] As described above, the device 100 in the present disclosure can convert the lower-limit voltage to a standard supply voltage for low-voltage circuits and systems. Furthermore, the device 100 in the present disclosure is also capable of converting the standard supply voltage to the lower-limit voltage according to practical applications. In other words, the device 100 in the present disclosure can operate over a wide voltage operating range.

Claims

[1] Device comprising: a level converter (140) comprising a first current limiter (141), wherein the level converter (140) is configured to generate a first output signal (VO1) at a first terminal of the first current limiter (141) and to generate a second output signal (VO2) at a second terminal of the first current limiter (141) according to a first input signal (VIN); and a selector (160) configured to selectively transmit one of the first output signal (VO1) and the second output signal (VO2) according to the first input signal (VIN). [2] The apparatus of claim 1, wherein the level converter (140) further comprises: a first pull-up unit (M1) configured to pull up a voltage level of the first terminal of the first current limiter (141) to a first voltage (VDDO) according to a control signal (VC) to generate the first output signal (VO1); a first pull-down unit (M2) configured to pull down a voltage level of the second terminal of the first current limiter (141) to a second voltage (VSS) according to the first input signal (VIN) to generate the second output signal (VO2); wherein the second voltage (VSS) is lower than the first voltage (VDDO) and the first current limiter (141) is configured to reduce a current flowing from the first pull-up unit (M1) to the first pull-down unit (M2). [3] The device according to claim 1 or 2, wherein the first current limiter (141) comprises: a diode coupled between the first pull-up unit and the first pull-down unit (M2). [4] The apparatus of claim 2, wherein the level converter (140) further comprises: a second current limiter (142); a second pull-up unit configured to pull up a voltage level of a first terminal of the second current limiter (142) to the first voltage (VDDO) according to the second output signal (VO2) to generate the control signal (VC); and a second pull-down unit (M4) configured to pull down a voltage level of a second terminal of the second current limiter (142) to the second voltage (VSS) according to a second input signal (VINB) which is an inverse of the first input signal (VIN); wherein the second current limiter (142) is configured to reduce a current flowing from the second pull-up unit to the second pull-down unit (M4). [5] The device of claim 4, further comprising: an inverter (120A) configured to generate the second input signal (VINB) according to the first input signal (VIN). [6] Apparatus according to claim 4 or 5, further comprising: an output stage (180) configured to adjust a voltage variation of the first output signal (VO1) or the second output signal (VO2) sent from the selector (160). [7] The apparatus of claim 6, wherein the level converter (140) further comprises: an enable unit configured to enable the first pull-up unit (M1) and the first pull-down unit (M2) according to a first enable signal or a second enable signal, wherein the first enable signal is the inverse of the second enable signal; wherein the enabling unit is configured to enable the level converter (140) according to the first enabling signal, wherein a first terminal of the enabling unit is coupled to the first pull-down unit (M2) and the second pull-down unit (M4), and a second terminal of the enabling unit is configured to receive the second voltage; wherein, when the enabling unit is configured to enable the level converter (140) according to the enabling signal, a first terminal of the enabling unit is coupled to the first pull-up unit (M1) and the second pull-up unit, and a second terminal of the enabling unit is configured to receive the first voltage. [8] The apparatus of claim 7, wherein the output stage (180) comprises: a first buffer (184) configured to generate a third output signal (VO3) according to the first output signal (VO1) or the second output signal (VO2) sent from the selector (160); a control circuit (184A) configured to output a buffer signal (VB) according to the first enable signal (EN) and the third output signal (VO3); and a second buffer (186) configured to generate a fourth output signal (VO4) according to the buffer signal (VB). [9] The apparatus of claim 7, wherein the output stage (180) comprises: a control circuit (184) configured to pull up the voltage level of the first output signal (VO1) or the second output signal (VO2) sent from the selector (160) to the first voltage (VDDO) according to the first enable signal; a first buffer (182) configured to generate a third output signal (VO3) according to the first output signal (VO1) or the second output signal (VO2) sent from the selector (160); and a second buffer (186) configured to generate a fourth output signal (VO4) according to the third output signal (VO3). [10] The device of claim 4, further comprising: an enable unit (120B) configured to generate the second input signal (VINB) according to an initial input signal and an enable signal (EN); and an inverter (120A) configured to generate the first input signal (VIN) according to the second input signal (VINB). [11] Device according to one of the preceding claims, wherein the selector (160) comprises: a first switching unit configured to be switched on according to the first input signal (VIN) to send the first output signal (VO1); and a second switching unit configured to be switched on according to the first input signal (VIN) to send the second output signal (VO2). [12] Device comprising: a first pull-up unit (M1) configured to pull up a voltage level of a first node to a first voltage (VDDO) according to a control signal (VC) to generate a first output signal (VO1); a first pull-down unit (M2) configured to pull down a voltage level of a second node to a second voltage (VSS) according to the first input signal (VIN) to generate a second output signal; a first current limiter (141) coupled between the first node and the second node and configured to reduce a current flowing from the first pull-up unit (M1) to the first pull-down unit (M2); a selector (160) configured to send the first output signal or the second output signal according to the first input signal (VIN); and an output stage (180) configured to adjust a voltage variation of the first output signal (VO1) or the second output signal (VO2) sent from the selector (160). [13] The apparatus of claim 12, further comprising: a second current limiter (142); a second pull-up unit (M3) configured to pull up a voltage level of a first terminal of the second current limiter (142) to the first voltage (VDDO) according to the second output signal; and a second pull-down unit (M4) configured to pull down a voltage level of a second terminal of the second current limiter (142) to the second voltage (VSS) according to a second input signal (VINB) to generate the control signal (VC); wherein the second current limiter (142) is configured to reduce a current flowing from the second pull-up unit (M3) to the second pull-down unit (M4), and the second input signal (VINB) is an inverse of the first input signal (VIN). [14] The apparatus of claim 13, further comprising: an enable unit (120B) configured to generate the second input signal (VINB) according to an initial input signal (IN) and an enable signal (EN); and an inverter (120A) configured to generate the first input signal according to the second input signal (VINB). [15] The apparatus of claim 12, further comprising: an enable unit configured to enable the first pull-up unit (M1) and the first pull-down unit (M2) according to a first enable signal (EN) or a second enable signal (ENB), wherein the first enable signal (EN) is the inverse of the second enable signal (ENB); wherein, when the enabling unit is configured to enable the first pull-up unit (M1) and the first pull-down unit (M2) according to the first enabling signal (EN), a first terminal of the enabling unit is coupled to the first pull-down unit (M2) and the second pull-down unit (M4) and a second terminal of the enabling unit is configured to receive the second voltage; wherein, when the enabling unit is configured to enable the first pull-up unit (M1) and the first pull-down unit (M2) according to the second enabling signal (ENB), a first terminal of the enabling unit is coupled to the first pull-up unit (M1) and the second pull-up unit (M3) and a second terminal of the enabling unit is configured to receive the first voltage. [16] The apparatus of claim 15, wherein the output stage (180) comprises: a first buffer (182) configured to generate a third output signal according to the first output signal or the second output signal sent from the selector (160); a control circuit (184) configured to output a buffer signal according to the first enable signal and the third output signal; and a second buffer (184) configured to generate a fourth output signal according to the buffer signal. [17] The apparatus of claim 15, wherein the output stage (180) comprises: a control circuit (184) configured to pull up the voltage level of the first output signal and the second output signal sent from the selector (160) to the first voltage (VDDO) according to the first enable signal (EN); a first buffer (182) configured to generate a third output signal according to the first output signal or the second output signal sent by the selector; and a second buffer (184) configured to generate a fourth output signal according to the third output signal. [18] Method comprising: Pulling up a voltage level of a first terminal of a first current limiter (141) by a first switch to a first voltage (VDDO) according to a control signal (VC) to generate a first output signal (VO1); Pulling down a voltage level of a second terminal of the first current limiter (141) by a second switch to a second voltage (VSS) according to the first input signal (VIN) to generate a second output signal (VO2), wherein the first voltage (VDDO) is higher than the second voltage (VSS); and Sending the first output signal (VO1) or the second output signal (VO2) by a selector (160) according to the first input signal (VIN). [19] The method of claim 18, further comprising: Pulling up a voltage level of a first terminal of a second current limiter (142) by a third switch to a first voltage (VDDO) according to the second output signal (VO2); and Pulling down a voltage level of a second terminal of the second current limiter (142) by a fourth switch to the second voltage (VSS) according to the second input signal (VINB) to generate a control signal (VC), where the first input signal (VIN) is the inverse of the first input signal (VINB).

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