A process for electroplating supported by a current distribution layer

Abstract

The method comprises providing several electronic components, embedding the electronic components in an encapsulation layer, forming vias in the encapsulation layer, wherein the vias extend from a main surface of the encapsulation layer to the electronic components, and depositing a metallic layer on the encapsulation layer including the vias by electroplating, wherein the method further comprises providing a current distribution layer to effect distributed growth of the metallic material during electroplating.

Description

FIELD OF THE INVENTIONThe present disclosure relates to methods of manufacturing an electronic device package.GENERAL STATE OF THE ARTIn the course of processing an electronic device package, for example, a metallic layer must very often be deposited over the entire area of an intermediate product. In particular, in the case of extended wafer level packaging, a metallic layer needs to be deposited over the entire region of an intermediate product having the size of an artificial wafer. Such a metallic layer may fulfil the function of a redistribution layer (RDL) for redistributing the spatial arrangement of electrical contact pads of electronic components such as semiconductor chips.For depositing metallic layers, electroplating has been found to provide metallic layers of high quality and homogeneity, particularly when used for depositing metallic layers on surfaces comprising depressions or holes. However, problems may arise when the area to be covered with the metallic layer becomes very large.The publication DE 10 2014 115 653 A1 discloses a method in which an electrically conductive frame 204 is placed around chips and encapsulated with these chips. Access holes are then formed in the encapsulation compound, which contact both the electronic chips and the electrically conductive frame. Thereafter, a metal layer may be electroplated so that an electrically conductive contact is established between the frame and the chip. During later singulation, a part of the frame necessarily remains in the finished component, since the electrical contact to the chip is produced in this way.The publication US 2012 / 0199971 A1 discloses a frame carrier which has a plurality of chip receiving points. The frame carrier has a lead frame structure at the chip receiving locations. As can be seen from FIG. 3 c, the structures remain in the electronic components, they form the outer contact points.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of examples and are incorporated in and constitute a part of this specification. The drawings illustrate examples and together with the description serve to explain principles of examples. Other examples and many of the intended advantages of examples will be readily understood as they become better understood by reference to the following detailed description.The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. FIG. 1 shows a flow diagram of a method for manufacturing an electronic device package according to a first aspect including providing a plurality of electronic devices and a current distribution grid and applying an encapsulation layer over the electronic devices and the current distribution grid. FIG. 2 is a top view illustration of a current distribution grid according to an example, particularly for use with an 8-inch eWLB wafer. FIG. 3 includes FIGS. 3A to 3E and shows a top view illustration of a top portion of a wafer level package (FIG. 3E ) manufactured by a method according to the first aspect and cross-sectional side view illustrations along a plane as indicated by line A-B in FIG. 3E for illustrating a method for manufacturing the wafer level package (FIGS. 3A to 3D ). FIG. 4 includes FIGS. 4A and 4B and shows a schematic top view illustration of an electronic device package, the electronic device package including a flat metallic rail (A), and a schematic cross-sectional side view illustration of the electronic device package along a plane indicated by line B-B in FIG. 4A (B). FIG. 5 includes FIGS. 5A and 5B and shows a schematic top view illustration of an electronic device package, the electronic device package including a metallic rail with an upward extension (A), and a schematic cross-sectional side view illustration of the electronic device package along a plane indicated by line B-B of FIG. 5A (B).DETAILED DESCRIPTIONThe aspects and examples will now be described with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the examples. However, it may be apparent to one skilled in the art that one or more aspects of the examples may be practiced with a lesser degree of the specific details. In other instances, well-known structures and elements are shown in schematic form to facilitate describing one or more aspects of the examples. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be further noted that the drawings are not to scale or are not necessarily to scale.Additionally, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Moreover, to the extent that the terms "include," "have," "with," or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise.". The terms "coupled" and "connected" may be used together with derivatives. It will be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact or whether they are not in direct contact with each other. Moreover, the term "exemplary" is intended to mean merely an example rather than the best or optimum. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.The examples of an electronic device package and a method of manufacturing an electronic device package may use different types of transistor devices. The examples may use transistor devices embodied in semiconductor dies or semiconductor chips, wherein the semiconductor dies or semiconductor chips may be provided in a form of a block of semiconducting material, as manufactured from a semiconductor wafer and cut from the semiconductor wafer, or in another form in which further process steps have been carried out, such as applying an encapsulation layer to the semiconductor die or the semiconductor chip. The examples may also use horizontal or vertical transistor devices, wherein those structures may be provided in a form in which all contact elements of the transistor device are provided on one of the main surfaces of the semiconductor die (horizontal transistor structures), or in a form in which at least one electrical contact element is arranged on a first main surface of the semiconductor die and at least one other electrical contact element is arranged on a second main surface opposite the main surface of the semiconductor die (vertical transistor structures), such as MOS transistor structures or IGBT (insulated gate bipolar transistor) structures. Insofar as the transistor chips are configured as power transistor chips and if driver chips are also integrated into the package, the examples of an electronic device package disclosed below may be classified as Intelligent Power Modules (IPM).In any case, the electronic components, e.g. semiconductor dies or semiconductor chips, may comprise contact elements or contact pads on one or more of their outer surfaces, wherein the contact elements serve for electrically contacting the semiconductor dies. The contact elements may have any desired shape or shape. They may, for example, be in the form of contact pads, i.e. flat contact layers on an outer surface of the semiconductor die. The contact elements or contact pads may be made of any electrically conductive material, e.g. a metal such as aluminum, gold or copper, for example, or a metal alloy or an electrically conductive organic material or an electrically conductive semiconductor material. The contact elements can also be formed as layer stacks of one or more of the above-mentioned materials.The examples of an electronic device package may include an encapsulant or an encapsulant with the semiconductor transistor chips embedded therein and the at least one semiconductor driver chip. The encapsulation material may be any electrically insulating material, such as any type of molding material, any type of resin material, or any type of epoxy material. The encapsulating material may also be a polymeric material, a polyimide material, a thermoplastic material, a silicone material, a ceramic material, and a glass material. The encapsulating material may also comprise any of the above mentioned materials and further include fill materials embedded therein, such as thermally conductive increments. These fill increments can consist, for example, of AlO or Al 2 O 3, AlN, BN or SiN. Furthermore, the fill increments may be in the form of fibers and may be made of carbon fibers or nanotubes, for example.Examples of a method of manufacturing an electronic device package and an electronic device package may include forming a metallic layer on the encapsulation layer including filling conductive material in vias of the encapsulation layer. The metallic layer may in particular have the function of a redistribution layer (RDL) configured to redistribute or rearrange the spatial distribution or arrangement of the electrical contact pads of the electronic devices. The redistribution layer may be disposed on an upper surface of the encapsulation layer and may include a plurality of metallic traces, each of the metallic traces being connected to an electrical contact pad by a via connection formed in the encapsulation layer.Insofar as methods for manufacturing an electronic device package and for depositing a metallic layer are described as having a specific order of method steps, it should be noted that one skilled in the art may use any other appropriate order of method steps.FIG. 1 includes a flow chart for illustrating a method for manufacturing an electronic device package according to a first aspect. The method comprises: providing a plurality of electronic devices (s1); providing a current distribution grid comprising a plurality of current distribution rails (s2); applying an encapsulation layer over the electronic devices and the current distribution grid (s3); forming vias in the encapsulation layer, the vias extending from a main surface of the encapsulation layer to the electronic devices and the current distribution grid (s4); and depositing a metallic layer on the encapsulation layer including the vias by electroplating (s5).It has been previously shown that the deposition of metallic layers on large areas, as required for extended wafer level packaging, for example, can lead to unsatisfactory results when carried out by electroplating, as soon as the growth of the metallic layer starts only from edge portions of the wafer and proceeds therefrom in the direction of the centre. The results were characterized by an inhomogeneous metal layer with significant thickness variations and, in the worst case, by very poor or even no metallic growth in the middle of the wafer. Therefore, a current distribution grid as described throughout the present disclosure may help to effect distributed growth of the metallic material during electroplating. As will be shown in more detail below, the vias may be spatially distributed such that they allow homogeneous growth of the metallic layer.According to an example of the method according to the first aspect, the electronic components are arranged in a spatially regular arrangement, and the current distribution grid is arranged relative to the electronic components such that the electronic components are at least partially surrounded by the current distribution rails. In particular, the electronic components and the current distribution grid are arranged on an auxiliary carrier and thereafter the encapsulation layer is applied both on the electronic components and on the current distribution grid.According to an example of the method according to the first aspect, the provision of the current distribution grid comprises the preliminary preparation of the current distribution grid, in particular in order to obtain a freely manageable current distribution grid which can be arranged as a whole on the auxiliary carrier.According to an example of the method according to the first aspect, the provision of the current distribution grid comprises the printing, the sputtering or the plasma dust deposition of an electrically conductive layer on the auxiliary layer. In conjunction with these fabrication techniques, a mask may be positioned over the substrate, with the openings of the mask defining the shape of the current distribution grid to be fabricated. The electrically conductive layer may then be deposited through the openings of the mask. It is also possible to move a nip roller or squeegee over the mask and to press the electrically conductive material into all the non-masked areas.According to an example of the method according to the first aspect, the current distribution grid comprises a ring-like circumferential current distribution rail and a plurality of straight current distribution rails, wherein each individual one of the straight current distribution rails is connected between two points of the ring-like circumferential current distribution rail. According to another example thereof, the plurality of straight power distribution rails includes first straight power distribution rails extending in parallel along a first direction and second straight power distribution rails extending in parallel along a second direction perpendicular to the first direction. It may further be the case that the distance between adjacent first straight current distribution rails is constant and also the distance between adjacent second straight current distribution rails is constant, so that as a result a plurality of rectangular shaped regions are obtained, wherein each of the rectangular shaped regions contains an equal number of electronic components.According to an example of the method according to the first aspect, the current distribution grid comprises a thickness in a range from 10 μm to 500 μm. The thickness may be constant throughout the current distribution grid. Alternatively, the thickness may be different, for example, since the outer circumferential current distribution rail may have a greater thickness than the straight current distribution rails for stability reasons. It is also possible that the straight current distribution rails can have different thicknesses. It is further possible that individual current distribution rails may have a laterally varying thickness. A specific example thereof will be shown and explained later.According to an example of the method according to the first aspect, the current distribution grid is made of copper.According to an example of the method according to the first aspect, the current distribution rails comprise a width in a range from 1 mm to 30 mm.According to an example of the method according to the first aspect, arranging the electronic components comprises placing the electronic components on an auxiliary carrier and also arranging the current distribution grid comprises placing the current distribution grid on the auxiliary carrier. The auxiliary carrier may comprise a metallic plate, in particular a steel plate, and a double-sided adhesive film, such as a thermal release film, may be applied to the metallic plate such that the electronic components and the current distribution grid may be placed on the adhesive film.According to an example of the method according to the first aspect, forming the vias comprises forming first vias extending from a main surface of the encapsulation layer to electrical contact pads of the electronic components. According to another example thereof, the first vias comprise diameters in a range from 200 μm to 600 μm.According to another example of the method according to the first aspect, forming the vias includes forming second vias extending from a main surface of the encapsulation layer to an upper surface of the current distribution grid. According to another example thereof, the second vias comprise diameters in a range from 0.5 mm to 1.5 mm.According to another example thereof, the second vias are equally spaced apart along the current distribution rails.According to an example of the method according to the first aspect, the vias are formed into the encapsulation layer by laser drilling.According to an example of the method according to the first aspect, filling conductive material into the vias comprises depositing a seed layer on the encapsulation layer and in the vias followed by galvanic plating. According to another example thereof, the seed layer consists of an organic seed layer. According to yet another example thereof, the seed layer is deposited by wet chemical deposition.According to an example of the method according to the first aspect, an extended wafer level package is produced and, after depositing the metallic layer on the encapsulation layer and possible further steps, the extended wafer level package is singulated into a plurality of electronic device packages. According to another example thereof, the singulating of the extended wafer level package is carried out such that nothing of the current distribution grid remains in the singulated electronic device packages. This can be accomplished either by removing the current distribution grid, for example by etching or sawing at the edges of the current distribution rails. According to another example, the singulation of the extended wafer level package is performed such that specific portions of the current distribution grid remain in the electronic device packages, thereby manufacturing electronic device packages, which are described in more detail by examples below. The remaining specific portions of the current distribution grid may be configured such that they may be used as one or more of a heat sink or an electrical connector during operation of the electronic device package.FIG. 2 shows an example of a current distribution grid in a plan view illustration. The current distribution grid 10 of FIG. 2 is configured to be used with an 8-inch eWLB wafer in an extended wafer level fabrication process. The power distribution grid 10 of FIG. 2 includes a ring-like circumferential power distribution rail 1 and a plurality of straight power distribution rails 2, each one of the straight power distribution rails 2 being connected between two points of the ring-like circumferential power distribution rail 1. The straight power distribution rails 2 include first straight power distribution rails 2A extending parallel to each other along a first horizontal direction and second straight power distribution rails 2B extending parallel to each other along a second vertical direction perpendicular to the first direction. According to the example shown in FIG. 2, the power distribution grid 10 comprises three first straight power distribution rails 2A and three second straight power distribution rails 2B. The current distribution grid 10 is configured, for example, as a prefabricated, freely manageable current distribution grid 10 and comprises, for example, a diameter of 200 mm and can furthermore be produced from copper with a thickness of approximately 100 μm. The current distribution grid 10 of FIG. 2 may further comprise positioning aids 3 which assist in arranging the current distribution grid 10 in a precise position relative to the electronic components on the carrier.FIG. 3 includes FIGS. 3A to 3E and illustrates a method of manufacturing an electronic device package according to an example. The cross-sectional side view representations of FIGS. 3A through 3D are taken along a plane indicated by line A-B in FIG. 3E, showing an upper portion of the manufactured wafer level package.According to FIG. 3A, a plurality of electronic components 31 (drawn with hatching) and a current distribution grid 30 are placed on an auxiliary carrier 32. The auxiliary carrier 32 comprises a metallic plate 32.1 and an adhesive film 32.2, in particular a thermal release film 32.2, which is applied to a main surface of the metallic plate 32.1. The electronic components 31 may comprise electrical contact pads (not shown) arranged on an upper main surface facing away from the auxiliary carrier 32. The current distribution grid 30 may be formed like the current distribution grid 10 as shown and described in connection with FIG. 2. The electronic devices 31 may be one or more of semiconductor chips or passive devices, wherein the semiconductor chips may be one or more of transistor chips, driver chips, processor chips or any other semiconductor chips. The electronic components 31 may be arranged in a regular manner. The top view of FIG. 3E shows an example of arranging the electronic devices 31. Also in FIG. 3E, the positioning of the electronic devices 31 in relation to the current distribution grid 30 is shown. In the present example, the wafer level package is partitioned into multiple similar regions, each region to become an electronic device package, each region including two electronic devices surrounded by current distribution rails 30.1 of the current distribution grid 30.According to FIG. 3B, an encapsulation layer 33 is applied on the electronic components 31, the current distribution grid 30 and the auxiliary carrier 32. The encapsulation layer 33 is deposited to have a prescribed thickness over the electronic devices 31 and the current distribution grid 30.Referring to FIG. 3C, after curing the encapsulation layer 33, the auxiliary carrier 32 may be removed and a wafer level package 34 is obtained. Vias 33.1 may then be formed in the encapsulation layer 33, the vias 33.1 extending from an upper main surface of the encapsulation layer 33 to the electrical contact pads of the electronic components 31 and to the current distribution grid 30. The locations of vias 33.1 are shown in FIG. 3E, and it can be seen that vias 33.1 are placed to current distribution grid 30 with a constant distance between adjacent vias 33.1 along current distribution rails 30.1. The formation of the vias 33.1 can be carried out, for example, by laser drilling.According to FIG. 3D, after the formation of the vias 33.1, a metallic layer 35 made of copper, for example, is deposited on the encapsulation layer 33 and the vias 33.1 by galvanic plating. As a first step, an organic seed layer (not shown) may be deposited by wet chemical deposition on the encapsulation layer 33 and the vias 33.1. Thereafter, in a second step, the electroplating is carried out such that the vias 33.1 are not completely filled by the metallic material, but the bottom of the via and the side wall are covered with a certain prescribed thickness by the metallic material.A few further steps can then follow, such as, for example, the application of a solder resist layer and external contact elements. In a final step, the wafer level package is singulated to obtain multiple electronic device packages. According to an example, the current distribution grid 30 is removed, for example, by etching prior to dicing. However, it is also possible to leave the current distribution grid 30 on the wafer level package. The step of singulating may be carried out in such a way that the obtained electronic component packages do not contain any residues of the current distribution grid 30. However, it is also possible that portions of the current distribution grid 30 remain in the electronic device packages and are used during operation of the electronic device packages for the purpose of one or more electrical functions and heat sink functions.The present disclosure also relates to a method for manufacturing an electronic device package according to a second aspect. The method according to the second aspect comprises the features of independent patent claim 10. According to a further example thereof, the current distribution layer may be provided in the form of a current distribution grid, wherein the current distribution grid may also be embedded in the encapsulation layer. According to a further example thereof, both the electronic components and the current distribution grid are arranged on an auxiliary carrier and the encapsulation layer is applied on the electronic components, the current distribution grid and the auxiliary carrier.According to an example of the method according to the second aspect, the method further comprises providing the current distribution layer in a different level than the electronic components. According to another example thereof, the current distribution layer comprises the form of a current distribution grid, such as that shown for example in FIGS. 2 and 3. According to another example, the current distribution layer does not comprise the form of a current distribution grid, such as that shown for example in FIGS. 2 and 3. Instead, the current distribution layer may have another form of a metallic layer, which may also be embedded in the encapsulation layer or may consist of a carrier, in particular a carrier supporting the semiconductor chips. The current distribution layer can in this case consist of a full-area metallic layer or a system carrier, for example. In this case, vias could also be formed from a top surface of the encapsulation layer to the current distribution layer. For example, in comparison with FIGS. 3B and 3C, the current distribution layer could be below the level of the electronic devices 31 and the vias could be formed in the encapsulation layer such that they would pass between the electronic devices 31 until reaching the current distribution layer.Further examples of the method according to the second aspect can be formed by incorporating examples and features which have been described above in connection with the method according to the first aspect.The present disclosure also relates to a method for depositing a metallic layer according to a third aspect, which method is not part of the invention. The method according to the third aspect comprises providing a material layer and depositing a metallic layer on the material layer by electroplating, the method further comprising providing a current distribution layer for causing distributed growth of the metallic material during the electroplating.According to an example of the method of the third aspect, providing the material layer comprises applying the material layer over the current distribution layer and forming vias in the material layer, the vias extending from a main surface of the material layer to the current distribution layer.According to an example of the method of the third aspect, the current distribution layer may have the form of a current distribution grid such as that shown and described in connection with FIGS. 2 and 3 of the present disclosure. According to a further example, the current distribution layer may have the form of a full-area metallic plane or layer or any other type of metallic plane or layer, such as a leadframe.According to an example of the method of the third aspect, the material layer comprises the same or similar features as the encapsulation layer as described above in connection with the methods according to the first and second aspect.Further examples of the method according to the third aspect can be formed by incorporating examples or features which have been described above in connection with the methods according to the first and second aspects.FIG. 4 includes FIGS. 4A and 4B, and shows an example of an electronic device package not belonging to the invention according to a fourth aspect in a schematic plan view illustration (A) and a schematic cross-sectional side view illustration (B). The electronic device package 40 of FIG. 4 includes two semiconductor chips 41, an encapsulation layer 42 covering the semiconductor chips 41, a redistribution layer (RDL) 43 disposed over the encapsulation layer 42, and a metallic rail 44 extending along an edge of the encapsulation layer 42. Further elements or parts of the electronic device package 40, such as vias between the RDL 43 and the chips 41 or external connectors disposed over the RDL 43, are omitted here for clarity.The electronic device package 40, as shown in the example of FIG. 4, includes a metallic rail 44 having a ring-like peripheral configuration and thus extending along each of the side edges of the encapsulation layer 42. Such an electronic device package 40 may be obtained, for example, by cutting the wafer level package as shown in FIG. 3E along central axes of the current distribution rails 30. The metallic rail 44 is thus a remainder of the previous current distribution rail 30, but it is also possible that the metallic rail 44 does not extend along all side edges of the encapsulation layer 42, but for example only along one, two or three side edges of the encapsulation layer 42.According to an example of the electronic device package 40 of the fourth aspect, the metallic rail 44 may be configured such that it may be used for specific purposes for the operation of the electronic device package 40. For example, the metallic rail 44 may be used as a heat sink to assist in dissipating excess heat generated by one or more of the semiconductor chips 41. To this end, the metallic rail 44 may be thermally connected to one or more of the semiconductor chips 41. It is also possible that the metallic rail 44 serves an electrical function during operation of the electronic component package 40. To this end, the metallic rail 44 may be electrically connected to one or more of the semiconductor chips 41 or to the RDL 43. The cutting of the wafer level package of FIG. 3E may be performed such that not only a portion of the power distribution rail remains as part of the electronic device package, but also at least one of the vias connecting the power distribution rail to the RDL. It is further possible that the metallic rail 44 comprises different parts that are not directly connected to each other, wherein these different parts serve different functions, i.e. one or more of thermal and electrical functions.FIG. 5 includes FIGS. 5A and 5B and shows another example of an electronic device package according to the fourth aspect in a schematic plan view illustration (A) and a schematic cross-sectional side view illustration (B). The electronic device package 50 of FIG. 5 includes two semiconductor chips 51, an encapsulation layer 52 covering the semiconductor chips 51, a redistribution layer (RDL) 53 disposed over the encapsulation layer 52, and a metallic rail 54 extending along an edge of the encapsulation layer 52. Further elements or parts of the electronic device package 50, such as vias between the RDL 53 and the chips 51 or external connectors disposed over the RDL 53, are omitted here for clarity.The electronic device package 50 of FIG. 5 may include all features and characteristics as previously described in connection with the electronic device package 40 of FIG. 4. The electronic device package 50 of FIG. 5 differs from the electronic device package 40 of FIG. 4 in that the metallic rail 54 includes a raised portion 54.1, which may be directly connected to the RDL 53. Such a raised portion 54.1 may be useful for serving one or more of thermal and electrical functions of the metallic rail 54 during operation of the electronic device package 50. The raised portion 54.1 can be obtained, for example, by providing a current distribution grid such as that shown in one of Figures 2 or 3 such that the individual current distribution rails have varying thicknesses, in particular comprise raised portions at their longitudinal edges facing the chip regions. It is also possible for the current distribution rails to have a thickness overall such that they extend as far as the RDL, wherein then no vias need to be formed between the upper surface of the encapsulation layer and the current distribution grid (see FIGS. 3B and 3C ).

Claims

A method of manufacturing an electronic device package, the method comprising: providing a plurality of electronic devices (31); providing a current distribution grid (30) comprising a plurality of current distribution rails; manufacturing an extended wafer level package (34) by applying an encapsulation layer (33) over the plurality of electronic devices (31) and the current distribution grid (30); forming first vias (33.1) in the encapsulation layer (33) extending from a main surface of the encapsulation layer (33) to electrical contact pads of the electronic devices (31); forming second vias extending from the main surface of the encapsulation layer (33) to an upper surface of the current distribution grid (30); and depositing a metallic layer (35) on the encapsulation layer (33) including the vias (33.1) by electroplating; Singulating the extended wafer level package (34) such that nothing remains from the current distribution grid (30) in the singulated electronic device packages.The method of claim 1, wherein providing the power distribution grid (30) comprises pre-fabricating the power distribution grid (30).The method of claim 1 or 2, wherein the power distribution grid (30) comprises an annular circumferential power distribution rail and a plurality of straight power distribution rails, each one of the straight power distribution rails being connected between two points of the annular circumferential power distribution rail.The method of claim 3, wherein the plurality of straight power distribution rails comprise first straight power distribution rails extending parallel along a first direction and second straight power distribution rails extending parallel along a second direction perpendicular to the first direction.The method of any preceding claim, wherein arranging the electronic devices (31) comprises placing the electronic devices (31) on a carrier (32).The method of claim 5, wherein disposing the power distribution grid (30) comprises placing the power distribution grid (30) on the carrier (32).The method of any preceding claim, further comprising: forming the vias (33.1) by laser drilling.The method of any preceding claim, wherein filling conductive material into the vias (33.1) comprises depositing an organic seed layer on the encapsulation layer and in the vias (33.1) followed by electroplating.The method of claim 8, further comprising: depositing the organic seed layer by wet chemical deposition.A method of manufacturing an electronic device package, the method comprising: providing a plurality of electronic devices (31); embedding the electronic devices (31) in an encapsulation layer (33) to form an extended wafer level package (34); forming vias (33.1) in the encapsulation layer (33), the vias (33.1) extending from a main surface of the encapsulation layer (33) to the electronic devices (31); and depositing a metallic layer (35) on the encapsulation layer (33) including the vias (33.1) by galvanic plating; the method further comprising providing a current distribution layer (30) to effect distributed growth of the metallic layer (35) during the galvanic plating, wherein nothing of the current distribution layer (30) remains in the electronic device package.The method of claim 10, further comprising: providing the current distribution layer (30) in the same plane as the electronic devices (31).The method of claim 10, further comprising: providing the current distribution layer (30) in a different level than the electronic devices (31).

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