Self-testable bus system and use of this self-test capability for assigning bus node addresses

Abstract

Self-testable bus node (SL1, SL2, SL2) for a serial data bus - with a bus shunt resistor (R2) inserted into the data bus and - with a controllable addressing current source (Iq1, Iq2, Iq2) of this bus node for determining the bus position of this bus node in the data bus, which can additionally feed an addressing current into the data bus in such a way that the total current (i1, i2, i3) through the bus shunt resistor (R2) of this bus node corresponds to a predetermined, calculated, or otherwise determined total current (I ref ) corresponds, - so that this bus node regulates its output current (i1, i2, i3) towards the bus master (ECU) and it meets a specified maximum value of the addressing current (I amax ) plus a basic current, and - wherein the addressing current of the addressing current source (Iq1, Iq2, Iq2) of this bus node flows through the bus shunt resistor (R2) of this bus node towards the bus master (BM) during an addressing phase.

Description

General term

[0001] The proposal focuses on a self-testable serial data bus system and a method for assigning bus addresses within this serial data bus from a chain of bus nodes. General Introduction and State of the Art

[0002] Various methods for address assignment in LIN bus systems are known from the prior art. Examples include the German patent applications DE 10 2010 026 431 B4, DE 10 147 512 B4, EP 1 490 772 B1, US 2014 / 0 095 749 A1, and US 9 331 866 B2. Corresponding products are available on the market. In this context, reference is made to the datasheet ELMOS: LIN Controller with Position Detection E521.31, Production Data Oct. 6, 2015.

[0003] All these protocols share the common feature that the number of bus nodes addressable by the bus master is limited, since each bus node introduces a defined current into the bus during auto-addressing. Shunt resistors (bus shunts) are inserted into each bus node in the single-wire data bus. These currents cause a voltage drop across the shunts as they travel towards the bus master, where a current sink is active during the address assignment process. The bus nodes closest to the bus master register a higher voltage drop than those furthest away. The voltage across the bus shunt is compared to a threshold value. If this threshold is exceeded, the bus node at whose bus shunt this threshold exceedance occurs can assume that it is not the last bus node in the chain of bus nodes from the bus master.It then switches off its power source and waits for the next initialization cycle.

[0004] The bus node that is the last bus node in the bus node chain from the bus master does not switch off its power source. After a predetermined initialization time, this bus node can assume that it is the last bus node in the chain. It then adopts the bus node address transmitted by the bus master and no longer participates in further initialization cycles until a reset command or other reset condition invalidates the received bus address.

[0005] The problem is that, firstly, the electrical resistance of the bus shunt should be as low as possible. Secondly, as many bus nodes as possible should be addressable. Thirdly, the addressing system must be able to operate with a negative ground offset. Fourthly, the signal level across the bus shunt must be maximized, which requires the highest possible addressing current. Fifthly, the total current that the bus master draws during the address assignment process must not exceed a predefined value, currently 40 mA for LIN buses.

[0006] From DE 10 2010 026 431 B4, a method is known in which the individual bus nodes do not operate with a constant addressing current as in DE 10 147 512 B4 and EP 1 490 772 B1, but rather increase this addressing current continuously or in a stepwise fashion until the thresholds at the preceding bus nodes are exceeded. This has several disadvantages: Firstly, with a very large number of bus nodes, this leads to a very long rise time. However, the time for performing auto-addressing is limited. Therefore, it is necessary to shorten this time until the bus node furthest from the bus master, which has not yet been addressed, is addressed. DE 10 2010 026 431 B4 therefore does not completely solve the problem of being able to address a very large number of bus nodes and to be able to lower the resistance value of the bus shunt resistor sufficiently. Furthermore, the technical teaching disclosed in DE 10 2010 026 431 B4 does not lead to a self-testing capability.

[0007] Another disadvantage of DE 10 2010 026 431 B4 is that, for robustness reasons, a certain level range must be kept free to prevent overloading the master or incorrect addressing. To minimize the bus shunt resistances and ensure compliance with the LIN bus, it is therefore advisable to maximize the DC component in the addressing current. However, in the technical teaching disclosed in DE 10 2010 026 431 B4, this value fluctuates around an addressing current level. This unnecessarily reduces the available addressing current level.

[0008] EP 1 490 772 B1 relates to a method for addressing participants in a bus system with a control unit, a bus, and multiple addressable participants. EP 1 490 772 B1 discloses an identification mechanism in which unaddressed participants are detected by injecting an identification current into the bus. EP 1 490 772 B1 describes how a participant that detects no current or only a current below a threshold is identified as a participant to be addressed. According to EP 1 490 772 B1, this identified participant is assigned an address, whereupon the process is iteratively continued for further participants until all participants have been addressed. EP 1 490 772 B1 further discloses that addressing can be improved by injecting quiescent currents and by using differential current detection.Furthermore, EP 1 490 772 B1 teaches alternative methods for current and voltage detection to identify participants. The devices described in EP 1 490 772 B1 are not self-testing. Therefore, bus nodes according to the technical teaching of EP 1 490 772 B1 do not meet the requirements of ISO 26262 without additional effort or special safeguards. The number of bus participants in a data bus system is limited according to the technical teaching of EP 1 490 772 B1. This is a significant disadvantage and is frequently criticized by users in the market. Therefore, there is a need to overcome these limitations.

[0009] The datasheet ELMOS: LIN Controller with Position Detection E521.31, Production Data Oct.6 2015 discloses a LIN controller with position detection in accordance with the technical teaching of EP 1490 772 B1. Task

[0010] The proposal is therefore based on the task of creating a solution that avoids the aforementioned disadvantages of the prior art and offers further advantages. In particular, a self-testing device is needed that can detect a loss of the bus shunt resistance or a malfunction of the addressing current source.

[0011] This problem is solved by a method according to claim 1. Solution to the task

[0012] For better orientation, the following directions on the data bus are agreed upon: From the perspective of a bus node, everything located on the data bus between the bus node and the bus master is considered BEFORE the bus node, and everything located between the bus node and the end of the data bus is considered AFTER the bus node. These definitions apply to the entire following document.

[0013] The following describes the procedure for automatic address assignment using a standard-compliant LIN bus system. In contrast to the methods and devices of DE 10 147 512 B4, EP 1 490 772 B1, and US 9 331 866 B2, the resistance value of the bus shunt resistor is reduced here to such an extent that standard compliance can be achieved again. The Local Interconnect Network (LIN), also called LIN bus, is a serial communication system for networking sensors and actuators; it is a fieldbus. LIN is used where the bandwidth and versatility of CAN are not required. Typical application examples include networking within the door or seat of a motor vehicle. The relevant standard is ISO 17987-1, "Road vehicles - Local interconnect network (LIN) - Part 1-7".

[0014] The basic idea of ​​the proposal presented here is to use the addressing current source for self-testing and thus meet the requirements of ISO 26262. For this purpose, deviating from the technical teaching of DE 10 2010 026 431 B4, the bus current flowing into the respective bus node from subsequent bus nodes is not measured, but rather the total current (i1, i2, i3) leaving the respective bus node. This total current is composed of the addressing current fed into the data line by the addressing current source (Iq1, Iq2, Iq3) of that respective bus node and the bus current flowing into the respective bus node from subsequent bus nodes.Architecturally, this means that the bus shunt resistor (R2) of each bus node (SL1, SL2, SL3) is located in front of the respective auto-addressing current source (Iq1, Iq2, Iq3), so that the addressing current of each bus node must flow through this bus shunt resistor (R2) to reach the bus master (ECU), where it is diverted to ground.

[0015] Furthermore, another idea of ​​the proposal presented here is that, in contrast to all the aforementioned writings, an essentially constant output stream (i) is generated from the output of each bus node during the address assignment process. j ) of the relevant bus junction (SL) j ) is fed into the preceding data bus towards the bus master (ECU).

[0016] A potential problem arises from existing standard bus nodes (CS1, CS2) that lack the auto-addressing capability described in this document. This document assumes that there is no mixed installation with bus nodes that do possess auto-addressing capabilities according to other auto-addressing methods. These bus nodes (CS1, CS2) without auto-addressing capability each feed a bus current, the basic bus node current, into the data bus towards the bus master (ECU) via their bus power source (S1, R3, d1). Preferably, these are bus nodes (CS1, CS2) that exist only once in the data bus and are therefore easily distinguishable from one another by the assembly technicians, for example, during the assembly of a motor vehicle. This eliminates the need for self-addressing during the assembly of these bus nodes, for example, in a motor vehicle.Each of these standard bus nodes (CS1, CS2) feeds a base current into the data bus via a pull-up current source (S1, R3, d1), in accordance with the LIN standard. These standard bus nodes (CS1, CS2) thus collectively generate a maximum base current. This base current can be estimated by the number of standard bus nodes without auto-addressing capability, hereinafter referred to as auto-addressing bus nodes.

[0017] There are two extreme configurations that can illustrate the resulting problem. In both extreme configurations, the number of standard bus nodes without auto-addressing capability is maximized, while the number of auto-addressing bus nodes with auto-addressing capability is minimized. Configuration A

[0018] In configuration A, all n standard bus nodes that lack auto-addressing capability are located, from the perspective of the bus master (ECU), behind only two auto-addressing bus nodes that possess auto-addressing capability as described in this proposal. The maximum number n of standard bus nodes behind the two auto-addressing bus nodes with auto-addressing capability is then (n+2). max / I k . Here, I max The maximum current value that the bus master (ECU) can accept during the ISO standard auto-addressing phase. Preferably, the maximum current value I max chosen to be slightly smaller than the actual maximum current value of the bus master (ECU) to compensate for manufacturing variations and fluctuations in operating parameters. k ​is the upper limit value for the base current that each standard bus node without auto-addressing capability injects into the data bus. Preferably, each of the standard bus nodes without auto-addressing injects approximately the same base current into the data bus. The standard bus nodes without auto-addressing capability then generate a maximum base current of I at the input of the second auto-addressing bus node with auto-addressing capability. G =n*I k . A current range of I remains for auto-addressing by the auto-addressing bus nodes with auto-addressing. amax =2*I kfor the maximum addressing current of each auto-addressing bus node. This current range for the maximum addressing current of each auto-addressing bus node can then be used for auto-addressing. For this purpose, the auto-addressing bus nodes in an upstream phase A can measure this base current through their respective bus shunt resistors (R2) and then determine the current range for the maximum addressing current of each auto-addressing bus node and subsequently use it for auto-addressing. This maximizes the voltage drop across the bus shunt resistors (R2). Therefore, these can be minimized. This contrasts with DE 10 2010 026 431 B1, which does not solve this problem. Configuration B

[0019] In configuration B, all n standard bus nodes that lack auto-addressing capability are located upstream of the two auto-addressing bus nodes, which possess the capability described here, as seen from the bus master (ECU). Unlike configuration A, the auto-addressing bus nodes now cannot receive information about the number of standard bus nodes upstream of them in the direction of the bus master (ECU). Therefore, there is a risk that the maximum addressing current used by the auto-addressing bus nodes, in combination with the baseline current arriving at the bus master from all preceding bus nodes in the data bus, will be too high, leading to an error message. However, the maximum number n of standard bus nodes downstream of the two auto-addressing bus nodes is again (n+2). max / I k . Here, I max ​This is again the maximum current value that the bus master (ECU) can accept during the auto-addressing phase. Preferably, the maximum current value I max Here too, a value slightly lower than the actual maximum current of the bus master (ECU) was chosen to compensate for manufacturing variations and fluctuations in operating parameters. k This is the upper limit value for the base current that each standard bus node without auto-addressing capability feeds into the data bus. Preferably, each of the standard bus nodes again feeds approximately the same base current into the data bus. The standard bus nodes without auto-addressing capability then generate a maximum base current of I at the input of the bus master (ECU). G =n*I k For auto-addressing by the subsequent auto-addressing bus nodes, only a current range of 2*I remains. k for the addressing stream (I aThe subsequent auto-addressing bus nodes cannot receive information via this current range. While this current range can be used for auto-addressing, it must now be communicated to the auto-addressing bus nodes by the bus master (ECU). This can be done by the bus master informing all bus nodes of the number of standard bus nodes without auto-addressing capability via a message sent to all bus nodes, or by pre-communicating a suitable addressing current value via such a command. This makes it possible to maximize the addressing current in the respective auto-addressing bus nodes. Configuration C

[0020] Configuration C is a mixture of Configuration A and Configuration B

[0021] In this case, standard bus nodes without auto-addressing capability are located upstream and downstream of the auto-addressing bus nodes in the serial data bus. The bus master (ECU) then only needs to transmit the number n of standard bus nodes located upstream of the auto-addressing bus nodes. The auto-addressing bus nodes can determine the total base current by measuring the base current through their bus shunt resistance relative to the downstream bus nodes. This total base current is then summed by n times the base current of the bus nodes. k Alternatively, the bus master (ECU) can of course transmit a different value from which the basic bus current can be calculated. Based on this, each auto-addressing bus node can then determine the maximum addressing current I. amax calculate and maximize settings.

[0022] Before the bus addresses are assigned, the bus master (ECU) preferably signals to all bus nodes which of the configurations specified above is present, how many standard bus nodes are in the system that do not have the ability to auto-address, and / or how large the expected basic bus current is.

[0023] At the start of auto-addressing, the bus master (ECU) pulls the data line to ground using a switch (SB) or similar device. The current sink used for this purpose can handle the maximum current value I. max If the amount of bus current flowing into the bus master (ECU) exceeds this value, the bus master (ECU) may short-circuit and generate corresponding signals and error messages. Therefore, this maximum current value I must not exceed 1000. max The amount will not be exceeded during normal operation.

[0024] Depending on the number of standard bus nodes without auto-addressing capability and the standard-specified maximum permissible bus current I max Each bus node can then handle the maximum addressing current I amax calculate the permissible maximum addressing current (I) of its respective addressing current source (Iq1, Iq2, Iq3). max to exceed. Preferably, this value is determined by the received number n of standard bus nodes without auto-addressing capability in the respective auto-addressing bus node with auto-addressing capability. Preferably, a safety margin is also taken into account so that the actually set auto-addressing current I amax the auto-addressing current sources of the auto-addressing bus nodes (SL1, SL2, SL3) are lower than the actual maximum permissible auto-addressing current.

[0025] It must now be ensured that the maximum permissible bus current I max is not exceeded. In contrast to DE 10 2010 026 431 B4, the basic current and addressing current coming into the auto-addressing bus node from the subsequent bus nodes are not recorded, and the addressing current source itself is not deactivated if it deviates from the basic current.

[0026] Rather, the total current (i1, i2, i3) leaving each bus node via the data bus towards the bus master (ECU) is recorded. This consists of the bus current fed in by the subsequent bus nodes plus the self-generated addressing current.

[0027] For this purpose, each bus node (SL1, SL2, SL3) measures the outgoing bus current (i1, i2, i3) coming from the subsequent bus nodes (SL2, SL3), flows through the bus shunt (R2) of the respective bus node (SL1, SL2, SL3), and exits the respective bus node back towards the bus master (ECU). The respective auto-addressing bus node (SL1, SL2, SL3) then controls its own addressing current source (Iq1, Iq2, Iq3) so that the sum of the incoming bus current from the subsequent bus nodes (SL2, SL3) and the addressing current from its own addressing current source (Iq1, Iq2, Iq3) equals a predefined total current (I). s ) corresponds to the amplitude of the addressing stream (I). a ) is set so that the maximum bus current I maxThe amount of the outgoing bus current (i1, i2, i3) cannot be exceeded. Therefore, the bus current (1, i2, i3) leaving the respective bus node (SL1, SL2, SL3) remains constant and is not increased above a maximum value by the respective bus node (SL1, SL2, SL3). This prevents overloading of the bus master current sink during the address assignment process.

[0028] In this process, each of the auto-addressing bus nodes participating in the address allocation procedure detects an additional stream that deviates from the basic stream. This additional stream consists of the respective bus node's own addressing stream and the addressing stream of the bus node following that bus node (SL1, SL2, SL3).

[0029] To prevent the output current (i1, i2, i3) from being overdriven by I maxWhen a signal arrives, the respective bus node regulates its output current (i1, i2, i3) towards the bus master (ECU) in such a way that it always corresponds to the intended maximum value of the addressing current I. amax plus the base current. For this purpose, the addressing current source (Iq1, Iq2, Iq3) within each auto-addressing bus node (SL1, SL2, SL3) with auto-addressing capability is designed to be controllable. The addressing current of the respective addressing current source (Iq1, Iq2, Iq3) then depends, firstly, on the previously determined maximum value (I amax ) and secondly from a control signal which is determined by means of a control loop (F) and a measuring device (R2, D1) from the output current (i1, i2, i3) of the respective bus node (SL2) towards the bus master (ECU).

[0030] The control loop begins at a measuring device, preferably a bus shunt resistor (R2), which is inserted into the data bus upstream of each bus node (SL1, SL2, SL3) as viewed from the bus master (ECU). There, the bus current from the respective bus node towards the bus master (ECU) is converted into a voltage value. This voltage is then detected by a measuring device, e.g., an operational amplifier (D1), and, if necessary, filtered (F) before being converted into a control value. This control value is then used to control the respective auto-addressing current source (Iq1, Iq2, Iq3) so that the bus current (i1, i2, i3) towards the bus master (ECU) is kept constant during this address assignment phase.

[0031] Within each bus node (SL1, SL2, SL3), a controlled variable, the controlled value, preferably as an output signal of the aforementioned filter (F), occurs when the necessary control loop is appropriately designed. For the sake of simplicity, it is assumed here by way of example that this controlled variable is directly proportional to the respective output current (i1, i2, i3) of the respective auto-addressing bus node (SL1, SL2, SL3) towards the bus master (ECU).

[0032] If, after the specified initialization time, this rule value still exceeds a predefined threshold (SW), meaning that the addressing current source (Iq1, Iq2, Iq3) delivers the specified output current towards the bus master (ECU), then the respective auto-addressing bus node is the last in the chain of auto-addressing bus nodes from the bus master (ECU). The affected auto-addressing bus node then adopts the bus node address previously transmitted by the bus master (ECU) to all auto-addressing bus nodes (SL1, SL2, SL3) as its now valid bus node address and no longer participates in further initialization cycles until a reset command or other reset condition invalidates the received bus address.The other auto-addressing bus nodes that do not yet have a valid bus node address and are not the auto-addressing bus node that has just adopted the bus node address to be assigned as a valid bus node address, participate in the following initialization cycles.

[0033] Preferably, the output current value of the auto-addressing current sources Iq1, Iq2, Iq3 within the auto-addressing bus nodes (SL1, SL2, SL3) is controlled by a filter (F). Preferably, the control loop is a PI controller. This filtering is necessary to prevent overshoot when the addressing current is generated by all the auto-addressing bus nodes (SL1, SL2, SL3) at the bus master (ECU). If this were to occur, the maximum permissible bus current I could be exceeded. max The limit is exceeded and the bus master (ECU) detects a short circuit, which should be avoided.

[0034] Therefore, it is advantageous and preferable to include at least one low-pass filter (F) in the control loop of each auto-addressing bus node (SL1, SL2, SL3).

[0035] In a further, preferred embodiment of the proposal, the filter (F) is implemented non-linearly. Preferably, a first control time constant (τ1) of the non-linear filter (F) for increasing the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3) should be larger than a second control time constant (τ2) of the non-linear filter (F) for decreasing the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3). It has been shown that for m auto-addressing bus nodes, the second time constant (τ2) for a reduction of the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) by a factor of m should be shorter than the first time constant (τ1) for an increase of the addressing current of the respective addressing current source (Iq1, Iq2, Iq3).This results in the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3) decreasing faster than increasing. Consequently, subsequent auto-addressing bus nodes reduce their addressing current faster than it is increased by other auto-addressing bus nodes. Therefore, a constant bus current, or at least a permanent deviation below a maximum bus current value I, is ensured. max during the addressing phase. Simulations have shown that the first time constant (τ1), with which the addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3) is reduced, should preferably be a factor of 10, or better yet a factor of 100, faster (=smaller) than the second time constant (τ2), with which the addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3) is increased.

[0036] However, as previously described, a typical LIN bus also contains standard LIN bus nodes without auto-addressing capability. These supply a constant current to the bus master (ECU) during the addressing phase. In contrast to other methods that rely on a base current, the threshold for recognizing the last bus position can now be set very high for the auto-addressing bus node to be assigned a bus address in the relevant initialization run.

[0037] After an auto-addressing bus node with auto-addressing capability has received a valid bus address in this way, it preferentially uses its addressing current source like a basic bus node current source and then behaves like a bus node without auto-addressing capability. As a possible alternative, separate basic bus node current sources (S1, R3, d1) are shown in the figures within the auto-addressing bus nodes (SL1, SL2, SL3). These could then be omitted. This state of an auto-addressing bus node after a valid bus node address has been assigned is preferably only changed by resetting the auto-addressing bus node or deleting the validity of the bus node address. In the next initialization cycle, the last auto-addressing bus node receives a valid bus node address from the bus master (ECU) and from then on behaves like a standard bus node without auto-addressing capability.The auto-addressing bus nodes that have not yet received a valid bus node address continue to behave as auto-addressing bus nodes. This ends one initialization cycle. The bus master then initiates another initialization cycle, in which the second-to-last auto-addressing bus node from the bus master's (ECU) perspective, which is now the last auto-addressing bus node from the bus master's perspective, receives a valid bus node address, and so on. This repeated imitation of the initialization cycles by the bus master (ECU) and the assignment of a valid bus node address in each such initialization cycle to the last auto-addressing bus node from the bus master's perspective, which behaves as such, is carried out until all auto-addressing bus nodes have received a valid bus node address from the bus master (ECU).To determine this, the bus master (ECU) preferably checks after each initialization run whether the addressed auto-addressing bus node, which is supposed to have just received a valid bus node address, responds. Preferably, the addressed auto-addressing bus node then sends a random number to the bus master (ECU) at the ECU's instigation. If two auto-addressing bus nodes are active – for whatever reason – bus collisions occur. These can be detected by the bus nodes and signaled to the bus master. In certain cases, if the response is predictable, the bus master (ECU) can also detect a bus collision directly. The bus master can thus detect a bus collision either directly or indirectly and, if necessary, repeat the initialization of the affected bus address. For this purpose, it is advantageous if the bus master (ECU) can send a delete command for the last assigned bus address to all bus nodes.

[0038] During address assignment, the bus current can now be checked for various conditions via the bus shunt: a) If the voltage drop across the bus shunt resistor (R2) exceeds a maximum voltage drop threshold, a short circuit of the downstream bus to the supply voltage occurs. In this case, the affected bus node preferentially shuts down all power sources to prevent damage to the system. The bus master (ECU) usually also detects this short circuit. b) If the voltage drop across the bus shunt resistor is 0V, then the measuring input is typically short-circuited. c) If the voltage drop across the bus shunt resistor (R2) is below the maximum voltage drop threshold, but above a second voltage drop threshold, then the bus shunt resistor is probably disconnected from the subsequent bus nodes and the measuring input is still connected to the subsequent bus nodes, which raise the potential of this measuring line to the supply voltage. d) If the voltage drop across the bus shunt resistor is within the range of the voltage drop of the base current, the addressing current source (Iq1, Iq2, Iq3) of the affected bus node will not function, even though it is the last node. The bus node can signal this to the bus master (ECU), for example, by provoking a bus collision by accepting the bus node address to be assigned as a valid bus node address. This then results in two auto-addressing bus nodes responding to the bus master when checking the correct bus node addressing, which the bus master can then detect. Thus, a method for assigning bus node addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU) is proposed, in which the bus nodes (SL1, SL2, SL3) can be auto-addressing bus nodes or standard bus nodes, and the data bus includes a bus master (ECU).Each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1). Each bus node (SL2, SL3) is connected to its preceding bus node (SL1, SL2) via the data bus if it is not the first bus node (SL1). The first bus node (SL1) is connected to the bus master (ECU) via the data bus. Each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, SL2) via a bus node output if it is not the first bus node (SL1). The first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via a bus node output. Each bus node (SL1, SL2) receives a bus node input stream (i2, i3) from its subsequent bus nodes (SL2, SL3) via a bus node input if it is not the last bus node (SL3). The procedure comprises the following steps: • Determination of the maximum addressing current (I amax ). • Perform an initialization sequence with the following steps for each auto-addressing bus node of the bus nodes (SL1, Sl2, SL3) that does not yet have a valid bus node address until all auto-addressing bus nodes of the bus nodes (Sl1, Sl2, Sl3) have a valid bus node address: ◯ Signaling of a bus address to be assigned to all auto-addressing bus nodes; ◯ Performing the following steps through all auto-addressing bus nodes (SL1, SL2, SL3), hereinafter referred to as the relevant auto-addressing bus node (SLj): ▪ Receipt of the said auto-addressing command from the bus master (ECU) by the relevant auto-addressing bus node (SLj); ▪ Receipt of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (SLj); ▪ Switch off any existing bus node power sources (S1, R3, d1) within the respective auto-addressing bus node (SLj) ▪ Receipt of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (SLj) and start of a timer by the relevant auto-addressing bus node (SLj); ▪ Feeding in the bus input current received from the subsequent bus nodes (SL(j+1), SL(j+2)...) (i (j+1) ) into the bus node output of the relevant auto-addressing bus node (SLj) as part of the bus output stream (i j ) of the relevant auto-addressing bus node (SLj); ▪ Capturing the value of the bus node output current (i j ) of the relevant auto-addressing bus node (SL j ) using measuring instruments (R2, D1, D3); ▪ Generation of a control signal (rw) j ) from the recorded value of the bus node output current (i j ) of the relevant auto-addressing bus node (SLj) by means of control (F); ▪ Regulating the bus node output current (i j) by the relevant auto-addressing bus node (SLj), by means of a regulated auto-addressing current source (Iqj), whose addressing current is a portion of the bus output current (i j ) represents a given total flow value (I ref ) depending on the generated control signal (rwj), ▪ wherein an increase in the addressing current of the regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is performed with a first time constant (τ1) and ▪ wherein a reduction of the addressing current of the regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is performed with a second time constant (τ2) and ▪ where the second time constant (τ2) is smaller than the first time constant (τ1); ▪ Comparing the rule value (rj) of the relevant auto-addressing bus node (SLj) with a threshold value (SWj) of the relevant auto-addressing bus node (SLj); ▪ Freezing the control of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) at a first time t1 after the start of the timer; ▪ Adoption of the bus node address to be assigned from the bus master (ECU) as the valid bus node address of the relevant auto-addressing bus node (SLj) if a minimum time has elapsed since the start of the timer and if the comparison of the control value (rj) with a threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the relevant auto-addressing bus node (SLj) is above a current threshold value, and configuration of the relevant auto-addressing bus node (SLj) as a standard bus node without auto-addressing capability with the bus node address to be assigned as the bus node address of the relevant auto-addressing bus node (SLj) at a second time t2 after the first time t1, whereby this auto-addressing bus node (SLj) no longer participates in subsequent initialization sequences until further notice. ◯ Verification of successful address assignment by the bus master (ECU); ◯ If necessary, delete the validity of the last assigned bus node address, causing the relevant auto-addressing bus nodes (SLj) to behave again like auto-addressing bus nodes (SLj) without a valid bus node address; ◯ Checking whether all auto-addressing bus nodes have received a valid bus node address; • Execute another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address

[0039] In one variant of the proposed method, the second time constant (τ2) is smaller than the first time constant (τ1) by a factor greater than 10, preferably greater than 100. In another variant of the method, the first time constant (τ1) within the relevant auto-addressing bus node (SLj) depends on the value of the bus node output current (i) as measured by measuring instruments (R2, D1, D3). j ) of the relevant auto-addressing bus node (SL j). For example, it is advantageous if the first time constant (τ1) is very short at the beginning, when the total current through the bus shunt resistor is still small, and thus the addressing current source of the respective auto-addressing bus node increases the current very quickly, while later the addressing current of the auto-addressing current source increases slowly. It is therefore conceivable that the first time constant (τ1) within the respective auto-addressing bus node (SLj) depends on the value of the bus node output current (i) measured by means of measuring instruments (R2, D1, D3). j ) of the relevant auto-addressing bus node (SL j) depends in such a way that the value of the first time constant (τ1) has a first value below a threshold and a second value above the threshold. Likewise, it is of course conceivable that the second time constant (τ2) within the relevant auto-addressing bus node (SLj) depends on the value of the bus node output current (i) measured by measuring instruments (R2, D1, D3). j ) of the relevant auto-addressing bus node (SL j depends.

[0040] A data bus system with bus nodes (SL1, SL2, SL3) for a serial data bus is proposed, each node having a bus shunt resistor (R2) inserted into the data bus. Furthermore, they are to include an addressing current source (Iq1, Iq2, Iq3) for determining the bus position of the bus node in the data bus. This source can additionally inject an addressing current into the data bus in such a way that the total current (i1, i2, i3) through the bus shunt resistor (R2) of the bus node (SI1, SL2, SL3) is reduced to a predetermined, calculated, or otherwise determined sum current (I). refThe control is achieved via the aforementioned control loop (R2, D1, D3, F, Iq1, Iq2, Iq3). The addressing current flows through the bus shunt resistor (R2) of the respective auto-addressing bus node. One variant of the proposed bus node has means (R2, D1) to detect the current through the bus shunt resistor (R2), which can include the acquisition of a measured value. This detected current through the bus shunt resistor (R2) can be used for a self-test in such a way that the errors described above (e.g., bus shunt resistor failure) can be detected. In a particularly preferred variant of the auto-addressing bus node, the addressing current source (Iq1, Iq2, Iq2) increases the addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) that is smaller than the first time constant (τ1). Advantage of the proposal

[0041] The proposed method and device enable partial self-testing of the bus nodes and the data bus system.

[0042] In contrast to the preceding devices and methods from the prior art, the proposed method thus operates with an essentially constant bus node output current during the address assignment phase, which, apart from manufacturing variations in design-configured parameters, should be essentially the same for all auto-addressing bus nodes. This avoids EMC emissions such as those shown in DE 10 2010 026 431 B1, which exhibits a sawtooth-like current waveform.

[0043] Furthermore, this addressing current can now be chosen to be very large, or at least maximal. This allows for a corresponding reduction in the resistance values ​​of the bus shunt resistors (R2), since only an addressing current flows through these resistors along with the basic current. This ensures that, after successful completion of all initialization cycles, a LIN bus system only contains bus nodes that behave according to the LIN standard.

[0044] However, the advantages are not limited to this. List of characters Fig. Figure 1 shows a simplified, schematic representation of a proposed bus system, where the measurement of the total current is carried out by measuring the total current at a shunt resistor in the bus output of the respective auto-addressing bus node (SL1, SL2, SI3). Fig. Figures 2 to 4 show the course of the output currents (i1, i2, i3) of the bus nodes (SL1, SL2, SI3) and the currents of the addressing current sources (Iq1, Iq2, Iq3) for different time constants of the control. Fig. Figure 5 schematically simplifies a category A bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Fig. Figure 6 schematically simplifies a category B bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Fig. Figure 7 schematically simplifies a category C bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Description of the figures: Figure 1

[0045] Fig. Figure 1 shows a simplified and schematic representation of a proposed bus system.

[0046] At the start of the auto-addressing process, the bus master (ECU) signals to all auto-addressing bus nodes that bus node addresses are to be assigned. The subsequent address assignment is divided into address assignment phases. In each phase, preferably exactly one auto-addressing bus node—namely, the last of the auto-addressing bus nodes (SL1, SI2, SI3) in the bus node chain that has not yet received a bus node address—receives a valid bus node address from the bus master (ECU) via an initialization pass. Preferably, the bus master transmits, via a so-called broadcast command, to all auto-addressing bus nodes the number of standard bus nodes located before the auto-addressing bus nodes (SI1, SI2, SI3), i.e., between them and the bus master (ECU), or a maximum addressing current level. Naturally, this maximum addressing current level I can be... amaxThe bus node must also be programmed in, since the bus topology is typically design-related and not operationally determined, and therefore predictable. This defines which total current (I) ref ) should flow through the bus shunt resistor (R2).

[0047] At the beginning of each address assignment phase, the bus master (ECU) closes its switch (SB) again for a predetermined addressing time T. AThis current sink (SB) of the bus master (ECU) is typically a more complex structure capable of detecting a bus short circuit and is only shown here in a simplified form. In this way, the bus master (ECU) provides a current sink for the addressing current of the auto-addressing current sources and the bus node base currents during the subsequent address assignment phase. The auto-addressing-capable bus nodes (SL1), (SL2), and (SL3) register that the data bus is pulled to ground and open their respective switches S1 and S2. This prevents the auto-addressing bus nodes (SL1, SL2, SL3) from feeding any further bus node base current into the data bus.

[0048] After an initial time interval (dt1) has elapsed, the auto-addressing bus nodes determine the base current through their respective bus shunt resistors (R2) by measuring the voltage drop across this resistor. This voltage drop can be temporarily stored as an offset voltage value in a sample-and-hold circuit and subsequently subtracted from the later measured voltage drop across the bus shunt resistor (R2) by a subtractor circuit. This ensures that only the bus current that deviates from the respective base current, and which is the addressing current of the auto-addressing bus nodes, is used for address assignment and the control of the addressing current sources (Iq1, Iq2, Iq3).

[0049] This phase ends after a second period of time (dt2) has elapsed.

[0050] All auto-addressing bus nodes that do not yet have a valid bus node address detect the current through their respective bus shunt resistor (R2) that deviates from the base current and, based on this bus current measurement obtained, subsequently regulate their respective addressing current source (Iq1, Iq2, Iq3) so that the current through their respective bus shunt resistor (R2) corresponds to the previously determined or specified current sum (I ref). For this purpose, each auto-addressing bus node has measuring devices (R2, D1, D3) to determine the actual current sum in the form of the respective bus node output current (i1, i2, i3) towards the bus master (ECU). The voltage drop across the bus shunt resistor (R2) is measured and, preferably after subtracting the voltage value for the bus base current, further processed as a current sum signal. As already explained, the current sum signal thus generated is filtered into a control signal in a preferably non-linear filter (F1). This is compared with a reference value (Ref) by a differential amplifier stage, which is a comparison of the respective bus node output current (i1, i2, i3) with a reference current (I). ref ) is equivalent in its effect. When setting or calculating the reference current (I refIn reality, this reference value (Ref) is typically determined. This comparison can be performed before and after filtering in the filter (F). Preferably, this is a difference calculation. Further filtering, not shown in the figures, can also occur after this comparison. The resulting control value (rw1, rw2, rw3) then controls the respective addressing current source (Iq1, Iq2, Iq3) of the respective auto-addressing bus node (SL1, SL2, SL3).

[0051] Since the sum of the currents at the output of each auto-addressing bus node (SL1, SI2, SI3) must always be constant, only the last auto-addressing bus node (SL3) ultimately supplies electrical current to the data bus, while all other addressing current sources (Iq1, Iq2) of the other auto-addressing bus nodes (SL1, SI2) are regulated down by the regulators (R2, D1, D3, F) of the other auto-addressing bus nodes (SL1, SI2). As a result, the control value (rw3) of the last bus node (SL3) differs from the control values ​​(rw1, rw2) of the other bus nodes (SL1, SI2) in that it fully drives the addressing current source (Iq3) of its bus node (SL3), while the control values ​​(rw1, rw2) of the preceding bus nodes (SL1, SL2) have values ​​that cause them to reduce their addressing current sources (Iq1, Iq2). Thus, each bus node (SL1, SL2, SL3) can compare this rule value (rw1, rw2, rw3) with a preferably approximately equal threshold value (SW).

[0052] This phase ends after a third period (dt3).

[0053] The end of this addressing phase is preferably marked by the opening of the current sink switch (SB). This brings the data bus back to supply voltage. The bus nodes (SL1, SL2, SL3) then preferably freeze the value of their respective control value (rw1, rw2, rw3) and evaluate it against the aforementioned threshold value (SW). Based on this, they decide whether they are the last auto-addressing bus node (here SL3) in the bus node chain (SL1, SL2, SL3) or a preceding auto-addressing bus node (SL1, SL2). If they are the last bus node (SL3), they take over the bus address to be assigned, which was signaled by the bus master (ECU) at the very beginning and which they preferably stored in a suitable memory for this case after receiving it. This auto-addressing bus node (SL3) then no longer participates in further addressing phases in the form of initialization cycles.This means that this auto-addressing bus node (SL3) will no longer feed an addressing current into the data bus via its addressing current source (Iq3). Naturally, it will also no longer accept the additional bus addresses offered by the bus master (ECU), since it already has a valid bus address and should behave like a standard bus node until its valid bus node address becomes invalid. The bus node address of an auto-addressing bus node becomes invalid, for example, if the operating voltage drops below a certain threshold, or due to a command from the bus master, or due to some other signaling.

[0054] Preferably, the bus master checks for successful address assignment at the end of each initialization run.

[0055] The addressing phase then follows in the form of an initialization pass, in which the next, and now last, unaddressed auto-addressing bus node (SL2) receives its valid bus address in the same way. The process is analogous. This auto-addressing bus node (SL2), like the first auto-addressing bus node (SL3) to be assigned a valid bus address, no longer participates in subsequent addressing phases. It then behaves like a standard bus node. This means that it no longer feeds an addressing stream into the data bus via its addressing stream source (Iq2). Naturally, it also no longer accepts the further bus addresses offered by the bus master (ECU), since it now has a valid bus address. This process continues until all auto-addressing bus nodes have received a valid bus address. Figure 2

[0056] Fig. Figure 2 shows the waveform of the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_intern) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_intern) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_intern) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for ramping up and ramping down the addressing current sources are approximately equal. This results in an overshoot.It is clearly visible that the current (I1_intern) of the addressing current source (Iq1) of the first bus node (SL1) and the current (I2_intern) of the addressing current source (Iq2) of the second bus node (SL2) are regulated down by the controllers of these auto-addressing bus nodes, while the current (I3_intern) of the addressing current source (Iq3) of the third bus node (SL3) is regulated to the reference value. Unlike in DE 10 2010 026 431 B4, the settling time is determined only by the first time constant (τ1). Figure 3

[0057] Fig. Figure 3 shows the waveform of the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_intern) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_intern) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_intern) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for increasing the addressing current sources are approximately ten times longer than the time constants for decreasing the addressing current sources. This results in a minimal overshoot. Figure 4

[0058] Fig.Figure 4 shows the waveform of the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2), and the output current (i3) of the third bus node (SL3). It also shows the current (I1_intern) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_intern) of the addressing current source (Iq2) of the second bus node (SL2), and the current (I3_intern) of the addressing current source (Iq3) of the third bus node (SL3). Here, the time constants for increasing the addressing current sources are approximately one hundred times longer than the time constants for decreasing the addressing current sources. No overshoot occurs. Figure 5

[0059] The diagram schematically simplifies a category A bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Figure 6

[0060] The diagram schematically simplifies a category B bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Figure 7

[0061] The diagram schematically simplifies a category C bus system with two standard bus nodes (CS1, CS2) that do not have auto-addressing capability. Reference symbol list D1 first differential amplifier; D2 second differential amplifier; D3 third differential amplifier; ECU Busmaster; F nonlinear filter of an auto-addressing bus node(SL1, SL2, SL3); Iq1 is the regulated addressing current source of the first auto-addressing bus node (SL1), which supplies the addressing current of the first auto-addressing bus node (SL1); i1 Bus node output current of the first auto-addressing bus node (SL1); Iq2 regulated addressing current source of the second auto-addressing bus node (SL2), which supplies the addressing current of the second auto-addressing bus node (SL2); i2 Bus node output current of the second auto-addressing bus node (SL2) Iq3 regulated addressing current source of the third auto-addressing bus node (SL3), which supplies the addressing current of the third auto-addressing bus node (SL3). i3 Bus node output current of the third auto-addressing bus node (SL3) I ref specified current sum for the bus node output currents R1 Auxiliary shunt resistor of an auto-addressing bus node (SL1, SL2, SL3) R2 Bus shunt resistor of an auto-addressing bus node (SL1, SL2, SL3) Reference value rw1 Rule value of the first auto-addressing bus node (SL1) rw2 Rule value of the second auto-addressing bus node (SL2) rw3 Rule value of the third auto-addressing bus node (SL3) S1 is the first switch of an auto-addressing bus node (SL1, SL2, SL3) S2 second switch of an auto-addressing bus node (SL1, SL2, SL3) S3 third switch of an auto-addressing bus node (SL1, SL2, SL3) self-service counter SL1 first auto-addressing bus node SL2 second auto-addressing bus node SL3 third auto-addressing bus node List of cited works DE 10 2010 026 431 B4, DE 10 147 512 B4, EP 1490 772 B1, US 2014 / 0 095 749 A1, US 9 331 866 B2

Claims

[1] Self-testable bus node (SL1, SL2, SL2) for a serial data bus - with a bus shunt resistor (R2) inserted into the data bus and - with a controllable addressing current source (Iq1, Iq2, Iq2) of this bus node for determining the bus position of this bus node in the data bus, which can additionally feed an addressing current into the data bus in such a way that the total current (i1, i2, i3) through the bus shunt resistor (R2) of this bus node corresponds to a predetermined, calculated, or otherwise determined total current (I ref ) corresponds, - so that this bus node regulates its output current (i1, i2, i3) towards the bus master (ECU) and it meets a specified maximum value of the addressing current (I amax ) plus a basic current, and - wherein the addressing current of the addressing current source (Iq1, Iq2, Iq2) of this bus node flows through the bus shunt resistor (R2) of this bus node towards the bus master (BM) during an addressing phase. [2] Bus junction according to the preceding claim, - wherein the bus node has means (R2, D1) to detect the current through the bus shunt resistor (R2) of this bus node. [3] Bus junction according to the preceding claim, - where the detected current through the bus shunt resistor (R2) of this bus node is used for a self-test. [4] Bus junction according to one or more of the two preceding claims, - wherein the addressing current source (Iq1, Iq2, Iq2) of this bus node increases its addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) that is smaller than the first time constant (τ1).

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