Microelectromechanical component

Abstract

Microelectromechanical component (400), comprising: • a first layer (102) and a second layer (106) arranged above the first layer (102), wherein a cavity (104g) is provided between the two layers (102, 106) and wherein the second layer (106) has a contact area (100k), • a liner layer (108) which is arranged in the contacting area (100k) above the second layer (106), wherein the liner layer (108) comprises an undoped oxide material and wherein the liner layer (108) has a layer thickness of less than 50 nm, • a cover layer (110) which is arranged in the contact area (100k) above the liner layer (108), wherein the cover layer (110) has a doped oxide material and wherein the cover layer (110) has a greater layer thickness than the liner layer (108), • wherein a contact hole (424) extends through the liner layer (108) and the cover layer (110) to the second layer (106) to contact a surface section (406a) of the second layer (106); • an electrically conductive diffusion barrier layer (414) covering the top layer (110), a side wall (110w, 108w) of the contact hole (424) and the surface section (406a) of the second layer (106); and • a metal layer (416) arranged above the diffusion barrier layer (414) for contacting the second layer (106) in the contacting area (100k).

Description

[0001] Several embodiments relate to a microelectromechanical component.

[0002] In general, various microstructured components can be fabricated using semiconductor technology or other technologies. For example, there are numerous applications for microstructured components, such as sensors, actuators, filters, and the like. A microstructure (e.g., with a feature size in the micrometer range or smaller) can also be created in conjunction with a suitable electrical structure. If mechanical properties of a microstructure are utilized, such as vibration, strain, or similar properties, such a microstructure can be referred to as a micromechanical structure. Together with an electrical structure for operating (e.g., powering, reading, etc.) the micromechanical structure, this can be called a microelectromechanical system (MEMS) or a microelectromechanical component. It can be fabricated, for example, using conventional methods or...It can be difficult to produce cavities for microstructures in sufficient quality and at the same time in an economically viable way.

[0003] Various MEMS components are described in the publications DE 10 2012 208 030 A1, US 2012 / 0 138 436 A1, and US 2016 / 0 090 299 A1.

[0004] According to various embodiments, a cavity can be created in a layered structure by using a sacrificial layer as a placeholder between two layers of the structure, wherein the sacrificial layer is at least partially removed, thus leaving the cavity. For example, access holes can be provided in at least one of the layers to remove the sacrificial layer, allowing it to be removed through these access holes using an etching solution. Visually, the sacrificial layer can be removed at least section by section through a perforated layer using wet chemical etching.

[0005] According to various embodiments, a method is provided by which a sacrificial layer arranged between two layers can be efficiently and with sufficient quality removed. This is also successful if, for example, for process-related reasons, a top layer that can only be removed wet-chemically with a low etch rate is arranged above the layer containing the access holes. To this end, an additional liner layer is used between the top layer and the layer. This liner layer comprises a material that can be removed with a high etch rate, for example, to quickly create access through the access holes to the sacrificial layer, even if the top layer has not yet been completely removed in some sections. The liner layer and the top layer can also function as a dielectric layer stack, e.g.,in a contact area to contact at least one of the layers.

[0006] According to various embodiments, for example, the inner wall of a recess (e.g., a through-hole, a trench, etc.) is lined with a liner layer made of a material that is easily removed (e.g., with a high etch rate, e.g., by wet chemical etching). The recess can then be partially or completely filled with another material that is difficult to remove (e.g., with a low etch rate, e.g., by wet chemical etching). In subsequent wet chemical etching, the recess is quickly and cleanly etched down to the liner layer before the remaining material has been completely removed. This allows for a time saving and a clean etching result, for example, when etching down to the liner layer.

[0007] According to various embodiments, a so-called etch promoter layer made of a material that can be easily removed by wet chemical etching is used to ensure fast and clean wet chemical etching along a path defined by the extent of the etch promoter layer.

[0008] According to various embodiments, a layered structure can be processed, e.g., structured, using an etch promoter layer. For example, a cavity in a substrate can be formed using the etch promoter layer.

[0009] According to various embodiments, a layered structure can comprise a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, wherein the second layer has at least one opening, the at least one opening extending from a first side of the second layer to the sacrificial layer, wherein a method for processing the layered structure can comprise: forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer over the liner layer, the cover layer extending at least sectionally into the at least one opening; wet-chemical etching of the cover layer, the liner layer, and the sacrificial layer using an etching solution, wherein the etching solution has a higher etching rate for the liner layer than for the cover layer.

[0010] The etching rate, also known as the etching speed, represents the material removal rate of a structure (e.g., a layer) per unit of time. When etching a structure, the etching rate also represents the change in the structure's dimensions (e.g., length, width, depth, and / or height) due to material removal over time. When etching a layer from one side, the etching rate also represents the change in the layer's thickness due to material removal per unit of time.

[0011] According to various embodiments, the liner layer and the top layer are etched at different speeds in a common etching solution due to their different material properties or material configuration; in other words, their etching speeds are different from each other.

[0012] Based on the processing of the layer structure as described herein, it is simultaneously possible to establish improved electrical contact on the second layer, which is arranged above the sacrificial layer. The area where the second layer is contacted (referred to herein as the contact area) is located laterally to the area where the at least one opening is formed and from which, for example, the sacrificial layer is removed. Visually, the layer structure can include a cavity area and a contact area, with the liner layer and the cover layer serving as dielectric insulation in the contact area.

[0013] According to various embodiments, a microelectromechanical device can comprise: a first layer and a second layer arranged above the first layer, wherein a cavity is provided between the two layers and wherein the second layer has a contact area; a liner layer arranged in the contact area above the second layer, wherein the liner layer comprises an undoped oxide material and wherein the liner layer has a thickness of less than 50 nm; a cover layer arranged in the contact area above the liner layer, wherein the cover layer comprises a doped oxide material and wherein the cover layer has a greater thickness than the liner layer, wherein a contact hole extends through the liner layer and the cover layer to the second layer for contacting a surface section of the second layer;an electrically conductive diffusion barrier layer that completely covers the top layer, a side wall of the contact hole and the surface section of the second layer; and a metal layer arranged above the diffusion barrier layer for contacting the second layer in the contact area.

[0014] According to various embodiments, a method for processing a layer may include: forming a recess in the layer; covering an inner wall of the recess with a liner material; subsequently, filling a remaining area of ​​the recess with another material; completely removing the liner material and the other material from the recess by wet chemical etching of the liner layer using an etching solution, wherein the etching solution has a higher etching rate for the liner layer than for the cover layer.

[0015] Examples of implementation are shown in the figures and are explained in more detail below.

[0016] They show Fig. 1A to 1F each show a schematic view of a layer structure during the processing of the layer structure, according to different embodiments; Fig. 2A to 2C each show a schematic view of a layer structure during the processing of the layer structure, according to different embodiments; Fig. 3 a schematic view of a layer structure after processing the layer structure, according to different embodiments; Fig. 4A and Fig. 4B Various schematic views of a microelectromechanical component, according to different embodiments; Fig. 5 a schematic flowchart of a process for processing a layer structure, according to different embodiments; Fig. Figures 6A to 6C show different schematic views of a microelectromechanical structure according to different embodiments; and Fig. Figures 7A to 7C show different schematic views of a microelectromechanical structure, according to different embodiments.

[0017] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used with reference to the orientation of the described figure(s). Since components of embodiments can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention.It is understood that the features of the various exemplary embodiments described herein can be combined with one another, unless specifically stated otherwise. The following detailed description is therefore not to be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the appended claims.

[0018] Within the scope of this description, the terms "connected," "attached," and "coupled" are used to describe both direct and indirect connections, direct or indirect links, and direct or indirect couplings. In the figures, identical or similar elements are labeled with identical reference symbols where appropriate.

[0019] The following describes various embodiments in which a dielectric layer stack is used as an intermediate or planarizing material in the fabrication of component structures, e.g., micromechanical or microelectromechanical structures. The layer stack is configured to allow for rapid wet chemical etching. For this purpose, the layer stack can comprise at least a first layer, e.g., a liner layer, and a second layer, e.g., a cover layer. The materials of these two layers are selected such that the first layer facilitates wet chemical etching, in which the second layer also participates. According to various embodiments, the first layer can be a thin oxide liner (e.g., a TEOS (tetraethoxysilane) liner deposited by LP-CVD), and the second layer can be a so-called BPSG (borophosphosilicate glass) layer.

[0020] A BPSG layer may, for example, exhibit flow properties due to doping, allowing it to be planarized by heat treatment. This can be advantageous for some applications; for instance, it can ensure reliable contact between a layer and the BPSG layer, as described herein.

[0021] Although some embodiments described herein use a BPSG layer and an oxide liner (e.g., a USG liner or an LP-CVD-TEOS liner), which may be advantageous, other materials or material combinations can be used in a similar manner. The materials can be selected such that they exhibit different etching rates with respect to a given etching solution, with the first layer, e.g., the liner layer, having a higher etching rate than the second layer, e.g., the top layer.

[0022] According to various embodiments, the deposition of a liner layer can be conformal, i.e., the liner layer completely covers, for example, a structured substrate with a substantially uniformly thick layer.

[0023] The following describes a method for processing a layered structure, according to various embodiments, wherein this layered structure is in the Fig. 1A to 1F is illustrated in a schematic side view or cross-sectional view at different times during processing.

[0024] Fig. Figure 1A shows a layer structure 100 at the beginning 100a of the processing or before the processing, according to different embodiments.

[0025] The layer structure 100 can, for example, have a first layer 102. The first layer 102 can, for example, be any suitable layer, e.g., a metal layer, a polymer layer, a semiconductor layer, or the like. Furthermore, the first layer 102 can, for example, be any suitable layer stack 102, e.g., comprising one or more metal layers, one or more polymer layers, one or more electrically insulating layers, one or more semiconductor layers, or the like. According to various embodiments, the first layer 102 can be a single-crystal or polycrystalline semiconductor layer, e.g., a single-crystal or polycrystalline silicon layer. The first layer 102 can, for example, be freestanding or part of a support, e.g., a silicon wafer. The first layer 102 can, for example, have a layer thickness 102d in a range of approximately 0.1 µm to approximately 1 mm, e.g.,in a range of approximately 0.1 µm to approximately 2 µm, e.g. in a range of approximately 0.1 µm to approximately 0.5 µm.

[0026] According to various embodiments, the first layer 102 can be a substrate or be formed on a substrate. According to various embodiments, the first layer 102 can be a sensor layer of a sensor structure. According to various embodiments, the first layer 102 can be a diaphragm layer of a microphone structure. Furthermore, the layer structure 100 can include a sacrificial layer 104. The sacrificial layer 104 can be arranged above (e.g., directly on) the first layer 102. The sacrificial layer 104 can, for example, be deposited on the first layer 102. The sacrificial layer 104 can, for example, have a layer thickness 104d in the range of approximately 100 nm to approximately 10 µm.

[0027] Furthermore, the layer structure 100 can have a second layer 106. The second layer 106 can, for example, be any suitable layer 106, e.g., a metal layer, a polymer layer, a semiconductor layer, or the like. Furthermore, the second layer 106 can, for example, be any suitable layer stack 106, e.g., comprising one or more metal layers, one or more polymer layers, one or more electrically insulating layers, one or more semiconductor layers, or the like. According to various embodiments, the second layer 106 can be a single-crystal or polycrystalline semiconductor layer, e.g., a single-crystal or polycrystalline silicon layer. The second layer 106 can be deposited on the sacrificial layer. The second layer 106 can, for example, have a layer thickness 106d in the range of approximately 500 nm to approximately 50 µm.

[0028] According to various embodiments, the second layer 106 can be an electrode layer of a sensor structure. According to various embodiments, the second layer 106 can be an electrode layer of a microphone structure.

[0029] According to various embodiments, the sacrificial layer 104 can be configured such that it can be easily removed from between the two layers 102 and 106. For example, the sacrificial layer can comprise or consist of a material that can be easily removed by wet chemical etching; e.g., the sacrificial layer 104 can comprise or consist of an oxide, e.g., silicon oxide, e.g., LPCVD-TEOS.

[0030] To at least partially remove the sacrificial layer 104 between the two layers 102, 106, the second layer 106 can have at least one opening 106h (i.e., one or more openings 106h). The at least one opening 106h can, for example, extend from a first side 106a of the second layer 106 to a second side 106b of the second layer 106 opposite the first side 106a, e.g., to the sacrificial layer 104. Visually, the second layer 106 can be perforated or have a predefined number of through-holes 106h, corresponding to the dimensions of the cavity that is to be formed between the two layers 102, 106 by removing the sacrificial layer 104.

[0031] According to various embodiments, the two layers 102, 106 can form a micromechanical or microelectromechanical system (e.g. a sensor, e.g. a pressure sensor, e.g. a microphone, e.g. a loudspeaker, etc.) or be part of a micromechanical or microelectromechanical system (e.g. a sensor, e.g. a pressure sensor, e.g. a microphone, e.g. a loudspeaker, etc.) after at least partial removal of the sacrificial layer 104.

[0032] The layer structure 100 can be processed according to various embodiments as follows: in 100b, forming a liner layer 108 which covers at least one inner wall 106w of the at least one opening 106h (as for example in Fig. 1B is shown in a schematic side view or cross-sectional view); in 100c, forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h (as, for example, in Fig. 1C is shown in a schematic side view or cross-sectional view); and, in 110d-1 to 110d-3, wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution, wherein the etching solution has a higher etching rate for the liner layer 108 than for the top layer 110 (as, for example, in Fig. 1D, Fig. 1E and Fig. 1F is shown in a schematic side view or cross-sectional view).

[0033] The liner layer 108 can, if necessary, cover only the inner wall 106w of the at least one opening 106h, which can be achieved, for example, by means of spacer etching. According to various embodiments, the liner layer 108 can cover both the second layer 106 and, section by section, the sacrificial layer 104.

[0034] For example, in Fig. As illustrated in Figure 1B, the liner layer 108 can cover at least the inner wall 106w of the at least one opening 106h. The liner layer 108 can extend from the first side 106a of the second layer 106 to the sacrificial layer 104. The liner layer 108 can be, or become, in direct physical contact with the sacrificial layer 104. The liner layer 108 can, for example, completely line the respective opening 106h. The respective opening, or its inner wall 106w, can have any suitable shape.

[0035] According to various embodiments, the liner layer 108 can also partially or completely cover the surface of the sacrificial layer 104 exposed towards the opening 106h. Furthermore, the liner layer 108 can also partially or completely cover the first side 106a (i.e., the surface facing away from the sacrificial layer 104) of the second layer 106, as for example in Fig. 2A is shown in a schematic side view or cross-sectional view. In this case, the liner layer 108 can cover the exposed surface of the layer structure 100 as a conformal layer.

[0036] According to various embodiments, the liner layer 108 can be formed by means of a chemical or physical vapor deposition, e.g. by means of PE-CVD, SA-CVD, LP-CVD, ALD, RTO, thermal evaporation, laser deposition, cathode sputtering (also referred to as sputtering or sputter deposition), etc.

[0037] According to various embodiments, the top layer 110 can be formed over (e.g., directly on) the liner layer 108. According to various embodiments, the top layer 110 can be formed by chemical or physical vapor deposition, e.g., by PE-CVD, LP-CVD, SA-CVD, ALD, RTO, thermal evaporation, laser deposition, cathode sputtering, etc.

[0038] According to various embodiments, the remaining space in the respective opening 106h can be filled by means of the cover layer 110. Furthermore, the cover layer 110 can also be formed over the first side 106a (i.e., the surface facing away from the sacrificial layer 104) of the second layer 106 and may optionally partially or completely cover the liner layer 108 there, as for example in Fig. 1C and also in Fig. 2B is shown in a schematic side view or cross-sectional view.

[0039] According to various embodiments, the liner layer 108 can comprise an undoped oxide material, e.g., undoped silicon dioxide (also referred to as USG, "undoped silicate glass," "undoped silica glass," or "undoped silicon glass"). The cover layer 110 can, according to various embodiments, comprise a doped oxide material, e.g., doped silicon dioxide. For example, phosphorus (also referred to as PSG, "phosphosilicate glass"), boron (also referred to as BSG, "borosilicate glass"), or both (also referred to as BPSG, "borophosphosilicate glass") can be used as dopants for the silicon dioxide of the cover layer 110.

[0040] According to various embodiments, the top layer 110 can contain or consist of BPSG. After deposition, the top layer 110 can be thermally treated so that, for example, it can flow and thus be planarized. According to various embodiments, the liner layer 108 can be designed as a diffusion barrier below the top layer 110 so that, for example, one or more dopants cannot escape from the top layer 110 into the underlying layers, e.g., the second layer 106.

[0041] For example, if silicon oxide-based materials are used for the liner layer 108 and the top layer 110, the etching solution can be a hydrofluoric acid-based solution. Other materials can be used analogously with a suitable etching solution. Furthermore, the sacrificial layer 104 can consist of a silicon oxide-based material, e.g., undoped silicon oxide, so that this can be removed using the hydrofluoric acid-based etching solution. Additionally, layers 102 and 106 can consist of a material that is not substantially removed by the hydrofluoric acid-based etching solution, e.g., pure silicon.

[0042] The use of BPSG is well-established in semiconductor manufacturing. This dielectric material can fulfill a variety of functions, such as gettering mobile ions, protecting the substrate, or planarizing the surface topography. PE-CVD and SA-CVD BPSG oxides can be relatively unstable compared to thermal undoped LP-CVD oxides. However, densification and stabilization of the BPSG layer can be achieved through a curing process (also known as annealing or heat treatment) at temperatures exceeding 800°C. The liner layer 108 described herein prevents undesirable side effects such as dopant diffusion, defect formation within the BPSG layer, and / or the formation of boron- or phosphorus-induced doping profiles.

[0043] To minimize the interaction of the BPSG layer with the substrate and / or adjacent layers, the boron and phosphorus content of the layers can be precisely defined. If the defined dopant limits are not adhered to during BPSG deposition, the material can become a source of various defect formations, reducing the reliability and yield of a MEMS or other device, such as a purely electrical component. For example, process-related variations in boron and / or phosphorus content can lead to uncontrolled variations in the etch rates of the BPSG material. Furthermore, the increased diffusion tendency of introduced dopants can contribute to foreign doping of the layers or substrate beneath the BPSG if no diffusion barrier is present.This can lead to both a shift and an increased fluctuation of the electrical characteristics of the component (e.g., to an increased deviation of the pull-in voltage from wafer to wafer or lot to lot).

[0044] If, for example, a fixed-time etching process is used in the wet-chemical etching of perforated structures, an uncontrolled change in the etch rates of the dielectric BPSG material, without a correspondingly designed liner layer 108 or a correspondingly carried out procedure as described herein, leads to incomplete etching and the formation of residues that can remain on the corresponding structures (e.g. between the two layers 102, 106) and can negatively affect the integrity and reliability of the entire component.

[0045] If residues remain under the perforated counter electrode of a MEMS (e.g., under the second layer 106 with the openings 106h), these can contribute to a significant reduction in the robustness of the MEMS, as they can act as so-called hot spots where both membrane breakage and possible sticking of the two structural elements (e.g., the two layers 102, 106) are possible.

[0046] But also the formation of thin SiO x Layers or discolorations are further phenomena that lead to defect formation and thus to yield loss during the final optical inspection of the system disks. The formation of these layers is generally uncontrolled or strongly dependent on the deposition conditions of the BPSG layer, e.g., the supply and concentration of dopants. Slight variations in deposition can therefore lead to unwanted defect formation.

[0047] According to various embodiments, the aforementioned negative influences of a doped top layer 110 can be avoided or at least reduced by means of the appropriately designed liner layer 108 and the described method.

[0048] The top layer 110 could also be formed from an undoped oxide material, although this could lead to undesirable effects in the structure generation during subsequent processes (e.g., electrical contacting). According to various embodiments, it can be advantageous to form the liner layer 108 from an undoped oxide material with a small layer thickness 108d, e.g., with a layer thickness of less than 50 nm, e.g., with a layer thickness of 5 nm to 50 nm, or with a layer thickness of 10 nm to 40 nm (see, for example, [reference]). Fig. 4B). According to various embodiments, the layer thickness 108d of the liner layer 108 can be measured perpendicular to the respective surface of the substrate (e.g. the wall of the opening 106h or the top surface 106a of the second layer 106) on which the liner layer 108 is arranged.

[0049] According to various embodiments, the top layer 110 can have a greater layer thickness 110d than the liner layer 108. The layer thickness 110d of the top layer 110 can, for example, be measured perpendicular to the substrate (e.g., perpendicular to the surface of the underlying liner layer 108).

[0050] For example, in Fig. As illustrated in Figure 1D, the wet chemical etching 100d-1 can be carried out such that the liner layer 108 is completely removed from the at least one opening 106h before the cover layer 110 is completely removed from the at least one opening 106h. Visually, a channel (or gap or cavity) 108g forms along the liner layer 108, extending between the second layer 106 and the remaining section 110r of the cover layer 110 towards the sacrificial layer 104.

[0051] Through this channel 108g, the sacrificial layer 104 can already be partially removed by means of wet chemical etching 100d-2, i.e., at least one cavity 104g is formed in the sacrificial layer 104 below the opening 106h, even before the cover layer 110 is completely removed from the opening 106h, as for example in Fig. 1E is shown.

[0052] To illustrate, the sacrificial layer 104 can be at least partially removed before the cover layer 110 is completely removed from the at least one opening 106h. This facilitates or ensures the residue-free removal of the sacrificial layer 104 below the at least one opening 106h.

[0053] For example, in Fig. 1F and also in Fig. As shown in a schematic side view or cross-sectional view 2C, a cavity 104g can be formed between the two layers 102, 106 by removing the sacrificial layer 104 during wet chemical etching 100d (100d-1 to 100d-3). This exposes a surface section 102a of the first layer 102 and a surface section 106b of the second layer 106 in the area below the opening 106h or in an area below and between the multiple openings 106h.

[0054] After wet chemical etching 100d-1 to 100d-3, the liner layer 108 and the cover layer 110 can be completely removed from the at least one opening 106h. The sacrificial layer 104 can also be completely removed, at least in the area below the at least one opening 106h.

[0055] At the same time, the inner wall 106w of the respective opening 106h is or will be cleanly etched free along the sacrificial layer 104.

[0056] As previously presented and described, a method for processing the layer structure 100 may comprise: in 100b, forming a liner layer 108 which covers at least one inner wall 106w of the at least one opening 106h; in 100c, forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h; and, in 100d (or 100d-1, 100d-2, 100d-3), wet-chemical etching of the cover layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution, wherein the etching solution has a higher etching rate for the liner layer 108 than for the cover layer 110.

[0057] According to various embodiments, the method can further comprise in 100a the formation of the layer structure 100, wherein the layer structure 100 is designed as described above.

[0058] The formation of the layer structure 100 can, for example, include the following: depositing a sacrificial layer 104 over (e.g., directly onto) a first layer 102 and subsequently depositing a second layer 106 over (e.g., directly onto) the sacrificial layer 104. Furthermore, the method for forming the layer structure 100 can include structuring to form an opening 106h or several openings 106h in the second layer 106, wherein the opening(s) 106h expose the sacrificial layer 104 section by section.

[0059] According to various embodiments, the layer structure 100 can have a structural region 100s and a contact region 100k laterally adjacent to each other, so that, for example, the second layer 106 or both layers 102, 106 can be contacted laterally next to the cavity 104g created in the sacrificial layer 104. The liner layer 108 and the cover layer 110 are arranged in the contact region 100k above the second layer 106.

[0060] For example, in Fig. 2B and Fig. As shown in Figure 2c, the layer structure 100 can be structured using a mask 212, wherein the mask 212 partially covers the top layer 110 and wherein the structure area 100s is exposed for wet chemical etching 100d, as described above. According to various embodiments, the mask can be a lithographically structured lacquer layer.

[0061] Fig. Figure 3 illustrates a layer structure 100 in a schematic side or cross-sectional view after processing, according to various embodiments.

[0062] According to various embodiments, the second layer 106 can, for example, be multilayered, e.g., bilayered. The second layer 106 can comprise a first layer 306a and a second layer 306b arranged above the first layer 306a. According to various embodiments, the first layer 306a can comprise a nitride, e.g., silicon nitride. According to various embodiments, the second layer 306b can comprise a semiconducting material, e.g., silicon, GaAs, SiC, etc. The second layer 306b can have a greater thickness than the first layer 306a.

[0063] Furthermore, a protective layer 312 can be formed or created between the mask 212 and the cover layer 110. The protective layer can, for example, contain a nitride, e.g., silicon nitride.

[0064] Fig. Figure 4A illustrates a contact area 100k of the layer structure 100 in a schematic side or cross-sectional view, according to various embodiments. For example, the contact area 100k can be part of a microelectromechanical device 400.

[0065] According to various embodiments, the microelectromechanical device 400 can have a first layer 102 and a second layer 106 arranged above the first layer, wherein a cavity 104g is provided in a structural region 100s of the layer structure 100 between the two layers 102, 106, as described above. The second layer 106 can be electrically contacted in the contacting region 100k of the layer structure 100, as described above. Fig. 4A and Fig. Figure 4B illustrates this. According to various embodiments, the microelectromechanical component 400 can have a liner layer 108, which is arranged in the contact area 100k above the second layer 106. Furthermore, the microelectromechanical component 400 can have a cover layer 110, which is arranged in the contact area 100k above the liner layer 108. The configuration of the liner layer 108 and the cover layer 110 can be carried out as described above, for example.

[0066] According to various embodiments, the liner layer 108 can comprise an undoped oxide material with a layer thickness of less than 50 nm, e.g., with a layer thickness in the range of approximately 5 nm to approximately 50 nm, e.g., with a layer thickness in the range of approximately 5 nm to approximately 40 nm, e.g., with a layer thickness in the range of approximately 5 nm to approximately 30 nm. The cover layer 110 can, for example, comprise a doped oxide material. The cover layer 110 can, for example, have a greater layer thickness than the liner layer 108.

[0067] According to various embodiments, a contact hole 424 can extend through the liner layer 108 and the cover layer 110 to the second layer 106 for electrical contacting a surface section 406a of the second layer 106. According to various embodiments, the contact hole 424 can have an inner wall 424w (also referred to as side wall or inner circumferential wall) which is chamfered.

[0068] According to various embodiments, an electrically conductive diffusion barrier layer 414 can be formed, which partially or completely covers the top layer 110, the inner wall 424w of the contact hole 424, and the surface section 406a of the second layer 106. According to various embodiments, a metal layer 416 arranged above the diffusion barrier layer 414 can be used to contact the second layer 106 through the contact hole 424. Fig. Figure 4B shows a schematic detail representation of the microelectromechanical component 400 in the area of ​​the inner wall 424w of the contact hole 424, according to various embodiments.

[0069] According to various embodiments, the top layer 110 can have a chamfered side surface 110w that forms part of the contact hole 424. Furthermore, the liner layer 108 can have a side surface 108w that forms another part of the contact hole 424. Because the liner layer 108 is very thin, a tear in the diffusion barrier layer 414 in the interface 411 between the liner layer 108 and the top layer 110 at the contact hole 424 can be avoided, so that no material from the metal layer 416 arranged above the diffusion barrier layer 414 can diffuse into the second layer 106 or chemically bond with the material of the second layer 106.

[0070] The deterioration of the diffusion barrier layer 414 can be essentially prevented by the fact that etching of the cover layer 110 into the liner layer 108 can be essentially prevented or kept within an acceptable range due to the small thickness of the liner layer 108.

[0071] According to various embodiments, the second layer 106 can comprise silicon. The metal layer 416 for contacting the second layer 106 can comprise a metal (e.g., gold) that reacts with the silicon of the second layer 106 to form a metal silicide (e.g., gold silicide). The diffusion barrier layer 414 can comprise a material (e.g., titanium and / or platinum) that substantially prevents diffusion of the metal from the metal layer 416 into the second layer 106 and is chemically stable with respect to both the second layer 106 and the metal layer 416.

[0072] According to various embodiments, the liner layer 108 can have an undoped silicon oxide, as described above, and the cover layer can have a doped silicon oxide (e.g. BPSG), as described above.

[0073] The method described herein, according to various embodiments, describes a way to eliminate various reliability and defect density problems in the manufacture of both MEMS and electrical component structures.

[0074] A dielectric layer stack can be used in which an oxide liner 108 is deposited under a BPSG layer 110, the oxide liner performing, for example, both the function of a diffusion stop of possible dopants into the base substrate / device (e.g. into layers 102, 106) and the function of an etch accelerator (etch promoter) in the free etching of perforated MEMS structures 106, 106h.

[0075] According to various embodiments, optical defects (e.g., discoloration) and physical defects (e.g., residues, e.g., a SiO₂) can be eliminated (or at least reduced). x The oxide liner 108 is implemented using the oxide liner 108, which is arranged in such a way that it has virtually no negative impact on the component. The oxide liner 108 forms characteristic etched edges at contact holes or similar features.

[0076] According to various embodiments, a BPSG top layer 110 can function as an intermediate oxide or planarizing material in a component structure. The oxide liner 108 can be deposited prior to the BPSG deposition.

[0077] According to various embodiments, the first layer 102 can be a substrate, e.g. a Si substrate, a Ge substrate, a GaAs substrate, a Si / Ge substrate, a SiC substrate, a GaN substrate, or another III or V semiconductor substrate.

[0078] The deposition of the oxide liner 108 (e.g. having or consisting of an undoped oxide) takes place, for example, before the BPSG deposition with a layer thickness in a range of approximately 10 nm to approximately 300 nm, or in a range of approximately 5 nm to approximately 50 nm, or in a range of approximately 5 nm to approximately 30 nm.

[0079] The deposition (in other words, the depositing) of the BPSG (boron (B) and phosphorous (P)-doped silicon oxide (BPSG)) layer onto the liner can, for example, be carried out with a layer thickness in the range of approximately 100 nm to approximately 20 µm. After deposition of the BPSG layer, flow / annealing of the BPSG layer can occur.

[0080] According to various embodiments, the liner layer 108 and the cover layer 110 can be depositioned using CVD processes (e.g., PE-CVD, LP-CVD, SA-CVD, AP-CVD, or HDP-CVD). According to various embodiments, the liner layer 108 can comprise an undoped oxide, e.g., SiO₂. x with 0 <x≤2).

[0081] According to various embodiments, the oxide liner 108 can be a LP-CVD TEOS liner. The oxide liner 108 acts both as a diffusion barrier against typical dopants and dopant concentrations and as an etch accelerator during the free etching of perforated structures. Alternatively, a BSG or PSG can be used instead of a BPSG, with a layer thickness in the range of, for example, approximately 100 nm to approximately 20 µm.

[0082] According to various embodiments, the implementation of an oxide liner 108 and its influence on reliability and defect density are described using the example of a MEMS structure (e.g., a microphone structure). The exemplary schematic drawings provided serve only to illustrate the basic principle and show only the component structures and process steps necessary for understanding this principle. The structures depicted in the graphics are not necessarily to scale.

[0083] According to various embodiments, the use of the oxide liner 108 described herein can also be used in the manufacture of purely electrical components.

[0084] The liner layer 108 described herein, for example, has the function of preventing a possible diffusion of dopants from the cover layer 110, especially during the healing / flowing of a BPSG cover layer 110, without changing the flow properties of the BPSG.

[0085] This eliminates or at least reduces any negative influence of potentially diffusing dopants on the underlying layers or substrate (e.g., it also improves the homogeneity of electrical parameters). Furthermore, the liner layer 108, due to its higher etch rate compared to the top layer 110, effectively acts as an etch promoter. When the top layer 110 is wet-chemically etched, for example, a BPSG top layer (e.g., with an RF-based etching solution), the liner layer 108 is removed more quickly. This enables both early lateral etching of the top layer 110 and earlier etching of underlying layers (e.g., the sacrificial layer 104).

[0086] The Fig. Figures 1A to 3 each illustrate the position of the oxide liner 108 within a dielectric layer stack and its function as an etch accelerator in a wet chemical etching of BPSG and other oxides within a MEMS structure.

[0087] According to various embodiments, the liner layer 108 creates lateral and vertical access during the wet-chemical etching of perforated structures as soon as the wet-chemical etching reaches the oxide liner 108. This is caused by the increased etch rate of the liner oxide 108 compared to the cover layer 110. Thus, even perforated structures can be etched completely without residue, e.g., freed from the material of a sacrificial layer 104.

[0088] According to various embodiments, the second layer 106 forms part of a MEMS structure. For example, a section of the second layer 106 is exposed by means of the cavity 104g created below the second layer 106, with the exposed section of the second layer 106 being laterally held (in other words, clamped). Notching in the clamping area can be characteristic of the higher etch rate of the liner oxide, thereby generating lateral undercutting (below the cover layer 110).

[0089] The oxide liner 108 can, according to various embodiments, be sufficiently thick to prevent diffusion of the dopants and thus doping of underlying layers or the substrate material. The necessary thickness of the oxide liner 108 to function as a diffusion barrier generally depends on the dopant concentration of the top layer 110 (e.g., the BPSG material). With typical concentration values ​​of, for example, 5% phosphorus and 4% boron, the oxide liner 108 can have a minimum thickness of 10 nm. Simultaneously, the thickness of the oxide liner 108 supports the capillary forces acting during the etching of perforated structures.

[0090] According to various embodiments, the liner layer 108 and the top layer 110 can be produced by means of in-situ deposition, i.e., figuratively within the same coating device, wherein the undoped oxide liner 108 is deposited as USG directly before the BPSG deposition of the top layer 110 using the same method.

[0091] According to various embodiments, the oxide liner 108 can be generated directly on the substrate (e.g., a substrate or a layer) using a thermal process, e.g., oxidation of Si, provided that the necessary process temperatures are permissible for the component. Alternatively, a BSG or PSG can be used instead of a BPSG.

[0092] According to various embodiments, the liner layer 108 can be deposited using LP-CVD deposition, which, compared to methods such as PE-CVD or SA-CVD deposition, enables reproducible deposition of even very thin oxide layers, e.g. oxide layers with a layer thickness of 5 nm to 50 nm.

[0093] Alternatively or additionally to a pure oxide, other liner materials such as Si3N4 or SiON can also be used as a diffusion barrier. Layer stacks (e.g., a so-called ONO layer stack -> oxide / nitride / oxide) are also conceivable. In these cases, however, the advantage of the liner acting as a kind of etch accelerator may be reduced or even eliminated, since these materials generally have a lower etch rate in RF-based solutions.

[0094] According to various embodiments, BPSG can be produced from a mixture of oxides and hydrides of silicon (e.g., SiH4), boron (B2H6), and phosphorus (PH3) as a precursor in a CVD deposition. According to various embodiments, PSG can be produced from a mixture of POCl3, oxygen (O2), and nitrogen (N2) as a precursor in a CVD deposition. According to various embodiments, USG can be deposited by CVD at low temperatures.

[0095] According to various embodiments, an HF solution buffered with ammonium fluoride (NH4F) can be used as an etching solution to maintain consistent etching characteristics. This also prevents or reduces creep under paint masks and similar materials.

[0096] The respective etch rates of the liner layer 108 and the top layer 110 can depend, for example, on the density and stoichiometry of the oxides used. For doped oxides, the type of impurity is crucial for the etch rate. The etch rate decreases, for example, with heavy boron doping and increases, for example, with phosphorus doping. An RF-based etching solution is selective towards pure silicon, which is essentially unaffected at room temperature (e.g., 25°C). Furthermore, a chemically neutral wetting agent, such as one containing fluorocarbon compounds, can be added to the etching solution.

[0097] For example, in Fig. As illustrated in Figure 4B, the increased etch rate of the liner layer 108 leads to increased lateral undercutting in the contact area 100k and thus to the formation of negative flanks 108w in the contact hole 424. This can lead to a disruption of the (e.g., Ti / Pt) diffusion barrier 414 if the liner layer 108 is too thick (e.g., has a layer thickness of more than 50 nm). Direct contact between the metal layer 416 (e.g., the bonding metal) and the second layer 106 (e.g., made of silicon or polysilicon) then poses the risk of alloying the materials and weakening the contact area.

[0098] Fig. Figure 5 illustrates a method 500 for processing a layered structure (e.g., for processing a MEMS structure) in a schematic flowchart, according to various embodiments. The method 500 may, for example, include: in 510, forming a layered structure 100 comprising a first layer 102, a sacrificial layer 104 arranged above the first layer, and a second layer 106 arranged above the sacrificial layer, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h extending from a first side 106a of the second layer 106 to the sacrificial layer 104; in 520, forming a liner layer 108, which covers at least one inner wall 106w of the at least one opening 106h; in 530, forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h;and, in 540, wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution to form a cavity 104g between the first layer 102 and the second layer 106, wherein the etching solution has a higher etching rate for the liner layer 108 than for the top layer 110. According to various embodiments, the method 500 can be carried out as described above using the example of the layer structure 100.

[0099] The following is in the Fig. Figures 6A to 6C and 7A to 7C each illustrate a MEMS structure comprising at least one layer structure, according to various embodiments. The at least one layer structure of the respective MEMS structure can, for example, be designed and / or formed in a similar or identical manner as described above with respect to layer structure 100, and vice versa. According to various embodiments, the MEMS structure can be a microelectromechanical device, or at least part of a microelectromechanical device, e.g., in a similar manner to that described above with respect to the Fig. 4A and Fig. 4B is described.

[0100] Fig. Figure 6A illustrates a MEMS structure 600 in a schematic cross-sectional view, according to various embodiments. The MEMS structure 600 can, for example, have a layer structure 600s formed on a support substrate 620 for supporting the layer structure 600s.

[0101] The support substrate 620 can be, for example, a semiconductor wafer (e.g., a silicon wafer), a semiconductor chip (e.g., a silicon chip), or another suitable support. The support substrate 620 can, for example, have a thickness ranging from approximately 50 µm to approximately 1 mm.

[0102] The support substrate 620 can, for example, have an opening 620d above which the layer structure 600s can be arranged or formed, analogous to the preceding description. To form the layer structure 600s above the opening 620d, an auxiliary layer 610 can, for example, be used, which can be arranged between the support substrate 620 and the layer structure 600s. The auxiliary layer 610 can, for example, have a thickness in the range of approximately 100 nm to approximately 3 µm. The auxiliary layer 610 can, for example, be designed as a sacrificial layer, i.e., it can be removed at a later time, at least partially, to expose part of the layer structure 600s (see, for example, [reference]). Fig. 6B). The auxiliary layer 610 can, for example, be an oxide layer, e.g. a silicon oxide layer, e.g. an LPCVD-TEOS layer.

[0103] According to various embodiments, the layer structure 600s of the MEMS structure 600 can, for example, comprise the following: a first layer 102 (e.g., a membrane layer), a sacrificial layer 104 arranged above the first layer 102, and a second layer 106 (e.g., an electrode layer) arranged above the sacrificial layer 104. The second layer 106 can, for example, as described above, have at least one opening 106h, wherein the at least one opening 106h extends from a first side 106a of the second layer 106 to the sacrificial layer 104. Furthermore, the layer structure 600s can comprise a liner layer 108, which covers at least one inner wall 106w of the at least one opening 106h. Furthermore, the layer structure 600s can have a cover layer 110 which is arranged above the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h.According to various embodiments, the liner layer 108 can, in addition to the inner wall 106w of the at least one opening 106h, also cover the section of the sacrificial layer 104 exposed towards the opening 106h (see, for example, . Fig. 1C and Fig. 2B).

[0104] The first layer 102 of the layer structure 600s can, for example, be a membrane layer. In this case, the MEMS structure 600 can be a microphone structure or part of a microphone structure. The membrane layer can be, or become, exposed at least partially on both sides, for example, by removing the sacrificial layer 104 and the auxiliary layer 610 section by section. The cover layer 110 and the liner layer 108 can also be removed section by section, as described above.

[0105] Fig. 6B illustrates the in Fig. Figure 6A shows an exemplary schematic cross-sectional view of the MEMS structure 600, according to various embodiments, after the first layer 102 (e.g., the membrane layer) has been at least partially exposed. A cavity 104g may be formed, e.g., in a similar or identical manner to that described above. Furthermore, the auxiliary layer 610 may also be partially removed, e.g., by etching, so that at least a section of the first layer 102 is exposed on both sides.

[0106] A vibration of the membrane layer can be determined, for example, from its changes in position relative to the second layer 106. The second layer 106 can, for example, be configured as an electrode layer (also referred to as a perforated backplate), e.g., comprise an electrically conductive material. According to various embodiments, both the first layer 102 and the second layer 106 can be electrically contacted (see also Fig. 4A and Fig. 4B). In a visual representation, a capacitive microphone structure can be formed, with the first layer 102 acting as the diaphragm layer of the microphone structure.

[0107] The membrane layer 102 can, for example, have a layer thickness in a range of approximately 0.1 µm to approximately 10 µm, e.g. in a range of approximately 0.1 µm to approximately 2 µm, e.g. in a range of approximately 0.1 µm to approximately 0.5 µm.

[0108] According to various embodiments, the second layer 106 can be or become multilayered, e.g. it can have an electrically conductive layer which is arranged between two electrically insulating layers.

[0109] Fig. Figure 6C illustrates a schematic cross-sectional view of a MEMS structure 600, according to various embodiments. The respective layers 102 and 106 of the MEMS structure 600 can be electrically contacted by means of a metallization structure 600m. According to various embodiments, the first layer 102 can be contacted by means of a first contact structure 612. Furthermore, the second layer 106 can be contacted by means of a second contact structure 616.

[0110] According to various embodiments, the carrier substrate 620 can also be electrically contacted by means of a further contact structure 636.

[0111] Fig. Figure 7A illustrates a MEMS structure 700 in a schematic cross-sectional view, according to various embodiments. The MEMS structure 700 can, for example, have a layer structure 700s formed on a support substrate 720 for supporting the layer structure 700s. The support substrate 720 can, for example, be a semiconductor wafer (e.g., a silicon wafer), a semiconductor chip (e.g., a silicon chip), or another suitable support. The support substrate 720 can, for example, have a thickness in the range of approximately 50 µm to approximately 1 mm.

[0112] The carrier substrate 720 can, for example, have an opening 720d above which the layer structure 700s can be arranged or formed.

[0113] The layer structure 700s of the MEMS structure 700 can, for example, comprise the following: a first layer 102, a first sacrificial layer 104 arranged above the first layer 102, and a second layer 106 arranged above the first sacrificial layer 104, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h of the second layer 106 extending from a first side 106a of the second layer 106 to the first sacrificial layer 104. Furthermore, the layer structure 700s can comprise a first liner layer 108, which covers at least one inner wall 106w of the at least one opening 106h of the second layer 106. The layer structure 700s can also comprise a cover layer 110, which is arranged above the first liner layer 108. The top layer 110 can extend at least partially into the at least one opening 106h of the second layer 106.According to various embodiments, the first liner layer 108 can, in addition to the inner wall 106w of the at least one opening 106h of the second layer 106, also cover the section of the first sacrificial layer 104 exposed towards the opening 106h (see . Fig. 1C and Fig. 2B).

[0114] The layer structure 700s can be arranged in a mirror-symmetrical fashion with respect to its layer sequence (sacrificial layer 104 / second layer 106 / liner layer 108 / top layer 110) to the first layer 102. In other words, the layer structure 700s can additionally comprise the following: a second sacrificial layer 704 arranged below the first layer 102, a third layer 706 arranged below the second sacrificial layer 704, wherein the third layer 706 has at least one opening 706h, the opening 706h extending from a first side 706a of the third layer 706 to the second sacrificial layer 704. Furthermore, the layer structure 700s can additionally comprise a second liner layer 708, which covers at least one inner wall 706w of the opening 706h of the third layer 706.Furthermore, the layer structure 700s can additionally have a second cover layer 710, which covers the second liner layer 708 and is arranged between the support substrate 720 and the second sacrificial layer 704. The second cover layer 710 can extend at least partially into the at least one opening 706h of the third layer 706.

[0115] The second sacrificial layer 704 can be designed in the same or a similar way to the first sacrificial layer 104. Furthermore, the third layer 706 can be designed in the same or a similar way to the second layer 106. Furthermore, the second liner layer 708 can be designed in the same or a similar way to the first liner layer 108. Furthermore, the second cover layer 710 can be designed in the same or a similar way to the first cover layer 110.

[0116] The first layer 102 of the layer structure 700s can, for example, be a membrane layer. In this case, the MEMS structure 700 can be a microphone structure or part of a microphone structure after the membrane layer has been exposed, at least partially, e.g., by removing the first and second sacrificial layers 104, 704 section by section. The first and second cover layers 110, 720 and the first and second liner layers 108, 708 can also be removed section by section.

[0117] Fig. Figure 7B illustrates the MEMS structure 700 in a schematic cross-sectional view, according to various embodiments, after the first layer 102 (e.g., the membrane layer) has been at least partially exposed. A first cavity 104g and a second cavity 704g were formed, e.g., in a similar or identical manner to that described above. For example, the first sacrificial layer 104 and the second sacrificial layer 704, the first cover layer 110 and the second cover layer 720, and the first liner layer 108 and the second liner layer 708 are removed section by section, e.g., by etching, so that the first layer 102 is at least partially exposed on both sides.

[0118] A vibration of the first layer 102 (e.g., the membrane layer) can be determined, for example, from its changes in position relative to the second layer 106 and / or the third layer 706. The second layer 106 and / or the third layer 706 can be configured as electrode layers (also referred to as a perforated dual backplate). For this purpose, the first layer 102, the second layer 106, and the third layer 706 can be electrically contacted (see also Fig. 4A and Fig. 4B). A capacitive microphone structure can be visualized, with the first layer 102 serving as the diaphragm layer of the microphone structure.

[0119] The membrane layer 102 can, for example, have a layer thickness in a range of approximately 0.1 µm to approximately 10 µm, e.g. in a range of approximately 0.1 µm to approximately 2 µm, e.g. in a range of approximately 0.1 µm to approximately 0.5 µm.

[0120] According to various embodiments, the second layer 106 can be or become multilayered, e.g., it can have an electrically conductive layer arranged between two electrically insulating layers. According to various embodiments, the third layer 706 can be or become multilayered, e.g., it can have an electrically conductive layer arranged between two electrically insulating layers.

[0121] According to various embodiments, the respective layer structure 600s, 700s of the MEMS structure 600, 700 can have a structural area and a contacting area side by side, so that, for example, the respective layers 102, 106, 706 can be contacted side by side next to the cavity 104g, 704g created in the respective sacrificial layer 104, 704.

[0122] Fig.Figure 7C illustrates a schematic cross-sectional view of a MEMS structure 700, according to various embodiments. The respective layers 102, 106, and 706 of the MEMS structure 700 can be electrically contacted by means of a metallization structure 700m. According to various embodiments, the first layer 102 can be contacted by means of a first contact structure 712. Furthermore, the second layer 106 can be contacted by means of a second contact structure 716. Finally, the third layer 706 can be contacted by means of a third contact structure 726.

[0123] According to various embodiments, the carrier substrate 720 can also be electrically contacted by means of a further contact structure 736.

[0124] The following are various examples that relate to what has been described and presented above.

[0125] Example 1 is a method comprising: forming a layered structure 100 comprising a first layer 102, a sacrificial layer 104 arranged above the first layer, and a second layer 106 arranged above the sacrificial layer, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h extending from a first side 106a of the second layer 106 to the sacrificial layer 104; forming a liner layer 108, which covers at least one inner wall 106w of the at least one opening 106h; forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h;and wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution to form a cavity 104g between the first layer 102 and the second layer 106, wherein the etching solution has a higher etching rate for the liner layer 108 than for the top layer 110.;

[0126] Alternatively, Example 1 is a process for processing a carrier, comprising: forming a layered structure 100 comprising a first layer 102, a sacrificial layer 104 arranged above the first layer, and a second layer 106 arranged above the sacrificial layer, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h extending from a first side 106a of the second layer 106 to the sacrificial layer 104; covering at least one inner wall 106w of the at least one opening 106h by means of a liner layer 108; forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h;and wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution to form a cavity 104g between the first layer 102 and the second layer 106, wherein the etching solution has a higher etching rate for the liner layer 108 than for the top layer 110.;

[0127] Alternatively, Example 1 is a process for processing a carrier, comprising: forming a layer structure 100 comprising a first layer 102, a sacrificial layer 104 arranged above the first layer, and a second layer 106 arranged above the sacrificial layer, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h extending from a first side 106a of the second layer 106 to the sacrificial layer 104; depositing a liner layer 108, wherein the liner layer 108 comprises a first material and covers at least one inner wall 106w of the at least one opening 106h; depositing a cover layer 110 over the liner layer 108, wherein the cover layer 110 comprises a second material and extends at least sectionally into the at least one opening 106h;and wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 by means of an etching solution to form a cavity 104g between the first layer 102 and the second layer 106, wherein the etching solution has a higher etching rate for the first material than for the second material.;

[0128] The first layer 102 and second layer 106 of the layer structure 100 described above can, for example, be a first layer 102 and a second layer 106 of a common substrate. The first layer 102 and second layer 106 of the layer structure 100 described above can, for example, be a first layer 102 and a second layer 106 of a common MEMS structure, e.g., a microphone structure or another pressure sensor structure.

[0129] Example 1 is a method for processing a layer structure 100, wherein the layer structure 100 comprises a first layer 102, a sacrificial layer 104 arranged above the first layer 102, and a second layer 106 arranged above the sacrificial layer 104, wherein the second layer 106 has at least one opening 106h, the at least one opening 106h extending from a first side 106a of the second layer 106 to the sacrificial layer 104, wherein the method comprises: forming a liner layer 108, which covers at least one inner wall 106w of the at least one opening 106h; forming a cover layer 110 over the liner layer 108, wherein the cover layer 110 extends at least sectionally into the at least one opening 106h; and wet chemical etching of the top layer 110, the liner layer 108 and the sacrificial layer 104 using an etching solution, wherein the etching solution has a higher etching rate for the liner layer 108 than for the top layer 110.

[0130] In Example 2, the method according to Example 1 can optionally include the wet chemical etching having a complete removal of the liner layer 108 from the at least one opening 106h and an at least partial removal of the sacrificial layer 104 before the cover layer 110 is completely removed from the at least one opening 106h.

[0131] In Example 3, the method according to Example 1 or 2 may optionally include wet chemical etching that involves a complete removal of the liner layer 108 and the cover layer 110 from the at least one opening 106h, as well as a complete removal of the sacrificial layer 104 in an area below the at least one opening 106h.

[0132] In Example 4, the process according to any one of Examples 1 to 3 may optionally include the wet chemical etching forming a cavity 104g between the first layer 102 and the second layer 106, exposing a surface section 102a of the first layer 102 and a surface section 106b of the second layer 106.

[0133] In Example 5, the method according to one of Examples 1 to 4 may optionally include the formation of the liner layer 108 such that the liner layer 108 is further arranged at least sectionally above the second layer 106 in an area outside the at least one opening 106h, and wherein the formation of the cover layer 110 above the liner layer 108 is such that the cover layer 110 is arranged above the liner layer 108 in the area outside the at least one opening 106h.

[0134] In Example 6, the method according to any one of Examples 1 to 5 may optionally include that the liner layer 108 comprises an undoped oxide material, preferably undoped silicon dioxide; and that the cover layer 110 comprises a doped oxide material, preferably doped silicon dioxide.

[0135] In Example 7, the method according to any one of Examples 1 to 6 may optionally include that the cover layer 110 comprises phosphorus-doped oxide material, preferably phosphorus-doped silicon dioxide; or that the cover layer 110 comprises oxide material, preferably silicon dioxide, which is doped with boron and phosphorus.

[0136] In Example 8, the procedure according to any one of Examples 1 to 7 may optionally include that the etching solution is a hydrofluoric acid-based etching solution.

[0137] In Example 9, the method according to any one of Examples 1 to 8 may optionally include the first layer 102 and / or the second layer 106 comprising or consisting of a semiconducting material, preferably silicon.

[0138] In Example 10, the method according to one of Examples 1 to 9 can optionally include the top layer 110 having a greater layer thickness than the liner layer 108.

[0139] In Example 11, the method according to any one of Examples 1 to 10 may optionally include that the first layer 102 has or consists of single-crystal silicon and that the second layer 106 has or consists of polycrystalline silicon.

[0140] In Example 12, the method according to any one of Examples 1 to 11 may optionally include the second layer 106 having a first layer 306a and a second layer 306b arranged above the first layer 306a, wherein the first layer 306a comprises silicon nitride and wherein the second layer 306b comprises a semiconducting material, preferably silicon or polysilicon.

[0141] Example 13 is a microelectromechanical device 400 comprising: a first layer 102 and a second layer 106 arranged above the first layer 102, wherein a cavity 104g is provided between the two layers 102, 106 and wherein the second layer 106 has a contact area 100k, a liner layer 108 which is arranged in the contact area 100k above the second layer 106, wherein the liner layer 108 comprises an undoped oxide material and wherein the liner layer 108 has a layer thickness of less than 50 nm (e.g.less than 40 nm or less than 30 nm), a cover layer 110 which is arranged in the contact area 100k above the liner layer 108, wherein the cover layer 110 comprises a doped oxide material and wherein the cover layer 110 has a greater thickness than the liner layer 108, wherein a contact hole 424 extends through the liner layer 108 and the cover layer 110 to the second layer 106 for contacting a surface section 406a of the second layer 106; an electrically conductive diffusion barrier layer 414 which covers the cover layer 110, a side wall 110w, 108w of the contact hole 424 and the surface section 406a of the second layer 106; and a metal layer 416 arranged above the diffusion barrier layer 414 for contacting the second layer 106 in the contact area 100k.

[0142] In Example 14, the microelectromechanical device 400 according to Example 13 can optionally have the liner layer 108 having undoped silicon oxide and the cover layer 110 having doped silicon oxide.

[0143] In Example 15, the microelectromechanical device 400 according to Example 13 or 14 may optionally have a cover layer 110 made of silicon oxide doped with phosphorus or doped with boron and phosphorus.

[0144] In Example 16, the microelectromechanical device 400 according to one of Examples 13 to 15 can optionally have the first layer 102 and / or the second layer 106 having a semiconducting material, for example silicon.

[0145] In Example 17, the microelectromechanical device 400 according to one of Examples 13 to 16 can optionally have the first layer 102 having single-crystal silicon and the second layer 106 having polycrystalline silicon.

[0146] In Example 18, the microelectromechanical device 400 according to one of Examples 13 to 17 can optionally have the second layer 106 comprising a first layer 306a and a second layer 306b arranged above the first layer 306a, wherein the first layer 306a comprises silicon nitride and wherein the second layer 306b comprises a semiconducting material, preferably silicon.

[0147] In Example 19, the microelectromechanical device 400 according to one of Examples 13 to 18 can optionally have a surface section of the first layer 106 and a surface section of the second layer 106 exposed outside the contact area 100k. Visually, the respective exposed surface sections are not covered by solid material.

[0148] In Example 20, the microelectromechanical device 400 according to one of Examples 13 to 19 may optionally have the diffusion barrier layer 414 comprising titanium and / or platinum.

[0149] In Example 21, the microelectromechanical device 400 according to one of Examples 13 to 20 may optionally have the metal layer 416 made of gold.

[0150] In Example 22, the microelectromechanical device 400 according to one of Examples 13 to 21 can optionally have the liner layer 108 having a layer thickness of more than 5 nm, e.g. more than 10 nm.

[0151] In Example 23, the microelectromechanical device 400 according to one of Examples 13 to 22 can optionally have the cover layer 110 having a layer thickness in the range of 100 nm to 20 µm.

[0152] Example 24 is a process for processing a layer 106, comprising: forming at least one recess 106h (e.g., a blind hole or a through hole) in the layer 106; covering an inner wall 106w of the at least one recess 106h with a liner material; subsequently, filling a remaining area of ​​the at least one recess 106h with another material; completely removing the liner material and the other material by wet chemical etching of the liner material using an etching solution, wherein the etching solution has a higher etching rate for the liner material than for the other material.

[0153] In Example 25, the method according to Example 24 may optionally include the wet chemical etching having a complete removal of the liner material from the at least one recess 106h before the further material is completely removed from the at least one recess 106h.

[0154] In Example 26, the method according to Example 24 or 25 may optionally further include: covering an area of ​​layer 106 outside the at least one recess 106h at least sectionally with the liner material, and covering the liner material in the area of ​​layer 106 outside the at least one recess 106h with the additional material.

[0155] In Example 27, the method according to any one of Examples 24 to 26 may optionally include that the liner material comprises or is an undoped oxide material, preferably undoped silicon dioxide; and that the further material comprises or is a doped oxide material, preferably doped silicon dioxide.

[0156] In Example 28, the method according to any of Examples 24 to 27 may optionally include that the further material comprises or is phosphorus-doped oxide material, preferably phosphorus-doped silicon dioxide; or that the further material comprises or is oxide material, preferably silicon dioxide, which is doped with boron and phosphorus.

[0157] In Example 29, the procedure according to one of Examples 24 to 28 may optionally include that the etching solution is a hydrofluoric acid-based etching solution.

[0158] In Example 30, the method according to one of Examples 24 to 29 may optionally include layer 106 comprising or consisting of a semiconducting material, preferably silicon or polysilicon.

[0159] In Example 31, the method according to one of Examples 24 to 30 may optionally include the liner material being formed as liner layer 108 and the further material being formed as cover layer 110, the cover layer 110 having a greater layer thickness than the liner layer 108.

[0160] In Example 32, the method according to one of Examples 24 to 31 may optionally include that the layer 106 has a first layer 306a and a second layer 306b arranged above the first layer 306a, wherein the first layer 306a comprises silicon nitride and wherein the second layer 306b comprises a semiconducting material, preferably silicon.

Claims

[1] Microelectromechanical device (400) comprising: • a first layer (102) and a second layer (106) arranged above the first layer (102), wherein a cavity (104g) is provided between the two layers (102, 106) and wherein the second layer (106) has a contact area (100k), • a liner layer (108) which is arranged in the contacting area (100k) above the second layer (106), wherein the liner layer (108) comprises an undoped oxide material and wherein the liner layer (108) has a layer thickness of less than 50 nm, • a cover layer (110) which is arranged in the contact area (100k) above the liner layer (108), wherein the cover layer (110) has a doped oxide material and wherein the cover layer (110) has a greater layer thickness than the liner layer (108), • wherein a contact hole (424) extends through the liner layer (108) and the cover layer (110) to the second layer (106) to contact a surface section (406a) of the second layer (106); • an electrically conductive diffusion barrier layer (414) covering the top layer (110), a side wall (110w, 108w) of the contact hole (424) and the surface section (406a) of the second layer (106); and • a metal layer (416) arranged above the diffusion barrier layer (414) for contacting the second layer (106) in the contacting area (100k). [2] Microelectromechanical device (400) according to claim 1, wherein the liner layer (108) comprises undoped silicon oxide and wherein the cover layer (110) comprises doped silicon oxide. [3] Microelectromechanical device (400) according to claim 1 or 2, wherein the cover layer (110) comprises silicon oxide doped with phosphorus or doped with boron and phosphorus. [4] Microelectromechanical device (400) according to one of claims 1 to 3, wherein the first layer (102) comprises a semiconducting material, preferably silicon and / or wherein the second layer (106) comprises a semiconducting material, preferably silicon. [5] Microelectromechanical device (400) according to any one of claims 1 to 4, wherein the first layer (102) comprises monocrystalline silicon and wherein the second layer (106) comprises polycrystalline silicon. [6] Microelectromechanical device (400) according to any one of claims 1 to 5, wherein the second layer (106) has a first layer (306a) and a second layer (306b) arranged above the first layer (306a), wherein the first layer (306a) has silicon nitride and wherein the second layer (306b) has a semiconducting material, preferably silicon. [7] Microelectromechanical device according to any one of claims 1 to 6, wherein a surface section of the first layer (102) and a surface section of the second layer (106) are exposed outside the contacting area (100k). [8] Microelectromechanical device according to any one of claims 1 to 7, wherein the diffusion barrier layer (414) comprises titanium and / or platinum. [9] Microelectromechanical device according to any one of claims 1 to 8, wherein the metal layer (416) comprises gold. [10] Microelectromechanical device according to any one of claims 1 to 9, wherein the liner layer (108) has a layer thickness of more than 5 nm, preferably more than 10 nm. [11] Microelectromechanical device according to any one of claims 1 to 10, wherein the cover layer (110) has a layer thickness in the range of 100 nm to 20 µm.

Images