Semiconductor device and RFSOI switch

Abstract

Semiconductor device (200), comprising: a transistor gate (118) in a device layer (102); an intermediate compound layer (104) above the device layer (102), wherein the intermediate compound layer (104) comprises a local intermediate compound layer (130) above the device layer (102) and a first metal layer (132) above the local intermediate compound layer (130), wherein the local intermediate compound layer (130) comprises a first intermediate dielectric layer (134) and the first metal layer (132) comprises a second intermediate dielectric layer (136); and an air gap (288) which extends partially into the local interlayer layer (130) above the transistor gate (118), such that a section of the first interlayer dielectric layer (134) is located above the transistor gate (118) and below the air gap (288), wherein a further section of the first interlayer dielectric layer (134) is located between the air gap (288) and a conductive via (150) in the local interconnect layer (130), wherein the air gap (288) comprises sections with a first width (W1) and sections with a second width (W2) along its length dimension, which is smaller than the first width (W1), wherein the sections with the second width (W2) are arranged at contacts (150) or vias (194).

Description

Technical area

[0001] The present invention relates to semiconductor devices and RFSOI switches, and more particularly to an air gap across a transistor gate. The air gap reduces the off-state capacitance (C aus ) in applications such as radio frequency switches in semiconductor-on-insulator (SOI) substrates. State of the art

[0002] Telecommunications devices, such as smartphones, generally use radio frequency (RF) switches to route high-frequency telecommunications signals through transmission paths. For example, RF switches are commonly used in smartphones so that different wireless digital technology standards used in different geographical locations can be deployed. Current RF switches are generally manufactured using semiconductor-on-insulator (SOI) substrates. SOI substrates typically use a layered silicon-insulator-silicon substrate instead of a conventional silicon substrate (bulk substrate). SOI-based devices differ from conventional devices constructed from silicon in that the silicon interconnect is disposed over an electrical insulator, typically silicon dioxide or (less typically) sapphire.

[0003] A challenge with RF switches formed in SOI substrates is to control two competing parameters: the on-resistance (R ein ), which represents the resistance of the switch when switched on, and the capacitance in the off state (C aus ), which indicates the crosstalk or noise that may occur within the system, in particular, the amount of transmitted signals in one circuit creates an undesirable effect in another circuit. If the RF switch is to reduce power consumption, R ein be as low as possible, and C aus should be minimized to reduce unwanted coupling noise. In conventional semiconductor manufacturing processes, a reduction of R ein or C aus to opposing effects.

[0004] JP 2015-207640 A shows an electric field effect transistor and its manufacturing method, which enables the reduction of external components of the off-capacitance by comprising a semiconductor layer having a gate electrode and source and drain regions arranged thereon, contact plugs on the source and drain regions, and a first metal stacked on the contact plugs, and a low dielectric region provided below the bottom surface of the first metal in the layer stacking direction.

[0005] DE 10335101 A1 describes a method for fabricating field-effect transistors in which the gate electrode is protected during silicide formation to enable linewidth reduction; the gate electrode receives nickel silicide, while drain and source regions receive cobalt disilicide, which decouples the doping profiles of the gate and drain / source. SUMMARY

[0006] A first aspect of the invention includes a semiconductor device comprising: a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer over the transistor gate.

[0007] A second aspect of the invention relates to a radio frequency semiconductor-on-insulator (RFSOI) switch comprising: a transistor gate in a semiconductor-on-insulator (SOI) layer of an SOI substrate; an interconnect layer over the SOI layer, the interconnect layer comprising a local interconnect layer over the SOI layer and a first metal layer over the local interconnect layer; and an air gap extending through a dielectric of the interconnect layer over the transistor gate.

[0008] The foregoing and other features of the invention will become apparent from the following more particular description of embodiments of the invention. SHORT DESCRIPTION OF THE CHARACTERS

[0009] The embodiments of this invention will be described in detail with reference to the following figures, wherein like reference numerals denote like elements, and wherein: Fig. 1 shows a cross-sectional view of an embodiment of a method for manufacturing the device according to the invention. Fig. Figure 2 shows an enlarged view of an illustrative transistor gate. Fig. 3A-E show cross-sectional views of an etching of an opening according to embodiments of a method of manufacturing the device of the invention. Fig. 4 shows a cross-sectional view of removing an air gap mask according to embodiments of the invention. Fig. 5-7 show plan views of embodiments of structures manufactured by the described methods, wherein Fig. 6 shows the implementation according to the invention. Fig. 8A-C show cross-sectional views of a recessing of an opening according to one of the described methods. Fig. 9 an enlarged sectional view of a detail from the embodiment according to Fig. 8B shows. Fig. 10 shows a cross-sectional view of a semiconductor device, such as a radio frequency SOI switch with an air gap across a transistor gate thereof, according to embodiments of the invention. Fig. 11 and Fig. 12 show cross-sectional views of alternative semiconductor devices having an air gap across a transistor gate thereof according to embodiments of the invention.

[0010] The figures of the invention are not to scale. The figures are intended to illustrate only typical aspects of the invention and are therefore not intended to be limiting. In the figures, elements that are similar throughout the figures are designated by similar numbering. DETAILED DESCRIPTION

[0011] The present invention relates to semiconductor devices having an air gap across a transistor gate to reduce the capacitance between the transistor gate and adjacent wires, contacts, and vias used to contact the source and drain of the transistor. This reduction in capacitance can reduce the off-state capacitance of the transistor when used in appropriate applications, such as radio frequency (RF) switches in semiconductor-on-insulator (SOI) or bulk (non-SOI) substrates.The use of an air gap across a transistor gate according to various embodiments of the present invention provides a mechanism for reducing off-capacitance of any device using it by controlling a primary contributor to the intrinsic capacitance of the field-effect transistor (FET): the effective dielectric constant of the contact or local interconnect layer and the first metal layer. While the teachings of the invention are described with reference to a SOI substrate and relative to an RF switch, the embodiments can be applied to various alternative semiconductor devices, such as, but not limited to, low-noise amplifiers (LNAs) and power amplifiers. Furthermore, the teachings can be applied to various substrates, such as a bulk substrate.

[0012] With reference to Fig. 1 is a cross-sectional view of a first process of a method of forming an air gap for a semiconductor device according to embodiments of the invention. Fig. 1 shows a semiconductor device 100 after formation of a device layer 102 and an interconnect layer 104. The device layer 102 is illustrated as comprising a semiconductor-on-insulator (SOI) substrate 106 having thereover a semiconductor substrate 108 with an insulator layer 110 and thereover a semiconductor-on-insulator (SOI) layer 112. The substrate 108 and the SOI layer 112 may comprise, without limitation, silicon, germanium, silicon germanium, silicon carbide, and those formed essentially of one or more III-V semiconductors having a composition according to the formula Al X1 Ga X2 In X3 Ace Y1 P Y2 N Y3 Sb Y4where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportionalities that are each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 represents the total relative molar size). Other suitable materials include II-VI semiconductors with a composition of Zn A1 CD A2 See B1 The B2 , where A1, A2, B1, and B2 represent relative proportionalities that are each greater than or equal to zero and for which A1+A2+B1+B2=1 (where 1 represents a total mole size). Furthermore, a region or the entire semiconductor substrate 108 and / or the SOI layer 112 may be strained. For example, the SOI layer 112 may be strained. The SOI layer 112 may be divided by shallow trench isolations (STI) 114. The insulator layer 110 may comprise any dielectric material suitable for the desired application, e.g., silicon oxide (SiO x) or (less commonly) sapphire. The insulator layer 110 and / or the STI 114 may also comprise the same material, such as silicon dioxide or another interlayer dielectric material described herein.

[0013] Device layer 102 may also include a plurality of transistors 116 formed therein. Each transistor 116 may include a known or later developed transistor structure, such as source / drain regions (not referenced) in SOI layer 112 with a transistor gate 118 above and between them. Fig. 2 shows an enlarged cross-sectional view of an illustrative transistor gate 118. Each transistor gate 118 may include, among other things, a body 120 of polysilicon or a metal gate conductor (commonly referred to as "PC"), spacers 122 on the body 120, a gate dielectric 124 under the body 120, a silicide layer 125 over the body 120 (e.g., a silicon-to-metal interconnect), and an etch stop layer 126 over the silicide layer 125 and / or the spacers 122. The spacers 122 may comprise any semiconductor material known or later developed, such as silicon nitride (Si3N4), and the gate dielectric 124 may comprise any gate dielectric material known or later developed, such as hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiO x), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, or a combination of these materials. The etch stop layer 126 may comprise any now known or later developed etch stop material, such as silicon nitride. The silicide layer 125 may comprise any now known or later developed silicide material, such as titanium, nickel, cobalt, etc. Each transistor gate 118 may extend into the illustrated side, out of the illustrated side, or across the illustrated side.

[0014] With reference to Fig. 1, an interconnect layer 104 as described herein may include a plurality of layers including a contact or local interconnect layer 130 (commonly referred to as a contact area (CA) layer) and a first metallization layer 132. Each layer 130, 132 may include a corresponding interlayer dielectric (ILD) layer 134, 136.The ILD layers 134, 136 may include, without limitation, silicon nitride (Si3N4), silicon oxide (SiO2), fluorine-doped SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (organic silicates) comprising silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms, SiLK (polyarylene ether, available from Dow Chemical Corporation), a spin-coated polymer material comprising silicon carbon, available from JSR Corporation, or a low dielectric constant (<3.9) material, or layers thereof. Each layer 130, 132 may also include a corresponding capping layer 138, 140 on a top surface thereof. Each cap layer 138, 140 may include at least one layer, e.g., a silicon oxide layer 142 and an etch stop layer 144 made of silicon nitride (nitride), silicon carbon nitride (SiCN), etc.formed as is known in the art. Various other types of cover layers may be used. Furthermore, it should be emphasized that while the cover layers 138, 140 are illustrated as identical, they may comprise different materials, thicknesses, etc.

[0015] A plurality of contacts 150 may extend through the ILD layer 134 or the contact layer or local interconnect layer 130 (hereinafter referred to as "local interconnect layer 130") to various parts of the device layer 102. In the illustrated example, the contacts 150 extend to source / drain regions of the transistor 116. Each contact 150 may comprise a conductor, such as aluminum or copper, within a thin reflow metal layer of ruthenium; however, other reflow metals may also be used, such as tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), etc., or mixtures thereof. Typically, the contacts 150 extend mostly vertically within the semiconductor device 100 to connect the conductors in the layers, in particular vertically on the side, as illustrated. The first metal layer 132 may include a plurality of metal wires 152 therein.Each metal wire 152 may use the same materials listed for the contacts 150. Unlike the contacts 150, the metal wires 152 most often extend horizontally or laterally in a layer within the semiconductor device 100 to connect the contacts 150 therein, particularly in, out, or along a side, as illustrated. In this way, the first metal layer 132 may include a metal wire 152 extending laterally parallel to the transistor gate 118 in the device layer 102, particularly vertically across, but parallel to, the transistor gate 118. The semiconductor device 100, as shown in FIG. Fig. 1 can be formed using any known or later developed semiconductor manufacturing techniques, such as material deposition, photolithographic patterning and etching, doping, etc. Although in Fig. 1 contacts 150 and wires 152 are shown as single damascene levels, they could be formed using dual damascene levels comprising a thin reflow metal layer of copper or tungsten, as is known in the art.

[0016] "Deposition" or "deposition" as used herein may represent any known or later developed techniques suitable for the material to be deposited, including, but not limited to: chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma assisted CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputter deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitriding, spin-on deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, evaporation.

[0017] Fig. 1 also shows forming an air gap mask 160 exposing a portion 162 of the interconnect layer 140 above the device layer 102. The mask 160 may be formed, for example, after a damascene planarization of the first metal layer 132, such as by chemical mechanical polishing (CMP), and may comprise any known or later developed masking material. The mask 160 is patterned and etched in a conventional manner to create openings 164 therein. In one embodiment, a width of the transistor gate 120 may be approximately 200 nm, and openings 164 in the air gap mask 160 may have a size of approximately 0.16 micrometers (µm) to 0.24 µm, in particular 0.2 µm. These widths could scale with larger and smaller channel transistor widths or with larger or smaller widths of contacts 150 and wires 152.

[0018] The Fig. 3A-E show etching of an opening 166 through the interconnect layer 104 using the air gap mask 160 over the transistor gate 118. The opening 166 exposes sidewalls 170 of a dielectric 134, 136 of the interconnect layer 104. Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place so that material from certain areas of the substrate can be selectively removed while leaving the material in other areas of the substrate unaffected. Etching generally falls into two categories: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (such as an acid or a base) selected for its ability to selectively dissolve a given material (such as an oxide) while dissolving another material (such asPolysilicon or nitride) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor manufacturing processes. Generally, a homogeneous material (e.g., an oxide) is etched isotropically by wet etching, but a crystalline material (e.g., a silicon wafer) can also be etched anisotropically by wet etching. Dry etching can be performed using a plasma. Plasma systems can operate in different modes by adjusting the plasma parameters. Conventional plasma etching generates energetic free radicals that are neutrally charged, which react with the wafer surface. Because neutral particles attack the wafer from all angles, this process is isotropic. In ion etching, or sputter etching, the wafer is bombarded with energetic noble gas ions that approach the wafer from approximately one direction, and consequently, this process is highly anisotropic.Reactive ion etching (RIE) operates under conditions intermediate between sputtering and plasma etching and can be used to create deep, narrow features, such as STI trenches. In the . Fig. 3A-E can etch (only in Fig. 3A with arrows). With reference to the opening 116 and / or any air gap formed therein, "over the transistor gate" means that the transistor gate 118 is arbitrarily overlaid.

[0019] According to the representations of the Fig. 3A-E, the opening 166 may extend above the transistor gate 118 to a variety of different depths. With respect to the depth of the opening 166, the etching of the opening 166 may terminate when: the opening 166 reaches or extends to the etch stop layer 126 ( Fig. 3A); the etch stop layer 126 is excluded ( Fig. 3B); the etch stop layer 126 is removed (the etching extends beyond it), exposing the silicide layer 125 ( Fig. 3C); the body 120 is exposed ( Fig. 3D), such as when the silicide layer 125 is not present or has been completely removed; or the etch stop layer 126 is not exposed, but does not extend through the dielectric layer 134 above the gate 118 ( Fig. 3E). Accordingly, the etching of the Fig. 3A-E to select the degree to which a top surface 168 of the transistor gate 118 is exposed.

[0020] Fig. 4 shows the semiconductor device after removal of the air gap mask 160 (in the embodiment of Fig. 3B merely for clarity). The air gap mask 160 ( Fig. 3A-E) can be removed using any known or later developed lacquer stripper, in-situ or ex-situ.

[0021] The Fig. 5-7 show a plan view or top view of embodiments of the structure after processing according to Fig. 4, in particular partly by the described methods. Fig. 5-7 show exemplary layouts of the openings 166 and consequently of the air gaps 188 to be formed thereby ( Fig. 10) as described herein. The cross sections of the Fig. 5-7 pass through the dielectric 134 in Fig. 4. The Fig. 5-7 show the SOI layer 112 (active region) with gates 118 formed thereover with contacts 150 extending from the gate 118 and the SOI layer 112. Metal wires 152 are shown connected to certain contacts 150 above the SOI layer 112. The metal wires 152 are shown running parallel to certain gates, labeled 118A. As shown, the openings 166 can take a variety of shapes. In Fig. 5, the openings 166 above the transistor gate 118 are etched as laterally extended openings. That is, the openings 166 have a length, for example, slightly shorter than a transistor gate 118 to which they are parallel, as opposed to simple vertical openings. In one embodiment, a portion of the opening 166 may be etched in a laterally arranged T-shape 174, in particular in a T-shape laid out horizontally in the plane of the side, although this is not required. In any case, the openings 166 do not expose the contacts 150 or metal wires 152; in particular, a portion of the dielectric 134, 136 ( Fig. 4) between the contacts 150 and the wires 152 and the openings 166. In Fig. 6, the openings 166 through the interconnect layer 104 are designed according to the invention such that they are formed at the contacts 150 (or following the formation of vias 194 ( Fig. 10-12)) are closer together to reduce the probability of a contact 150 crossing an air gap 188 ( Fig. 10). That is, the opening 166 can be connected to a contact 150 (or a via 194 ( Fig. 10-12)) should be narrower laterally (width W2) and between the contacts 150 (or through-plating 194 ( Fig. 10-12)) may be wider laterally (width W1) to reduce the likelihood of contact 150 (or via 194) being exposed by air gap 188, which would allow filling of air gap 188 with a conductor. Consequently, air gap 188 ( Fig. 10-12) have the same layout, especially as in Fig. 6, wherein a first width W2 is present laterally at a contact 150 (or a via 194) and a second width W1, which is wider than the first width W2, is present laterally between the contacts 150 (or vias 194). The variable width may occur in the local interconnect layer 130 and / or the first metal layer 134 and / or subsequent layers 190 ( Fig. 10-12). In particular, the air gap 188 would have a similar width variation whether viewed through the local interconnect layer 130, the first metal layer 132, or a subsequent air gap cap layer 190 ( Fig. 10-12). Fig. 7, openings 166 can be etched as many, not necessarily elongated, unconnected openings. In Fig. 7, some openings 166 are designed such that they are not located near the contact 150 (or subsequently formed vias 194 ( Fig. 10-12)) to reduce the likelihood of the contact 150 or the vias 194 crossing an air gap 188 ( Fig. 8A-C), which would allow the air gap 188 to be filled with a conductor. By selecting from the various lengths of the opening 166 provided in the Fig. 5-7, one can finally see air gaps 188 ( Fig. 10) that measure the on-resistance and off-capacitance of a semiconductor device 200 ( Fig. 10) by reducing an effective dielectric constant for the interconnect layer 104 and avoid short circuits through openings 166 that have a contact 150, a via 194 ( Fig. 10-12) or a wire 152. The air gap openings 166 can also be formed with different widths, as in Fig. 6. For example, the width of the air gap opening 166 may be reduced in width near the contacts 150 or vias 194 to reduce the likelihood of the air gap 188 crossing the contacts or vias due to misalignment.

[0022] The Fig. 8A-C show an optimal recession of exposed sidewalls 170 of the dielectric 134, 136 of the interconnect layer 104 in the opening 166. Among other advantages, the recession of the sidewalls 170 serves to enlarge the opening 166 and consequently the air gaps 188 ( Fig. 10), whereby the effective dielectric constant of the interconnect layer 104 is reduced, while the upper opening of the air gap to be closed in the next process step is narrower than the air gap itself. If silicon oxide films are used for local interconnect and first metal layers 130, 132 and silicon nitride is used for a cap layer (or cap layers) 138, 140, then this recess (for the sake of brevity only in Fig. 3A with arrows), a wet etch with hydrofluoric acid (HF) may be used. HF concentrations could range from a 10:1 to 500:1 dilution with water, as is known in the art. Since the dielectrics of layers 130 and 132 are etched faster than the dielectric of the cap layer(s) 138, 140 ( Fig. 1), shows Fig. 9 that opening widths BB and CC are wider than an upper opening AA of the air gap. The recess may, for example, comprise a wet etch as described elsewhere herein. In one embodiment, recessing exposed sidewalls 170 of the dielectric 134, 136 of the interconnect layer 104 in the opening 166 may form an edge 180, 182 of the local interconnect cap layer 130 and / or the first metal cap layer 132 in the opening 166 as shown in FIGS. Fig. 8A-C. The edges 182 assist in closing the opening 166 to form an air gap, for example, by facilitating the pinching off of the opening 166.

[0023] According to the presentation in the Fig. 8A-C, the recessing in this phase can also be used to further deepen the opening 166. For example, if it is assumed that the recessing is carried out after removal of the air gap mask 160 in Fig. 4 occurs, but can be used in the embodiment of the Fig. 3E, in which the dielectric layer 134 remains over the transistor gate 118, a recess as shown in the Fig. 8A-C, the opening 166 may further deepen to each of the depths shown in the Fig. 3A-E. For example, where the opening 166 has not extended through the dielectric layer 134 to reach or contact the etch stop layer 126, a recess may thereby lengthen the opening 166 ( Fig. 8A, left side). Similarly, a recess could lengthen the opening 166 so that the etch stop layer 126 ( Fig. 8A, right side) or the silicide 125 ( Fig. 8B, left side) or the body 120 ( Fig. 8B, right side). Furthermore, a cutout could extend the opening 166 further into the dielectric layer 134, but not expose the gate 118 ( Fig. 8C). In this way, a degree to which the transistor gate 118 is exposed to an air gap 188 formed by the opening 166 ( Fig. 10), in addition to the etching of the Fig. 3A-E provided control can be precisely adjusted.

[0024] Fig. 10 shows forming an air gap 188 over the transistor gate 118 by depositing an air gap cap layer 190 to close the opening 166 ( Fig. 9) on a surface of the interconnect layer 104. As shown, the air gap 118 is vertically aligned with the transistor gate 118, although perfect alignment is not required. The air gap capping layer 190 may comprise any dielectric material capable of closing the opening 166 and serving as an ILD for a first via layer (not shown) to be formed therein. In one embodiment, the air gap capping layer 190 may comprise a dielectric deposited by chemical vapor deposition (CVD). In another embodiment, the air gap capping layer 190 may comprise a silane oxide deposited by plasma enhanced chemical vapor deposition (PECVD). PECVD silane oxide may be chosen because it has poor step coverage, resulting in a larger air gap volume.In other embodiments, the air gap cap layer 190 may comprise a thin silicon nitride layer with an ILD oxide, such as TEOS based on PECVD, PVD, or a similar oxide (individual layers are not shown for brevity). Edges 182 of the first metal cap layer 140 (. Fig. 1) of the first metal layer 132 serve to pinch off the opening 166 to assist in closing the air gap 188. The air gap 188 does not expose any contact 150 or any metal wire 152; in particular, the dielectric 134, 136 of the interconnect layer 140 at the air gap 188 covers any conductive wire 152 in the first metal layer 132 or any conductive contact 150 in the local interconnect layer 130. The air gap 188 may have any of the lateral layouts of the opening 166, as shown in FIGS. Fig. 5-7. The first metal layer 132 may further include a metal wire 152 ( Fig. 10) located in the device layer 102 laterally parallel to the transistor gate 118 (cf. Fig. 5-7). According to the illustration in Fig. 10, the air gap 188 extends vertically above and below the metal wire 152, in particular below the dielectric 132 of the first metal layer 32 and above the metal wire 152 in the cover layer 190. The air gap 188 extends above a top surface of the first metal layer 132. As also in Fig. 10, the air gap 188 may extend only partially into the air gap cover layer 190, so that the layer 190 may serve as a first via layer ILD that is minimally affected by the air gap 88. Vias 194 to another metal layer (not shown) may be formed in the air gap cover layer 190 using a conventional or later developed technique. As shown only in the right side of Fig. 10, a thin layer 192 of the air gap cover layer 190 can selectively cover the transistor gate 118 in the opening 116, thus providing additional control over the extent to which the transistor device 118 is exposed to the air gap 188. The air gap cover layer 190 closes the opening 166 regardless of the lateral layout it may have according to the Fig. 5-7, for example, elongated or a non-elongated narrow opening, with a T-shape or with varying width ( Fig. 6). The lateral formation of the opening 166 (with respect to the Fig. 5-7) can be controlled to prevent it from being exposed by subsequently formed vias 194. This prevents a conductor of the vias 194 from entering the air gap 188.

[0025] In the Fig. 11 and Fig. 12 shows alternative air gap embodiments. Fig. 11 shows an air gap 288 which has a smaller etching depth ( Fig. 3A-E) to avoid touching the transistor gate 118. Fig. Figure 12 shows an air gap 388 in which the recess etching formed in the Fig. 8A-C. This structure has a smaller air gap 388 than in Fig. 11, however, avoids exposing the dielectric of the local interconnect layer 130 and the first metal layer 132 to the etchant.

[0026] With reference to the Fig. 10-12 also illustrates a semiconductor device 200 according to embodiments of the invention. In one embodiment, semiconductor device 200 may include transistor gate 118 in device layer 102. Transistor gate 118 may include a body 120, a silicide layer 125 over body 120, and an etch stop layer 126 over silicide layer 125. Transistor 166 may take any known form or later developed form in the field of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). Semiconductor device 200 may also include interconnect layer 104 over device layer 102. The interconnect layer 104 may include at least one interconnect layer, e.g., the local interconnect layer 130 and the first metal layer 132. The semiconductor device 200 also includes the air gap 188 extending through the interconnect layer 104 above the transistor gate 118.As described, the degree to which the transistor gate 118, particularly the top surface 168 thereof, is exposed and / or which portion of the gate 118 is exposed to the air gap 118 can be controlled by the etching, recessing, and capping processes. It is understood that the air gap 118 can be formed with any embodiment of the provided opening 166. That is, the air gap 118 can include the etch stop layer 126 (left side in FIG. Fig. 10) or extend thereto; extend into the etch stop layer 126 (cf. Fig. 3B, Fig. 4 and Fig. 8A, right side), leaving the silicide layer 125 unexposed; remove the etch stop layer 126 (and perhaps portions of the spacers 122) that expose the silicide layer 125 ( Fig. 3C, left side of Fig. 8B); a region of the body 120 ( Fig. 3D, right side of Fig. 8B) if the silicide layer 125 is not present or has been completely removed; extend to the thin layer 192 of the cap layer 190 or the dielectric layer 134 above the transistor gate 118 if a thin layer 192 of the cap layer 190 is present in the opening 166 (right side of Fig. 10) or the opening 166 does not extend through the dielectric layer 134 ( Fig. 3E, Fig. 8C and Fig. 11). Accordingly, an air gap above the transistor gate 118 may contact the dielectric, such as the dielectric layer 134 or the thin layer 192 of the cap layer 190, contact the etch stop layer 126 (either fully or partially), contact the silicide layer 125 or the body 120 of the transistor gate 118. In any case, the dielectric 124, 136 of the interconnect layer 104 covers each conductor at the air gap 188, for example, each conductor wire 152 in the first metal layer 132 or each conductive contact 150 in the local interconnect layer 130. The edges 180 and / or 182 of at least one of the local interconnect cap layer 138 and the first metal cap layer 140 may extend into the air gap 188. As shown in Fig. 9, the first metal cover layer 140 may have a width AA in the air gap (where the opening 166 in Fig. 9) which is smaller than a width BB of the air gap (where the opening 166 in Fig. 9) in the dielectric 136 of the first metal layer 132 beneath the first metal cap layer 140. As such, the edges 182 of the first metal cap layer 140 are intended to pinch off the dielectric 190, thereby allowing a smaller amount of the dielectric 190 to close the opening 166.

[0027] At least a portion of the etch stop layer 126 of the transistor gate 118 may be excluded ( Fig. 4 and Fig. 8). In one embodiment, the air gap 188 may have an aspect ratio greater than about 3 to 1, for example, 4 to 1. In one embodiment, the air gap 188 may have a width of about 1-2 µm and a height of about 8-10 µm. As shown in Fig. 5, the air gap 188 may have a laterally extended or T-shaped opening 166 used to form it.

[0028] The semiconductor device 200 can be used to form a variety of devices, such as a radio frequency semiconductor-on-insulator (RFSOI) switch, a low-amplitude amplifier, a power amplifier, etc. The use of the air gap 188, 288, or 388 above the transistor gate 118 according to the various embodiments of the invention provides a mechanism for reducing the off-capacitance of a device using it by controlling at least a portion of the intrinsic FET capacitance: the effective dielectric constant of the local interconnect layer 130 and the first metal layer 132. In one example, a reduction in the off-capacitance between approximately 15-60% was observed, with an effective dielectric constant of the interconnect layer 104 reduced from approximately 4 to 2 using the air gap 188, 288, or 388.

[0029] The process described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of unfinished wafers (in particular, a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chip is mounted on a single chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier having either single- or double-sided surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end devices to advanced computer products with a display, keyboard or other input device, and a central processor.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms "a," "an," "an," and "the" are intended to include the plural forms unless otherwise indicated. The terms "comprises" and / or "comprising" specify the presence of the indicated features, numbers, steps, operations, elements, and / or components as used in this description, but are intended to exclude the presence or addition of at least one other feature, number, step, operation, element, component, and / or groups thereof. "Optional" means that the event or circumstance described below may or may not occur, and the description includes instances where the event occurs and describes instances where it does not occur.

[0031] The approximate language used herein in the description and claims may modify any quantitative representation, which may vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by a phrase or phrases such as "approximately" and "substantially" should not be considered limited to the specific, precise value. In at least some cases, the approximate language may correspond to the accuracy of an instrument for measuring the value. Here and in the description and claims, range limits may be combined and / or interchanged. Corresponding ranges are identified to include all subranges contained therein unless the context or language indicates otherwise."Approximately", as applied to a specific value within a range, applies to both values ​​and, unless otherwise dependent upon the accuracy of the instrument measuring the value, may indicate + / - 10% of the stated value(s).

[0032] The corresponding structures, materials, acts, and equivalents of all means-plus-function or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements that are specifically claimed.

Claims

[1] A semiconductor device (200) comprising: a transistor gate (118) in a device layer (102); an interconnect layer (104) over the device layer (102), the interconnect layer (104) comprising a local interconnect layer (130) over the device layer (102) and a first metal layer (132) over the local interconnect layer (130), the local interconnect layer (130) comprising a first interlayer dielectric layer (134) and the first metal layer (132) comprising a second interlayer dielectric layer (136); and an air gap (288) extending partially into the local interconnect layer (130) above the transistor gate (118) such that a portion of the first interlayer dielectric layer (134) is located above the transistor gate (118) and below the air gap (288), wherein a further portion of the first interlayer dielectric layer (134) is located between the air gap (288) and a conductive via (150) in the local interconnect layer (130), the air gap (288) comprising, along its length dimension, portions having a first width (W1) and portions having a second width (W2) that is smaller than the first width (W1), the portions having the second width (W2) being arranged on contacts (150) or vias (194). [2] The semiconductor device (200) of claim 1, wherein a portion of the second interlayer dielectric layer (136) is located between the air gap (288) and a conductive wire (152) in the first metal layer (132). [3] The semiconductor device (200) of claim 1, wherein the first metal layer (132) comprises a metal wire (152) extending laterally parallel to the transistor gate (118) in the device layer (102), and wherein the air gap (288) extends vertically above and below the metal wire (152). [4] The semiconductor device (200) of claim 1, wherein the air gap (288) extends vertically only partially into an air gap cap layer (190) above the first metal layer (132). [5] The semiconductor device (200) of claim 4, wherein the air gap cap layer (190) comprises a chemical vapor deposition dielectric. [6] The semiconductor device (200) of claim 5, wherein the chemical vapor deposition dielectric comprises a plasma-assisted chemical vapor deposition silicon oxide. [7] The semiconductor device (200) of claim 1, wherein the transistor gate (118) comprises a body (120), a silicide layer (125) over the body (120), and an etch stop layer (126) over the silicide layer (125). [8] RFSOI switch, comprising: a transistor gate (118) in an SOI layer (112) of an SOI substrate (106); an interconnect layer (104) over the SOI layer (106), wherein the interconnect layer (104) comprises a local interconnect layer (130) over the SOI layer (106) and a first metal layer (132) over the local interconnect layer (130), wherein the local interconnect layer (130) comprises a first interlayer dielectric layer (134) and the first metal layer (132) comprises a second interlayer dielectric layer (136); and an air gap (288) extending partially into the local interconnect layer (130) above the transistor gate (118) such that a portion of the first interlayer dielectric layer (134) is located above the transistor gate (118) and below the air gap (288), wherein a further portion of the first interlayer dielectric layer (134) is located between the air gap (288) and a conductive via (150) in the local interconnect layer (130), the air gap (288) comprising, along its length dimension, portions having a first width (W1) and portions having a second width (W2) that is smaller than the first width (W1), the portions having the second width (W2) being arranged on contacts (150) or vias (194). [9] The RFSOI switch of claim 8, wherein a portion of the second interlayer dielectric layer (136) is located between the air gap (288) and a conductive wire (152) in the first metal layer (132). [10] The RFSOI switch of claim 8, wherein the transistor gate (118) comprises a body (120), a silicide layer (125) over the body (120), and an etch stop layer (126) over the silicide layer (125). [11] The RFSOI switch of claim 8, wherein the air gap (288) extends vertically only partially into an air gap cap layer (190) above the first metal layer (132).

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