DEVICE AND METHOD FOR SINGLE-PHASE SPOT CIRCUITS

Abstract

Spot splitter (100), which has the following features: two or more spot circuits electrically connected in a ring, and a first single-phase spot circuit (104) having a spot input (YOUR), a spot output (OFF) and a clock input (CLKB), wherein the first single-phase spot circuit (104) has the following: a first input field-effect transistor (FET) (202) with a first polarity, which is electrically connected between a first supply node (VDD) and a signal node (V1), wherein a gate electrode of the first FET (202) is electrically connected to the spot input (DEIN), a first clock FET (206) with a second polarity opposite to the first polarity, a second input FET (212) with the second polarity, which is electrically connected in series with the first clock FET (206) between the signal node (V1) and a second supply node (VSS), a second clock FET (204) with the first polarity, wherein a gate electrode of the first clock FET (206) and a gate electrode of the second clock FET (204) are electrically connected to the clock input (CLKB), and an output FET (208) of the first polarity, which is electrically connected in series with the second clock FET (204) between the first supply node (VDD) and the spot output (OFF), wherein a gate electrode of the output FET (208) is electrically connected to the signal node (V1), wherein the first single-phase spot circuit (104) further comprises at least one of a reset input (RST) or a set input (SB) designed to initialize a state of the first single-phase spot circuit (104).

Description

BACKGROUND area

[0001] Embodiments of the invention relate to electronic circuits and in particular to spot circuits. Description of the state of the art

[0002] A spot circuit or spot motion stage can be used in a wide variety of applications.

[0003] In one example, a frequency divider comprises spot circuits electrically connected in a ring, and the frequency divider is used to divide an input clock signal to generate an output clock signal. Each spot circuit is capable of passing or moving a spot, which can be represented using a logical one or zero, to the next spot circuit in the ring. The spot advances from one spot circuit to the next based on the timing of the input clock signal, and the output clock signal is generated based on the time it takes for the spot to move around the ring.

[0004] The frequency divider, in turn, can be used in a wide variety of applications, such as phase-locked loops (PLLs) or frequency synthesizers. For example, a PLL can use the frequency divider to divide the output of a controllable oscillator to generate a feedback clock signal used by a phase-locked frequency detector (PFD).

[0005] The paper by Elgamel, M. et al., "Noise tolerant low-power dynamic TSPCL D flip-flops" in "Proceedings IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design," ISVLSI 2002, Pittsburgh, PA, USA, 2002, pages 89–94, concerns the use of dynamic switching techniques in D flip-flops to achieve higher performance, particularly in microprocessors. With the transition to deep submicron technologies, noise immunity is becoming as important as power, speed, and area. The authors propose a method to reduce power consumption in TSPCL D flip-flops by reducing the switching activity of some internal nodes. Simulations show that the modified flip-flop achieves a power reduction of 4.6% to 80%, depending on the input pattern and the technology used. However, the modified flip-flop is more susceptible to noise, so a well-known noise immunization technique should be applied.Finally, the work shows that despite the lower noise immunity of the modified flip-flops, a significant reduction in energy consumption can be achieved.

[0006] US 9 013 213 B2 relates to a digital fractional frequency divider for fractionally dividing a digital frequency signal, comprising a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. Each of the clock division counter modules can receive an input clock signal that is phase-shifted from the remaining input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can be coupled to an output of one of the clock division counter modules and generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

[0007] The October 2014 publication by Andersson, NU et al., "A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture" in "IEEE Transactions on Circuits and Systems II: Express Briefs," Volume 61, Number 10, pages 773–777, describes a new Vernier time-to-digital converter (TDC) architecture that uses a delay line and a delay latch chain. This architecture replaces the usual second delay chain and sample register, resulting in improvements in power and hardware efficiency. A 7-bit Vernier TDC is implemented in a 65 nm CMOS process and achieves a timing resolution of 5.7 ps at a power consumption of 1.75 mW. The architecture can be implemented with both standard digital cells and fully custom cells and is suitable for FPGA implementations or digital application-specific integrated circuits.Measurements show that the TDC architecture offers competitive performance in terms of area and power consumption compared to recently released TDCs. SUMMARY

[0008] According to one aspect, a spot splitter is provided. The spot splitter comprises two or more spot circuits electrically connected in a ring, each of which includes a first single-phase spot circuit having a spot input, a spot output, and a clock input. The first single-phase spot circuit includes a first input field-effect transistor (FET) of a first polarity electrically connected between a first supply node and a signal node, with a gate electrode of the first FET electrically connected to the spot input.The first single-phase spot circuit further includes: a first clock FET having a second polarity opposite to the first polarity; a second input FET having the second polarity electrically connected in series with the first clock FET between the signal node and a second supply node; a second clock FET having the first polarity; and an output FET having the first polarity electrically connected in series with the second clock FET between the first supply node and the spot output. Additionally, a gate electrode of the first clock FET and a gate electrode of the second clock FET are electrically connected to the clock input, and a gate electrode of the output FET is electrically connected to the signal node.

[0009] In certain implementations, the first single-phase spot circuit further comprises a second type feedback FET having a gate electrode electrically connected to the spot output, a drain electrode electrically connected to the spot input, and a source electrode electrically connected to the second supply node.

[0010] In certain implementations, the clock input is configured to receive a clock signal, where, when a spot is present at the spot input, the first single-phase spot circuit holds the spot for approximately one cycle of the clock signal.

[0011] In a number of implementations, the two or more spot circuits advance a spot around the ring using only a single clock signal phase.

[0012] In various implementations, the first polarity is p-type and the second polarity is n-type. In some implementations, the clock input is configured to receive a clock signal, and when the spot input is logic high, the first single-phase spot circuit is configured to drive the spot output to a logic high state in response to a falling edge of the clock signal. According to a number of implementations, if the spot input is logic low, the first single-phase spot circuit does not drive the spot output, regardless of the state of the clock signal.

[0013] In certain implementations, the first polarity is n-type and the second polarity is p-type. In a number of implementations, the clock input is configured to receive a clock signal, and when the spot input is logic low, the first single-phase spot circuit is configured to drive the spot output to a logic low state in response to a rising edge of the clock signal.

[0014] According to various implementations, the two or more spot circuits electrically connected in the ring comprise at least three single-phase spot circuits.

[0015] In some implementations, the spot splitter further includes a spot removal circuit having a spot input electrically connected to the spot output of the first single-phase spot circuit and a spot output that selectively provides a spot from the ring to a splitter output. According to certain implementations, the spot splitter further includes an outer splitter circuit configured to control the timing at which the spot removal circuit provides the spot from the ring to the splitter output. In a number of implementations, the outer splitter circuit includes two or more outer spot circuits electrically connected in a cascade.

[0016] In various implementations, the first single-phase spot circuit further comprises at least one of a reset input or a set input configured to initialize a state of the first single-phase spot circuit.

[0017] In another aspect, a time-to-digital converter is provided. The time-to-digital converter comprises two or more spot circuits electrically connected in a cascade, each comprising a first single-phase spot circuit having a spot input, a spot output, and a clock input. The first single-phase spot circuit comprises a first input FET having a first polarity electrically connected between a first supply node and a signal node, wherein a gate electrode of the first FET is electrically connected to the spot input.The first single-phase spot circuit further includes a clock FET having a second polarity opposite to the first polarity, electrically connected to the clock input, a second input FET having the second polarity, electrically connected in series with the clock FET between the signal node and a second supply node, and an output FET having the first polarity, electrically connected between the first supply node and the spot output. Additionally, a gate electrode of the output FET is electrically connected to the signal node.

[0018] In some implementations, the clock input is configured to receive a pulse signal, and the two or more spot circuits are configured to advance a spot signal in response to a first edge of the pulse signal and to stop advancing the spot signal in response to a second edge of the pulse signal.

[0019] In a number of implementations, the first single-phase spot circuit further comprises a buffered output FET of the first polarity having a gate electrode electrically connected to the signal node and a drain electrode electrically connected to a buffered output.

[0020] In various implementations, the first single-phase spot circuit further comprises a read FET having the first polarity electrically connected in series with the buffered output FET between the first supply node and the buffered output, the buffered output FET having a gate electrode receiving a read signal configured to prevent the buffered output from changing state when a spot signal advances from the spot input to the spot output.

[0021] In another aspect, a method for moving a spot using a single-phase clock signal phase is provided. The method comprises providing a spot signal to a spot input of a single-phase spot circuit; providing a single-phase clock signal varying between a first logic voltage and a second logic voltage to a clock input of the single-phase spot circuit; blocking transmission of the spot signal to a spot output of the single-phase spot circuit when the spot signal has the first logic voltage; and transmitting the spot signal to the spot output of the single-phase spot circuit in response to a clock edge of the single-phase clock signal when the spot input has the second logic voltage.

[0022] In some implementations, the method further comprises: driving the spot input of the single-phase spot circuit to the first logic voltage during a clock cycle of the clock edge after the spot signal is transferred to the spot output.

[0023] In another aspect, an electronic circuit is provided. The electronic circuit includes a plurality of spot movement stages configured to move a spot represented by a logic high value based on the timing of a single-phase clock signal. The plurality of spot movement stages includes a first spot movement stage and a second spot movement stage. The first spot movement stage includes a first spot input, a first spot output, and a first number of FETs configured to selectively control the first spot output based on a logic value of the first spot input and the timing of the single-phase clock signal.The second spot movement stage includes a second spot input electrically connected to the first spot output, a second spot output, and a second number of FETs configured to selectively control the second spot output based on a logic value of the second spot input and the timing of the single-phase clock signal. Additionally, when the first spot input has the logic high value indicating the presence of the spot, the first number of FETs drives the first spot output to the logic high value in response to a falling edge of the single-phase clock signal. Further, the first number of FETs does not control the first spot output when the first spot input has a logic low value.

[0024] In some implementations, the first spot movement stage further includes a feedback element configured to drive the first spot input to the logic low value in response to the first spot output transitioning from a logic low value to a logic high value. In a number of implementations, the first spot movement stage is configured such that the spot is present at the first spot input for approximately one complete clock cycle of the single-phase clock signal.

[0025] In various implementations, when the second spot input has a logic high value, the second number of FETs drives the second spot output to the logic high value in response to a falling edge of the single-phase clock signal, and the second number of FETs does not drive the second spot output when the second spot input has the logic low value.

[0026] In several implementations, the plurality of spot movement stages are electrically connected in a ring, and the plurality of spot movement stages are configured to generate a divided clock signal based on the time required to move the spot around the ring, wherein the divided clock signal has a lower frequency than the single-phase clock signal.

[0027] In various implementations, the first number of FETs includes a clock n-type field-effect transistor (NFET), an input NFET connected in series with the clock NFET between a signal node and a first supply node, an input p-type field-effect transistor (PFET) connected between a second supply node and the signal node, a clock PFET, and an output PFET electrically connected in series with the clock PFET between the second supply node and the first spot output. Additionally, a gate of the clock NFET and a gate of the clock PFET receive the single-phase clock signal, a gate of the output PFET is connected to the signal node, and a gate of the input PFET and a gate of the input NFET are connected to the first spot input.

[0028] In a number of implementations, the plurality of spot movement stages are electrically connected in a cascade, and the plurality of spot movement stages are configured to generate a digital representation of the time duration of a pulse of the single-phase clock signal.

[0029] According to some implementations, the first number of FETs includes a clock NFET, an input NFET connected in series with the clock NFET between a signal node and a first supply node, an input PFET connected between a second supply node and the signal node, and an output PFET electrically connected between the second supply node and the first spot output. Additionally, a gate of the clock NFET receives the single-phase clock signal, a gate of the output PFET is connected to the signal node, and a gate of the input PFET and a gate of the input NFET are connected to the first spot input.

[0030] In another aspect, an electronic circuit is provided. The electronic circuit includes a plurality of spot movement stages configured to move a spot represented by a logic low value based on the timing of a single-phase clock signal. The plurality of spot movement stages includes a first spot movement stage and a second spot movement stage. The first spot movement stage includes a first spot input, a first spot output, and a first number of FETs configured to selectively control the first spot output based on a logic value of the first spot input and the timing of the single-phase clock signal.The second spot movement stage includes a second spot input electrically connected to the first spot output, a second spot output, and a second number of FETs configured to selectively control the second spot output based on a logic value of the second spot input and the timing of the single-phase clock signal.

[0031] When the first spot input has a logic low value, indicating the presence of the spot, the first number of FETs drives the first spot output to a logic low value in response to a rising edge of the single-phase clock signal. Additionally, when the first spot input has a logic high value, the first number of FETs does not drive the first spot output.

[0032] In some implementations, the first spot movement stage further includes a feedback element configured to drive the first spot input to the logic high value in response to the first spot output transitioning from a logic high value to a logic low value. In a number of implementations, the first spot movement stage is configured so that the spot is present at the first spot input for approximately one complete clock cycle of the single-phase clock signal.

[0033] In various implementations, when the second spot input has a logic low value, the second number of FETs drives the second spot output to the logic low value in response to a rising edge of the single-phase clock signal, and the second number of FETs does not drive the second spot output when the second spot input has the logic high value.

[0034] In a number of implementations, the plurality of spot movement stages are electrically connected in a ring, wherein the plurality of spot movement stages are configured to generate a divided clock signal based on the time required to move the spot around the ring, wherein the divided clock signal has a lower frequency than the single-phase clock signal.

[0035] In certain implementations, the first number of FETs includes an input NFET connected between a first supply node and a signal node, a clock PFET, an input PFET connected in series with the clock PFET between the signal node and a second supply node, a clock NFET, and an output NFET electrically connected in series with the clock NFET between the first supply node and the first spot output. Additionally, the gate of the clock PFET and the gate of the clock NFET receive the single-phase clock signal, the gate of the output NFET is connected to the signal node, and the gate of the input NFET and the gate of the input PFET are connected to the first spot input.

[0036] In some implementations, the multiple spot motion stages are electrically connected in a cascade, and the multiple spot motion stages are configured to generate a digital representation of the duration of a pulse of the single-phase clock signal. According to certain implementations, the multiple spot motion stages comprise between 8 and 1024 spot motion stages.

[0037] In another aspect, a spot movement circuit stage is provided. The spot movement circuit stage includes a spot input configured to receive a spot signal having a first logic value when a spot is present and a second logic value when the spot is not present, a single-phase clock input configured to receive a signal phase clock signal varying between the first logic value and the second logic value, a spot output, and a plurality of FETs configured to selectively control the spot output based on a logic value of the spot input and the timing of the single-phase clock signal. When the spot input has the first logic value, the plurality of FETs additionally control the spot output in response to a transition of the single-phase clock signal from the first logic value to the second logic value to the first logic value.Furthermore, when the spot input has the second logic value, the multiple FETs do not control the spot output.

[0038] In some implementations, the spot motion circuit stage is implemented in a time-to-digital converter.

[0039] In various implementations, the spot motion circuit stage is implemented in a frequency divider.

[0040] In a number of implementations, the spot movement circuit stage further comprises a feedback element configured to drive the spot input to the second logic value in response to the spot output transitioning from the second logic value to the first logic value.

[0041] In another aspect, a frequency divider is provided. The frequency divider includes a plurality of spot movement stages electrically connected in a ring and a spot removal circuit. When a spot signal is present in the ring, the plurality of spot movement stages advance the spot signal around the ring based on the timing of a single-phase clock signal. The plurality of spot movement stages includes a first spot movement stage having a spot input for receiving the spot signal and a spot output for forwarding the spot signal. Additionally, the spot removal circuit has an input electrically connected to the spot output of the first spot movement stage. The spot removal circuit is configured to selectively remove the spot signal from the ring based on the state of a spot removal control signal.The spot removal circuit further includes an output that provides a divided clock signal having a frequency corresponding to the rate at which the spot signal is removed from the ring.

[0042] In certain implementations, the spot distance control signal is capable of controlling the number of times the spot signal travels around the ring.

[0043] In various implementations, the frequency divider further includes an outer divider circuit configured to generate the spot distance control signal. In a number of implementations, the outer divider circuit includes two or more spot movement stages electrically connected in a cascade. In several implementations, the plurality of spot movement stages are configured to generate a round-trip clock signal that controls the timing of the outer divider circuit, and the round-trip clock signal has a frequency corresponding to the time it takes for the spot signal to complete one round-trip around the ring.

[0044] In some implementations, the frequency divider further includes a spot insertion circuit designed to selectively insert the spot signal into the ring.

[0045] In certain implementations, the first spot movement stage further comprises a feedback element electrically connected between the spot output and the spot input, the feedback element capable of canceling the spot signal from the spot input in response to the presence of the spot signal at the spot output.

[0046] In a number of implementations, the first spot movement stage includes a clock NFET, an input NFET connected in series with the clock NFET between a signal node and a first supply node, an input PFET connected between a second supply node and the signal node, a clock PFET, and an output PFET electrically connected in series with the clock PFET between the second supply node and the spot output. Additionally, the gate of the clock NFET and the gate of the clock PFET receive the single-phase clock signal, the gate of the output PFET is connected to the signal node, and the gate of the input PFET and the gate of the input NFET are connected to the spot input.

[0047] In some implementations, the first spot movement stage includes an input NFET connected between a first supply node and a signal node, a clock PFET, an input PFET connected in series with the clock PFET between the signal node and a second supply node, a clock NFET, and an output NFET electrically connected in series with the clock NFET between the first supply node and the first spot output. Additionally, the gate of the clock PFET and the gate of the clock NFET receive the single-phase clock signal, the gate of the output NFET is connected to the signal node, and the gate of the input NFET and the gate of the input PFET are connected to the first spot input.

[0048] In certain implementations, the multiple spot movement levels have at least three spot movement levels.

[0049] In another aspect, a method for frequency division is provided. The method comprises propagating a spot signal around a ring of multiple spot movement stages based on the timing of a single-phase clock signal; selectively removing the spot signal from the ring using a spot removal circuit based on a spot removal control signal; and generating a divided clock signal using the spot removal circuit, the divided clock signal having a frequency corresponding to the rate at which the spot signal is removed from the ring.

[0050] In some implementations, the method further controls the number of round trips the spot signal propagates around the ring using the spot distance control signal.

[0051] In various implementations, the method further generates the spot distance control signal using an external divider circuit having two or more spot movement stages electrically connected in a cascade.

[0052] In a number of implementations, the method further generates a recirculation clock signal based on the time it takes for the spot signal to complete one revolution around the ring. According to some implementations, the method further generates the spot distance control signal using an outer divider circuit, and the timing of the outer divider circuit is controlled using the recirculation clock signal.

[0053] In some implementations, the method further inserts the spot signal into the ring using a spot insertion circuit.

[0054] According to certain implementations, the method further comprises holding the spot signal for approximately one complete clock cycle of the single-phase clock signal using at least one of the plurality of spot movement stages. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a schematic diagram of a true single phase (TSP) spot splitter according to one embodiment. The Fig. 2A-2E are schematic diagrams of TSP spot circuits according to various embodiments. Fig. Figure 3A is an example of a plot of simulated waveforms for the TSP spot splitter from Fig. 1. Fig. Figure 3B is another example of a plot of simulated waveforms for the TSP spot splitter from Fig. 1. Fig. 4 is a schematic diagram of a TSP spot splitter according to another embodiment. Fig. 5 is a schematic diagram of a time-to-digital converter (TDC) according to one embodiment. Fig. 6 is a schematic diagram of one embodiment of a TDC spot circuit. DETAILED DESCRIPTION OF EMBODIMENTS

[0055] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be embodied in a variety of different ways as defined and covered by the claims. Reference is made throughout this description to the drawings, wherein like reference numerals may indicate identical or functionally similar elements.

[0056] Frequency dividers can be incorporated into fast phase-locked loops (PLLs), clock distribution circuits, frequency converters, and / or other circuitry to provide frequency division of clock signals. The speed and performance of a frequency divider can be important for a variety of applications. For example, in a frequency synthesizer application, the performance of a frequency divider can affect the synthesizer's power, frequency, and / or phase noise specifications.

[0057] A spot divider may comprise two or more spot circuits electrically connected in a ring. Each spot circuit passes or moves a spot (e.g., a logic one) to the next spot circuit in the ring. The spot advances from one spot circuit to the next based on the timing of an input clock signal, and the spot divider generates an output clock signal based on the time it takes for the spot to move around the ring. Additional details of spot dividers and spot circuits may be as described in U.S. Patent 7,812,648, entitled "FREQUENCY DIVIDER," issued October 12, 2012, assigned to the assignee of the present application, the entire disclosure of which is incorporated herein by reference.

[0058] Spot dividers offer a wide variety of advantages over other types of frequency dividers. For example, spot dividers are significantly faster than conventional complementary metal oxide semiconductor (CMOS) dividers. Additionally, spot dividers can have lower power consumption and / or better phase noise performance than current mode logic (CML) and / or prescaler-based dividers.

[0059] Certain spot dividers are implemented using spot circuits that operate using multiple clock signal phases, for example, using both a non-inverted clock signal and an inverted clock signal to move the spot. However, operating a spot divider using multiple clock signal phases can limit the maximum operating frequency of the spot divider.

[0060] For example, a multi-phase spot circuit can be implemented to hold a spot when a non-inverted clock signal is logic high and an inverted clock signal is logic low, and to move the spot when the non-inverted clock signal is logic low and the inverted clock signal is logic high. When a spot divider is implemented using such multi-phase spot circuits, each multi-phase spot circuit can hold the spot for about half a clock cycle. At high operating frequencies, the multi-phase spot circuits may not have enough time to function properly in half a clock cycle, which can limit the maximum operating frequency of the spot divider. In contrast, a single-phase spot circuit can hold a spot for about an entire clock cycle.By holding the spot for a longer clock cycle duration, the single-phase spot circuit operates with relaxed timing constraints. Accordingly, the single-phase spot circuit can operate with a shorter minimum clock period and a correspondingly higher maximum operating frequency than a multi-phase spot circuit.

[0061] Accordingly, there is a need for a spot circuit capable of operating using only one clock signal phase and that can meet stringent functional specifications including those related to frequency, power, and / or phase noise.

[0062] A spot divider capable of operating using only one clock signal phase may be referred to herein as a single-phase or true single-phase (TSP) spot divider. Additionally, a spot circuit capable of operating using only one clock signal phase may be referred to herein as a single-phase or TSP spot circuit.

[0063] In contrast to a spot splitter, which operates using two or more clock signal phases, for example, a non-inverted clock signal and an inverted clock signal, a TSP spot splitter can be smaller and / or faster.

[0064] For example, a multiphase spot splitter may include complementary pairs of spot stages that operate using different clock signal phases. For example, a particular complementary pair of spot stages may include a first spot stage implemented with 6 transistors and operating using a non-inverted clock signal, and a second spot stage implemented with 6 transistors and operating using an inverted clock signal. Such a complementary pair of spot stages may include 12 transistors and operate using two clock signal phases. In contrast, certain TSP spot circuits here include 7 transistors and operate using a single clock signal phase.Accordingly, a TSP spot splitter can have fewer transistors and lower clock capacitance than a multiphase spot splitter and operate at a higher frequency while still maintaining low phase noise.

[0065] Additionally, a TSP spot splitter can operate using a smaller number of clock buffers compared to a multiphase spot splitter, which operates using multiple clock signal phases and multiple corresponding clock buffers. Accordingly, the teachings provided herein can be used to eliminate clock buffers for additional clock signal phases compared to a multiphase spot splitter implementation.

[0066] Fig. Figure 1 is a schematic diagram of a TSP spot splitter 100 according to one embodiment. The TSP spot splitter 100 includes an inverter 102, a first TSP spot circuit 104, a second TSP spot circuit 106, and a third TSP spot circuit 108. The TSP spot splitter 100 receives a single-phase clock signal CLK. EIN and a reset signal RESET and generates an output clock signal CLK AUS .

[0067] The TSP spot circuits 104, 106, and 108 each have a data input DEIN, a data output OUT, and a clock input CLKB. The first TSP spot circuit 104 additionally has a set input SB, while the second and third TSP spot circuits 106, 108 each additionally have a reset input RST. As shown in Fig. As shown in Figure 1, the reset signal RESET is provided to the reset inputs RST of the second and third TSP spot circuits 106, 108 and to an input of the inverter 102. The inverter 102 further has an output that provides an inverted version of the reset signal RESET to the set input SB of the first TSP spot circuit 104.

[0068] The TSP spot circuits 104, 106, 108 are electrically connected in a ring. For example, the data output OUT of the first TSP spot circuit 104 is electrically connected to the data input DEIN of the second TSP spot circuit 106 at a signal node VA, the data output OUT of the second TSP spot circuit 106 is electrically connected to the data input DEIN of the third TSP spot circuit 108 at a signal node VB, and the data output OUT of the third TSP spot circuit 108 is electrically connected to the data input DEIN of the first TSP spot circuit 104 at a signal node VC, thus forming a ring. As shown in Fig. 1, the output clock signal CLK AUS provided by the signal node VC.

[0069] Although a TSP spot splitter having three TSP spot circuits is illustrated, the teachings herein are also applicable to configurations having more or fewer TSP spot circuits. Furthermore, a spot splitter may be implemented using a combination of one or more TSP spot circuits and one or more multiphase spot circuits, as disclosed in U.S. Patent 7,812,648, which is hereby incorporated by reference in its entirety.

[0070] As in Fig. 1, each TSP spot circuit 104, 106, 108 receives the single-phase clock signal CLK at a respective clock input CLKB EIN The illustrated TSP spot divider 100 is capable of dividing the frequency of the single-phase clock signal CLK EIN by a factor of three. Accordingly, the frequency of the output clock signal CLK AUS be about a factor of three smaller than the frequency of the input clock signal CLKEIN However, by designing the TSP spot divider 100 to have more or fewer TSP spot circuits, a desired frequency division factor can be obtained.

[0071] The TSP spot splitter 100 has been designed to operate with a state initialization or reset functionality. Specifically, according to the illustrated embodiment, the reset input RESET can be pulsed to force the first TSP spot circuit 104 to a "1" state, the second TSP spot circuit 106 to a "0" state, and the third TSP spot circuit 108 to a "0" state. By resetting the TSP spot splitter 100 in this manner, the first TSP spot circuit 104 can be initialized to begin holding the spot. For example, the logic pulse of the reset input RESET can force the logic levels at signal nodes VA, VB, and VC to be high, low, and low, respectively.By implementing a TSP spot divider to include reset functionality, appropriate circuit operations can be ensured and / or the generation of an output clock signal with a known phase can be supported.

[0072] Although an example of reset functionality is shown, a spot splitter can be reset in a wide variety of ways. For example, one or more spot splitter TSP spot circuits can have set and / or reset inputs, including, for example, inputs that are synchronous or asynchronous and / or that operate using non-inverted or inverted logic polarity.

[0073] According to the illustrated embodiment, the spot corresponds to a logical one, which is determined based on the timing of the input clock signal CLK EINis moved around the ring. However, other implementations are also possible, such as configurations where the spot corresponds to a logical zero that is moved around a ring of spot circuits.

[0074] The TSP spot circuits 104, 106, 108 each receive data input logic signals having one of two logic levels: high or low. In addition, the TSP spot circuits 104, 106, 108 cause a first logic level corresponding to the spot to be transmitted and a complementary logic level to be blocked in response to a clock edge of a particular clock cycle. For example, after a reset logic pulse, the second TSP spot circuit 106 may dynamically transmit the spot (corresponding to a high logic signal in this example) from signal node VA to signal node VB in response to a first clock edge of a first clock cycle. Also, during the first clock cycle, the first and third TSP spot circuits 104, 108 may initially block the transmission of the low logic signals at signal nodes VB and VC. In this way, the spot at signal node VA is transferred to signal node VB during the first clock cycle.During a second clock cycle following the first clock cycle, the spot at signal node VB may be similarly transferred through the third TSP spot circuit 108 to signal node VC.

[0075] The TSP spot circuits 104, 106, 108 may each further include a feedback element to cause the data input of that particular TSP spot circuit to be reset to its complementary logic level after the spot is passed to the next TSP spot circuit in the ring. For example, during the first clock cycle, when the spot (in this example, the high logic signal) is transferred from the data input at signal node VA to the data output at signal node VB, the second TSP spot circuit 106 may cause the logic level or state at signal node VA to transition to a low logic state via the feedback element of the second TSP spot circuit. During the second subsequent clock cycle, the third TSP spot circuit 108 may cause the high state at signal node VB to return to the low state after the spot is transferred to signal node VC.

[0076] According to the illustrated embodiment, a spot returns to an original signal node every three clock cycles. For example, the spot is moved to signal node VB after the first clock cycle and returns to signal node VB after the fourth clock cycle. Therefore, according to this embodiment, it can be observed that the frequency of the spot signal at node VB is one-third that of the input clock signal CLK. EIN Similarly, the frequencies at nodes VA and VC are about one-third of the frequency of the input clock signal CLK EIN However, a TSP spot splitter may have more or fewer TSP spot circuits in a ring to provide a desired amount of frequency division.

[0077] Although the TSP spot splitter 100 has been described with reference to transmitting a spot with a high logic level or state, the TSP spot splitter 100 can also be configured to transmit a spot with a low logic state. Furthermore, more or fewer TSP spot circuits in a ring can be electrically connected to provide frequency dividers with a division factor other than three. For example, two TSP spot circuits in a loop can be electrically connected to form a divide-by-two divider. Similarly, four TSP spot circuits in a loop can be electrically connected to form a divide-by-four divider.

[0078] Additional details of the TSP spot splitter 100 may be as previously described.

[0079] The Fig. 2A-2E are schematic diagrams of TSP spot circuits according to various embodiments.

[0080] Fig. 2A is a schematic diagram of a TSP spot circuit 200 according to one embodiment. The TSP spot circuit 200 includes a first or input stage 201 and a second or output stage 203. The first stage 201 includes an input PMOS or first input FET 202, a clock NMOS or first clock FET 206, and an input NMOS or second input FET 212. Additionally, the second stage 203 includes a clock PMOS or second clock FET 204 and an output PMOS or output FET 208. The TSP spot circuit 200 further includes a reset NMOS or reset FET 210 and a feedback NMOS or feedback FET 214.

[0081] Although a specific embodiment using metal oxide semiconductor (MOS) transistors is illustrated, the teachings are applicable to configurations using other types of field effect transistors (FETs).

[0082] The input PMOS 202 has a source electrode electrically connected to a first supply node VDD and a drain electrode electrically connected to a first signal node V1. The clock NMOS 206 and the input NMOS 212 are electrically connected in series between the first signal node V1 and a second supply node VSS. The clock NMOS 206 has a drain electrode electrically connected to the first signal node V1 and a source electrode electrically connected to the drain electrode of the input NMOS 212. The source electrode of the input NMOS 212 is electrically connected to the second supply node VSS. A data input or spot input DEIN is electrically connected to the gate electrode of the input PMOS 202 and the gate electrode of the input NMOS 212, while a clock input CLKB is electrically connected to the gate electrode of the clock NMOS 206.

[0083] The clock PMOS 204 and the output PMOS 208 are electrically connected in series between the first supply node VDD and a data output or spot output OUT. The clock PMOS 204 has a source electrically connected to the first supply node VDD and a drain electrically connected to the source of the output PMOS 208. The data output OUT is electrically connected to the drain of the output PMOS 208. The gate of the output PMOS 208 is electrically connected to the first signal node V1, and the gate of the clock PMOS 204 is electrically connected to the clock input CLKB.

[0084] The reset NMOS 210 has a drain electrode electrically connected to the data input DEIN, a source electrode electrically connected to the second supply node VSS, and a gate electrode electrically connected to a reset input RST. The feedback NMOS 214 has a drain electrode electrically connected to the data input DEIN, a source electrode electrically connected to the second supply node VSS, and a gate electrode electrically connected to the data output OUT.

[0085] The second stage 203 can either provide a low impedance between the first supply node VDD to the data output OUT or provide a high impedance to electrically isolate the data output OUT from the first supply node VDD. When the data input DEIN receives a low logic input signal, the input PMOS 202 turns on and conducts, driving the first signal node V1 to a high logic level. The output PMOS 208, in turn, turns off, so the second stage 203 electrically isolates the data output OUT from the first supply node VDD. Therefore, regardless of the state of a clock signal at the clock input CLKB, when the data input DEIN receives an input signal with a low logic level (indicating that no spot is present at the data input DEIN), the second stage 203 provides a high impedance between the data output OUT and the first supply node VDD.

[0086] However, if the data input DEIN receives an input signal with a high logic level (thereby indicating that a spot is present at the data input DEIN), the TSP spot circuit 200 can dynamically transition the high logic level from the data input DEIN to the data output OUT in response to a falling edge of the clock signal. Accordingly, according to this embodiment, the spot is transitioned from the data input DEIN to the data output OUT on a falling edge of the clock signal.

[0087] For example, when the spot is present, both the data input DEIN and the clock input CLKB may have high logic levels after the clock signal rises. Accordingly, in response to a rising edge of the clock signal, a low-impedance path is provided to the first signal node V1 via the input NMOS 212 and the clock NMOS 206 from the second supply node VSS, thereby turning on the output PMOS 208. When the clock signal subsequently falls, the clock PMOS 204 turns on, and a low-impedance path is provided to the output node OUT from the first supply node VDD, pulling the data output OUT high. Accordingly, the TSP spot circuit 200 passes the spot from the data input DEIN to the data output OUT in response to a falling edge of the clock signal.

[0088] Additionally, the illustrated embodiment advantageously includes feedback NMOS 214, which clears the spot from the data input DEIN as soon as the spot reaches the data output OUT. Specifically, feedback NMOS 214 turns on in response to a rising edge of the data output OUT, thereby providing a low-impedance path from the second supply node VSS to the data input DEIN and clearing the spot from the data input DEIN.

[0089] Accordingly, the feedback NMOS 214 operates with respect to the Fig. 1 as a feedback element. After a falling clock edge causes the data output OUT to transition to a high logic level, the data output OUT drives the gate of the feedback NMOS 214, causing the feedback NMOS 214 to conduct. The data input DEIN is, in turn, charged to a low logic level by the feedback NMOS 214, removing the spot from the data input DEIN. In this way, during a single clock cycle, the TSP spot circuit 200 transfers the high logic level at the data input DEIN to the data output OUT and then charges the data input DEIN to the low logic level.

[0090] Accordingly, the illustrated TSP spot circuit 200 holds a spot for approximately one clock cycle. Holding the spot for approximately one clock cycle can mitigate timing constraints compared to a configuration in which a spot is held for only approximately a fraction of a clock cycle. For example, certain multi-phase spot circuits can hold a spot for approximately half a clock cycle. The TSP spot circuit 200 can operate with a shorter minimum clock period and a correspondingly higher maximum operating frequency than such multi-phase spot circuits.

[0091] According to one embodiment, a TSP spot circuit holds a spot between 80% and 100% of a clock cycle when operating above 1 GHz. This, in turn, can advantageously simplify or mitigate a design that uses the TSP spot circuit instead of a spot circuit that holds a spot between 40% and 60% of a clock cycle, and more importantly, can enable improved clock speeds. For example, a TSP spot circuit that holds a spot between 80% and 100% of a clock cycle can operate 30% faster than a spot circuit that holds a spot between 40% and 60% of a clock cycle.

[0092] The illustrated TSP spot circuit 200 also includes the reset NMOS 210, which can be used to asynchronously reset the TSP spot circuit 200 by clearing the spot from the data input DEIN. While the illustrated configuration includes the reset NMOS 210, other configurations are possible. For example, according to another embodiment, the reset NMOS 210 can be omitted. According to yet another embodiment, the reset NMOS 210 is included in series with a clocked FET to provide a synchronous reset. According to yet another embodiment, set and / or reset functionality is provided in other ways, for example, using an asynchronous set and / or a synchronous set.

[0093] Additional details of the TSP spot circuit 200 may be as previously described.

[0094] Fig. Figure 2B is a schematic diagram of a TSP spot circuit 220 according to another embodiment. The TSP spot circuit 220 of Fig. 2B is similar to the TSP spot circuit 200 from Fig. 2A except that in the TSP spot circuit 220, the reset NMOS 210 is omitted in favor of including a set PMOS 216.

[0095] As in Fig. As shown in Figure 2B, the set PMOS 216 has a source electrically connected to the first supply node VDD, a drain electrically connected to the data output OUT, and a gate receiving a set signal SB. The set PMOS 216 provides the set functionality that charges the data output OUT to a high logic level when the set signal SB at the gate of the PMOS 216 is logic low.

[0096] Additional details of the TSP spot circuit 220 may be as previously described.

[0097] Fig. 2C is a schematic diagram of a TSP spot circuit 230 according to another embodiment. The TSP spot circuit 230 of Fig. 2C is similar to the TSP spot circuit 200 from Fig. 2A except that the order in the series of the clock PMOS 204 and the output PMOS 208 is as shown in Fig. 2C compared to the embodiment shown in Fig. 2A is reversed. In particular, the clock PMOS 204 comprises Fig. 2C has a drain electrode electrically connected to the data output OUT and a source electrode electrically connected to the drain electrode of the output PMOS 208, and the output PMOS 208 comprises Fig. 2C has a source electrode electrically connected to the first supply node VDD.

[0098] By reversing the order of the series of clock PMOS 204 and output PMOS 208, operating speed can be increased by reducing the delay in transferring the spot from the data input DIN to the data output OUT in response to a falling clock edge. However, configuring the TSP spot circuit 230 in this manner also increases clock throughput.

[0099] Additional details of the TSP spot circuit 230 may be as previously described.

[0100] Fig. Figure 2D is a schematic diagram of a TSP spot circuit 240 according to another embodiment. The TSP spot circuit 240 of Fig. 2D is similar to the TSP spot circuit 200 from Fig. 2A, except that the TSP spot circuit 240 further includes an enable NMOS 242 electrically connected in series with the clock NMOS 206 and the input NMOS 212 between the first signal node V1 and the second supply node VSS. According to the illustrated embodiment, the enable NMOS 242 has a drain electrode electrically connected to the source electrode of the input NMOS 212, a source electrode electrically connected to the second supply node VSS, and a gate electrode electrically connected to an enable input EN.

[0101] The enable NMOS 242 provides the TSP spot circuit 240 with enabling functionality such that the enable NMOS 242 enables circuit operation when the enable input EN is high and disables circuit operation when the enable input EN is low. For example, the enable NMOS 242 operates as shown in Fig. 2D, in an electrical path of the first stage 201 between the first signal node V1 and the second supply node VSS. When the enable input EN is logic low, the enable NMOS 204 turns off, operating an open circuit that prevents the first stage 201 from turning on the output PMOS 208 in response to a rising edge of the clock signal. Conversely, when the enable input EN is high, the enable NMOS 204 electrically connects the source electrode of the input NMOS 212 to the second supply node VSS, thereby enabling operation.

[0102] Additional details of the TSP spot circuit 240 may be as previously described.

[0103] Fig. 2E is a schematic diagram of a TSP spot circuit 250 according to another embodiment. The TSP spot circuit 250 includes a first or input stage 251 and a second or output stage 253. The first stage 251 includes an input NMOS or first input FET 262, a clock PMOS or first clock FET 258, and an input PMOS or second input FET 254. Additionally, the second stage 253 includes a clock NMOS or second clock FET 264 and an output NMOS or output FET 260. The TSP spot circuit 250 further includes a reset PMOS or reset FET 252 and a feedback PMOS or feedback FET 256.

[0104] The TSP spot circuit 250 from Fig. Figure 2E illustrates an embodiment of a TSP spot circuit that operates using a spot represented using a logical zero. The TSP spot circuit 250 of Fig. 2E corresponds to a complementary implementation of the TSP spot circuit from Fig. 2A, where the polarity of the transistors is reversed and the first and second supply nodes are swapped. As will be understood by those of ordinary skill in the art, complementary implementations of the TSP spot circuits can be derived from the Fig. 2B - 2D, which have a logically low spot, can also be realized in a similar way.

[0105] The logic operation of the TSP spot circuit 250 from Fig. 2E can be added to that of the TSP spot circuit 200 from Fig. 2A complementary. For example, the TSP spot circuit 250 can be Fig. 2E as well as the TSP spot circuit 200 from Fig. 2A transmits a spot. However, unlike the TSP spot circuit 200, which transmits a spot with a high logic state, the TSP spot circuit 250 transmits a spot with a low logic state. In addition, the TSP spot circuit 250 from Fig. 2E transfers the spot from the data input DEINB to the data output OUT on a rising edge of a clock signal received at the clock input CLK. In contrast, the TSP spot circuit 200 transfers Fig. 2A a spot on a falling edge of a clock signal.

[0106] Accordingly, the TSP spot circuit 250 is made of Fig. 2E complementary to the TSP spot circuit 200 from Fig. 2A. The TSP spot circuit 250 from Fig. 2E shows transistors of opposite device polarity and supply nodes connected with respect to the TSP spot circuit 200 of Fig. 2A are reversed or exchanged.

[0107] As in Fig. As shown in Figure 2E, the input NMOS 262 has a source electrically connected to the first supply node VSS and a drain electrically connected to the first signal node V1. Additionally, the input PMOS 254 and the clock PMOS 258 are electrically connected in series between the first signal node V1 and the second supply node VDD. The clock PMOS 258 has a drain electrically connected to the first signal node V1 and a source electrically connected to the drain of the input PMOS 254. The source of the input PMOS 254 is electrically connected to the second supply node VDD. A data input or spot input DEINB is electrically connected to the gate electrode of the input NMOS 262 and the gate electrode of the input PMOS 254, and a clock input CLK is electrically connected to the gate electrode of the clock PMOS 258.

[0108] The output NMOS 260 and the clock NMOS 264 are electrically connected in series between the first supply node VSS and the data output or spot output OUT. The NMOS 264 has a source electrode electrically connected to the first supply node VSS and a drain electrode electrically connected to a source electrode of the output NMOS 260. The data output OUT is electrically connected to the drain electrode of the output NMOS 260. The gate electrode of the output NMOS 260 is electrically connected to the first signal node V1, and the gate electrode of the clock NMOS 264 is electrically connected to the clock input CLK.

[0109] The reset PMOS 252 has a drain electrode electrically connected to the data input DEINB, a source electrode electrically connected to the second supply node VDD, and a gate electrode electrically connected to a reset input RSTB. The feedback PMOS 256 has a drain electrode electrically connected to the data input DEINB, a source electrode electrically connected to the second supply node VDD, and a gate electrode electrically connected to the data output OUT.

[0110] When the data input DEINB receives a high logic input signal (indicating that there is no spot at the data input DEINB), the input NMOS 262 conducts, so that the first signal node V1 is logic low. The output NMOS 260, in turn, is turned off, operating as an open circuit, causing the second stage 253 to electrically isolate the data output OUT from the first supply node VSS. Therefore, regardless of the state of a clock signal at the clock input CLK, when the data input DEINB receives an input signal with a high logic level, the second stage 253 provides a high impedance between the data output OUT and the first supply node VSS.

[0111] However, when the data input DEINB receives an input signal with a low logic level (indicating that a spot is present at the data input DEINB), the TSP spot circuit 250 can dynamically transfer the low logic level from the data input DEIN to the data output OUT in response to a rising edge of the clock signal. Accordingly, according to this embodiment, the spot is transferred from the data input DEINB to the data output OUT on a rising edge of the clock signal.

[0112] For example, when the spot is present, both the data input DEINB and the clock input CLK may have low logic levels after the clock signal falls. Accordingly, in response to a falling edge of the clock signal, a low-impedance path is provided via the input PMOS 254 and the clock PMOS 258 from the second supply node VDD to the first signal node V1, thereby turning on the output NMOS 260. When the clock signal subsequently rises, the clock NMOS 264 turns on and provides a low-impedance path from the first supply node VSS to the output node OUT, pulling the data output OUT low. In this way, the TSP spot circuit 250 passes the spot from the data input DEINB to the data output OUT in response to a rising edge of the clock signal.

[0113] The feedback PMOS 256 operates as a feedback element. Specifically, after a rising clock edge causes the data output OUT to transition to a low logic level, the feedback PMOS 256 conducts to charge the data input DEINB to a high logic level, thereby clearing the spot from the input.

[0114] The reset PMOS 252 can be used to reset the data input DEINB to a high logic level by providing a pulse to the reset input RSTB, thereby clearing the spot from the input.

[0115] Additional details of the TSP spot circuit 250 may be as previously described.

[0116] Fig. Figure 3A is an example of a plot of 300 simulated waveforms for the TSP spot splitter 100 from Fig. 1. The plot 300 includes a single-phase clock input signal waveform 302 with rising and falling clock edges. In addition, the plot 300 includes a first spot signal waveform 304, a second spot signal waveform 306, and a third spot signal waveform 308, which are waveforms at the signal nodes VA, VB, and VC, respectively, of the TSP spot divider 100. Fig. 1 correspond.

[0117] As in Fig. 3A, each of the TSP spot circuits 104, 106, 108 from Fig. 1 the spot for about one clock cycle. In addition, the TSP spot circuits from Fig. 1 the spot responds to a falling clock edge.

[0118] As in Fig. 3A, the first spot signal waveform 304 transitions to a high logic state, for example, in response to a first falling clock edge 311 of a first clock cycle. After the first spot signal waveform 304 reaches the high logic level at signal node VA, the third spot signal waveform 308 transitions to a low logic level at signal node VC during the first clock cycle. The transition of the third spot signal waveform 308 to a low logic state corresponds to the charging of the signal node VC to a low logic level by the feedback element of the first TSP spot circuit 104 of Fig. 1.

[0119] Similarly, the second spot signal waveform 306 transitions to a high logic state in response to a second falling clock edge 312 of a second clock cycle. Subsequently, the first spot signal waveform 304 transitions to a low logic level during the second clock cycle. This corresponds to the case where the second TSP spot circuit 106 charges the signal node VB to a high logic level and then charges the signal node VA to a low logic level via a feedback element.

[0120] Furthermore, the third spot signal waveform 308 transitions to a high logic state in response to a third falling clock edge 313 of a third clock cycle. Subsequently, the third spot signal waveform 308 transitions to a low logic level during the third clock cycle. This corresponds to the case where the third TSP spot circuit 108 charges the signal node VC to a high logic level and subsequently charges the signal node VB to a low logic level via a feedback element.

[0121] Fig. 3B is another example of a plot 310 of simulated waveforms for the TSP spot splitter 100 of Fig. 1. Plot 310 shows a portion of spot signal waveforms 304, 306, 308 Fig. 3A, which are superimposed on each other. As with regard to Fig. 3A, each of the spot signal waveforms 304, 306, 308 remains in a spot state for approximately one clock cycle. Also, the respective spots overlap each other, so that the subsequent spot transitions to the spot state, the high logic state, before its preceding spot transitions to a low logic state. For example, the spot signal waveform 304 rises at signal node VA, as shown in Fig. 3B, to the high logic state before the spot signal waveform 308 at signal node VC falls to the low logic state.

[0122] Although the Fig. 3A and Fig. 3B shows two examples of simulated waveforms for the spot splitter 100 from Fig. As shown in Figure 1, other results are also possible. For example, the operation of a spot splitter may vary depending on the implementation and / or application.

[0123] Fig. 4 is a schematic diagram of a TSP spot splitter 400 according to another embodiment. The TSP spot splitter 400 includes an outer splitter circuit 401 including a first outer TSP spot circuit 411, a second outer TSP spot circuit 412, a third outer TSP spot circuit 413, and a multiplexer (MUX) 418. The TSP spot splitter 400 further includes an inner splitter circuit 403 including a first inner TSP spot circuit 421, a second inner TSP spot circuit 422, a third inner TSP spot circuit 423, a spot loading TSP spot circuit 424, and a spot removing TSP spot circuit 425.

[0124] Although the illustrated outer divider circuit 401 includes three TSP spot circuits and a multiplexer, other configurations are possible. For example, the outer divider circuit 401 may include more or fewer TSP spot circuits to achieve a desired frequency division factor. According to another embodiment, the outer divider circuit omits the TSP spot circuits in favor of implementing the outer divider using complex logic. Additionally, although the illustrated input divider circuit 403 includes three inner TSP spot circuits in a ring, a spot-loading TSP spot circuit, and a spot-removing TSP spot circuit, other configurations are also possible. For example, the input divider circuit 402 may include more or fewer inner TSP spot circuits in a ring and / or may include other configurations of spot loading, spot removal, and / or state initialization.

[0125] Each of the TSP spot circuits has a data input D, a data output Q, and a clock input. The second inner TSP spot circuit 422 further has an enable input, and the spot removal TSP spot circuit 425 further has an enable rail input.

[0126] The outer TSP spot circuits 411-413 are electrically connected in a cascade. The data output Q of the first outer TSP spot circuit 411 is electrically connected to the data input D of the second outer TSP spot circuit 412, and the data output Q of the second outer TSP spot circuit 412 is electrically connected to the data input D of the third outer TSP spot circuit 413. The data output Q of the third outer TSP spot circuit 413 is electrically connected to a first input of the MUX 418. A second input and a third input of the MUX 418 are electrically connected to the data output Q of the second outer TSP spot circuit 412 and the data output Q of the first outer TSP spot circuit 411, respectively. The fourth input of the MUX 418 is electrically connected to a first control signal CNT1, which also serves as data input D for the first outer TSP spot circuit 411. As in Fig. 4, the clock inputs of the outer TSP spot circuits 411 - 413 are controlled by a circulating clock signal CLK UMLAUF controlled by the data output Q of the first inner TSP spot circuit 421.

[0127] The MUX 418 has a control input that receives a second control signal CNT2. The MUX 418 further has an output electrically connected to the enable input of the second inner TSP spot circuit 422 and to the enable rail input of the spot removal TSP spot circuit 425.

[0128] The inner TSP spot circuits 421-423 are electrically connected in a ring. Additionally, the spot loading TSP spot circuit 424 is used to load a spot from a spot input IN into the ring of inner TSP spot circuits 421-423, and the spot removal TSP spot circuit 425 is used to remove the spot from the ring and provide the spot to a spot output OUT. As shown in Fig. 4, the inner TSP spot circuits 421-423, the spot load TSP spot circuit 424, and the spot remove TSP spot circuit 425 each have a clock input that receives a single-phase clock signal CLKN.

[0129] As in Fig. 4, the data output Q of the first inner TSP spot circuit 421 is at a node that receives the circulation clock signal CLK UMLAUFgenerated, electrically connected to the data input D of the second inner TSP spot circuit 422 and to the data input D of the spot removal TSP spot circuit 425. In addition, the data output Q of the second inner TSP spot circuit 422 is electrically connected to the data input D of the third inner TSP spot circuit 423. Furthermore, the data output Q of the third inner TSP spot circuit 423 is electrically connected to the data input D of the first inner TSP spot circuit 421. The data input D of the spot load TSP spot circuit 424 receives the spot input IN, and the data output Q of the spot load TSP spot circuit 424 is electrically connected to the data input D of the first inner TSP spot circuit 421. The data input D of the spot removal TSP spot circuit 425 is electrically connected to the data output Q of the first inner TSP spot circuit 421, and the data output Q of the spot removal TSP spot circuit 425 generates the spot output signal OUT.

[0130] The TSP spot divider 400 divides the single-phase clock signal CLKN using the inner divider circuit 403 and the outer divider circuit 401. In addition, the amount of division provided by the TSP spot divider 400 is controllable using the first control input CNT1 and the second control input CNT2. Therefore, the frequency can be controlled by the first control input CNT1 and the second control input CNT2, and in contrast to the TSP spot divider 100 of Fig. 1, which provides a division with a fixed divisor, the TSP spot divider 400 provides Fig. 4 advantageously provides division using a selectable division value. Implementing a divider with a selectable division value is advantageous for a wide variety of applications, including, for example, frequency synthesizer applications.

[0131] The spot input IN, the first control input CNT1, and the second control input CNT2 can be used to control the inner divider circuit 403 and the outer divider circuit 401, thereby controlling the division value of the TSP spot divider. For example, the spot load TSP spot circuit 424 is used to load a spot from the spot input IN into the ring of inner TSP spot circuits 421-423. The spot is moved around the ring of inner TSP spot circuits 421-423 based on the timing of the single-phase clock signal CLKN. Because the ring of inner TSP spot circuits 421-423 has three TSP spot circuits, the recirculating clock signal CLK UMLAUFa frequency approximately one-third that of the single-phase clock signal CLKN when a spot is present in the inner ring. The outer divider circuit 401 is used to control timing when the spot is removed from the ring of inner TSP spot circuits 421-423 to the spot output OUT, thereby controlling the value of the divisor of the TSP spot divider.

[0132] Accordingly, the rate at which the spot appears at the spot output OUT corresponds to the division rate of the TSP spot divider 400. As in Fig. As shown in Figure 4, the outer divider circuit 401 is used to control the timing in the case where the spot is removed from the ring of inner TSP spot circuits 421-423 to the spot output OUT using the spot removal TSP spot circuit 425. In particular, the output of the MUX 418 controls the enable rail inputs of the second inner TSP spot circuit 422 and the spot removal TSP spot circuit 425 and can accordingly be used to either remove the spot from the inner ring to the spot output OUT or to allow the spot to complete one more circuit around the inner ring.

[0133] In one example, to achieve a division rate of 2 using the TSP spot circuit 400, a spot may be moved from the input of the first inner TSP spot circuit 421 to the input of the spot removal TSP spot circuit 425 in a first clock cycle and then moved from the input of the spot removal TSP spot circuit 425 to the spot output OUT in a second clock cycle. Accordingly, when dividing by a factor of 2, the TSP spot divider 400 may provide a spot at the spot output OUT every other cycle of the single-phase clock signal CLKN.

[0134] In another example, a division rate of 5 can be achieved by moving a spot from the input of the first inner TSP spot circuit to the output in a first clock cycle, moving the spot from the input of the second inner TSP spot circuit to the output in a second clock cycle, moving the spot from the input of the third inner TSP spot circuit to the output in a third clock cycle, moving the spot from the input of the first inner TSP spot circuit to the output in a fourth clock cycle, and moving the spot from the input of the spot removal TSP spot circuit to the output in a fifth clock cycle.

[0135] To provide a specific divisor, the timing of providing a spot is controlled at the spot input IN. Additionally, to provide large division rates, a control spot can be provided at the first control input CNT1. The control spot can be controlled based on the timing of the circulating clock signal CLK. UMLAUF , which has a frequency that, in this example, is approximately one-third of the single-phase clock signal CLKN, can be moved through the outer TSP spot circuits 411-413. The second control input CNT2 can be used to control the MUX 418 and thus to control the time at which the control spot reaches the enable rail input of the spot removal TSP spot circuit 425.

[0136] With reference to Fig. 1, it should be noted that the TSP spot divider 100 provides frequency division with a divisor equal to the number of TSP spot dividers electrically connected in a ring. Accordingly, N TSP spot dividers can be electrically connected in a ring to achieve frequency division with a divisor N. While a ring of TSP spot dividers can be used to achieve a desired amount of frequency division, such a configuration may have relatively high cost, relatively high power, and / or relatively high size if the divisor is relatively large because the number of TSP spot dividers may scale linearly with the divisor N.

[0137] In contrast, the number of TSP spot dividers of the single-phase spot divider 400 scales logarithmically with the divisor N. In particular, by including k outer TSP spot circuits in the outer divider circuit 401, the divisor N is increased by a factor of 2k so that the number of outer TSP spot circuits increases with log(N). Accordingly, the explained TSP spot divider 400 can be Fig. 4 a frequency division using a smaller number of TSP spot circuits than in the TSP spot divider 100 of Fig. 1 provide.

[0138] Although the embodiment of the TSP spot divider 400 shows a total of eight TSP spot circuits, other configurations with more or fewer TSP spot circuits for TSP spot dividers with different divisors can be realized.

[0139] Fig. Figure 5 is a schematic diagram of a time-to-digital converter (TDC) 500 according to one embodiment. The TDC 500 includes a first TDC spot circuit 502, a second TDC spot circuit 504, a third TDC spot circuit 506, and a fourth TDC spot circuit 508 electrically connected in a cascade.

[0140] Although the illustrated embodiment includes four TDC spot circuits in a cascade, other numbers of TDC spot circuits may also be used. According to one embodiment, a TDC may include between 8 and approximately 1024 or more TDC spot circuits in a cascade. Providing a cascade with a relatively high number of TDC spot circuits allows a TDC to generate a digital representation of a pulse with a relatively long duration.

[0141] The TDC 500 uses spot circuits referred to here as TDC spot circuits, which in certain respects are similar to the TSP spot circuits from the Fig. 2A - 2E. Unlike the TSP spot circuits from the Fig. 2A - 2E the TDC spot circuits are Fig. 5, however, is implemented to measure the pulse width of a gate or clock signal G. In certain implementations, the TDC spot circuits can operate without a feedback element, so that the spot is not erased from the input of a TDC spot circuit in these implementations.

[0142] As in Fig. 5, a data output Q of the first TDC spot circuit 502 is electrically connected to a data input D of the second TDC spot circuit 504. In addition, a data output Q of the second TDC spot circuit 504 is electrically connected to a data input D of the third TDC spot circuit 506. Furthermore, a data output Q of the third TDC spot circuit 506 is electrically connected to a data input D of the fourth TDC spot circuit 508. As shown in Fig. 5, a data input D of the first TDC spot circuit 502 receives a high logic signal (corresponding to a spot in this example) through its connection to a first supply node VDD. Additionally, a first buffered output signal OUT1 is provided at a buffer output B of the first TDC spot circuit 502. Similarly, the second through fourth buffered output signals OUT2, OUT3, and OUTn are provided at a buffered output B of the second, third, and fourth TDC spot circuits 504, 506, 508, respectively. In certain configurations, the buffered output signals OUT1 - OUTn are provided to a decoder or other digital processing circuitry.

[0143] As in Fig. As shown in Figure 5, each of the TDC spot circuits has a gate or clock input G, a reset input R, a read buffer input RDB, a spot or data input D, a spot or data output Q, and a buffer output B. The gate input G of each of the TDC spot circuits receives a gate signal GATE, and the reset input R of each receives a reset signal RESET. Also, the read buffer input RDB of each of the TDC spot circuits receives a read buffer signal RDB.

[0144] The TDC 500 measures the time during which the gate signal GATE is in a gate logic state. For example, the TDC 500 may measure the pulse width of the gate signal GATE, such as the time during which the gate signal GATE has a high logic level. In response to the onset of a pulse of the gate signal GATE, a spot (in this example, a high logic state) flows from the data input D to the data output Q of the cascade of TDC spot circuits starting with the first TDC spot circuit 502 and traveling down the chain of spots to the fourth TDC spot circuit 508. The spot may travel down the cascade of TDC spot circuits until the end of the pulse of the gate or pulse signal GATE, thereby preventing the spot from traveling any further. Further, a digital representation of the pulse time of the gate signal is determined by a state of the buffered outputs OUT1 - OUTn.

[0145] Although Fig. 5 shows a configuration in which a spot corresponding to a high logic level is used, the teachings presented here are also applicable to configurations in which a spot is represented using a low logic level.

[0146] The TDC 500 provides buffered output data via the buffered outputs OUT1 - OUTn. When the read buffer signal RDB is set to a read state, each buffered output provides the output state of the data output Q of a corresponding TDC spot circuit. For example, if the second TDC spot circuit 504 provides a low logic state at the data output Q, the buffered output OUT2 is low. Also, the buffered output OUT2 is high when the second TDC spot circuit 504 provides a high logic state at the data output Q.

[0147] Implementing each TDC spot circuit to have a buffered output B reduces charge effects at the data output Q, thereby reducing the propagation delay through the TDC spot circuit and providing higher resolution. For example, the illustrated configuration may have temporal resolution based on the propagation delay of a spot through a TDC spot circuit. By reducing capacitive charge effects at the data outputs of the TDC spot circuits, higher resolution may be achieved. The illustrated TDC 500 may achieve finer resolution than a TDC implemented using CMOS inverters. For example, the TDC 500 may have a resolution of about 27 ps or less, while a CMOS inverter-based TDC fabricated using a similar process may have a resolution of about 50 ps or more.

[0148] Resetting the TDC 500 is achieved using the reset signal RESET. Specifically, the reset signal RESET can be used to remove the spot from the illustrated TDC spot circuits, thereby clearing the state of the data output Q and buffer output B of each TDC spot circuit. In one example, the buffered outputs OUT1 - OUTn can be cleared to a low logic state when the reset signal RESET is switched high.

[0149] Although it is shown that the TDC 500 is made of Fig. 5 has four TDC spot circuits, other configurations are also possible, including fewer or more TDC spot circuits. Additionally, even if the TDC 500 has TDC spot circuits that pass the high logic state and block the low logic state, other configurations are possible. For example, a TDC can be implemented using TDC spot circuits that pass a low logic state and block a high logic state.

[0150] The TDC 500 can be used in a wide variety of applications. In one example, the TDC 500 is used in a PLL (e.g., an all-digital PLL) to control a digitally controlled oscillator (DCO) based on the duration of an output pulse from a digital PFD. In another example, the TDC 500 is used in a positron emission tomography (PET) system to generate a digital representation of the time period between a radiation burst and resulting positron emissions from biologically active molecules.

[0151] Fig. 6 is a schematic diagram of one embodiment of a TDC spot circuit 600. The TDC spot circuit 600 includes a first, or input, stage 201, which may be as previously described. The TDC spot circuit 600 further includes a second, or output, stage 603, which includes the output PMOS 208. The TDC spot circuit 600 further includes a third, or buffered output stage 605, which includes a buffered output PMOS 618 and a sense PMOS 620. The TDC spot circuit 600 further includes a first reset NMOS 622 and a second reset NMOS 624.

[0152] As with reference to the TDC 500 from Fig. As discussed in Figure 5, the TDC 500 can be implemented with the TDC spot circuits in which a feedback element for resetting the data input D after a spot (in this example, a high logic state) has been transferred from the data input D to the data output Q is omitted. Accordingly, in the illustrated TDC spot circuit 600, a feedback element is omitted.

[0153] The output PMOS 208 is electrically connected between the first supply node VDD and the output Q and has a gate electrode electrically connected to the first signal node V1. In addition, the buffered output PMOS 618 and the read PMOS 620 are electrically connected in series between the first supply node VDD and the buffered output B. As shown in Fig. As shown in Figure 6, the gate of the buffered output PMOS 618 is electrically connected to the first signal node V1, and the gate of the read PMOS 620 is electrically connected to the read buffer input RDB. The first reset NMOS 622 is electrically connected between the data output Q and the second supply node VSS and has a gate electrically connected to the reset input R. The second reset NMOS 624 is electrically connected between the buffered output B and the second supply node VSS and has a gate electrically connected to the reset input R.

[0154] The TDC spot circuit 600 from Fig. 6 shows an embodiment of a TDC spot circuit that operates using a spot represented using a logical one. However, the teachings provided herein are also applicable to TDC spot circuits that operate using a spot represented using a logical zero. For example, similar to the above with respect to the complementary TSP spot circuit 250 of Fig. 2E, complementary TDC spot circuits can be implemented by reversing the polarity of the transistors and reversing the first and second supply nodes.

[0155] As with reference to the TDC 500 from Fig.As discussed in Section 5, when the reset input R receives a high logic reset signal RESET, the buffer output B and the data output Q can be cleared to a low logic state in this example. Also, when the data input D is at a high logic state (corresponding to a spot present), a high GATE signal applied to the gate input G allows a high logic state to be transferred to the data output Q, thereby transferring the spot from the input to the output of the TDC spot circuit. The state of the spot can be read at the buffer output B while the read buffer input RDB is at a low logic state.

[0156] By including the read buffer input RDB and the corresponding read PMOS 620, the buffered output B can be prevented from undergoing a transition when the spot is transferred from the data input D to the gate input G. Configuring the TDC spot circuit 600 in this manner can result in the buffered output stage 605 providing a relatively small and constant capacitive load on the first signal node V1. Additionally, by including the PMOS 620, power consumption can be reduced compared to other configurations that do not include the PMOS 620 because the TDC spot circuit 600 can enable the TDC to reduce decode logic operations and execute them only when needed, so that the decode logic can be programmed to run only when required. Applications

[0157] Devices using the spot circuitry described above can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include circuits of optical networks or other communication networks. The consumer electronic products can include, but are not limited to, a motor vehicle, a camcorder, a camera, a digital camera, a portable memory chip, a washing machine, a dryer, a washer-dryer combination, a copier, a fax machine, a scanner, a multifunctional peripheral device, etc. Furthermore, the electronic device can include unfinished products, including those for industrial, medical, and automotive applications.

[0158] The foregoing description and claims may refer to elements or features that are "connected" or "coupled" to one another. Here, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, not necessarily mechanically. Accordingly, while the various schematics illustrated in the figures depict exemplary arrangements of elements and components, additional intervening elements, devices, features, and components may be present in an actual embodiment (assuming that the functionality of the illustrated circuits is not affected).

[0159] Although this invention has been described with reference to specific embodiments, other embodiments that would be apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above may be combined to provide additional embodiments. In addition, certain features shown in connection with one embodiment may also be incorporated into other embodiments. Accordingly, the scope of the present invention is defined only with reference to the appended claims.

Claims

[1] Spot splitter (100) comprising: two or more spot circuits electrically connected in a ring and comprising a first single-phase spot circuit (104) having a spot input (DEIN), a spot output (AUS) and a clock input (CLKB), the first single-phase spot circuit (104) comprising: a first input field effect transistor (FET) (202) having a first polarity, electrically connected between a first supply node (VDD) and a signal node (V1), wherein a gate electrode of the first FET (202) is electrically connected to the spot input (DEIN), a first clock FET (206) having a second polarity opposite to the first polarity, a second input FET (212) having the second polarity, electrically connected in series with the first clock FET (206) between the signal node (V1) and a second supply node (VSS), a second clock FET (204) having the first polarity, wherein a gate electrode of the first clock FET (206) and a gate electrode of the second clock FET (204) are electrically connected to the clock input (CLKB), and an output FET (208) having the first polarity, electrically connected in series with the second clock FET (204) between the first supply node (VDD) and the spot output (OUT), wherein a gate electrode of the output FET (208) is electrically connected to the signal node (V1), wherein the first single-phase spot circuit (104) further comprises at least one of a reset input (RST) or a set input (SB) configured to initialize a state of the first single-phase spot circuit (104). [2] The spot splitter (100) of claim 1, further comprising a second type feedback FET (214) having a gate electrode electrically connected to the spot output (OUT), a drain electrode electrically connected to the spot input (DEIN), and a source electrode electrically connected to the second supply node (VSS). [3] The spot splitter (100) of claim 1 or 2, wherein the clock input (CLKB) is configured to receive a clock signal, wherein when a spot is present at the spot input (DEIN), the first single-phase spot circuit (104) holds the spot for approximately one cycle of the clock signal. [4] A spot splitter (100) according to any preceding claim, wherein the two or more spot circuits advance a spot around the ring using only a single clock signal phase. [5] A spot splitter (100) according to any one of the preceding claims, wherein the first polarity is p-type and the second polarity is n-type. [6] Spot splitter (100) according to claim 5, wherein the clock input (CLKB) is adapted to receive a clock signal (CLK EIN ), wherein, when the spot input (DEIN) is logic high, the first single-phase spot circuit (104) is configured to drive the spot output (OUT) to a logic high state in response to a falling edge of the clock signal. [7] The spot splitter (100) of claim 6, wherein when the spot input (DEIN) is logic low, the first single-phase spot circuit (104) does not control the spot output (OUT) regardless of the state of the clock signal. [8] The spot splitter (100) of any one of claims 1 to 4, wherein the first polarity is n-type and the second polarity is p-type. [9] The spot splitter (100) of claim 8, wherein the clock input (CLKB) is configured to receive a clock signal, wherein when the spot input (DEIN) is logic low, the first single-phase spot circuit (104) is configured to drive the spot output (OUT) to a logic low state in response to a rising edge of the clock signal (CLKB). [10] Spot splitter (100) according to one of the preceding claims, wherein the two or more spot circuits electrically connected in the ring comprise at least three single-phase spot circuits (104, 106, 108). [11] The spot splitter (100) of any preceding claim, further comprising a spot removal circuit (425) having a spot input (DEIN) electrically connected to the spot output (OUT) of the first single-phase spot circuit (104) and a spot output (OUT) selectively providing a spot from the ring to a splitter output. [12] The spot splitter (100) of claim 11, further comprising an outer splitter circuit (401) configured to control the timing at which the spot removal circuit provides the spot from the ring to the splitter output. [13] The spot splitter (100) of claim 12, wherein the outer splitter circuit (401) comprises two or more outer spot circuits (411, 412, 413) electrically connected in a cascade. [14] Time-to-digital converter (500) comprising: two or more spot circuits electrically connected in a cascade and comprising a first single-phase spot circuit (104) having a spot input (DEIN), a spot output (AUS) and a clock input (CLKB), the first single-phase spot circuit (104) comprising: a first input field effect transistor (FET) (202) having a first polarity, electrically connected between a first supply node (VDD) and a signal node (V1), wherein a gate electrode of the first FET (202) is electrically connected to the spot input (DEIN), a clock FET (206) having a second polarity opposite to the first polarity, which is electrically connected to the clock input (CLKB), a second input FET (212) having the second polarity, electrically connected in series with the clock FET (206) between the signal node (V1) and a second supply node (VSS), and an output FET (208) having the first polarity, electrically connected between the first supply node (VDD) and the spot output (OUT), wherein a gate electrode (208) of the output FET is electrically connected to the signal node (V1), wherein the clock input (CLKB) is configured to receive a pulse signal, wherein the two or more spot circuits are configured to advance a spot signal in response to a first edge of the pulse signal and to interrupt the advance of the spot signal in response to a second edge of the pulse signal. [15] The time-to-digital converter of claim 14, wherein the first single-phase spot circuit (104) further comprises a buffered output FET (618) of the first polarity having a gate electrode electrically connected to the signal node (V1) and a drain electrode electrically connected to a buffered output (B). [16] The time-to-digital converter of claim 14 or 15, wherein the first single-phase spot circuit (104) further comprises a read FET (620) of the first polarity electrically connected in series with the buffered output FET (618) between the first supply node (VDD) and the buffered output (B), the buffered output FET (618) having a gate electrode receiving a read signal configured to prevent the buffered output (B) from changing state when a spot signal advances from the spot input (DIN) to the spot output (OUT). [17] A method for moving a spot using a single clock signal phase, the method comprising: Initializing, using at least one reset input (RST) or one set input (SB), a state of a single-phase spot circuit (104; 106; 108), Providing a spot signal for a spot input (DEIN) of the single-phase spot circuit (104; 106; 108), Providing a single-phase clock signal (CLK EIN ) which varies between a first logic voltage and a second logic voltage, for a clock input of the single-phase spot circuit (104; 106; 108), Blocking the transmission of the spot signal to a spot output (OUT) of the single-phase spot circuit (104; 106; 108) when the spot signal has the first logic voltage, and Transmitting the spot signal to the spot output (OUT) of the single-phase spot circuit (104; 106; 108) in response to a clock edge of the single-phase clock signal (CLK EIN ) when the spot input (YOUR) has the second logic voltage. [18] The method of claim 17, further comprising: Driving the spot input (DEIN) of the single-phase spot circuit (104; 106; 108) to the first logic voltage during one clock cycle of the clock edge after the spot signal has been transferred to the spot output (OUT). [19] Frequency divider, which has the following: a plurality of spot movement stages (104; 106; 108) electrically connected in a ring, wherein, when a spot signal is present in the ring, the plurality of spot movement stages (104; 106; 108) move the spot signal based on the timing of a single-phase clock signal (CLK EIN ) around the ring, wherein the plurality of spot movement stages (104; 106; 108) comprise a first spot movement stage (104) with a spot input (DEIN) for receiving the spot signal and a spot output (AUS) for forwarding the spot signal, and a spot removal circuit (425) having an input electrically connected to the spot output (OUT) of the first spot movement stage (104), the spot removal circuit (425) being configured to selectively remove the spot signal from the ring based on the state of a spot removal control signal, the spot removal circuit (425) further having an output providing a divided clock signal having a frequency corresponding to the rate at which the spot signal is removed from the ring. [20] A frequency divider according to claim 19, wherein the spot distance control signal is capable of controlling the number of round trips the spot signal makes around the ring. [21] A frequency divider according to claim 19 or 20, further comprising an outer divider circuit (401) adapted to generate the spot distance control signal. [22] A frequency divider according to claim 21, wherein the outer divider circuit (401) comprises two or more spot movement stages electrically connected in a cascade. [23] A frequency divider according to claim 21 or 22, wherein the plurality of spot movement stages are adapted to generate a circulating clock signal (CLK UMLAUF ) which controls the timing of the outer divider circuit (401), wherein the circulation clock signal (CLK UMLAUF ) has a frequency that corresponds to the time it takes for the spot signal to complete one orbit around the ring. [24] A frequency divider according to any one of claims 19 to 23, further comprising a spot insertion circuit configured to selectively insert the spot signal into the ring. [25] A frequency divider according to any one of claims 19 to 24, wherein the first spot movement stage (104) further comprises a feedback element (214) electrically connected between the spot output (OUT) and the spot input (DEIN), the feedback element (214) being capable of cancelling the spot signal from the spot input (DEIN) in response to the presence of the spot signal at the spot output (OUT). [26] A frequency divider according to any one of claims 19 to 25, wherein the first spot movement stage (104) comprises a clock n-type field effect transistor (NFET) (206), an input NFET (212) connected in series with the clock NFET (206) between a signal node (V1) and a first supply node (VSS), an input p-type field effect transistor (PFET) (202) connected between a second supply node (VDD) and the signal node (V1), a clock PFET (204), and an output PFET (208) electrically connected in series with the second PFET between the second supply node (VDD) and the spot output (OUT), wherein a gate electrode of the clock NFET (206) and a gate electrode of the clock PFET (204) receive the single-phase clock signal,wherein a gate electrode of the output PFET (208) is connected to the signal node (V1), and wherein a gate electrode of the input PFET (202) and a gate electrode of the input NFET (212) are connected to the spot input (DEIN). [27] Frequency divider according to one of claims 19 to 25, wherein the first spot movement stage (104) comprises an input NFET (262) connected between a first supply node (VSS) and a signal node (V1), a clock PFET (258), an input PFET (254) connected in series with the clock PFET (258) between the signal node (V1) and a second supply node (VDD), a clock NFET (264), and an output NFET (260) electrically connected in series with the clock NFET (264) between the first supply node (VSS) and the first spot output (OUT), wherein a gate electrode of the clock PFET (258) and a gate electrode of the clock NFET (264) receive the single-phase clock signal (CLK EIN), wherein a gate electrode of the output NFET (260) is connected to the signal node (V1), and wherein a gate electrode of the input NFET (262) and a gate electrode of the input PFET (254) are connected to the first spot input (DEIN). [28] Frequency divider according to one of claims 19 to 27, wherein the plurality of spot movement stages (104, 106, 108) comprise at least three spot movement stages (104, 106, 108). [29] A method for frequency division, the method comprising: Propagating a spot signal around a ring of multiple spot movement stages based on the timing of a single-phase clock signal (CLK EIN ), selectively removing the spot signal from the ring using a spot removal circuit (425) based on a spot removal control signal, and Generating a divided clock signal using the spot removal circuit (425), the divided clock signal having a frequency corresponding to the rate at which the spot signal is removed from the ring. [30] The method of claim 29, further comprising controlling the number of round trips the spot signal propagates around the ring using the spot distance control signal. [31] The method of claim 29 or 30, further comprising generating the spot distance control signal using an external divider circuit (401) having two or more spot movement stages electrically connected in a cascade. [32] Method according to one of claims 29 to 31, further comprising a circulation clock signal (CLK UMLAUF ) is generated based on the time it takes for the spot signal to complete one orbit around the ring. [33] The method of claim 32, wherein the spot distance control signal is further generated using an outer divider circuit (401) and the timing of the outer divider circuit (401) is controlled using the recirculating clock signal (CLK UMLAUF ) is controlled. [34] The method of any one of claims 29 to 33, further comprising inserting the spot signal into the ring using a spot insertion circuit. [35] The method of any one of claims 29 to 34, further comprising generating the spot signal during approximately one complete clock cycle of the single-phase clock signal (CLK EIN ) using at least one of the plurality of spot movement stages (104, 106, 108).

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