Semiconductor assembly, method and semiconductor package

Abstract

Semiconductor arrangement which features: a first FET (102) which is integrated within the semiconductor arrangement (200) and which has gate, source and drain terminals; a low-voltage switching device (118) that is integrated within the semiconductor arrangement (200) and that is configured to electrically short-circuit a gate-source capacitance of the first FET (102) in response to a control signal (DRV2); a semiconductor package (106) comprising an electrically conductive conductor frame (120) having gate, source, and drain leads, wherein the gate, source, and drain leads of the first FET (102) are each electrically connected to the gate, source, and drain leads of the conductor frame (120); and an inverter integrated in the semiconductor package (106) and having an input and output terminal, wherein the input terminal of the inverter is electrically connected to the gate terminal of the conductor frame (120), and wherein the output terminal of the inverter is electrically connected to the gate terminal of the low-voltage switching device (118).

Description

[0001] The present application relates to III nitride transistors and in particular to the control of the gate voltage of III nitride transistors.

[0002] Non-ideal transistor behavior is the so-called "unintended turn-off" and "unintended turn-on" effect. These effects refer to unintended switching behavior caused by negative voltage feedback to the gate during a switching event. Unintended turn-off occurs during an ON switching operation. Although the device receives a positive voltage (in the case of a positive-threshold device) intended to turn it ON, feedback generated by the switching operation reduces the voltage at the gate. If the feedback is large enough, this negative voltage will reduce the gate voltage below the device's threshold and initiate an OFF switching operation, i.e., the opposite of what is intended. A symmetrical effect occurs during a switch from ON to OFF, meaning the device temporarily turns itself back ON.

[0003] Unwanted turn-off and turn-on can occur in both high-power applications, such as those requiring switching high voltages like 200 V, 400 V, or more, and medium- or low-power applications, such as those requiring switching 20 V or less. In high-power applications, the relatively high voltage present at the transistor's output terminals (e.g., drain-source terminals) will decrease rapidly during a turn-on operation, and vice versa. Consequently, a large dV / dt signal will appear at the transistor's output terminals. GS (Gate-source capacity) and the C GD The gate-drain capacitance of the transistor acts as a capacitive voltage divider for this dVIdt. As a result, the gate capacitor of the transistor charges.

[0004] High-electron-mobility transistors (HEMTs) are generally preferred in power switching applications due to their advantageous power density, single-state resistance, switching frequency, and efficiency compared to, for example, silicon MOSFETs. A HEMT is a transistor with a heterojunction between two materials with different band gaps, such as GaN and AlGaN. In a GaN / AlGaN-based HEMT, a two-dimensional electron gas (2DEG) forms near the interface between the AlGaN barrier layer and the GaN buffer layer. In a HEMT, the 2DEG forms the device channel. Without further modification, the heterojunction configuration results in an intrinsically conductive (i.e., self-conducting) transistor. Numerous solutions exist to modify this intrinsically conductive configuration into a non-conducting (blocking) device.For example, a p-type GaN material can be incorporated into the gate structure of the HEMT to make the device a self-blocking device.

[0005] Unwanted switching on and off is particularly difficult to control in HEMT devices. Generally, an increase in C GS or V th(Threshold voltage) mitigates the problem, as the device can absorb more charge before the threshold is reached. This is difficult and / or costly to achieve in HEMTs due to the gate structure design. The problem can also be addressed by redesigning the gate driver circuitry. However, in many applications, the driver circuitry is provided externally. In this case, parasitic inductances and capacitances present between the driver circuitry and the power transistor can make it difficult or impossible to rapidly dissipate the charges from the device's gate.

[0006] US patent 7,834,669 B2 describes a source follower circuit with a first FET and a second FET, wherein a drain-source path of the second FET is connected between the gate and source of the first FET. The first FET and the second FET are each driven by the same drive signal.

[0007] DE 10 2009 002 732 A1 describes a circuit arrangement with a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element.

[0008] US patent 2015 / 0 171 852 A1 describes a circuit arrangement with an IGBT and a driver circuit for the IGBT. The driver circuit comprises three FETs whose drain-source paths are each connected between the base and emitter of the IGBT and which are controlled by a logic circuit.

[0009] One embodiment of the invention relates to a semiconductor arrangement according to claim 1. Further embodiments relate to a method according to claim 15 and a semiconductor housing according to claim 17.

[0010] The features and advantages of the invention will be apparent to a person skilled in the art upon reading the following detailed description and examining the accompanying drawings. The components in the figures are not necessarily to scale; instead, the emphasis is placed on illustrating the principles of the invention. Furthermore, in the figures, the same reference numerals denote corresponding parts. The following applies to the drawings:

[0011] Fig. Figure 1 illustrates a semiconductor arrangement with a power switching element according to one embodiment.

[0012] Fig. Figure 2 illustrates voltage and current waveforms during a switching event of the semiconductor arrangement. Fig. 1 according to one embodiment.

[0013] Fig. Figure 3 illustrates a semiconductor arrangement with a power switching element and a low-voltage switching element according to one embodiment.

[0014] Fig. Figure 4 illustrates voltage and current waveforms during a switching event of the semiconductor arrangement. Fig. 4 according to one embodiment.

[0015] Fig. Figure 5 illustrates voltage and current waveforms during a switching event of the semiconductor arrangement. Fig. 4 according to one embodiment.

[0016] Fig. Figure 6 illustrates a semiconductor package with a low-voltage switching device and a power HEMT integrated within the semiconductor package, according to one embodiment.

[0017] Fig. Figure 7 illustrates a semiconductor package with a low-voltage switching device and a power HEMT integrated within the semiconductor package, according to another embodiment.

[0018] Fig. Figure 8 illustrates a semiconductor package with a low-voltage switching device and a power HEMT integrated within the semiconductor package, according to another embodiment.

[0019] Fig. Figure 9 illustrates a semiconductor package with a low-voltage switching device and a power HEMT integrated within the semiconductor package, according to another embodiment.

[0020] Fig. Figure 10 illustrates a semiconductor package with a low-voltage switching device and a power HEMT integrated within the semiconductor package, according to another embodiment.

[0021] According to the embodiments described herein, a semiconductor arrangement is provided comprising a first field-effect transistor (FET) and a low-voltage switching device integrated within the same semiconductor package. The low-voltage switching device can be monolithically integrated in the same die as the first FET or, alternatively, can be provided in a separate die. The low-voltage switching device is connected to the first FET in a clamping configuration, thus stabilizing the gate voltage of the first FET. In particular, the output terminals of the low-voltage switching device (e.g., a source and drain terminal) are connected via the input terminals (e.g., a gate and source terminal) of the first FET. In this way, the low-voltage switching device can be operated to prevent unwanted turn-on or turn-off of the first FET.When the first FET is in the OFF state, the low-voltage switching device is ON and therefore maintains the gate-source voltage V. GS of the first FET to zero. In this state, the gate-source capacitor C GS The first FET is electrically short-circuited. When the first FET is in the ON state, the low-voltage switching device is OFF and holds the V GS of the first FET above the threshold.

[0022] The low-voltage switching device is advantageously placed within the package close to the first FET. This minimizes parasitic inductances and capacitances and provides an effective way to control the unwanted turn-on effect at low power. In comparison, current control using an external gate driver is less effective due to the parasitic capacitance and inductance between the gate driver and the first FET. Furthermore, the intrinsic capacitances of the low-voltage switching device can be added to the gate capacitances C. GS of the first FET to stabilize the gate voltage of the first FET and reduce unwanted turn-on without adversely affecting turn-off speed.

[0023] With reference to Fig. Figure 1 comprises a semiconductor arrangement 100, a first FET 102, and a first gate driver 104. In one embodiment, the first FET 102 is a self-blocking (i.e., enhancement) GaN-based HEMT device. Alternatively, the first FET 102 can be any other type of FET device, such as a silicon-based MOSFET or IGBT. The first gate driver 104 is configured to generate a first control signal that switches the first FET 102 between ON / OFF states in a generally known manner. That is, the first gate driver 104 generates a high voltage (e.g., 4 V) that turns the first FET 102 ON and a low voltage (e.g., 0 V) ​​that turns the first FET 102 OFF. In the embodiment shown in Figure 1, the first gate driver 104 is configured to generate a first control signal that switches the first FET 102 between ON / OFF states in a generally known manner. Fig. 1 is the first gate driver 104 external to the semiconductor package 106, in which the first FET 102 is provided. For example, the semiconductor package 106 and the first gate driver 104 can both be part of an assembly connected by a printed circuit board (PCB). Alternatively, the first gate driver 104 can be integrated into the semiconductor package 106.

[0024] With reference to Fig. Figure 2 shows a switching operation of the semiconductor arrangement 100. The drain-source voltage 108 of the first FET 102 is represented by the top curve. The gate-source voltage 110 of the first FET 102 is represented by the middle curve. The displacement current 112 in the gate-drain capacitor of the first FET 102 is represented by one of the bottom curves, and the displacement current 114 in the gate-source capacitor of the first FET 102 is represented by the other of the bottom curves.

[0025] Initially, the first FET 102 is switched OFF. At this time, the gate-source voltage 110 is at 0 V, and a voltage of 400 V is observed between the drain and source terminals of the first FET 102. This is merely an example, and the phenomenon described here can occur with a wide variety of devices under various conditions, including switching voltages of 20 V, 200 V, 400 V, 600 V, or higher. A switch-on operation of the first FET 102 is initiated by a rise in the gate-source voltage 110 of the first FET 102. This causes the FET 102 to enter conduction mode. Consequently, a dramatic drop in the drain-source voltage 108 occurs. That is, the drain-source voltage 108 experiences a large dV / dt. This large dV / dt propagates via a capacitive voltage divider, which is the gate-source capacitance C. GS of the first FET 102 and the gate-drain capacitance C GDThis includes the gate-source capacity C. In this example, the amount of the gate-source capacity is C. GS The voltage of the first FET 102 is not large enough to absorb all the charges associated with its dV / dt. Consequently, the gate-source voltage 110 must drop to dissipate these excess charges away from the gate terminal of the first FET 102. This drop is shown by the downward movement 116 of the gate-source voltage 110.

[0026] The downward movement 116 of the gate-source voltage 110 is strong enough to fall below V THThe charge of the first FET 102 drops. As a result, the first FET 102 begins to turn off again. Accordingly, an "unwanted turn-off" event occurs. As shown by the curves, the first FET 102 then oscillates between being turned on and off due to a feedback loop effect. Eventually, enough charge is dissipated from the gate of the first FET 102 to break this feedback loop and keep the first FET 102 in an ON state. The device remains in an ON state until a turn-off event occurs. During this time, due to the symmetry of the problem, a corresponding "unwanted turn-on" event occurs. As can be seen, the "unwanted turn-off" and the "unwanted turn-on" add a significant delay to the switching operation and also result in considerable energy losses.

[0027] With reference to Fig. Figure 3 shows a semiconductor arrangement 200 configured to mitigate the “undesired turn-on” effect described above. The semiconductor arrangement 200 includes a semiconductor package 106 containing the first FET 102 and a first gate driver 104 configured to control the operation of the first FET 102 as described previously. Furthermore, a low-voltage switching device 118 is provided within the semiconductor package 106. The low-voltage switching device 118 can be any of a variety of switching devices. According to one embodiment, the low-voltage switching device 118 is a GaN-based HEMT. Likewise, the first FET 102 is a GaN-based HEMT. Alternatively, the low-voltage switching device 118 can be any other type of switching device, such as a silicon- or silicon nitride-based FET.

[0028] The properties of the low-voltage switching device 118 are correlated with the properties of the first FET. "Correlated" refers to a proportional relationship, e.g., 3X, 5X, etc. Such a correlation exists between the V TH of the first FET 102 and the rated reverse voltage of the low-voltage switching device 118. Unlike the first FET 102, the low-voltage switching device 118 only needs to block a sufficient voltage to keep the first FET 102 above or below its threshold. Accordingly, the rated reverse voltage of the first FET 102 can be as low as twice the threshold voltage of the first FET 102 (i.e., a rated reverse voltage of 8 V in the case that the first FET has a V TH(of 4V). In one embodiment, the nominal reverse voltage of the low-voltage switching device 118 is five times the threshold voltage of the first FET 102. Another correlation exists between the voltage drop of the first FET 102 and the threshold voltage of the first FET 102 under arbitrary operating conditions. The voltage drop is defined as the R DSONThe (on-resistance) of the low-voltage switching device 118 is multiplied by the maximum displacement current of the first FET 102. Maintaining this correlation ensures that the low-voltage switching device 118 can be switched ON without inadvertently switching on the first FET 102. The low-voltage switching device 118 is considered "low voltage" because it does not need to block essentially high voltages, such as the voltages of 200 V, 400 V, or more that the first FET 102 might be designed to handle. The characteristics described above can be achieved by a relatively small device (compared to the first FET 102) that dissipates very little power.

[0029] The low-voltage switching device 118 has its drain and source terminals connected via the gate and source terminals of the first FET 102. Accordingly, when the low-voltage switching device 118 is switched ON, the gate terminal of the first FET 102 is connected to the source terminal of the first FET 102, and the gate-source capacitance of the first FET 102 is electrically short-circuited. In the illustrated embodiment, the drain of the low-voltage switching device 118 is connected to the gate of the first FET 102, and the source of the low-voltage switching device 118 is connected to the source of the first FET 102. However, if the gate-source blocking capability of the low-voltage switching device is sufficient, the orientation can be reversed, with the source of the low-voltage switching device 118 being connected to the gate of the first FET 102 and the drain of the low-voltage switching device 118 being connected to the source of the first FET 102.

[0030] The assembly made of Fig. 3 further includes a second gate driver 119, which is located outside the semiconductor package 106 and is connected to the gate terminal of the low-voltage switching device 118. The second gate driver 119 is configured to generate a second control signal, different from the first control signal, and controls a conductive state of the low-voltage switching device 118. Accordingly, the second control signal can be used to short-circuit the gate-source capacitance of the first FET 102 independently of, or out of phase with, the switching operation of the first FET 102.

[0031] With reference to Fig. Figure 4 shows a switching operation of the semiconductor arrangement 200. The drain-source voltage 108, the gate-source voltage 110, and the displacement currents 112, 114, as previously described with reference to Fig. 2 described, are in Fig. 4 is represented accordingly. In this embodiment, the first FET 102 is represented in a similar manner to that described in reference to Fig. As described in section 2, when the first FET 102 is switched ON, an unwanted switch-off is observed. However, when the first FET 102 is switched OFF, an unwanted switch-on condition is avoided. When the first FET 102 is switched OFF, the low-voltage switching device 118, which is controlled by the (not shown) second control signal, is switched ON, and the gate-source capacitance C GS The first FET 102 is electrically short-circuited. As a result, the charges that appear at the gate of the first FET 102 are quickly dissipated by the low-voltage switching device 118, and the gate voltage can easily transition from high to low.

[0032] With reference to Fig. Figure 5 shows a switching operation of the semiconductor arrangement 200 according to another embodiment. The in Fig. The semiconductor arrangement 5 used was modified so that the unwanted ON switching no longer occurs. In particular, the gate-source capacitance of the first FET 102 was compared to the gate-source capacitance of the one in Fig. The capacitance of the first FET 102 used in the 4th step was intentionally increased (e.g., by 3x). This can be achieved by using a discrete capacitor or by modifying the gate structure of the first FET 102. Furthermore, since the low-voltage switching device 118 is connected between the gate and source terminals of the first FET 102, the intrinsic capacitances associated with the first FET 102 (e.g., C) are also increased. DS , C GS etc.), the C GS -value in the capacitive voltage divider of the first FET 102. As a result, the gate-source voltage 110 remains above the threshold and the device remains switched ON.

[0033] With reference to Fig. Figure 6 shows a configuration of the semiconductor package 106 according to one embodiment. The semiconductor package 106 includes a conductor frame 120. The conductor frame 120 is made of an electrically conductive material, such as copper, aluminum, etc., and alloys thereof. The conductor frame 120 includes four connection lines: a first gate connection line 122, a second gate connection line 124, a source connection line 126, and a drain connection line 128. All of these connection lines 122, 124, 126, and 128 are electrically insulated and separated from each other. That is, all connection lines 122, 124, 126, and 128 each form separate electrical nodes.

[0034] A first die 130 is mounted on the conductor frame 120. In this embodiment, the first die 130 includes both the first FET 102 and the low-voltage switching device 118. For example, the first die 130 can be a GaN chip, with both the first FET 102 and the low-voltage switching device 118 being GaN devices. The connection between the drain terminal of the low-voltage device 118 and the gate terminal of the first FET 102 is provided by an intermediate connection at the chip level of the first die 130. Accordingly, the parasitic capacitance at this connection is minimal. The remaining electrical connections can be provided by an intermediate connection at the package level.In the illustrated embodiment, a first bond wire 132 (or wires) connects the gate terminal of the first FET 102 to the first gate lead 122, a second bond wire 134 (or wires) connects the gate terminal of the low-voltage switching device 118 to the second gate lead 124, a third bond wire 136 (or wires) connects the drain terminal of the first FET 102 to the drain lead 128, and a fourth bond wire 138 (or wires) connects the source terminals of both devices to the source lead 126. Alternatively, a different interconnection technique can be used at the package level. For example, a PCB or clamps can be used to connect the terminals of the first die 130 to the associated external leads of the semiconductor package 106.

[0035] With reference to Fig. Figure 7 shows a configuration of the semiconductor package 106 according to another embodiment. In the embodiment from Fig. In Figure 7, the first FET 102 and the low-voltage switching device 118 are implemented in two separate dies. Specifically, the first FET 102 is monolithically integrated into a first die 130, and the low-voltage switching device 118 is monolithically integrated into a second die 140, which is adjacent to the first die 130. Both the first and second dies 130 and 140 are mounted on the conductor frame 120, with their bottom surfaces directly connected to and facing the conductor frame 120. The top surfaces 142 and 144 of the first and second dies 130 and 140, which face the bottom surfaces, are oriented away from the conductor frame 120. Both the first FET 102 and the low-voltage switching device 118 are designed as lateral devices, with a gate, source and drain terminal of each switching device arranged on the top side 142, 144 of the respective die.For example, this configuration can be implemented if both the first FET 102 and the low-voltage switching device 118 are self-blocking lateral HEMT devices. The first, second, third, and fourth bond wires 132, 134, 136, and 138 are connected in a similar manner as described in [reference to be added]. Fig. 7 described, connected. Furthermore, a fifth bond wire 146 provides the electrical connection between the drain terminal of the low-voltage switching device 118 and the gate terminal of the first FET 102. The fifth bond wire 146 connects the drain terminal of the low-voltage switching device 118 to the first gate terminal 122, which in turn is connected to the gate terminal of the first FET 102. Consequently, all of the electrical connections between the first die 130, the second die 140, and the conductor frame 120 are each provided by bond wires at the package level. Alternatively, any of the connections described in Fig. The bond wires shown in Figure 7 can be replaced by other forms of intermediate connections at the housing level, such as a PCB or clamps.

[0036] With reference to Fig. Figure 8 shows a configuration of the semiconductor package 106 according to another embodiment. In the embodiment from Fig. In Figure 8, the low-voltage switching device 118 is implemented as a vertical MOSFET. The gate and source terminals of the low-voltage switching device 118 are located on the top side 144 of the second die 140, and the drain terminal of the low-voltage switching device 118 is located on the bottom side of the second die 140. Because the drain terminal of the second die 140 faces the conductor frame 120, electrical isolation is required between the second semiconductor die and the conductor frame 120 to prevent the drain of the low-voltage switching device 118 from being short-circuited with the source of the first FET 102. This electrical isolation is provided by a DCB substrate 148 (DCB: Direct Copper Bond) located between the bottom side of the second die 140 and the conductor frame 120.A fifth bond wire 146 is used, which connects the DCB substrate (DCB: Direct Copper Bond) to the first gate connection line 122.

[0037] With reference to Fig. Figure 9 shows a configuration of the semiconductor package 106 according to another embodiment. The semiconductor package 106 is made of Fig. Embodiment 9 differs from the previous embodiments in that it includes an inverter integrated within the housing 106. According to the illustrated embodiment, the inverter is provided by a third die 150, which is mounted adjacent to the first and second dies 130, 140. The low-voltage switching device 118 and the first FET 102 are integrated into the first and second dies 130, 140, as previously discussed. Alternatively, the inverter can be integrated into either the first or the second die 130, 140. An input terminal of the inverter is electrically connected to the first gate terminal 122. Accordingly, the inverter receives the same input signal as the first FET 102. An output terminal of the inverter is electrically connected to the gate terminal of the low-voltage switching device 118 via a sixth bond wire 152.The inverter can receive a power supply from a separate connection line 154 of the ladder frame.

[0038] The configuration from Fig. 9 uses the signal applied to the first gate connection line to provide the first and second control signals for the first FET 102 and the low-voltage switching device 118, respectively. In this case, the second control signal is the logic complement of the first control signal. That is, the low-voltage switching device 118 is OFF when the first FET 102 is ON, and vice versa. Consequently, the in Fig. The second gate driver 119 shown in Figure 3 can be removed from the precursor circuit, and the first gate driver 104 can be used to control both the first FET 102 and the low-voltage switching device 118. Furthermore, the second gate connection 124 can be removed from the circuit board, since both the first FET 102 and the low-voltage switching device 118 receive their control signals (either directly or indirectly) from the first gate connection 122. Other solutions can be implemented to achieve equivalent functionality and eliminate one of the gate connections. For example, instead of providing the inverter, the low-voltage switching device 118 can be implemented as a self-conducting JFET device, in which a positive voltage turns the device off. That is, the low-voltage switching device 118 can be configured in a complementary way to the FET 102.In this way, when one is switched OFF, the other is switched ON, and vice versa. In this case, the gates of both the low-voltage switching device 118 and the FET 102 can be directly connected to the first gate terminal 122.

[0039] With reference to Fig.Figure 10 shows a side view of the semiconductor package 106 according to another embodiment. In this embodiment, the first FET 102 and the low-voltage switching device 118 are implemented in a first and second (separate) die. However, unlike the previous embodiments, in this embodiment the second die 140, which contains the low-voltage switching device 118, is mounted directly on the first die 130, which contains the first FET 102. The second die 140 includes a gate terminal 156 that is sufficiently large to accommodate both a connection to the second die 140 and an area for connecting the first bond wire 132, which connects the gate terminal 156 of the first FET 102 to the gate lead 122.The second die 140 is configured such that the drain terminal 158 of the low-voltage switching device 118 is located on one side, and the source and gate terminals 162 face opposite sides. The drain terminal 158 is directly connected to the gate terminal 156 of the first FET 102, thus providing an electrical connection with minimal parasitic capacitance. The other connections (not shown) can be made in a similar manner as previously discussed.

[0040] Spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, are used for the sake of simplicity to describe the positioning of one element relative to another. These terms are intended to encompass various orientations of the building element, in addition to the different orientations depicted in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and these are not intended to be restrictive. Throughout the description, identical terms refer to identical elements.

[0041] As used here, the terms "possessing," "containing," "encompassing," "comprehensive," and the like are open terms that indicate the presence of the specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

Claims

[1] Semiconductor arrangement comprising: a first FET (102) which is integrated within the semiconductor arrangement (200) and which has gate, source and drain terminals; a low-voltage switching device (118) that is integrated within the semiconductor arrangement (200) and that is configured to electrically short-circuit a gate-source capacitance of the first FET (102) in response to a control signal (DRV2); a semiconductor package (106) comprising an electrically conductive conductor frame (120) having gate, source, and drain leads, wherein the gate, source, and drain leads of the first FET (102) are each electrically connected to the gate, source, and drain leads of the conductor frame (120); and an inverter integrated in the semiconductor package (106) and having an input and output terminal, wherein the input terminal of the inverter is electrically connected to the gate terminal of the conductor frame (120), and wherein the output terminal of the inverter is electrically connected to the gate terminal of the low-voltage switching device (118). [2] Semiconductor arrangement according to claim 1, wherein a nominal reverse voltage of the low-voltage switching device (118) is correlated with a threshold voltage of the first FET (102). [3] Semiconductor arrangement according to claim 2, wherein the nominal reverse voltage of the low-voltage switching device (118) is less than or equal to five times the threshold voltage of the first FET (102). [4] Semiconductor arrangement according to claim 2 or 3, wherein a forward voltage drop of the low-voltage switching device (118) is smaller than the threshold voltage of the first FET (102). [5] Semiconductor arrangement according to one of the preceding claims, wherein the first FET (102) is a self-blocking HEMT and wherein the low-voltage switching device (118) is a transistor having gate, source and drain terminals, wherein the conductor frame (120) also has a second gate connection line (124), and wherein the source and drain terminals of the low-voltage switching device (118) are connected to the gate and drain terminals of the first FET (102). [6] Semiconductor arrangement according to claim 5, wherein the first FET (102) and the low-voltage switching device (118) are monolithically integrated in a single die (130) and wherein the connection between the drain terminal of the low-voltage switching device (118) and the gate terminal of the first FET (102) is provided by a connection that is internal in the single die (130). [7] Semiconductor arrangement according to claim 5, wherein the first FET (102) is monolithically integrated in a first die (130) mounted on a conductor frame (120), and the low-voltage switching device (118) is monolithically integrated in a second die (130, 140) mounted on the conductor frame (120). [8] Semiconductor arrangement according to claim 7, wherein the first die (130) is mounted directly on the conductor frame (120) and the second die (140) is mounted directly on the conductor frame (120) adjacent to the first die (130). [9] Semiconductor arrangement according to claim 7, wherein the first die (130) is mounted directly on the conductor frame (120) and the second die (140) is mounted directly on the conductor frame (120). [10] Semiconductor arrangement according to claim 7, wherein the low-voltage switching device (118) is a self-blocking HEMT and wherein the gate, source and drain terminals of the low-voltage switching device (118) are arranged on an upper side of the second die (140) facing away from the conductor frame (120). [11] Semiconductor arrangement according to claim 7, wherein the low-voltage switching device (118) is a vertical MOSFET, wherein the gate and source terminals of the low-voltage switching device (118) are arranged on an upper side of the second die (140) facing away from the conductor frame (120), wherein the drain terminal of the low-voltage switching device (118) is arranged on a lower side of the second die (140) facing the conductor frame (120), and wherein the semiconductor package (106) further comprises a DCB substrate (148) arranged between the lower side of the second die (140) and the conductor frame (120). [12] Semiconductor arrangement according to one of claims 5 to 11, wherein the gate terminals of the first FET (102) and the low-voltage switching device (118) are each connected to the same connecting line. [13] Semiconductor arrangement according to any one of claims 5 to 12, further comprising: a first gate driver (104) which is located outside the semiconductor package (106) and is configured to generate a first control signal which controls an ON / OFF state of the first FET (102). [14] Semiconductor arrangement according to claim 13, further comprising: a second gate driver (119) which is arranged outside the semiconductor housing (106) and is configured to generate a second control signal which controls an ON / OFF state of the low-voltage switching device (118). [15] Method for operating a semiconductor arrangement comprising a first FET (102) integrated within the semiconductor arrangement (200) and having gate, source and drain terminals, and a low-voltage switching device (118) integrated within the assembly and connected to the gate and source terminals of the first FET (102), wherein the method comprises: Applying an initial control signal to the first FET (102), which switches the first FET (102) between an ON / OFF state; and Applying a second control signal to the low-voltage switching device (118), which short-circuits a gate-source capacitance of the first FET (102) during the OFF state of the first FET (102), wherein the application of the first control signal involves the use of a first gate driver (104) located outside the semiconductor arrangement (200), and the application of the second control signal involves the use of a second gate driver (119) located outside the semiconductor arrangement (200). [16] Method according to claim 15, wherein the application of the first control signal comprises the use of a first gate driver (104) located outside the semiconductor arrangement (200) and wherein the application of the second control signal comprises the use of an inverter located inside the semiconductor arrangement (200). [17] Semiconductor package which features: an electrically conductive conductor frame (120); a first FET (102) integrated within the semiconductor package (106); and a low-voltage switching device (118) integrated within the semiconductor package (106) and having gate, source and drain terminals, and terminated to the first FET (102) such that intrinsic capacitances of the low-voltage switching device (118) are added to a gate-source capacitance of the first FET (102), wherein the first FET (102) and the low-voltage switching device (118) each include control terminals that can be controlled independently.

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