Semiconductor component with air spacer and manufacturing process

Abstract

Procedure (100) with the following steps: Fabricating a gate structure (208) on a substrate (202); Manufacturing a sealing spacer (214) that covers one side wall of the gate structure (208); Producing a sacrificial spacer (216) that covers one side wall of the sealing spacer (214); Creating S / D regions (218, 218a) with a channel region (224) in between, which is located under the gate structure (208); Deposition of a CES layer (220) covering a side wall of the sacrificial spacer (216); Deposition of a dielectric layer (228) covering the substrate (202); Structuring the dielectric layer (228) such that a via opening (230) is created which exposes one of the S / D regions (218, 218a); Establishing an S / D contact (232) in the through-hole (230); After establishing the S / D contact (232), remove the dielectric layer (228) to expose a top surface of the sacrificial spacer (216); Removing the sacrificial spacer (216) to create a trench (250), the trench (250) extending between a side wall of the CES layer (220) and the side wall of the sealing spacer (214); and Deposition of an ILD layer (252), wherein the ILD layer (252) caps the trench (250), thereby defining an air gap in the trench (250).

Description

Background of the invention

[0001] The IC (semiconductor integrated circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. Over the course of IC evolution, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component or circuit that can be created using a manufacturing process) has decreased. This process of downsizing generally offers benefits by increasing production output and reducing corresponding costs. However, this downsizing has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required.

[0002] For example, it is generally desirable to reduce the stray capacitance between the structural elements of field-effect transistors, such as the capacitance between a gate structure and source / drain contacts, to increase switching speed, reduce switching power consumption, and / or reduce the coupling noise of the transistors. Certain low-k materials with a lower dielectric constant than that of silicon oxide have been proposed as insulating materials, offering a lower relative dielectric constant, to reduce stray capacitance. As semiconductor technology evolves toward smaller feature sizes, the distances between the gate structure and the source / drain contacts are further reduced, still resulting in large stray capacitance.Therefore, existing approaches to transistor manufacturing are not entirely satisfactory in all respects, even though they have generally been sufficient so far.

[0003] Publication US 2013 / 0 248 950 A1 discloses a method for manufacturing a semiconductor device. The method comprises fabricating a gate structure with a multilayer spacer structure. A layer of the spacer structure can be removed, and a dielectric can be deposited over the resulting structure to create cavities between S / D contacts and the gate structure.

[0004] US 2007 / 0 296 039 A1 discloses various methods for fabricating semiconductor structures with voids. One method involves evaporating a volatile spacer layer through a porous conformal spacer layer in an annealing process, allowing voids to form around the gate structure. In another method, a conformal stress layer is formed over junction spacers, and an access path is etched through the stress layer to selectively remove the junction spacers. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 is a flow diagram of a method of manufacturing a semiconductor device according to various aspects of the present invention. The Fig. 2A, Fig. 2B, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B and Fig. 9 are sectional views of a portion of a semiconductor device manufactured by the method of Fig. 1, according to some embodiments. Detailed description

[0006] Improved manufacturing methods and an improved structure that address the foregoing problems are provided according to claims 1, 10, and 15. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. The fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated throughout the various examples in the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] The present invention generally relates to semiconductor devices and methods for fabricating them. More particularly, the present invention relates to providing methods and structures for reducing stray capacitance between a gate structure and source / drain contacts of field-effect transistors (FETs) during semiconductor fabrication. In FET fabrication, it is desirable to increase switching speed, lower switching power consumption, and reduce coupling noise. Stray capacitance generally has a negative impact on these parameters, particularly the stray capacitance between a gate structure and source / drain contacts. As semiconductor technology evolves toward smaller feature sizes, the distances between the gate and the source / drain contacts shrink, resulting in larger stray capacitance. Therefore, stray capacitance has become more problematic in FETs.The present invention offers solutions instead of the spacers conventionally made of a solid dielectric material by proposing the fabrication of air spacers surrounding the gate structures, thereby reducing the relative permittivity (or dielectric constant) between the gate and the source / drain contacts and thereby reducing the stray capacitance.

[0009] Fig. 1 illustrates a flow diagram of a method 100 for fabricating semiconductor devices according to the present invention. The method 100 is an example and is not intended to limit the present invention beyond what is expressly set forth in the claims. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be replaced, omitted, or shifted in further embodiments of the method. The method 100 is described below in connection with the Fig. 2 to 9, which show cross-sectional views of a semiconductor device 200 during various manufacturing steps according to an embodiment of the method 100. The device 200 may be an intermediate device formed during processing of an integrated circuit (IC) or a portion thereof, and may include static random access memory (SRAM) or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as pFETs (pFETs), n-FETs (nFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.Moreover, the various structural elements, such as transistors, gate stacks, active regions, isolation structures, and other structural elements, are provided in various embodiments of the present invention for convenience and understanding and do not necessarily limit the embodiments to any type of device, number of devices, number of regions, or configuration of structures or regions.

[0010] In step 102, the method 100 ( Fig. 1) a precursor of the component 200 ( Fig. 2A). For ease of discussion, the precursor to device 200 is also referred to as device 200. Device 200 may include a substrate 202 and various structural elements fabricated therein or thereon. Substrate 202 is a silicon substrate in the present embodiment. Alternatively, substrate 202 may also include: another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, substrate 202 is a semiconductor on insulator (SOI).

[0011] In some embodiments, the substrate 202 includes an insulator (or isolation structure), which may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or another suitable isolation material. The insulator may be a shallow trench isolation (STI) feature. In one embodiment, the insulator is formed by etching trenches in the substrate 202, filling the trenches with an isolation material, and performing a chemical mechanical planarization (CMP) process on the substrate 202 with the isolation material. The substrate 202 may include one or more further isolation structures, such as field oxide and a local oxidation of silicon (LOCOS) structure. The substrate 202 may be a multilayer isolation structure.

[0012] In step 104, the method 100 ( Fig. 1) one or more FETs 204 (e.g., FETs 204a and 204b) are fabricated on the substrate 202 ( Fig. 2A). FETs 204 may be nFETs, p-FETs, or a combination thereof. In some embodiments, FETs 204a and 204b are both n-FETs, or they are both p-FETs. In alternative embodiments, FET 204a is an n-FET, and FET 204b is a p-FET.

[0013] Each FET 204 includes a gate stack 208. The gate stack 208 is disposed above the substrate 202. In various embodiments, the gate stack 208 is a multi-layer structure. The gate stack 208 may include a gate dielectric layer 210 and a gate electrode layer 212. In some embodiments, the gate dielectric layer 210 further includes a high-k dielectric layer and an interlayer sandwiched between the substrate 202 and the high-k dielectric layer. In various embodiments, the interlayer may comprise a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer is formed using a suitable process such as atomic layer deposition (ALD).Other methods for forming the high-k dielectric layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV ozone oxidation, and molecular beam epitaxy (MBE). In one embodiment, the high-k dielectric material comprises hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof. Alternatively, the high-k dielectric material comprises metal nitrides or metal silicates.

[0014] In some embodiments, the gate electrode layer 212 may be a polysilicon layer or a metal gate electrode layer. The metal gate electrode layer may further comprise multiple layers, such as a work function metal layer and a metal fill layer. The work function metal layer may be a p-type work function metal layer or an n-type work function metal layer. The p-type work function metal layer comprises a metal selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof, among others. The n-type work function metal layer comprises a metal selected from the group consisting of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof, among others.The p-type or n-type work function metal layer may further comprise a plurality of layers and may be deposited by CVD, PVD, and / or another suitable method. The one or more metal layers may comprise aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials and may be formed by CVD, PVD, plating, and / or other suitable methods. The metal fill layer may comprise aluminum (Al), tungsten (W), or copper (Cu) and / or other suitable materials and may be formed by CVD, PVD, plating, and / or other suitable methods.

[0015] A gate spacer is fabricated on the sidewalls of each gate stack 208. In Fig. 2A, in various embodiments, the gate spacer may include multiple layers, such as a sealing spacer 214 and a dummy spacer 216. The sealing spacer 214 comprises a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), another dielectric material, or a combination thereof. The sealing spacer 214 protects the four approximately vertical sides of the gate stack 208. The dummy spacer 216 may be made of silicon oxide (SiO2), aluminum oxide (AlO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon carbon oxynitride (SiCON). Typically, the compositions of the sealing spacer 214 and the dummy spacer 216 are selected such that the sealing spacer 214 has a higher etch selectivity than the dummy spacer 216.The dummy spacer 216 is removed in subsequent steps of the method 100, creating a cavity as an air spacer, while the sealing spacer 214 substantially remains. Therefore, the dummy spacer 216 is also referred to as a sacrificial spacer 216. The formation of the air spacer will be described in more detail later. In one example, the sealing spacer 214 is formed by protectively depositing a dielectric layer (e.g., a silicon nitride layer with a substantially constant thickness) over the device 200 using a CVD process and then anisotropically etched to remove portions of the dielectric layer to create the sealing spacer 214. The sacrificial spacer 216 may be formed using a similar process. In some embodiments, the sacrificial spacer 216 has a thickness in the range of about 2 nm to about 4 nm.

[0016] Source / drain (S / D) regions 218 are also formed in the substrate 202. The S / D regions 218 may be n-doped regions and / or p-doped regions for forming active devices. The S / D regions 218 may be heavily doped S / D regions (HDD regions), lightly doped S / D regions (LDD regions), raised regions, strained regions, epitaxially grown regions, and / or other suitable features. The S / D regions 218 may be formed by etching and epitaxial growth, S / D implantation, S / D activation, and / or other suitable methods. In one embodiment, the S / D regions 218 further include silicidation or germanosilicidation regions.Silicidation may be achieved, for example, with a process comprising the following steps: depositing a metal layer, annealing the metal layer so that the metal layer can react with the silicon to form silicide, and then removing the unreacted metal layer. In one embodiment, the device 200 includes fin-like active regions for fabricating multi-gate FETs, such as FinFETs. Furthermore, in this embodiment, the S / D regions 218 and a channel region 224 may be formed in or on the fins. The channel region 224 is located beneath the gate stack 208 and sandwiched between a pair of S / D regions 218. The channel region 224 conducts currents between the respective S / D regions 218 when the semiconductor device 200 is turned on, such as by biasing the gate electrode layer 212.

[0017] Furthermore, Fig. 2A, in the present embodiment, the S / D regions 218 are formed by first etching S / D recesses in the substrate 202 and then epitaxially growing the S / D regions 218 in the respective recesses. Due to the profile of the S / D recesses, the S / D regions 218 may have a substantially U-shaped profile, and a sidewall of each of the S / D regions 218 is substantially aligned with the edge (or outer boundary) of the sacrificial spacer 216. The respective sidewall has a distance 260 from the gate stack 208. In some embodiments, the distance 260 is in the range of about 2 nm to about 10 nm.In some embodiments where the spacers 214 / 216 are thicker than desired, thereby increasing the spacing 260, and yet still wanting the spacing 260 to be within a smaller range, the S / D regions 218 may be fabricated to have a substantially diamond-shaped profile, such as S / D regions 218a in FIG. Fig. 2B. In Fig. 2B, some sidewalls of the S / D regions 218a extend under the spacers 214 / 216 to the gate stack 208. In one example, the S / D recesses are formed using an etch process comprising a dry etch and a wet etch process, wherein the etch parameters [such as the etchants used, etch temperature, etch solution concentration, etch pressure, voltage source power, radio frequency (RF) bias voltage, RF bias power, etchant throughput, and other suitable parameters] are adjusted to achieve the desired recess profile. For ease of discussion, the device 200 with the S / D regions is shown in Fig. 2A is used as an example for subsequent steps. Those skilled in the art will recognize that the device 200 with the S / D regions in the form shown in Fig. The form shown in Figure 2B can also be used for the subsequent steps.

[0018] Let’s get to Fig. 2A. In the present embodiment, device 200 includes a contact etch stop layer (CES layer) 220 over substrate 202 and on sidewalls of sacrificial spacer 216, and an interlayer dielectric (ILD) layer 222 over CES layer 220. CES layer 220 may include a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), other dielectric materials, or a combination thereof. CES layer 220 may be formed by plasma-enhanced chemical vapor deposition (PECVD) and / or other suitable deposition or oxidation techniques.The ILD layer 222 may include the following materials: silicon oxide, doped silicon oxide, such as borophosphosilicate glass (BPSG), tetraethylorthosilicate oxide (TEOS oxide), undoped silica glass, fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), low-k dielectric materials, and / or other suitable dielectric materials. The ILD layer 222 may be formed using PECVD, flowable chemical vapor deposition (FCVD), or another suitable deposition method. The compositions of the CES layer 220 and the ILD layer 222 are selected such that the CES layer 220 has a higher etch selectivity than the ILD layer 222. In one embodiment, the CES layer 220 is deposited as a protective layer over the substrate 202 to cover various structures thereon, and the ILD layer 222 is deposited over the CES layer 220. The method 100 then proceeds (. Fig. 1) to step 106, where a chemical mechanical planarization (CMP) is performed to polish the ILD layer 222 and expose the gate stack 208 ( Fig. 2A). This leaves portions of the CES layer 220 above the substrate 202 between adjacent sacrificial spacers 216.

[0019] In step 108, in the method 100 ( Fig. 1) another ILD layer 228 is formed over the component 200 ( Fig. 3). The ILD layer 228 may comprise silicon oxide, a low-k dielectric material, or another suitable dielectric material deposited by CVD or another suitable method. The ILD layer 228 may be formed, for example, by PECVD, FCVD, or other suitable deposition methods. In some embodiments, the ILD layer 228 may comprise a different or the same material as the ILD layer 222. A CMP process may follow step 108 to remove excess dielectric materials.

[0020] In step 110, in the method 100 ( Fig. 1) the ILD layer 228 is structured to form S / D via openings 230 over the S / D regions 218 ( Fig. 4). In one embodiment, step 110 includes a photolithographic process and an etching process. The photolithographic process may include the following steps: forming a photoresist (or resist) over the ILD layer 228; exposing the resist to a pattern defining various geometric shapes for the S / D via openings 230; performing a post-exposure bake; and developing the resist into a masking element having the resist. The masking element, or a derivative thereof, is then used to etch recesses into the ILD layer 228. Subsequently, the masking element (e.g., a patterned resist) is removed. The etching processes may include one or more of dry etching processes, wet etching processes, and other suitable etching methods. The etching processes may, for example, include a two-step etch.In the first etch step, portions of the ILD layers 228 and 222 are removed to expose a lower portion of the CES layer 220, and in the second etch step, the lower portion of the CES layer 220 is removed, thereby exposing a portion of the S / D regions 218. In some embodiments, the ILD layer 222 is substantially completely removed in step 110.

[0021] In step 112, the method 100 ( Fig. 1) one or more S / D contacts 232 are made in the S / D via openings 230 ( Fig. 5). In one embodiment, the S / D contacts 232 comprise a metal, such as tungsten (W), aluminum (Al), copper (Cu), combinations thereof, or other suitable conductive material. In one embodiment, the contact metal is deposited using a suitable process, such as CVD, PVD, plating, and / or other suitable processes. Step 112 may be followed by a CMP process to remove excess metals.

[0022] In step 114, the ILD layer 228 is removed to form openings 240 that expose the layers 214, 216 and 220 and the gate stack 208, as shown in Fig. 6. In one embodiment, step 114 includes an etch process configured to etch the ILD layer 228 while leaving the other layers 214, 216, and 220 and the gate stack 208 substantially unchanged during the etch process. In some embodiments, a dry etch, a wet etch, or another suitable etch process may be used for step 114.

[0023] The procedure 100 ( Fig. 1) continues with step 116, in which a trench 250 is formed to create the air spacer structure ( Fig. 7). In particular, trench 250 is formed by etching sacrificial spacer 216. In one embodiment, trench 250 is filled with air, creating an air gap between sealing spacer 214 and CES layer 220. The sidewalls of sealing spacer 214 and CES layer 220 are exposed in trench 250.

[0024] Generally, the compositions of the sealing spacer 214 and the CES layer 220 are selected such that the sealing spacer 214 and the CES layer 220 have a higher etch selectivity than the sacrificial spacer 216. This allows the etching process to remove the sacrificial spacer 216 while the thicknesses of the sealing spacer 214 and the CES layer 220 remain relatively and / or substantially unchanged. In some embodiments, the sealing spacer 214 and the CES layer 220 include nitride (or are nitride-rich), and the sacrificial spacer 216 includes oxide (or is oxide-rich).The sealing spacer 214 and the CES layer 220 may have a composition selected, for example, from the group consisting of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride (which are tuned to be nitride-rich), and a combination thereof, while the sacrificial spacer 216 may have a composition selected from the group consisting of silicon oxide, aluminum oxide, silicon carbon oxynitride (which are tuned to be oxide-rich), and a combination thereof. The sealing spacer 214 and the CES layer 220 may contain the same or different materials. In a particular embodiment, the sealing spacer 214 contains silicon nitride, the CES layer 220 contains silicon carbonitride, and the sacrificial spacer 216 contains aluminum oxide.In another specific embodiment, the sealing spacer 214 includes silicon carbonitride, the CES layer 220 includes silicon carbon oxynitride, and the sacrificial spacer 216 includes aluminum oxide. In alternative embodiments, the sealing spacer 214 and the CES layer 220 include oxide (or are oxide-rich), and the sacrificial spacer 216 includes nitride (or is oxide-rich).The sealing spacer 214 and the CES layer 220 may each have a composition selected from, for example, the group consisting of silicon oxide, aluminum oxide, silicon carbon oxide nitride (adjusted to be rich in oxide), and a combination thereof, while the sacrificial spacer 216 may have a composition selected from the group consisting of silicon nitride, silicon carbonitride, silicon oxide nitride, silicon carbon oxide nitride (adjusted to be rich in nitride), and a combination thereof. In yet another specific embodiment, the sealing spacer 214 includes silicon oxide, the CES layer 220 includes silicon carbon oxide nitride, and the sacrificial spacer 216 includes silicon nitride.

[0025] In some embodiments, an etching process with an etchant is used for step 116 to selectively remove the sacrificial spacer 216. A dry etch, a wet etch, or another suitable etching method may be used for step 116. For a dry etching process, an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof may be used. A wet etching process may, for example, include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or in another wet etchant.In one example, the sacrificial spacer 216 includes silicon oxide, and the wet etching process includes the use of DHF. In another example, the sacrificial spacer 216 includes aluminum oxide, and the wet etching process includes the use of a mixture of ammonia and hydrogen peroxide (APM), such as an SC1 solution (NH4OH:H2O2:H2O). In yet another example, the sacrificial spacer 216 includes silicon nitride, and the wet etching process includes the use of an acid containing H3PO4.

[0026] The procedure 100 ( Fig. 1) proceeds to step 118, where a capping structure for the air gap (cavity) is formed over the trench 250. In particular, an ILD layer 252 is deposited over the device 200, as shown in Fig. 8A. The ILD layer 252 also forms a capping or top wall for the air gap in the trench 250. In one embodiment, the ILD layer 252 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plating, and / or another suitable method. In one embodiment, the ILD layer 252 is deposited using a CVD process. The formation of the ILD layer 252 is performed to effectively close the trench 250, thus creating the air gap. The parameters in the CVD process (e.g., pressure, temperature, and gas viscosity) are adjusted so that, during the gap filling process of deposition of dielectric materials, the air gap is maintained without filling the trench 250. In the present embodiment, the pressure for the CVD process is set to less than about 1 mbar (0.75 Torr) and the temperature is set to greater than about 75°C.This allows the dielectric material of the ILD layer 252 to be deposited on the upper portion of the trench 250 such that the opening of the trench 250 is enclosed without depositing a significant amount in a lower portion of the trench 250. The corresponding air gap can therefore be created beneath the dielectric material of the ILD layer 252 and between the sealing spacer 214 and the CES layer 220. The sidewalls of the sealing spacer 214 and the CES layer 220 are exposed in the air gap. Gases may be present in the air gap, such as one or more gases used in the deposition of the dielectric material of the ILD layer 252 or other gases that may penetrate the air gap. The ILD layer 252 extends laterally from the air gap to the top surfaces of the sealing spacer 214 and the gate stack 208. The ILD layer 252 also covers the CES layer 220 and the S / D contacts 232.In some embodiments, the ILD layer 252 may comprise silicon nitride, silicon oxynitride, or silicon carbonitride. In some embodiments, the ILD layer 252 may comprise an oxide, such as TEOS, BPSG, FSG, PSG, and BSG. The ILD layer 252 may comprise a different material than or the same material as the ILD layer 228. In the present embodiment, the ILD layer 252 is a silicon oxide layer.

[0027] Let us stay with Fig. 8A. In some embodiments, the substrate 202 is exposed in the trench 250 after the sacrificial layer 216 has been etched. Therefore, the air gap defined in the trench 250 extends horizontally from a sidewall of the spacer layer 214 to a sidewall of the CES layer 220 and extends vertically from a top surface of the substrate 202 to a bottom surface of the ILD layer 252. In alternative embodiments, the sacrificial layer 216 is not completely removed from the trench 250 in the etching process (e.g., by controlling the etch duration), and a residue 216a remains in the lower part of the trench 250 and still covers the substrate 202, as in Fig. 8B. In this case, the air gap instead extends vertically from a lower portion of the sacrificial layer 216 to a bottom surface of the ILD layer 252. In the present embodiment, the air gap has a width in the range of about 2 nm to about 4 nm. The air gap forms air spacer structures surrounding the gate stack 208, which contributes to lowering the effective dielectric constant of material layers between the gate stack 208 and the S / D contacts 232, thereby reducing the respective stray capacitance.

[0028] In step 120, the method 100 ( Fig. 1) another CMP process is performed to polish the ILD layer 252 and expose the S / D contacts 232 ( Fig. 9). The method 100 can be combined with further processes (in Fig.1) to complete the fabrication of device 200. For example, method 100 may fabricate a multilayer interconnect structure that connects gate stacks 208 and S / D contacts 232 to other portions of device 200 to form a complete IC.

[0029] One or more embodiments of the present invention provide numerous advantages for semiconductor devices, including fin field-effect transistors (FinFETs), and their fabrication. For example, the fins can be patterned to create a relatively small spacing between the features, for which the invention described above is well suited. Spacers used in the fabrication of fins for FinFETs can be processed according to the invention described above. For example, embodiments of the present invention provide a method for fabricating air spacers surrounding the gate stack. The relative permittivity (or dielectric constant) between the gate stack and the S / D contacts is lower, thereby reducing interference, noise, and parasitic coupling capacitance between the interconnects.Furthermore, the described processes can be easily integrated into existing semiconductor manufacturing processes.

[0030] In one exemplary aspect, the present invention is directed to a method. The method comprises the following steps: forming a gate structure on a substrate; forming a sealing spacer covering a sidewall of the gate structure; forming a sacrificial spacer covering a sidewall of the sealing spacer; forming source / drain (S / D) regions with a channel region therebetween, located beneath the gate structure; depositing a contact etch stop (CES) layer covering a sidewall of the sacrificial spacer; depositing a dielectric layer covering the substrate; patterning the dielectric layer to form a via opening exposing one of the S / D regions; forming an S / D contact in the via opening;After forming the S / D contact, selectively removing the dielectric layer to expose a top surface of the sacrificial spacer; removing the sacrificial spacer to form a trench, the trench extending between a sidewall of the CES layer and the sidewall of the sealing spacer; and depositing an ILD (interlayer dielectric) layer, the ILD layer capping the trench, thereby defining an air gap in the trench.

[0031] In another exemplary aspect, the present invention is directed to a method of manufacturing a semiconductor device. The method comprises the following steps: forming a gate stack on a semiconductor substrate; forming a sealing spacer covering a sidewall of the gate stack; forming a sacrificial spacer covering a sidewall of the sealing spacer; forming source / drain (S / D) regions with a channel region therebetween, located beneath the gate stack; forming a contact etch stop (CES) layer covering a sidewall of the sacrificial spacer; depositing a first interlayer dielectric (ILD) layer over the gate stack; patterning the first ILD layer, thereby forming an opening exposing one of the S / D regions; forming an S / D contact in the opening;After forming the S / D contact, selectively removing the first ILD layer to expose a top surface of the sacrificial spacer; After removing the first ILD layer, removing the sacrificial spacer to form a trench, the trench exposing a sidewall of the CES layer and the sidewall of the sealing spacer; and depositing a second ILD layer over the S / D contact, the sealing spacer, and the gate stack, the second ILD layer sealing the trench, thereby defining a cavity in the trench.

[0032] In another exemplary aspect, the present invention is directed to a semiconductor device.The semiconductor device comprises: a substrate having source / drain (S / D) regions with a channel region therebetween; a gate stack over the channel region; a spacer layer covering sidewalls of the gate stack; an S / D contact over one of the S / D regions; a contact etch stop layer (CES layer) covering sidewalls of the S / D contact; and an ILD layer (ILD: interlayer dielectric) covering the CES layer, the spacer layer, and the gate stack, wherein the CES layer and the spacer layer are spaced apart from each other, forming a gap therebetween that is capped by the ILD layer, wherein top surfaces of the gate stack, the spacer layer, and the CES layer are planar, and wherein top surfaces of the S / D contact and the ILD layer are planar and lie above the top surfaces of the gate stack, the spacer layer, and the CES layer.

Claims

[1] Method (100) comprising the following steps: forming a gate structure (208) on a substrate (202); forming a sealing spacer (214) covering a sidewall of the gate structure (208); Producing a sacrificial spacer (216) covering a sidewall of the sealing spacer (214); forming S / D regions (218, 218a) with a channel region (224) therebetween located beneath the gate structure (208); depositing a CES layer (220) covering a sidewall of the sacrificial spacer (216); depositing a dielectric layer (228) covering the substrate (202); Structuring the dielectric layer (228) to form a via opening (230) exposing one of the S / D regions (218, 218a); Making an S / D contact (232) in the via opening (230); After forming the S / D contact (232), removing the dielectric layer (228) to expose a top surface of the sacrificial spacer (216); Removing the sacrificial spacer (216) to create a trench (250), the trench (250) extending between a sidewall of the CES layer (220) and the sidewall of the sealing spacer (214); and Depositing an ILD layer (252), wherein the ILD layer (252) caps the trench (250), thereby defining an air gap in the trench (250). [2] The method (100) of claim 1, wherein removing the sacrificial spacer (216) comprises an etching process exposing a top surface of the substrate (202), wherein the air gap extends vertically from the top surface of the substrate (202) to a bottom surface of the ILD layer (252). [3] The method (100) of claim 1 or 2, wherein removing the sacrificial spacer (216) comprises an etching process in which a portion of the sacrificial spacer (216) covering a bottom surface of the trench (250) remains, the air gap extending vertically from a top surface of the portion of the sacrificial spacer (216) to a bottom surface of the ILD layer (252). [4] Method (100) according to one of the preceding claims, wherein: the sealing spacer (214) and the CES layer (220) each comprise nitride; and the sealing spacer (214) and the CES layer (220) have different material compositions. [5] The method (100) of any preceding claim, wherein the sealing spacer (214) and the CES layer (220) each have a composition selected from the group consisting of silicon nitride, silicon carbonitride, silicon carbon oxynitride, and a combination thereof. [6] The method (100) of any preceding claim, wherein the sacrificial spacer (216) comprises aluminum oxide. [7] The method (100) of any preceding claim, wherein the ILD layer (252) comprises oxide. [8] The method (100) of any preceding claim, wherein the ILD layer (252) extends laterally from the air gap to a top surface of the sealing spacer (214) and directly contacts the top surface of the sealing spacer (214). [9] Method (100) according to claims 1 to 8, further comprising the following steps: before depositing the dielectric layer (228), performing a first CMP process to expose the gate structure (208); and after depositing the ILD layer (252), performing a second CMP process on the ILD layer (252) to expose the S / D contact (232). [10] A method (100) for manufacturing a semiconductor device (200), comprising the following steps: forming a gate stack (208) on a semiconductor substrate (202); forming a sealing spacer (214) covering a sidewall of the gate stack (208); Producing a sacrificial spacer (216) covering a sidewall of the sealing spacer (214); forming S / D regions (218, 218a) with a channel region (224) therebetween located beneath the gate stack (208); Forming a contact etch stop layer, hereinafter referred to as CES layer (220), covering a sidewall of the sacrificial spacer (216); depositing a first ILD layer (228) over the gate stack (208); Patterning the first ILD layer (228) to form an opening (240) exposing one of the S / D regions (218, 218a); Establishing an S / D contact (232) in the opening (240); after forming the S / D contact (232), removing the first ILD layer (228) to expose a top surface of the sacrificial spacer (216); after removing the first ILD layer (228), removing the sacrificial spacer (216) to form a trench (250), the trench (250) exposing a sidewall of the CES layer (220) and the sidewall of the sealing spacer (214); and Depositing a second ILD layer (252) over the S / D contact (232), the sealing spacer (214) and the gate stack (208), wherein the second ILD layer (252) seals the trench (250), thereby defining a cavity in the trench (250). [11] The method (100) of claim 10, wherein the cavity exposes a top surface of the semiconductor substrate (202). [12] The method (100) of claim 10 or 11, further comprising the step of: after depositing the second ILD layer (252), performing a CMP process on the second ILD layer (252) to expose the S / D contact (232). [13] Method (100) according to one of claims 10 to 12, wherein the sealing spacer (214) and the CES layer (220) each comprise nitride, and the sacrificial spacer (216) and the second ILD layer (252) each comprise oxide. [14] Method (100) according to one of claims 10 to 13, wherein the sealing spacer (214) contains silicon carbonitride, the CES layer (220) contains silicon carbon oxide nitride, the sacrificial spacer (216) contains aluminum oxide, and the second ILD layer (252) contains silicon oxide. [15] Semiconductor device (200) with: a substrate (202) comprising S / D regions with a channel region (224) therebetween; a gate stack (208) over the channel region (224); a spacer layer (214) covering sidewalls of the gate stack (208); an S / D contact (232) over one of the S / D regions (218, 218a); a CES layer (220) covering sidewalls of the S / D contact (232); and an ILD layer (252) covering the CES layer (220), the spacer layer (214) and the gate stack (208), wherein the CES layer (220) and the spacer layer (214) are spaced apart from each other, thereby defining a gap (250) therebetween, which gap is capped by the ILD layer (252), wherein top surfaces of the gate stack (208), the spacer layer (214) and the CES layer (220) are planar, and wherein top surfaces of the S / D contact (232) and the ILD layer (252) are planar and lie above the top surfaces of the gate stack (208), the spacer layer (214) and the CES layer (220). [16] The semiconductor device (200) of claim 15, wherein the gap (250) extends vertically from a top surface of the substrate (202) to a bottom surface of the ILD layer (252). [17] A semiconductor device (200) according to claim 15 or 16, further comprising: a dielectric layer (216a) over the substrate (202) and between the spacer layer (214) and the CES layer (220), wherein the gap (250) extends vertically from a top surface of the dielectric layer (216a) to a bottom surface of the ILD layer (252). [18] A semiconductor device according to claim 17, wherein the dielectric layer (216a) is aluminum oxide. [19] Semiconductor component according to one of claims 15 to 18, wherein the ILD layer (252) contains silicon oxide, the spacer layer (214) and the CES layer (220) each have a composition selected from the group consisting of silicon nitride, silicon carbonitride, silicon carbon oxide nitride, and a combination thereof, and the spacer layer (214) and the CES layer (220) have different material compositions.

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