BACKING AND SELECTIVE DEPARTURE OF A METAL GATE

Abstract

Procedure that includes the following: Forming a first dummy gate stack (30, 232, 234, 236), Forming a dielectric layer (146, 246) wherein the first dummy gate stack (30, 232, 234, 236) is located in the dielectric layer, Removing the first dummy gate stack (30, 232, 234, 236) to form a first opening (247) in the dielectric layer (146, 246), Forming a second dummy gate stack (30, 132, 134, 136) simultaneously with the first dummy gate stack, Removing the second dummy gate stack to form a second opening (147) in the dielectric layer (146, 246), Forming a metal layer (162, 262) that partially fills the first opening (247) and completely fills the second opening (147), Etching back the metal layer (162, 262), wherein remaining sections of the metal layer in the first opening (247) have edges that are lower than a top surface of the dielectric layer (146, 246), wherein the etching back the metal layer (162, 262) comprises: Filling a protective layer (264) over the metal layer (162, 262) into the first opening (247), Etching of the metal layer (162, 262) using the protective layer (264) as an etching mask, Removing the protective layer (264); sparing the metal layer (162, 262) in the second opening (147) without using the protective layer (264) as an etching mask, material-selective deposition of a first conductive layer (266) in the first opening (247), wherein the first conductive layer (266) is located above the metal layer and the metal layer and the first conductive layer together form a substitute gate; and material-selective deposition of a second conductive layer (166) in the second opening (147).

Description

BACKGROUND

[0001] Metal-oxide-semiconductor (MOS) devices are the fundamental building blocks of integrated circuits. A state-of-the-art MOS device typically has a gate electrode made of polysilicon doped with p-type or n-type impurity atoms via doping operations such as ion implantation or thermal diffusion. The work function of the gate electrode can be tuned to the silicon band edge. For an n-type metal-oxide-semiconductor (NMOS) device, the work function can be tuned to near the silicon conduction band. For a p-type metal-oxide-semiconductor (PMOS) device, the work function can be tuned to near the silicon valence band. Tuning the work function of the polysilicon gate electrode can be achieved by selecting suitable impurity atoms.

[0002] US Patent 2015 / 0 108 577 A1 discloses a device comprising gate spacers, a high-k gate dielectric, a metal-containing layer over the high-k gate dielectric, and a conductive layer over the metal layers. Similar devices are disclosed in US Patent 2016 / 0 204 221 A1 and US Patent 2015 / 0 349 075 A1.

[0003] US 2016 / 0042954A1 discloses embodiments that provide a substitute metal gate and a manufacturing process with reduced lithography steps. Using selective etching techniques, a layer of filler metal is used to protect the dielectric layer in the grooves, thereby eliminating some lithography steps. This, in turn, reduces the overall cost and complexity of manufacturing. Furthermore, additional protection is provided during etching, which helps to improve product yield.

[0004] US 2015 / 0243564A1 discloses a method for fabricating a semiconductor device comprising the following steps: preparing a substrate with a PMOS region and an NMOS region; forming a first gate trench on the PMOS region; forming a first high-k dielectric layer and a first high-k top layer covering the bottom and sides of the first gate trench; forming a second gate trench on the NMOS region; forming a second high-k dielectric layer and a second high-k top layer covering the bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k top layer positioned on one side of the first gate trench. and removing part of the second high-k dielectric layer and part of the second high-k top layer, which are positioned on one side of the second gate trench.

[0005] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as polydepletion. This effect occurs when applied electric fields force carriers out of the gate region near the gate dielectrics, forming depletion layers. In an n-doped polysilicon layer, the depletion layer contains ionized non-mobile donor sites, while in a p-doped polysilicon layer, it contains ionized non-mobile acceptor sites. The depletion effect leads to an increase in the effective thickness of the gate dielectrics, making it more difficult to create an inversion layer on the semiconductor surface.

[0006] The polydepletion problem can be solved by forming metal-gate electrodes, where the metallic gates used in NMOS and PMOS devices can also have band-edge exit work. Accordingly, the resulting metal gates contain multiple layers to meet the requirements of NMOS and PMOS devices.

[0007] The formation of metal gates typically involves depositing metal layers and subsequently performing chemical-mechanical polishing (CMP) to remove excess portions of the metal layers. The remaining portions of the metal layers form the metal gates. The metal gates are then recessed, creating cavities between gate spacers such that these cavities can be filled with hard masks to insulate the metal gates. To reduce the stress effect during metal gate recession, metal gates from long-channel devices and metal gates from short-channel devices are recessed in separate processes, requiring multiple re-etching operations. During these processes, the interlayer dielectric in which the metal gates are located can become excessively thinned, leading to a gate loss problem. The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as desired for clarity. Fig. Figures 1 to 15A illustrate the cross-sectional and perspective views of intermediate stages in the formation of fin-type field-effect transistors (FinFETs) according to some embodiments. Fig. 15B, Fig. 15C and Fig. Figure 15D shows cross-sectional views of FinFETs according to some embodiments, wherein the top ends of metal layers and gate dielectrics in substitute gates have different heights and shapes. Fig. Figure 16 illustrates a flowchart of a process for forming a FinFET according to some embodiments. DETAILED DESCRIPTION

[0009] The following description provides many different embodiments or examples for implementing various features of the description. Specific examples of components and arrangements are described below to simplify the present description. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present description may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0010] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0011] Transistors and methods for forming transistors according to various exemplary embodiments are provided. The intermediate stages for forming the transistors according to some embodiments are illustrated. Some variations of certain embodiments are discussed. In all the different views and illustrative embodiments, the same reference numerals are used to denote the same elements. In the illustrated exemplary embodiments, the formation of fin-type field-effect transistors (FinFETs) is used as an example to explain the concepts of the present invention. Planar transistors can also adopt the concept of the present invention.

[0012] Fig. Figures 1 to 15A illustrate cross-sectional and perspective views of intermediate stages in the formation of transistors according to some embodiments of the present invention. The figures shown in the Fig. The steps shown in sections 1 to 15A are also shown schematically in the diagram in Fig. The process flow shown in Figure 16 is reflected. According to some exemplary embodiments, the transistors formed contain a long-channel transistor (such as a long-channel FinFET) and a short-channel transistor (such as a short-channel FinFET).

[0013] The in the Fig. The process steps shown in Figures 1 to 6 can represent an exemplary process for forming the long-channel FinFET and / or the short-channel FinFET. Accordingly, the process for forming semiconductor fins, dummy gate stacks, source / drain regions, and source / drain silicide regions, etc., of the long-channel FinFET and / or the short-channel FinFET can be described in the following sections. Fig. 1 to 6 can be used.

[0014] Fig. Figure 1 illustrates a perspective view of an initial structure. The initial structure contains a wafer 10, which further contains the substrate 20. The substrate 20 can be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed from other semiconductor materials. The substrate 20 can be doped with a p-type or n-type impurity atom. Insulating regions 22, such as shallow trench isolation (STI) regions, can be formed to extend from a top surface of the substrate 20 into the substrate 20, the top surface of the substrate 20 being a major face 10A of the wafer 10. The sections of the substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. The top surfaces of the semiconductor strips 24 and the top surfaces of the STI regions 22 can be substantially flush with each other according to some exemplary embodiments.

[0015] The STI regions 22 can contain a lining oxide (not shown). The lining oxide can be formed from a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20. The lining oxide can also be a deposited silicon oxide layer formed, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 22 can also contain a dielectric material over the lining oxide, the dielectric material being formed by flowable chemical vapor deposition (FCVD), spin deposition, or the like.

[0016] We turn to Fig. 2. STI regions 22 are recessed such that the upper sections of semiconductor strips 24 protrude higher than the tops of the STI regions 22 to form projecting ribs 24'. The respective step is referred to as step 302 in the Fig. The process flow shown in Figure 16 is illustrated. Etching can be carried out using a dry etching process, employing H₂ and NF₃ as etching gases. Plasma can be generated during the etching process. Argon may also be included. According to alternative embodiments of the present invention, the removal of the STI regions 22 is carried out using a wet etching process. The etching chemical may, for example, contain dilute HF.

[0017] We turn to Fig. 3. A dummy gate stack 30 is formed on the tops and side walls of the projecting ribs 24'. The respective step is designated as step 304 in the Fig. The process flow shown in Figure 16 is illustrated. The dummy gate stack 30 can contain a gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 can be formed, for example, using polysilicon, and other materials can also be used. The dummy gate stack 30 can also contain one or more hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 can be formed from silicon nitride, silicon carbonitride, or the like. The dummy gate stack 30 can intersect one or more projecting ribs 24' and / or STI regions 22. The dummy gate stack 30 can also have a longitudinal direction perpendicular to the longitudinal direction of the projecting ribs 24'.

[0018] Next, gate spacers 38 are formed on the side walls of the dummy gate stack 30. In addition, rib spacers (not shown) can also be formed on the side walls of the projecting ribs 24'. According to some embodiments of the present invention, gate spacers 38 are formed from a dielectric material such as silicon carbon oxynitride (SiCN), silicon nitride, or the like, and can have a single-layer structure or a multi-layer structure containing several dielectric layers.

[0019] An etching step (hereinafter referred to as source / drain recession) is then performed to etch the sections of the projecting ribs 24' that are not covered by the dummy gate stack 30 and gate spacer 38, resulting in the Fig. The structure shown in Figure 4 is derived from this. The recess can be anisotropic, and consequently, the sections of the ribs 24' that lie directly beneath the dummy gate stack 30 and the gate spacers 38 are protected and are not etched. According to some embodiments, the top surfaces 24A of the recessed semiconductor strips 24 can be lower than the top surfaces 22A of the STI regions 22. Accordingly, recesses 40 are formed between the STI regions 22. The recesses 40 are located on opposite sides of the dummy gate stack 30.

[0020] Next, epitaxial regions (source / drain regions) are formed by selectively growing a semiconductor material in recesses 40, resulting in the structure shown in Fig. 5 leads to the respective step. Fig. The process flow shown in Figure 16 is illustrated as step 306. According to some exemplary embodiments, the epitaxy regions contain silicon germanium or silicon. Depending on whether the resulting FinFET is a p-type or an n-type FinFET, a p-type or an n-type perturbation atom can be in situ doped as the epitaxy progresses. For example, if the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) can be grown. Conversely, if the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) can be grown. According to alternative embodiments of the present invention, epitaxy regions 42 are formed from a III-V composite semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof.After the recesses 40 have been filled with epitaxy regions 42, the further epitaxial growth of the epitaxy regions 42 causes the epitaxy regions 42 to expand horizontally, and facets can be formed.

[0021] Following the epitaxy step, further epitaxy regions 42 can be implanted with a p-type or n-type interfering atom to form source and drain regions, also designated by reference numeral 42. According to alternative embodiments of the present invention, the implantation step is omitted if epitaxy regions 42 are doped in situ with the p-type or n-type interfering atom during epitaxy. The epitaxy regions 42 comprise lower sections 42A formed within STI regions 22 and upper sections 42B formed over the top surfaces 22A of the STI regions 22. The lower sections 42A, whose side walls are defined by the shapes of the recesses 40 ( Fig. 4) can be formed, can have (essentially) straight edges, which can also be essentially vertical edges, running essentially perpendicular to the main surfaces (such as the bottom surface 20B) of the substrate 20.

[0022] Fig. Figure 6 illustrates a perspective view of the structure in which an interlayer dielectric (ILD) 46 is formed. The respective step is shown as step 308 in the figure in Fig. The process flow shown in Figure 16 is illustrated. According to some embodiments of the present invention, a buffer oxide layer (not shown) and a contact etch stop layer (CESL, not shown) are formed on source and drain regions 42 before the ILD 46 is formed. The buffer oxide layer can be formed from silicon oxide, and the CESL can be formed from silicon nitride, silicon carbonitride, or the like. The buffer oxide layer and the CESL can be formed by a conformal deposition process, such as ALD. The ILD 46 can contain a dielectric material formed, for example, by FCVD, spin deposition, CVD, or other deposition processes. The ILD 46 can also be formed from phosphosilicate glass (PSG), boron silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, or the like.A chemical-mechanical polishing (CMP) process can be performed to level the top surfaces of the ILD 46, the dummy gate stack 30 and the gate spacers 38.

[0023] Fig. Figure 7 illustrates cross-sectional views of an intermediate structure during the formation of a short-channel FinFET and a long-channel FinFET on the same substrate 20. The short-channel FinFET is formed in device region 100, and the long-channel FinFET is formed in device region 200. The short-channel device has a channel that is shorter than the channel of the long-channel device, as illustrated. For example, the channel length Lg1 of the short-channel device may be shorter than about 32 nm, and the channel length Lg1 of the long-channel device may be longer than about 72 nm. The ratio Lg2 / Lg1 may be greater than about 2.5 according to some embodiments. According to some embodiments, the short-channel device is a core transistor or a transistor in a static random-access memory (SRAM), and the long-channel device is a transistor in a driver circuit or peripheral circuit.Each of the short channel devices and the long channel device can correspond to the cross-sectional view obtained from the vertical plane which defines line AA in . Fig. Contains 6.

[0024] To distinguish the structural elements in the short-channel device from the structural elements in the long-channel device, the structural elements in the short-channel device are identified using the reference numbers of the corresponding structural elements in Fig. 6 plus the number 100 is represented, and the structural elements in the long channel device are represented using the reference numbers of the corresponding structural elements in Fig. 6 plus the number 200 is represented. For example, the source / drain regions 142 and 242 correspond to 600. Fig. 7 the Source / Drain regions 42 in Fig. 6, and the silicide regions 148 and 248 in Fig. 7 correspond to the source / drain silicic acid regions in Fig. 6. The corresponding structural elements in the short-channel device and the long-channel device can be formed in common processes.

[0025] After the in Fig. Once the structure shown in Figure 7 has been formed, the dummy gate stacks containing the hard mask layers 136 and 236, the dummy gate electrodes 134 and 234, and the dummy gate dielectrics 132 and 232 are replaced by metal gates and replacement gate dielectrics, as shown in the Fig. 8 to 15A shown. In the Fig. 8 to 15A the top surfaces 122A and 222A of the STI regions 22 are illustrated, and the semiconductor fins 124' and 224' protrude higher than the top surfaces 122A and 222A respectively.

[0026] To form the replacement gates, the hard mask layers 136 and 236, the dummy gate electrodes 134 and 234, and the dummy gate dielectrics 132 and 232 are used, as shown in Fig. 7 shown, removed, creating openings 147 and 247, as shown in Fig. 8 shown. The respective step is shown as step 310 in the in Fig. The process flow shown in Figure 16 is illustrated. The upper surfaces and side walls of the projecting ribs 124' and 224' are exposed towards the openings 147 and 247, respectively.

[0027] Next, we turn to Fig. 9, where gate dielectrics 154 / 156 and 254 / 256 are formed, extending into openings 147 and 247 respectively. The respective step is referred to as step 312 in the Fig. The process flow shown in Figure 16 is illustrated. According to some embodiments of the present invention, the gate dielectrics include interface layers (ILs) 154 and 254 formed on the exposed surfaces of the projecting ribs 124' and 224', respectively. The ILs 154 and 254 may contain an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the projecting ribs 124' and 224', a chemical oxidation process, or a deposition process. The gate dielectrics may also include high k-value dielectric layers 156 and 256 over the corresponding ILs 154 and 254. High k-value dielectric layers 156 and 256 may be formed on a high k-value dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like.The dielectric constant (k-value) of the high k-value dielectric material is greater than 3.9 and can be greater than approximately 7.0, and sometimes even 21.0 or higher. The high k-value dielectric layers 156 and 256 lie above the respective underlying ILs 154 and 254 and can contact them. The high k-value dielectric layers 156 and 256 are formed as conformal layers and extend along the side walls of the projecting ribs 124' and 224' and the top and side walls of the gate spacers 138 and 238, respectively. According to some embodiments of the present invention, the high k-value dielectric layers 156 and 256 are formed using ALD or CVD.

[0028] We'll stick with it Fig. 9, where metal-containing conductive layers 162 and 262 are formed by deposition. The respective step is described as step 314 in the Fig. The process flow shown in Figure 16 is illustrated. The deposition can be carried out using a conformal deposition method, such as ALD or CVD, such that the horizontal thickness T1 of the horizontal sections and the vertical thickness T2 of the vertical sections of the metal-containing layer 262 (and each of the sub-layers) are substantially equal. For example, the horizontal thickness T1 and the vertical thickness T2 may differ by less than about 20 percent or 10 percent of either the thickness T1 or the thickness T2. According to some embodiments of the present invention, the metal-containing layer 262 extends into the opening 247 and includes some sections above the ILD 246.

[0029] In the same deposition process in which the metal-containing layer 262 is formed, the opening 147 ( Fig. 9) also filled with the metal-containing conductive layers 162. Since the opening 147 is narrow, it can be completely filled (or substantially completely filled, leaving a small section unfilled).

[0030] Each of the metal-containing layers 162 and 262 contains at least one layer, or may contain several layers (such as 162A / 262A, 162B / 262B, and 162C / 262C), formed from different materials. The corresponding layers in the metal-containing conductive layers 162 and 262 are formed in common deposition processes. The specific material of the layers in the metal-containing layers 162 and 262 can be working exit metals, selected according to whether the respective FinFET is an n-type or a p-type FinFET. For example, if the FinFET is an n-type FinFET, the layers 162A / 262A, 162B / 262B and 162C / 262C can contain a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer or an Al-based layer (which is formed, for example, from TiAl, TiAlN, TiAlC, TaAlN or TaAlC).If the FinFET is a p-type FinFET, then layers 162A / 262A, 162B / 262B, and 162C / 262C can contain a TiN layer, a TaN layer, or another TiN layer, respectively. Layers 162 and 262 can also contain two layers or more than three layers.

[0031] After the deposition of the metal-containing layers 162 and 262, the protective layer 264 is formed to fill the remaining sections of the opening 247, as shown in Fig. 10 shown. The respective step is shown as step 316 in the Fig. The process flow shown in Figure 16 is illustrated. According to some embodiments, the protective layer 264 is formed from a material different from the materials of the underlying layers 256 and 262, so that in the subsequent etching steps, the protective layer 264 can be used as an etching mask to protect the underlying sections of layers 262 and 256. For example, the protective layer 264 can be formed from an organic material, such as a photoresist or a material consisting predominantly of carbon, hydrogen, and oxygen, wherein this material is suitable for forming a bottom-side antireflective coating (BARC). The protective layer 264 can also be formed from an inorganic material, such as silicon oxide, silicon nitride, silicon carbide, amorphous silicon (α-Si), or the like, which is resistant to etching.The protective layer 264 can have a substantially planar top surface, produced by spin coating if used. A planarization step, such as CMP, can be performed if required. Dashed lines 165 and 265 schematically illustrate the top surfaces of the protective layer 264 after coating.

[0032] Fig. Figure 10 also illustrates the etching back of the protective layer 264, symbolized by arrows 67. The respective step is also shown as step 316 in the [reference to be added]. Fig. The process flow shown in Figure 16 is illustrated. The etching can include dry etching and / or wet etching. Furthermore, the etching can be isotropic or anisotropic. According to some embodiments of the present invention, the back-etching is carried out using an etchant that etches layer 264 but hardly attacks layer(s) 162C / 262C. According to some exemplary embodiments in which layer 264 is formed from amorphous silicon, layer 264 can be back-etched using a mixture of HBr, Cl₂ and O₂, CF₄, or HF. During back-etching, the sections of the protective layer 264 over the ILDs 146 and 246 are completely removed, while a section remains in the opening 247.

[0033] Next, as in Fig. As shown in Figure 11, the protective layer 264 is used as an etching mask to etch the metal-containing layer 262, such that the top or edge of layer 262 is lowered. This step is described as step 318 in the figure shown in Fig. The process flow shown in Figure 16 is illustrated. The gate dielectric 256 can optionally be etched at the same time as the metal-containing layer 262. The metal-containing layer 162 is also etched in the same etching process. The etchant can also be selected to attack (or not attack) the dielectric layers 156 and 256. The etchant for etching the metal-containing layers 162 and 262 is selected so that it does not attack the gate spacers 138 / 238 and ILDs 146 and 246. Furthermore, if each of the metal-containing layers 162 and 262 contains several sub-layers, the etchant can be selected so that the etch rates of the sub-layers become uniform. As a result, after etching, the top surfaces of layers 156, 162A, 162B and 162C (and 256, 262A, 262B and 262C) can be essentially coplanar.It is understood that there may be differences in the etch rates of these layers, and each of the top surfaces of layers 156, 162A, 162B and 162C (and 256, 262A, 262B and 262C) may be higher than, lower than, or coplanar with the top surface of other layers in any combination.

[0034] During the etching back of the metal-containing layers 162 and 262, the protective layer 264 can also be partially consumed. According to some embodiments, the upper height H1 of the protective layer 264 ( Fig. 10), measured before etching the metal-containing layers 162 and 262, chosen (for example, larger than about 20 nm) so that after etching the metal-containing layers 162 and 262, a section of the protective layer 264 is still left to maintain a sufficient process margin to prevent the layers 256, 262A, 262B and 262C from being etched through.

[0035] After the etching back of the metal-containing layers 162 and 262 is complete, the remaining section of the protective layer 264 is removed, as shown in Fig. 12 shown. The respective step is shown as step 320 in the in Fig. The process flow shown in Figure 16 is illustrated. The remaining openings 147 and 247, as shown in Figure 16, are located at the end of the 16 openings. Fig. Figure 12 shows that, according to some embodiments, the metal layers 166 and 266 are then filled with a conductive material (which may contain metal) to form metal layers 166 and 266, respectively, as shown in Figure 12. Fig. 13 shown. The respective step is shown as step 322 in the Fig. The process flow shown in Figure 16 is illustrated. According to some exemplary embodiments, the filler metal is homogeneous and can be formed from W, Cu, Co, Al, Ru, etc., or alloys thereof, provided that the filler material has a low resistivity.

[0036] The metal layers 166 and 266 are formed by selective deposition, wherein the conductive material is deposited on the exposed surface of conductive materials (such as the metal-containing layers 162 and 262) and not on the exposed surfaces of gate spacers 238 and ILDs 146 and 246, etc. According to some exemplary embodiments, the deposition is carried out using ALD or CVD. The precursor may contain a metal halide (such as WCl5) or a metal-organic material and a reducing agent such as H2. The deposition process may be a thermal process carried out at an elevated temperature, such as in the range between approximately 275°C and approximately 500°C. The deposition may also be carried out with plasma activation.According to some embodiments, the reaction formula is MX + H2 -> M + HX, where M represents the metal and MX represents the metal halide, such as WCl5.

[0037] Due to selective deposition, the metal layers 166 and 266 can be conformal layers. Furthermore, the metal layer 266 can contain a central U-shaped section as well as horizontal sections connected to the upper ends of the two vertical legs of the U-shaped section. The depth D1 of the U-shape can be greater than approximately 2 nm and can range from approximately 2 nm to approximately 30 nm. The metal layer 166 can be essentially planar if the top surface of the metal-containing layer 162 is planar, or it can have a topology that follows the surface profile of the metal-containing layer 162. The thickness of the metal layers 166 and 266 is chosen to ensure that their resistivity is low. For example, the thickness T3 of the metal layers 166 and 266 can range from approximately 2 nm to approximately 12 nm.

[0038] Since the metal layers 166 and 266 can optionally be grown directly from gate dielectrics 154 and 254, vacancies may also form in regions 167 and 267, with the top surfaces of the gate dielectrics 156 and 256 exposed to the vacancies (the vacancies are also shown as 167 and 267). Because the gate dielectrics 156 and 256 are thin, the lateral growth of the metal layers 166 and 266 causes the vacancies 167 and 267 (if present) to be sealed, and the metal layers 166 and 266 grow laterally until they touch the gate spacers 138 and 238, respectively.

[0039] As in Fig. As shown in Figure 13, the metal layer 166 and the layers 154, 156, and 162 combine to form a replacement gate stack 174, and the metal layer 266 and the layers 254, 256, and 262 combine to form a replacement gate stack 274. Next, the remaining openings are filled with a dielectric material to form hard masks 172 and 272, as shown in Figure 13. Fig. Figure 14 shows that the hard masks 172 and 272 can be dielectric hard masks made of silicon nitride, silicon oxynitride, silicon oxycarbide, or the like. The respective step is shown as step 324 in Figure 14. Fig. The process flow shown in Figure 16 is illustrated. The hard masks 172 and 272 are also planarized such that their top surfaces are coplanar with the top surface of the ILDs 146 and 246.

[0040] In a subsequent step, some sections 46A ( Fig. 6) ILD 46 is removed to form contact openings. Then source / drain silicic acid regions 148 and 248 ( Fig. 14) on the surfaces of epitaxial regions 142 and 242, respectively. The formation process involves the deposition of a metal layer in the contact openings and the execution of a curing process to react the metal layer with the exposed surface portions of epitaxial regions 142 and 242, thus forming silicide regions 148 and 248. A conductive material, such as tungsten, is then filled into the contact openings to form contact plugs 150 and 250.

[0041] We turn to Fig. 15A, where an etch stop layer 78 is formed over the hard masks 172 and 272, respectively. The etch stop layer 78 is formed from a dielectric material that may contain silicon carbide, silicon nitride, silicon oxynitride, or the like. The ILD 80 is formed over the etch stop layer 78, and the contact plugs 182 and 282 are formed in the ILD 80. The formation process may include forming contact plug openings in the ILD 80 to expose the replacement gate stacks 174 / 274 and the source / drain contact plugs 150 / 250, and filling the contact plug openings with one or more conductive materials to form the contact plugs 182 and 282. Some sections of the hard masks 172 and 272 ( Fig. 16) are also removed, so that the gate contact plugs 182 and 282 extend into the recesses left by the removed sections of the hard masks 172 and 272. In this way, the short-channel FinFET 170 and the long-channel FinFET 270 are created.

[0042] Fig. Figure 15B illustrates FinFETs 170 and 270 according to some embodiments, wherein the gate dielectrics 156 and 256 have top surfaces that are higher than the top surfaces of the metal layers 162 and 262, or even higher than the top surfaces of the metal layers 166 and 166. This is due to the lower etch rate of the gate dielectrics 156 and 256 in the Fig. Step 11 is shown. As a result, the metal layers 166 and 266 do not overlap the top surfaces of the gate dielectrics 156 and 256.

[0043] Fig. 15C and Fig. Figure 15D illustrates the top edge profiles of layers 162A / 262A, 162B / 262B, and 162C / 262C according to some exemplary embodiments. As discussed in the preceding paragraphs, the top edges of layers 162A / 262A, 162B / 262B, and 162C / 262C can have different shapes due to the different etch rates. For example, in Fig. As shown in Figure 15C, the upper edges of layers 162B / 262B are higher than the upper edges of layers 162A / 262A and 162C / 262C. Fig. In 15D, the upper edges of layers 162B / 262B are lower than the upper edges of layers 162A / 262A and 162C / 262C. The top surfaces of layers 162A / 262A, 162B / 262B, and 162C / 262C can be higher, lower, or coplanar with each other in any combination, and the metal layers 166 and 266 also have bottom and top surfaces that follow the profiles of the upper edges of layers 162A / 262A and 162C / 262C.

[0044] The embodiments of the present invention have several advantageous features. By forming protective layers for etching one or more metal-containing layers and subsequently performing back-etching and selective deposition of the metal layers, it is not necessary to completely fill the opening (274) with metal layers and then perform computed metal layering (CMP). In this way, the gate height loss caused by CMP is avoided, the gate height loss resulting from the thinning of the ILD during CMP. Furthermore, with the selective deposition of the metal layers (162 and 262) in openings, all metal-containing layers are covered with a homogeneous metal material (166 and 266), and consequently, when gate contact openings are formed, a homogeneous metal material—instead of the upper edges of multiple materials of the metal layers—is exposed toward the gate contact openings.The process is therefore more predictable and easier to control.

Claims

[1] Procedure comprising: Forming a first dummy gate stack (30, 232, 234, 236), Forming a dielectric layer (146, 246), wherein the first dummy gate stack (30, 232, 234, 236) is located in the dielectric layer, Removing the first dummy gate stack (30, 232, 234, 236) to form a first opening (247) in the dielectric layer (146, 246), Forming a second dummy gate stack (30, 132, 134, 136) simultaneously with the first dummy gate stack, Removing the second dummy gate stack to form a second opening (147) in the dielectric layer (146, 246), Forming a metal layer (162, 262) partially filling the first opening (247) and completely filling the second opening (147), Etching back the metal layer (162, 262), wherein remaining portions of the metal layer in the first opening (247) have edges that are lower than a top surface of the dielectric layer (146, 246), wherein the etching back of the metal layer (162, 262) comprises: Filling a protective layer (264) over the metal layer (162, 262) into the first opening (247), Etching the metal layer (162, 262) using the protective layer (264) as an etching mask, Removing the protective layer (264); leaving out the metal layer (162, 262) in the second opening (147) without using the protective layer (264) as an etching mask, material-selectively depositing a first conductive layer (266) in the first opening (247), the first conductive layer (266) overlying the metal layer, the metal layer and the first conductive layer in combination forming a replacement gate; and material-selectively depositing a second conductive layer (166) in the second opening (147). [2] The method of claim 1, wherein filling the protective layer (264) comprises applying a photoresist. [3] The method of any preceding claim, wherein forming the metal layer (162, 262) comprises depositing a work function layer. [4] The method of claim 1, wherein when the first conductive layer (266) is selectively deposited into the first opening (247), no conductive layer is simultaneously deposited outside the first opening (247) and over the dielectric layer. [5] The method of any preceding claim, wherein forming the metal layer (162, 262) comprises forming a plurality of metal layers, and the plurality of metal layers are formed from different materials. [6] The method of claim 1 or 4, wherein the first conductive layer (266) comprises: a first section with a U-shaped cross-sectional view, and second horizontal sections connected to opposite upper ends of the U-shaped first section. [7] Procedure comprising: Forming a first dummy gate stack (30, 232, 234, 236) and a second dummy gate stack (30, 132, 134, 136), Forming first gate spacers (238) on sidewalls of the first dummy gate stack and second gate spacers (138) on sidewalls of the second dummy gate stack, Forming an interlayer dielectric (146, 246), wherein the first and second gate spacers and the first and second dummy gate stacks are arranged in the interlayer dielectric, Removing the first and second dummy gate stacks to form a first opening (147) and a second opening (247), respectively, wherein the first opening (147) is narrower than the second opening (247), Forming a gate dielectric layer (154, 156, 254, 256) extending into the first opening (147) and the second opening (247), Depositing a metal-containing layer (162, 262), wherein the metal-containing layer (162, 262) comprises a first portion that completely fills the first opening (147) and a second portion that partially fills the second opening (247), Filling a remaining portion of the second opening (247) with a protective layer (264), Using the protective layer (264) as an etching mask to etch back a portion of the second portion of the metal-containing layer, wherein a portion of the first portion of the metal-containing layer is etched simultaneously, Removing the protective layer (264), and material-selectively depositing a conductive material (166, 266) in the first opening (147) and the second opening (247), wherein no conductive material is formed over the interlayer dielectric (146, 246). [8] The method of claim 7, wherein, when the etching back is initiated, the protective layer (264) fills a lower portion of the second opening (247), leaving an upper portion of the second opening unfilled. [9] The method of claim 7 or 8, wherein the conductive material (266) is deposited on electrically conductive materials and not on dielectric materials in the second opening (247). [10] The method of any one of claims 7 to 9, wherein the first portion of the metal-containing layer (161, 262) is etched back without using a protective layer (264) in the first opening (147). [11] The method of any one of claims 8 to 10, wherein, after the protective layer (264) has been etched, the second portion of the metal-containing layer (262) has a U-shape. [12] The method of any one of claims 8 to 11, wherein the conductive material (266) is deposited into the first opening (147) and the second opening (247) as conformal layers.

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