Method and integrated circuit design with nonlinear power rails

Abstract

A method of manufacturing an integrated circuit (100), comprising: Receiving an integrated circuit layout having active zones (102) and conductive contact features (106) landing on the active zones, and having a conductive via feature (308) to land on a first subset of the conductive contact features (106A, 106E, 106C) and to be spaced from a second subset (106D, 106B, 106F) of the conductive contact features; Constructing an initial shape of the conductive via feature that overlaps with all or none of the conductive contact features, Evaluating a spatial parameter of the conductive via feature (308) to the conductive contact features (106); and Modifying the initial shape of the conductive via feature (308) according to the spatial parameter such that the conductive via feature (308) has a curved S-shape and lands on the first subset of the conductive contact features (106A, 106E, 106C) and is spaced from the second subset (106D, 106B, 106F) of the conductive contact features.

Description

GENERAL STATE OF THE ARTThe industry of semiconductor integrated circuits has been growing exponentially up to now. Technological advances in materials and integrated circuit design have produced generations of integrated circuits where each generation has smaller and more complex circuits than the previous generation. As integrated circuits develop, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry size (i.e., the smallest device (or line) that can be created using a fabrication process) has decreased.Integrated circuits may include a plurality of standard cell circuits each formed by a plurality of logic devices such as transistors, capacitors, or the like to provide a Boolean logic function or a storage function. Interconnect structures such as vias and power rails are then formed over the plurality of standard cell circuits to provide connections between the standard cell circuits and / or to provide connections to external devices. However, as the size of standard cells decreases gradually, gaps and distances between the bus bars and the other electronic devices may decrease, which may increase the risk of a short circuit. However, attempts to reduce the size of the bus bars may suffer from increased resistance and may result in speed degradation. Accordingly, a circuit structure and method of manufacturing the same are needed to address the foregoing problems.US2010 / 0044757A1 relates to a semiconductor device comprising a transistor having a gate electrode, a source region, a first interlayer insulating film covering the transistor; a first contact plug passing through the first interlayer insulating film and connected to either the source region or the drain region. US2013 / 0095650A1 relates to Weffle transistors. To efficiently connect the source (or drain) regions together, a serpentine metal interconnect pattern is used. The serpentine pattern reduces metal requirement outside the array. The serpentine pattern can be enhanced by offset contacts in the source and drain regions that result in the serpentine metal interconnects being more straighter.US2007 / 0049010A1 relates to sacrificial plugs for forming contacts in integrated circuits and methods for making connections in integrated circuit assemblies. A sacrificial material may be patterned in a continuous zigzag line pattern crossing word lines.US 2003 / 0162103A1 relates to correcting a main mask pattern of a photomask by adding serifs of one type (inside or outside) to a pair of mutually adjacent corners in the pattern and adding a serif of the opposite type (outside or inside) to the edge between the corners. Such a method is also known as Optical Proximity Correction.US 2014 / 0 304 666 A1 shows a modification of the initial form of a conductive through-contact feature.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure are best understood from reading the following detailed description in conjunction with the accompanying figures. It should be appreciated that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may have been arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a top view of a semiconductor structure, in accordance with some embodiments. FIGS. 1B and 1C are cross-sectional views of the semiconductor structure of FIG. 1A along dashed lines AA' and BB', respectively, in accordance with some embodiments. FIG. 2A is a top view of a semiconductor structure, in accordance with some embodiments. FIGS. 2B and 2C are cross-sectional views of the semiconductor structure of FIG. 2A along dashed lines AA' and BB', respectively, in accordance with some embodiments. FIG. 3A is a top view of a semiconductor structure, in accordance with some embodiments. FIGS. 3B and 3C are cross-sectional views of the semiconductor structure of FIG. 3A along dashed lines AA' and BB', respectively, in accordance with some embodiments. FIG. 4 is a top view of a portion of the semiconductor structure of FIG. 3A constructed in accordance with some embodiments. FIGS. 5A, 5B, 5C, and 5D are cross-sectional views of a conductive via feature in the semiconductor structure of FIG. 4, in accordance with some embodiments. FIGS. 6A, 6B, 6C, 6D, and 6E are cross-sectional views of the conductive via feature in the semiconductor structure of FIG. 4 constructed in accordance with some embodiments at various stages of fabrication. FIG. 7 is a flow diagram of a method of manufacturing integrated circuits, in accordance with some embodiments. FIGS. 8A, 8B, 8C, 8D, and 8E are cross-sectional views of the conductive via feature in the semiconductor structure of FIG. 4 constructed in accordance with some embodiments at various stages of fabrication. FIG. 9 is a flow diagram of a method of manufacturing integrated circuits, in accordance with some embodiments. FIG. 10 is a flow diagram of a method of manufacturing integrated circuits, in accordance with some other embodiments. FIGS. 11A, 11B, and 11C are cross-sectional views of the conductive via structure in the semiconductor structure of FIG. 4 constructed in accordance with some embodiments at various stages of fabrication.DETAILED DESCRIPTIONThe invention is set out in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for carrying out various features of the invention. Hereinafter, specific examples of components and arrangements will be described in order to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that it may be that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, terms indicating a spatial relationship, such as "below", "below", "lower / r / s", "over", "upper / r / s", and the like, may be used to describe the relationship between one element or feature and (one) other element / s or feature / s, as illustrated in the figures, for convenience of description. The terms indicating a spatial relationship are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is reversed, elements described as "below" other elements or features or "below" would then be oriented "above" the other elements or features. Thus, the example term "below" may include both an orientation above and below. The device may be oriented in another manner (rotated 90 degrees or in other orientations) and the spatial relationship descriptions used herein may be construed accordingly in the same manner.The present disclosure is directed to, but is not otherwise limited to, a field effect transistor (FET) device. The FET device may be, for example, a complementary metal oxide semiconductor (COMOS) device including a P-type metal oxide semiconductor FET (PMOS) device and an N-type metal oxide semiconductor FET (PMOS) device. The FET may be two-dimensional (planar FET) or three-dimensional, such as a fin-type FET (FinFET). The following disclosure continues with an example of a FinFET to illustrate various embodiments of the present invention. It should be understood, however, that the application should not be limited to any particular type of device unless specifically claimed.FIG. 1A is a plan view of a semiconductor structure 100; and FIGS. 1B and 1C are sectional views of the semiconductor structure 100 constructed according to some embodiments along the directions AA' and BB', respectively. The semiconductor structure 100 includes a semiconductor substrate having various active regions (such as 102A and 102B) separated by isolation features 103. Various devices such as FETs are formed on the active regions. Each of the active zones comprises an elongated, such as rectangular, shape oriented in a first direction (direction X). Various gate stacks, such as gate stacks 104A, 104B, 104C, and 104D, for FETs are formed on the active regions. Each of the gate stacks includes an elongated, such as rectangular, shape that is oriented in a second direction (direction Y) that is perpendicular to the first direction. The vertical direction is the Z direction that is perpendicular to the surface of the semiconductor substrate defined by the plane XY. Various source / drain features (not shown) are formed on the active fin regions and are configured with corresponding gate stacks to form FETs. The semiconductor structure 100 further includes conductive features 106 (also referred to as conductive contact features) formed on the semiconductor substrate and configured to form contact lands on the source / drain features. In the present example, the conductive contact features 106 include example conductive contact features 106A, 106B, 106C, 106D, 106E, and 106F. To aid in the present example, conductive contact features 106A, 106B, and 106C form contact lands and directly contact corresponding source / drain features on active region 102A, while conductive contact features 106D, 106E, and 106F form contact lands on and directly contact corresponding source / drain features on active region 102B. A conductive feature 108 (referred to as a conductive via feature) is disposed on the semiconductor substrate and is configured to directly connect the conductive contact features 106A, 106C, and 106E. The conductive via feature 108 is a power rail configured to provide power (such as high power Vdd or low power Vss) to the source / drain features in the semiconductor substrate. Additional interconnect structure, including various metal lines and via features, is formed on the semiconductor substrate and is configured to couple various FETs into an operable circuit. In particular, the interconnect structure includes a metal line 110 configured to form a contact ridge on the conductive via feature 108, as illustrated in FIG. 1B.FIG. 2A is a plan view of a semiconductor structure 200; and FIGS. 2B and 2C are sectional views of the semiconductor structure 100 constructed according to some embodiments along the directions AA' and BB', respectively. The semiconductor structure 200 includes a semiconductor substrate having various active regions (such as 102A and 102B) separated by isolation features 103. Various devices such as FETs are formed on the active regions. Each of the active zones comprises an elongated, such as rectangular, shape oriented in a first direction (direction X). Various gate stacks, such as gate stacks 104A, 104B, 104C, and 104D, for FETs are formed on the active regions. Each of the gate stacks includes an elongated, such as rectangular, shape that is aligned in a second direction (direction Y) that is perpendicular to the first direction. The vertical direction is the direction Z that is perpendicular to the surface of the semiconductor substrate defined by the plane XY. Various source / drain features (not shown) are formed on the fin active regions and are configured with corresponding gate stacks to form FETs. The semiconductor structure 200 further comprises conductive contact features 106 formed on the semiconductor substrate and configured to land on the source / drain features. In the present example, the conductive contact features 106 include the example conductive contact features 106A, 106B, 106C, 106D, 106E, and 106F. To aid in the present example, conductive contact features 106A, 106B, and 106C land on and directly contact corresponding source / drain features on active zone 102A, while conductive contact features 106D, 106E, and 106F land on and directly contact corresponding source / drain features on active zone 102B. Three example conductive via features 208A, 208B, and 208C are formed on the semiconductor substrate and are configured to connect the conductive contact features 106A, 106E, and 106C, respectively. The conductive via features 208 are power rails configured to provide power (such as high power Vdd or low power Vss) to the source / drain features in the semiconductor substrate. Additional interconnect structure, including various metal lines and via features, is formed on the semiconductor substrate and is configured to couple various FETs into an operable circuit. In particular, the interconnect structure includes a metal line 110 configured to land on and electrically connect to the conductive via features 208A, 208B, and 208C, as illustrated in FIG. 2B.FIG. 3A is a plan view of a semiconductor structure 300; and FIGS. 3B and 3C are sectional views of the semiconductor structure 300 constructed according to some embodiments along the directions AA' and BB', respectively. The semiconductor structure 300 includes a semiconductor substrate having various active regions (such as 102A and 102B) separated by isolation features 103. Various devices such as FETs are formed on the active regions. Each of the active zones comprises an elongated, such as rectangular, shape oriented in a first direction (direction X). Various gate stacks, such as gate stacks 104A, 104B, 104C, and 104D for FETs, are formed on the active regions. Each of the gate stacks includes an elongated, such as rectangular, shape that is oriented in a second direction (direction Y) that is perpendicular to the first direction. The vertical direction is the direction Z that is perpendicular to the surface of the semiconductor substrate defined by the plane XY. Various source / drain features (not shown) are formed on the fin active regions and are configured with corresponding gate stacks to form FETs. The semiconductor structure 300 further includes conductive contact features 106 formed on the semiconductor substrate and configured to land on the source / drain features. In the present example, the conductive contact features include the example contact features 106A, 106B, 106C, 106D, 106E, and 106F. To aid in the present example, conductive contact features 106A, 106B, and 106C land on and directly contact corresponding source / drain features on active zone 102A, while conductive contact features 106D, 106E, and 106F land on and directly contact corresponding source / drain features on active zone 102B. A curved conductive via feature 308 is formed on the semiconductor substrate and is configured to connect the conductive contact features 106A, 106E, and 106C, respectively. In particular, the conductive via feature 308 is designed to have a curved S-shape. The curved S-shape includes at least one edge oriented in an inclined direction different from the first and second directions (directions X and Y). The curved S-shape configuration having an inclined edge provides a conductive structure to properly connect to the intended conductive contact features with enough contact area (overlap target) and to space with enough spacing from unintentional conductive contact features (spacing target). The conductive via feature 308 is a power rail configured to provide power (such as high power Vdd or low power Vss) to the source / drain features in the semiconductor substrate. Additional interconnect structure, including various metal lines and via features, is formed on the semiconductor substrate and is configured to couple multiple FETs into a functional circuit. In particular, the interconnect structure includes a metal line 110 configured to land on the conductive via feature 308 as illustrated in FIG. 3B.A portion of the semiconductor structure 300 is further constructed in FIG. 4, while the active regions 102 and the metal line 110 have been removed for simplicity. In the present embodiment, the metal contact features 106 are divided into two groups (or two subsets) according to the relationship to the conductive via feature 308. The first set of conductive contact features includes conductive contact features 106A, 106C, and 106E, which are intended to be directly connected to conductive via feature 308 according to the design. The second set of conductive contact features includes conductive contact features 106B, 106D, and 106F, where they are intended to be spaced from conductive via feature 308 according to the design. The curved S-shape of the conductive via feature 308 is a continuous feature with various displacements and deformations to have proper relationships to the two groups of conductive contact features. The conductive via feature 308 having the curved S-shape is constructed according to various rules described below to form a contact ridge on the first group of conductive contact features, thereby meeting the overlap target, and to be spaced apart from the second group of conductive contact features, thereby meeting the distance target. To achieve this, the curved S-shape includes various polygons such as squares of different sizes, rectangles of different widths and lengths, inclined rectangles of different angles, triangles, trapezoids, diamonds, and parallelograms. Various example curved S-shapes of the conductive via feature 308 are illustrated in FIGS. 5A, 5B, 5C, and 5D, in accordance with some embodiments. Usually, the designer's original design of the integrated circuit cannot meet these criteria (such as the overlap target and the distance target) because it does not know enough about the fabrication capability and because of the inefficiency of communication between the designers and the manufacturers. The following method provides a proper way to modify the integrated circuit design to meet the manufacturing rules.FIG. 7 provides a flow diagram 700 for constructing the conductive via feature 308 with the abstract rules, in accordance with some embodiments. FIGS. 6A, 6B, 6C, 6D, and 6E are the shapes of the conductive via feature 308 at various stages. In the following description, the integrated circuit design of the semiconductor structure 100 for various features (including the active regions 102, gate stacks 104, and other features) still uses the integrated circuit design and corresponding spatial relationships in FIGS. 3A through 3C and FIG. 4.Referring to FIG. 7, the method 700 begins at a block 701 by receiving an integrated circuit layout for a semiconductor structure having multiple structure layers, such as those illustrated in FIGS. 3A to 3C. For example, the integrated circuit layout includes a first pattern layer defining active regions 102; a second pattern layer defining gate stacks 104; a third pattern layer defining conductive contact features 106 forming contact lands on corresponding active regions; and a fourth pattern layer defining a conductive via feature 308 forming contact lands on a subset (or first group) of the conductive contact features 106. Additional structure layers may be present in the integrated circuit layout. For example, an interconnect structure including various metal lines and via features in respective structure layers is formed on the semiconductor substrate and is configured to couple various FETs into an operable circuit.Referring to FIGS. 7 and 6A, the method 700 continues with an operation 702 by constructing the conductive via feature having a rectangle with a length and a width to form contact lands on all conductive contact features, thereby meeting the overlap goal. In the present example, the rectangle is oriented with its length in the first direction (direction X), as illustrated in FIG. 6A. This rectangle is referred to as an output rectangle.Referring to FIGS. 7 and 6B, the method 700 continues with an operation 704 by viewing a conductive contact feature from the second group and removing a polygon from the starting rectangle. In particular, the polygon is removed from the location of the overlap zone between the starting rectangle of the conductive via feature and the conductive contact feature under consideration. The dimensions of the polygon can be evaluated and determined according to certain rules, such as the overlap area plus the distance. The polygon may be a polygon having any number of sides, such as a square, a rectangle, a triangle, a trapezoid, a diamond, and a parallelogram. Edges of the polygon may be at any angle including an inclined angle different from the directions X and Y. For example, the conductive contact feature 106D is viewed and a polygon is removed from the overlap zone. In this case, the polygon is a rectangle. After removal at operation 704, the shape of the conductive via feature is illustrated in FIG. 6B.Referring to FIG. 7, the method 700 continues with an operation 706 by evaluating whether a lateral distance (or distance) between the considered conductive contact feature (106D in this example) and the conductive via feature meets the distance target. If not, the method returns to operation 704 by removing another polygon from the conductive via feature. If it satisfies the distance target, the method 700 continues with the following operation 708. The method 700 is repeated until the distance target is reached.Referring to FIG. 7, the method 700 continues with an operation 708 by checking whether all conductive contact features in the second group are exhausted. If not, the method 700 returns to operation 704 for another conductive contact feature in the second group. For example, a different conductive contact feature 106F in the second group is considered and a different polygon (such as a rectangle) is removed from the conductive via feature, resulting in a curved shape, as illustrated in FIG. 6C. For another example, yet another conductive contact feature 106B in the second group is considered and another polygon (such as a rectangle) is removed from the conductive via feature, resulting in a curved S-shape, as illustrated in FIG. 6D. Further, if the distance target is still not reached, another polygon is removed from the conductive via feature 308. For example, if the conductive contact feature 106D and the conductive via feature 308 are not sufficiently spaced, another polygon (such as a triangle) is removed. As another example, if the conductive contact feature 106F and the conductive via feature 308 are not spaced apart enough, another polygon, such as a triangle, is removed and so on, resulting in the conductive via feature 308 having a curved S-shape, as illustrated in FIG. 6E. In particular, the curved S-shape 308 in FIG. 6E includes one or more sloped edges, such as edges 602, 604, and other sloped edges, each having a corresponding sloped angle that is different from the directions X and Y.Referring to FIG. 7, the method 700 may include other operations, such as an operation 710 for generating a tape-out for mask fabrication according to the modified integrated circuit design including the conductive via feature 308 having a curved S-shape further having at least one sloped edge. The tape-out defines the modified integrated circuit design to be formed on photomasks for wafer fabrication or transferred directly to semiconductor wafers by direct writing techniques such as electron beam direct writing. The tape-out of the modified integrated circuit design includes various structural layers (such as a layer of active regions, a layer of gate stacks, and so forth) and the spatial relationships among these structural layers, particularly various shapes and sizes of various structural features in each structural layer. The method 700 may further include forming photomasks according to the tape-out defining the modified integrated circuit design having a conductive via feature 308 with a curved S-shape.FIG. 9 illustrates a flow diagram 900 for constructing the conductive via feature 308 with the addition rules, in accordance with some embodiments. FIGS. 8A, 8B, 8C, 8D, and 8E are the shapes of the conductive via feature 308 in various steps. In the following description, the integrated circuit design of the semiconductor structure 100 for various features (including the active regions 102, gate stacks 104, and other features) and corresponding spatial relationships still uses the integrated circuit design in FIGS. 3A to 3C and FIG. 4.Referring to FIG. 9, the method 900 begins at a block 701 by receiving an integrated circuit layout for a semiconductor structure having multiple structure layers. For example, the integrated circuit layout includes a first pattern layer defining active regions 102; a second pattern layer defining gate stacks 104; a third pattern layer defining conductive contact features forming contact lands on corresponding active regions; and a fourth pattern layer defining a conductive via feature forming contact lands on a subset of the conductive contact features, such as those illustrated in FIGS. 3A-3C. Additional structure layers may be present in the integrated circuit layout.Referring to FIGS. 9 and 8A, the method 900 continues with operation 902 by constructing the conductive via feature having a rectangle with a length and a width small enough so as not to form a contact ridge on one of the conductive contact features or to be spaced from any of the conductive contact features by a lateral distance that satisfies the spacing target, meaning that the lateral distance is equal to or greater than the spacing target. In the present example, the rectangle is oriented with its length in the first direction (direction X), as illustrated in FIG. 8A. This rectangle is referred to as an output rectangle.Referring to FIGS. 9 and 8B, the method 900 continues with operation 904 by viewing a conductive contact feature from the first group and adding a polygon to the output rectangle. In particular, the polygon is added at the location of the conductive contact feature under consideration such that the modified conductive via feature overlaps with the conductive contact feature under consideration. The dimensions of the polygon may be evaluated and determined according to certain rules, such as the existing distance plus the overlap target. The polygon may be a polygon having any number of sides, such as a square, a rectangle, a triangle, a trapezoid, a diamond, and a parallelogram. Edges of the polygon may be at any angle including an inclined angle different from the directions X and Y. For example, the conductive contact feature 106A is considered and a polygon is added to the conductive contact feature. In this case, the polygon is a rectangle. After the addition in operation 904, the shape of the conductive via feature is illustrated in FIG. 8B.Referring to FIG. 9, method 900 continues with operation 906 by evaluating whether the overlap area between the considered conductive contact feature (106A in this example) and the conductive via feature meets the overlap target. If not, return to operation 904 is made by adding another polygon to the conductive via feature. If it satisfies the overlap objective, the method 900 continues with the following operation 908 to check whether all conductive contact features in the first group are exhausted. The method 900 is repeated until the overlap target is reached.Referring to FIG. 9, the method 900 continues with an operation 908 by checking whether all conductive contact features in the first group are exhausted by the previous operations. If not, the method 900 returns to operation 904 for another conductive contact feature in the first group. For example, another conductive contact feature 106C is considered in the first group and another polygon (such as a rectangle) is added to the conductive via feature, resulting in a curved shape, as illustrated in FIG. 8C. For another example, another conductive contact feature 106E is considered in the first group and another polygon (such as a rectangle) is added to the conductive via feature, resulting in a curved S-shape, as illustrated in FIG. 8D. Further, if the overlap target is not yet reached, another polygon is added to the conductive via feature 308. For example, if the conductive contact feature 106A and the conductive via feature 308 do not have enough contact area, another polygon (such as a trapezoid) is added to the conductive via feature. For another example, if the conductive contact feature 106C and the conductive via feature 308 do not have enough contact area, another polygon (such as a trapezoid) is added and so on, resulting in the conductive via feature 308 having a curved S-shape, as illustrated in FIG. 8E. In particular, the curved S-shape 308 in FIG. 8E includes one or more sloped edges, such as edges 802, 804, and other sloped edges, each having a corresponding sloped angle that is different from the directions X and Y. The inclined angle of the conductive via feature 308 is generated because an inclined polygon is added to increase the contact area and also to avoid the violation of the distance target to the adjacent conductive contact features in the second group.Referring to FIG. 9, the method 900 may include other operations, such as an operation 910 of creating a tape-out for mask fabrication according to the modified integrated circuit design including the conductive via feature having a curved S-shape further having at least one sloped edge. The tape-out defines the modified integrated circuit design to be formed on photomasks or transferred directly to semiconductor wafers by direct writing techniques such as electron beam direct writing. The tape-out of the modified integrated circuit design includes different structural layers and spatial relationships among these structural layers, particularly different shapes and sizes of different structural features in each structural layer. The method 900 may further include manufacturing photomasks according to the tape-out defining the modified integrated circuit design having a conductive via feature with a curved S-shape.FIG. 10 provides a flow diagram 1000 for constructing the conductive via feature 308, in accordance with some embodiments. The method 1000 begins at a block 701 by receiving an integrated circuit layout for a semiconductor structure comprising a plurality of structure layers. For example, the integrated circuit layout includes a first pattern layer defining active regions 102; a second pattern layer defining gate stacks 104; a third pattern layer defining conductive contact features forming contact lands on respective active regions; and a fourth pattern layer defining a conductive via feature forming contact lands on a subset of the conductive contact features such as those illustrated in FIGS. 3A-3C. Additional structure layers may be present in the integrated circuit layout.The method 1000 continues with operation 1002 by constructing an initial shape of the conductive via feature. The initial shape may be a polygon or other suitable shape. The initial shape may be a shape from the designer when the original design of the integrated circuit is received by the designer. In one embodiment, operation 1002 constructs the initial shape of the conductive via feature to have a rectangle with a length and a width to form a contact ridge on all conductive contact features that meet the overlap target. In another embodiment, operation 1002 constructs the initial shape of the conductive via feature to have a rectangle with a length and width small enough to not form a contact ridge on one of the conductive contact features or to space from each of the conductive contact features by a lateral distance that meets the distance target.The method 1000 continues with an operation 1004 by viewing a conductive contact feature and determining which group it belongs to. In operation 1004, a spatial parameter between the conductive via feature and the considered conductive contact feature is evaluated. This spatial relationship defines whether the two are connected or spaced apart according to the integrated circuit layout. Accordingly, the conductive contact features are divided into two groups. The first group includes all conductive contact features to be contacted with the conductive via feature. The second group includes all conductive contact features to be spaced from the conductive via feature. If the considered conductive contact feature belongs to the first group, proceeding to an operation 1006. If it belongs to the second group, the process continues with an operation 1008.At operation 1004, if the considered conductive contact feature is from the first group, the method 1000 continues with operation 1006. At operation 1006, a polygon is added to the conductive via feature. In particular, the polygon is added at the location of the conductive contact feature under consideration such that the modified conductive via feature overlaps with the conductive contact feature under consideration. The dimensions of the polygon may be evaluated and determined according to certain rules, such as the existing distance plus the overlap target. The polygon may be a polygon having any number of sides, such as a square, a rectangle, a triangle, a trapezoid, a diamond, and a parallelogram. Edges of the polygon may be at any angle having an inclined angle different from the directions X and Y. For example, the conductive contact feature 106A is considered and a polygon is added to the conductive via feature.The method 1000 continues with an operation 1010 by evaluating whether the overlap area between the considered conductive contact and the conductive via feature meets the overlap target. If not, return to operation 1006 by adding another polygon to the conductive via feature. The method 1000 is repeated until the overlap target is reached. When the overlap target is reached, the method 1000 continues with the following operation 1014. The distance rule may also be considered in operations 1006 and 1010. If the addition of a polygon causes a lateral distance between the conductive via feature 308 and an adjacent conductive contact feature of the second group to be decreased, an inclined polygon may be added to satisfy both the overlap target and the distance target.At operation 1004, if the considered conductive contact feature belongs to the second group, method 1000 continues with operation 1008. At operation 1008, a polygon is removed from the conductive via feature. Specifically, the polygon is removed from the location of the target conductive contact feature such that the modified conductive via feature is spaced from the target conductive contact feature such that a lateral distance therebetween becomes equal to or greater than the distance target. The dimensions of the polygon can be evaluated and determined according to certain rules, such as the existing overlap plus the distance target. The polygon may be a polygon having any number of sides, such as a square, a rectangle, a triangle, a trapezoid, a diamond, and a parallelogram. Edges of the polygon may have any angle including an inclined angle different from the directions X and Y.The method 1000 continues with an operation 1012 by evaluating whether the distance between the considered conductive contact and the conductive via feature meets the distance target. If not, return to operation 1008 by removing another polygon from the conductive via feature. The method 1000 is repeated until the distance target is reached. When it reaches the distance target, the method 1000 continues with the following operation 1014. The overlap rule may also be considered in operations 1008 and 1012. If removing a polygon causes an overlap area between the conductive via feature 308 and an adjacent conductive contact feature of the first group to be reduced, an inclined polygon may be removed to satisfy both the distance target and the overlap target.Operation 1014 includes checking whether all conductive contact features (both the first group and the second group) are exhausted by the previous operations. If not, the method 1000 returns to operation 1004 for another conductive contact feature. Thus, the end conductive via feature 308 has a curved S-shape that includes one or more sloped edges each having a corresponding sloped angle that is different from the directions X and Y.The method 1000 may include other operations, such as an operation 910 of generating a tape-out for mask fabrication according to the thus modified integrated circuit design having a conductive via feature having a curved S-shape further having at least one sloped edge. The tape-out defines the modified integrated circuit design to be formed on photomasks or transferred directly to the semiconductor wafers by direct writing techniques such as electron beam direct writing. The tape-out of the modified integrated circuit design includes different structural layers and spatial relationships among these structural layers, particularly different shapes and sizes of different structural features in each structural layer. The method 900 may further include manufacturing photomasks according to the tape-out defining the modified integrated circuit design having a conductive via feature with a curved S-shape. The method 900 may further include manufacturing semiconductor wafers using the photomasks.Various embodiments of an integrated circuit design are provided for the semiconductor structure and the method for manufacturing the same. Other embodiments may be present. For example, the method 700 may begin with a starting shape and then a polygon may be added to reach another conductive contact feature in the first group in a manner (in terms of shape, size, and inclined angle) to be spaced from an adjacent conductive contact feature in the second group. This procedure continues until the conductive via feature on all conductive contact features in the first group forms a contact land with sufficient contact area (thereby achieving the overlap target) and is spaced apart from all conductive contact features in the second group by sufficient distance (thereby achieving the spacing target). The example conductive via feature 308 is illustrated in FIG. 11A in one step. After a few polygons have been added more, the example conductive via feature 308 is extended, as illustrated in FIG. 11B. After some further cycles in the iteration of adding polygons, the conductive via feature 308 is further extended, as illustrated in FIG. 11C.The present disclosure provides an integrated circuit design for a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a conductive via feature forming contact lands on a subset of conductive contact features in the underlying conductive layer to couple various source / drain features of FETs in the active regions. The conductive via feature in the integrated circuit design for the semiconductor structure is designed to have a curved S-shape. The curved S-shape includes at least one edge oriented in an inclined direction that is different from the standard directions, such as the orientation of the elongated gate stacks and the orientation of the elongated active fin zones.The embodiments of the present disclosure provide advantages over the prior art, although it should be understood that other embodiments may provide different advantages, not all advantages are necessarily discussed herein, and that no particular advantage is required for all embodiments. Through the use of the method and structure disclosed, the curved S-shape of the conductive via feature provides freedom and flexibility for the formation of contact lands on the intended conductive contact features with sufficient contact pads and sufficient distance from the unintentional conductive contact features.Thus, the present disclosure provides a method of manufacturing an integrated circuit. The method includes receiving an integrated circuit design having active zones, conductive contact features forming contact lands on the active zones, and a conductive via feature to form contact lands on a first subset of the conductive contact features and to be spaced apart from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the integrated circuit layout according to the spatial parameter such that the conductive via feature has a curved S-shape.The present disclosure provides a method of manufacturing an integrated circuit. The method includes receiving an integrated circuit layout having a first structure layer, a second structure layer, and a third structure layer to be formed on respective material layers of a semiconductor substrate. The first structure layer includes a first active region and a second active region, both having elongated shapes oriented in a first direction. The second structural layer includes a plurality of conductive contact features having an elongated shape oriented in a second direction that is orthogonal to the first direction, the conductive contact features forming contact lands on the first and second active zones. The third structure layer includes a conductive via feature that forms contact lands on the conductive contact features. The method further includes constructing an output shape of the conductive via feature; and modifying the output shape of the conductive via feature to a modified shape that overlaps with a first subset of the conductive contact features and is spaced apart from a second subset of the conductive contact features. The modified form is an S-shaped polygon having an edge oriented in an inclined direction that is different from the first and second directions.The present disclosure provides a method of manufacturing an integrated circuit. The method includes receiving an integrated circuit layout including a first structure layer and a second structure layer to be formed on respective material layers of a semiconductor substrate. The first structural layer includes first conductive contact features and second conductive contact features spaced apart along a first direction, each of the first and second contact features having an elongated shape oriented in a second direction that is orthogonal to the first direction. The second pattern layer includes a conductive via feature for forming a contact ridge on the first of the conductive contact features to be spaced apart from the second conductive contact features. The method further includes modifying the conductive via feature to a first polygon that overlaps with the first conductive contact features and is spaced apart from the second conductive contact features. The first polygon has an edge oriented in an inclined direction different from the first and second directions.

Claims

A method of manufacturing an integrated circuit (100), comprising: receiving an integrated circuit layout having active zones (102) and conductive contact features (106) landing on the active zones and having a conductive via feature (308) to landing on a first subset of the conductive contact features (106A, 106E, 106C) and to be spaced apart from a second subset (106D, 106B, 106F) of the conductive contact features; constructing an initial shape of the conductive via feature that overlaps with all or none of the conductive contact features; evaluating a spatial parameter of the conductive via feature (308) to the conductive contact features (106); and modifying the initial shape of the conductive via feature (308) according to the spatial parameter such that the conductive via feature (308) has a curved S-shape and lands on the first subset of the conductive contact features (106A, 106E, 106C) and is spaced apart from the second subset (106D, 106B, 106F) of the conductive contact features.The method of claim 1, further comprising: forming shallow trench isolation features on the semiconductor substrate (100), thereby defining the active zones (102); forming the conductive contact features (106) landing on respective active zones, respectively; and forming the conductive via feature (308) having the curved S-shape landing directly on the first subset (106A, 106E, 106C) of the conductive contact features.The method of claim 2, wherein forming the conductive contact feature (308) having the curved S-shape on the semiconductor substrate (100) comprises: forming a pattern on a photomask, the pattern defining the conductive via feature (308) having the curved S-shape; and transferring the pattern to the semiconductor substrate (100) through a lithography process using the photomask.The method of any preceding claim, wherein: evaluating the spatial parameter of the conductive via feature (308) to the conductive contact features (106) comprises evaluating an overlap area between the conductive via feature and one of the conductive contact features in the first subset (106A, 106E, 106C); and modifying the integrated circuit layout comprises adding a rectangle to the conductive via feature (308) if the overlap area is less than an overlap target.The method of any preceding claim, wherein: evaluating the spatial parameter of the conductive via feature (308) to the conductive contact features comprises evaluating a lateral distance between the conductive via feature (308) and one of the conductive contact features in a second subset (106D, 106B, 106F); and modifying the integrated circuit layout comprises removing a rectangle from the conductive via feature if the lateral distance is less than a distance target.The method of any preceding claim, wherein the conductive contact features (106) comprise a first conductive contact feature and a second conductive contact feature having elongated shapes and oriented in a first direction.The method of claim 6, further comprising assigning an initial shape to the conductive via feature (308), wherein the initial shape of the conductive via feature (308) comprises a rectangle whose length extends along a second direction orthogonal to the first direction.The method of claim 7, wherein evaluating the spatial parameter of the conductive via feature (308) to the conductive contact features (106) comprises: evaluating an overlap area between the first conductive contact feature (106) and the conductive via feature (308) when the first conductive contact belongs to the first subset (106A, 106E, 106C) of the conductive contact features; and evaluating a lateral distance between the second conductive contact feature and the conductive via feature (308) when the second conductive contact feature belongs to the second subset (106D, 106B, 106F) of the conductive contact features.The method of claim 8, wherein modifying the integrated circuit layout comprises: adding a first shape to the conductive via feature (308) if the overlap area is less than an overlap target; and removing a second shape from the conductive via feature (308) if the lateral distance is less than a distance target.The method of claim 9, wherein each of the first and second shapes is a two-dimensional polygon selected from a square, a rectangle, a triangle, a trapezoid, a diamond, and a parallelogram.The method of claim 10, wherein one of the first and second polygons comprises an edge oriented in a third direction that is different from the first and second directions.The method of any of the preceding claims 9 to 11, wherein modifying the integrated circuit layout comprises: adding a third shape to the conductive via feature (308) until the overlap area between the first conductive contact feature (106) and the conductive via feature (308) meets the overlap target; and removing a fourth shape from the conductive via feature (308) until the lateral distance between the second conductive contact feature (106) and the conductive via feature (308) reaches the clearance target.A method of manufacturing an integrated circuit (100), comprising: receiving an integrated circuit layout comprising a first structure layer, a second structure layer, and a third structure layer to be formed on respective material layers of a semiconductor substrate, wherein the first structure layer comprises a first active region (102A) and a second active region (102B) both having elongated shapes aligned in a first direction, the second structure layer comprises a plurality of conductive contact features (106) having an elongated shape aligned in a second direction orthogonal to the first direction, wherein the conductive contact features form contact lands (108) on the first and second active regions, and the third structure layer comprises a conductive via feature (308) landing on the conductive contact features; Constructing an initial shape of the conductive via feature that overlaps with all or none of the conductive contact features; and modifying the initial shape of the conductive via feature (308) to a modified shape that is overlapped by a first subset of the conductive contact features (106A, 106E, 106C) and spaced apart from a second subset of the conductive contact features (106D, 106B, 106F), wherein the modified shape comprises a curved S-shaped polygon having an edge oriented in an inclined direction that is different from the first and second directions.The method of claim 13, wherein constructing the initial shape of the conductive via feature (308) comprises constructing a first rectangle having a length and width large enough to overlap with each of the conductive contact features.The method of claim 14, further comprising: removing a second rectangle from the conductive via feature (308) in a zone corresponding to that of a first conductive contact feature (106) from the conductive contact features when the first conductive contact feature belongs to the second subset (106B, 106D, 106F) of the conductive contact features and when a lateral distance between the first conductive contact feature (106) and the conductive via feature (308) is less than a distance target.The method of any of the preceding claims 13 to 15, wherein constructing the initial shape of the conductive via feature (308) comprises constructing a first rectangle having a length and a width that are spaced from each of the conductive contact features (106).The method of claim 16, further comprising: adding a second rectangle to the conductive via feature (308) in a zone corresponding to that of a first conductive contact feature (106) of the conductive contact features when the first conductive contact feature belongs to the first subset (106A, 106E, 106C) of the conductive contact features and when an overlap area between the first conductive contact feature (106) and the conductive via feature (308) is less than an overlap target.A method of manufacturing an integrated circuit, comprising: receiving an integrated circuit layout having a first pattern layer and a second pattern layer to be formed on respective material layers of a semiconductor substrate, wherein the first pattern layer comprises first conductive contact features (106A, 106C) and second conductive contact features (106B, 106F) spaced apart along a first direction, each of the first and second contact features having an elongated shape aligned in a second direction orthogonal to the first direction, and the second pattern layer comprises a conductive via feature (308) to land on the first conductive contact features and to be spaced apart from the second conductive contact features; Constructing an output shape of the conductive via feature that overlaps with all or none of the conductive contact features, and modifying the output shape of the conductive via feature (308) to a first polygon that overlaps with the first conductive contact features (106A, 106C) and is spaced apart from the second conductive contact features (106B, 106F), wherein the first polygon has an edge that is oriented in an inclined direction that is different from the first and second directions.The method of claim 18, wherein modifying the conductive via feature (308) comprises: removing a second polygon from the conductive via feature (308) when a lateral distance between one of the second conductive contact features (106) and the conductive via feature is less than a clearance target; adding a third polygon to the conductive via feature (308) when an overlap area between one of the first conductive contact features (106) and the conductive via feature (308) is less than an overlap target; removing a fourth polygon from the conductive via feature until the lateral distance reaches the clearance target; and adding a fifth polygon to the conductive via feature (308) until the overlap area meets the overlap target.The method of claim 19, wherein modifying the conductive via feature (308) comprises: evaluating a lateral distance between each of the second conductive contact features (106) and the conductive via feature (308), and modifying the conductive via feature (308) until the corresponding lateral distance reaches the distance target; and evaluating an overlap area between each of the first conductive contact features (106) and the conductive via feature (308), and modifying the conductive via feature (308) until the corresponding overlap area meets the overlap target.

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