Method for removing an etching mask

Abstract

Method comprising: Forming a patterned etching mask (32) over a target layer (28) over a front side of a wafer (100), Structuring the target layer (28) using the structured etching mask (32) as a mask to form a structured target layer (28) and to create a residue layer (60) on sidewalls of the structured target layer (28) and the structured etching mask (32), Performing a first cleaning process (62) on the structured etching mask (32) and the structured target layer (28), wherein the first cleaning process (62) comprises a first solution, wherein the first cleaning process (62) removes a substantial portion of the residue layer (60) on the structured etching mask (32) and the structured target layer (28), wherein portions of the residue layer (60) remain on sidewalls of the structured etching mask (32) and the structured target layer (28), Performing a second cleaning process (64) to remove the patterned etch mask (32) and form an exposed patterned target layer (28), wherein the second cleaning process (64) comprises a second solution, wherein the second cleaning process (64) causes the remaining residue layer (60) to aggregate on sidewalls of the patterned target layer (28) and form a residue condensate (66) on sidewalls of the patterned target layer (28), Performing a third cleaning process (68) on the exposed structured target layer (28); and Performing a fourth cleaning process (80) on the exposed structured target layer (28), wherein the fourth cleaning process (80) comprises the first solution, wherein the third cleaning process (68) and the fourth cleaning process (80) remove the residual condensate (66) from the sidewalls of the structured target layer (28).

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and then patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. However, with the reduction of the smallest feature sizes, additional problems emerge that must be addressed.

[0003] The prior art relating to the subject matter of the invention can be found, for example, in the documents US 2015 / 0 128 991 A1, US 2006 / 0 148 197 A1, US 2015 / 0 147 882 A1, US 5 919 311 A, US 2006 / 0 051 930 A1 and US 2006 / 0 071 275 A1.

[0004] The invention is defined by independent claim 1. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1A, 1B and 2 to 27 show top and cross-sectional views of various intermediate stages of fabricating a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0008] Fig. 1A, 1B, and 2 through 27 illustrate top and cross-sectional views of intermediate stages in forming features in a target layer (e.g., an underlying mandrel layer) according to some embodiments. Some figures include a top and cross-sectional view of a wafer 100 in the same figure, where the edges of the illustrated features in the top view may be substantially aligned with the edges of the illustrated features in the respective cross-sectional view.

[0009] Fig. 1A illustrates wafer 100 at an intermediate stage of patterning a semiconductor device according to one embodiment. Fig. 1A shows a top view and a cross-sectional view of the semiconductor device at an intermediate stage of processing. The wafer 100 includes a substrate 120. The substrate 120 may, for example, include doped or undoped bulk silicon or an active layer of an SOI (semiconductor on insulator) substrate. In general, an SOI substrate includes a layer of a semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may, for example, be a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate 120 may include another elemental semiconductor, such asGermanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0010] As in Fig. 1A, the wafer includes an etch stop layer 26 formed over the substrate 120. The etch stop layer 26 may include multiple layers. The etch stop layer 26 may act as a mask (e.g., a three-layer mask) for a subsequent etch, which transfers a pattern of a target layer 28 overlying the etch stop layer 26 to the substrate 120. Referring to Fig. 1B, the etch stop layer 26 may include a first pad layer 26A, which may be a thin film formed from an oxide (e.g., silicon oxide). Accordingly, the first pad layer 26A may be referred to as a pad oxide layer. According to some embodiments of the present disclosure, the pad oxide layer 26A is formed in a thermal oxidation process, wherein a top surface layer of the substrate 120 is oxidized. The pad oxide layer 26A may have a thickness between approximately 1 nmÅ and approximately 5 nm (e.g., approximately 2.5 nm).

[0011] The pad oxide layer 26a may act as an adhesion layer between the substrate 120 and a second pad layer 26b, which may be formed from a nitride (e.g., silicon nitride), for example, using low-pressure chemical vapor deposition (LPCVD). Accordingly, the second pad layer 26b may be referred to as a pad nitride layer. According to other embodiments of the present disclosure, the pad nitride layer 26b is formed by thermal nitriding of silicon, plasma-enhanced chemical vapor deposition (PECVD), or anodic plasma nitriding. The pad nitride layer 26b may have a thickness between approximately 20 nm and approximately 30 nm (e.g., approximately 26 nm). According to some embodiments of the present disclosure, the etch stop layer 26 may include an oxide layer 26c formed over the pad nitride layer 26b.According to some embodiments, the oxide layer 26c may comprise silicon oxide and may be formed, for example, using PECVD or chemical vapor deposition (CVD). The oxide layer 26c may have a thickness between about 40 nm and about 80 nm (e.g., about 60 nm). The target layer 28 is further formed over the etch stop layer 26. In some embodiments, the target layer 28 is a layer to be etched in subsequent steps in which, according to embodiments of the present disclosure, a plurality of structures are to be formed therein. In some embodiments, the target layer 28 may comprise amorphous silicon, amorphous carbon, AlO. x N y, another material having high etch selectivity to the underlying etch stop layer 26, the like, or a combination thereof, and may be formed using CVD, atomic layer deposition (ALD), the like, or a combination thereof. The target layer 28 may be referred to as a first mandrel layer or an underlying mandrel layer in some embodiments.

[0012] As in Fig. 1A, a first mask layer 32 may overlie the target layer 28, and a second mask layer 34 may overlie the first mask layer 32. In some embodiments, the first mask layer 32 may be a first hard mask layer, and the second mask layer 34 may be a second hard mask layer. The first mask layer 32 may comprise silicon nitride, titanium nitride, titanium oxide, the like, or a combination thereof, and may be formed using CVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the first mask layer 32 may have a thickness of between about 10 nm and about 50 nm. The second mask layer 34 may comprise tetraethyl orthosilicate (TEOS), carbon-doped silicon oxide (SiCOH), SiOxCy, the like, or a combination thereof, and may be formed using spin-on coating, CVD, ALD, the like, or a combination thereof.In some embodiments, the second mask layer 34 may have a thickness of between approximately 10 nm and approximately 50 nm. In some embodiments, materials for the first mask layer 32 and the second mask layer 34 are selected such that the first mask layer 32 and the second mask layer 34 have desired etch rates for subsequent patterning processes. As described in more detail below, the second mask layer 34 is patterned by transferring a plurality of patterns to the second mask layer 34. The plurality of patterns in the second mask layer 34 are then transferred to the first mask layer 32, and the patterns of the first mask layer 32 are then transferred to the target layer 28.

[0013] A second mandrel layer 36 is formed over the second mask layer 34. In some embodiments, the second mandrel layer 36 (which may be referred to as an overlying mandrel layer) may comprise amorphous silicon, amorphous carbon, AlO x N y , another material having high etch selectivity to the underlying second mask layer 34, the like, or a combination thereof, and may be formed using CVD, ALD, the like, or a combination thereof.

[0014] A first three-layer mask is disposed over the second mandrel layer 36, comprising a bottom layer (sometimes referred to as a bottom layer) 38, a middle layer 40 over the bottom layer 38, and an upper layer 42 over the middle layer 40. The bottom layer 38 may comprise an organic material, such as a spin-on carbon (SOC) material or the like, and may be formed using spin coating, CVD, ALD, or the like. In some embodiments, a thickness of the bottom layer 38 may be between about 50 nm and about 200 nm. The middle layer 40 may comprise an inorganic material, which may be a nitride (such as SiN, TiN, TaN, or the like), an oxynitride (such as SiON), an oxide (such as silicon oxide), or the like, and may be formed using CVD, ALD, or the like.In some embodiments, a thickness of the middle layer 40 may be between about 10 nm and about 40 nm. The top layer 42 may comprise an organic material, such as a photoresist material, and may be formed using spin coating or the like. In some embodiments, a thickness of the top layer 42 may be between about 50 nm and about 150 nm. In some embodiments, the middle layer 40 has a higher etch rate than the top layer 42, and the top layer 42 is used as an etch mask for patterning the middle layer 40. The bottom layer 38 has a higher etch rate than the middle layer 40, and the middle layer 40 is used as an etch mask for patterning the bottom layer 38.

[0015] After applying the upper layer 42, the upper layer 42 is patterned to form openings 44 therein. The upper layer 42 is patterned using suitable photolithographic techniques. In some embodiments where the upper layer 42 comprises a photoresist material, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In some embodiments, each of the openings 44 has a width W1 between about 30 nm and about 50 nm and a length L1 between about 60 nm and about 6000 nm. As shown in the top view (also in Fig. 1A) on the wafer 100, the openings 44 may have stripe shapes. In some embodiments, the pitch P1 of the openings 44 is approximately three times the width W1 of the openings 44. Throughout the description, the structures of the openings 44 are also referred to as line A1 structures.

[0016] A first etching process is then performed to transfer the structure in the upper layer 42 to the second mandrel layer 36, resulting in the Fig. 2. During the etching step, the upper layer 42, the middle layer 40, and the lower layer 38 may be removed. If a residue of the upper layer 42, the middle layer 40, and the lower layer 38 remains after patterning, the residue is also removed. The etching is anisotropic, so that the openings 44 in the second mandrel layer 36 have the same sizes as their respective openings 44 in the upper layer 42 ( Fig. 1A). The one or more etching processes may include isotropic wet etching processes, anisotropic dry etching processes, or combinations thereof. The remaining portions of the second mandrel layer 36 in Fig. 2 are referred to as intermediate mandrels, which include intermediate mandrels 36A and 36B.

[0017] With reference to Fig. 3, a first spacer layer 46 is conformally formed (e.g., using ALD) over the intermediate mandrels 36A and 36B and in the openings 44. Accordingly, a width and a length of the openings 44 are reduced by approximately twice a thickness T1 of the first spacer layer 46. The first spacer layer 46 may comprise an oxide (such as silicon oxide, aluminum oxide, titanium oxide, or the like), a nitride (such as SiN, titanium nitride, or the like), an oxynitride (such as SiON or the like), an oxycarbide (such as SiOC or the like), a carbonitride (such as SiCN or the like), the like, or a combination thereof, and may be formed using CVD, PECVD, ALD, the like, or a combination thereof. In some embodiments, the thickness T1 of the first spacer layer 46 may be between approximately 10 nm and approximately 20 nm.

[0018] With reference to Fig. 4, the first spacer layer 46 is patterned to form first spacers 48 on sidewalls of the openings 44. In some embodiments, the first spacer layer 46 is patterned using an anisotropic dry etching process to remove horizontal portions of the first spacer layer 46 from a top surface of the intermediate mandrels 36A and 36B and bottom surfaces of the openings 44. Portions of the first spacer layer 46 remaining on the sidewalls of the openings 44 form the first spacers 48. In some embodiments, the first spacer layer 46 is patterned using a dry etching process, wherein the etching process gases Cl2, O2, C x H y F z , N2, H2, HBr, Cl2, He, the like, or a combination thereof. The intermediate mandrels 36A and 36B may then be removed. This process for removing the intermediate mandrels 36A and 36B is described in Fig. 5 and Fig. 6 shown.

[0019] With reference to Fig. 5, a second three-layer mask is formed over the intermediate mandrels 36A and 36B and the first spacers 48. The second three-layer mask includes a lower layer 50, a middle layer 52 over the lower layer 50, and an upper layer 54 over the middle layer 52. In some embodiments, the lower layer 50, the middle layer 52, and the upper layer 54 may be formed using similar materials and methods as, respectively, the lower layer 38, the middle layer 40, and the upper layer 42 of the first three-layer mask described above with reference to Fig. 1A, and the description is not repeated here for brevity. In some embodiments, a thickness of the lower layer 50 may be between about 50 nm and about 200 nm, a thickness of the middle layer 52 may be between about 10 nm and about 40 nm, and a thickness of the upper layer 54 may be between about 50 nm and about 150 nm. The upper layer 54 is patterned to form openings 56 such that the openings 44 in the intermediate mandrels 36A and 36B are protected by the upper layer 54. In some embodiments, the upper layer 54 may be patterned using similar techniques as the upper layer 42 of the first three-layer mask described above with reference to Fig. 1A, and the description is not repeated here for brevity. In the illustrated embodiment, the openings 56 are formed in the upper layer 54. In other embodiments, fewer or more than three openings 56 may be formed in the upper layer 54.

[0020] With reference to Fig. 6, a patterning process is performed to remove the intermediate mandrels 36A and 36B. In some embodiments, the patterning process includes one or more etching processes, wherein the second three-layer mask and the first spacers 48 are used as a combined etch mask to form openings 58 at positions previously occupied by the intermediate mandrels 36A and 36B. The one or more etching processes may include isotropic wet etching processes, anisotropic dry etching processes, or combinations thereof. During the patterning process used to remove the intermediate mandrels 36A and 36B, the top layer 54, the middle layer 52, and the bottom layer 50 may be removed. A pattern of the openings 58 may also be referred to as a line-B (LB) structure. Accordingly, the pattern described with reference to Fig. 5 described photolithographic process may also be referred to as LB photolithography, and which with reference to Fig. The etching processes described in 6 can also be referred to as LB etching.

[0021] With reference to Fig. 7, the first spacers 48 are used in conjunction with a patterning process as an etch mask to etch the underlying second mask layer 34 such that the openings 58 and 44 extend into the second mask layer 34. The patterning process may include one or more etching processes, wherein the first mask layer 32 is used as an etch stop layer. In some embodiments, the patterning process may include dry etching processes, wherein the etching process gases O2, CO2, C x H y F z, Ar, N2, H2, HBr, Cl2, He, the like, or a combination thereof, or any other suitable etchant capable of removing the exposed portions of the second mask layer 34 without damaging the first mask layer 32.

[0022] With reference to Fig. 8, the first spacers 48 may be selectively removed, for example, using one or more suitable etching processes. In some embodiments, the first spacers 48 may be removed, for example, using dry etching processes, wherein etching process gases include O2, Cl2, CO2, C x H y F z , Ar, N2, H2, the like or a combination thereof.

[0023] With reference to Fig. 9, a patterning process is performed on the first mask layer 32 to transfer the openings 58 and 44 to the first mask layer 32. The patterning process forms openings in the first mask layer 32 corresponding to the respective openings 58 and 44. The openings in the first mask layer 32 expose portions of the target layer 28 (e.g., comprising amorphous silicon). In some embodiments, the patterning process includes a suitable etching process, wherein the second mask layer 34 is used as an etch mask. A suitable etching process may include an isotropic wet etching process, an anisotropic dry etching process, or combinations thereof. In some embodiments, the first mask layer 32 is removed, for example, using a dry etching process, wherein etching process gases include Cl2, O2, C x H y F z, N2, H2, the like, or a combination thereof. Subsequently, the second mask layer 34 is removed, for example, using a suitable etching process. In some embodiments, the first mask layer 34 is removed, for example, using a dry etching process, wherein etching process gases O2, CO2, C x H y F z , Ar, N2, H2, the like or a combination thereof.

[0024] With reference to Fig. 10, a patterning process is performed on the target layer 28 to transfer the pattern of the first mask layer 32 to the target layer 28. The patterning process extends the openings 44 and 58 into the target layer 28 to expose portions of the etch stop layer 26. In some embodiments, the patterning process includes one or more suitable etch processes, wherein the first mask layer 32 (which, as discussed above, may comprise a nitride, such as silicon nitride) is used as an etch mask. The one or more suitable etch processes may include isotropic wet etch processes, anisotropic dry etch processes, or combinations thereof.

[0025] As mentioned above with reference to Fig. 4, the first spacers 48 can be removed, for example, using dry etching processes, wherein etching process gases O2, Cl2, CO2, C x H y F z, Ar, N2, H2, the like, or a combination thereof. In addition, as described above with reference to Fig. 9, the second mask layer 34 can be removed, for example, using other dry etching processes, wherein etching process gases O2, CO2, C x H y F z , Ar, N2, H2, the like, or a combination thereof. In addition, as described above with reference to Fig. 10, the target layer 28 may be patterned using isotropic wet etching processes, anisotropic dry etching processes, or combinations thereof.

[0026] These etching processes of the preceding steps may create a residue layer 60 over at least a portion of exposed portions of the etch stop layer 26 (e.g., the oxide layer 26c of the etch stop layer 26), the target layer 28, and the first mask layer 32. The residue layer 60 may comprise carbon, fluorine, or a compound thereof (e.g., a fluorocarbon compound such as CF x ). The residue layer 60 represents a defect that may cause a structural failure if not removed from the wafer 100. As a result, a cleaning process may be required to reduce or substantially eliminate the presence of the residue layer 60 from the wafer 100.

[0027] Fig. 11 shows a first cleaning process 62, which is carried out at the Fig. 10 according to one embodiment. The first cleaning process 62 may be a wet cleaning process using a first solution. In some embodiments, the first solution may be a mixture comprising water, hydrogen peroxide, and ammonia water. In some embodiments, a concentration of the ammonia water may be between approximately 10 parts per million (ppm) and 500 parts per million (ppm). As an example, the first cleaning process 62 may be a Standard Cleaning Process 1 (SC1 process). The first cleaning process 62 may remove a substantial portion of the residue layer 60 to expose at least a portion of the first mask layer 32. However, some portions of the residue layer 60 may still remain on sidewalls of the target layer 28 and the first mask layer 32, as shown in Fig. 12. In some examples, the first cleaning process 62 may be performed at room temperature (e.g., approximately 25 degrees Celsius).

[0028] Fig. 13 shows a second cleaning process 64 that may be performed to remove the first mask layer 32, according to one embodiment. The second cleaning process 64 may be a wet cleaning process using a second solution. In some embodiments, the second solution may be an acid solution. As an example, the second solution may be phosphoric acid, which may have a concentration of between about 80 wt. % and about 90 wt. %. The second cleaning process 64 may be performed at a temperature in a range between about 100 degrees Celsius and about 200 degrees Celsius. An effect of performing the second cleaning process 64 using an acid solution or at the specified temperature range may be that a material of the residue layer 60 aggregates and forms a residue condensate 66 that remains on sidewalls of the target layer 28.Subsequently, removal of the residual condensate 66 is carried out as described below with reference to . Fig. 14 to 16 described.

[0029] Fig. 14 shows a zoomed-out view of a third cleaning process 68 according to an embodiment, which is performed on the wafer 100. As in Fig. 14, the wafer 100 may be placed over a carrier 70 disposed within a chamber 72. In some embodiments, as in the Fig. 14, the carrier 70 may include at least one conduit 74 that may be used to supply deionized water 76 to a back surface of the wafer 100, as shown in Fig. 14. In some embodiments, the back surface of wafer 100 may be a surface of wafer 100 facing away from substrate 120. In some embodiments, deionized water 76 may include carbon dioxide. In such embodiments, deionized water 76 having carbon dioxide therein may be used to discharge static electricity that may have built up on wafer 100 as a result of previous processing steps.

[0030] With reference to Fig. 15, the third cleaning process 68 continues by further applying the deionized water 76 to a front surface of the wafer 100. In some embodiments, the front surface of the wafer 100 may be a surface of the wafer 100 over which the substrate 120 and subsequent layers are formed. The deionized water 76 may be dispensed over the front surface of the wafer 100 using a nozzle 78 disposed over the wafer 100. The combination of the Fig. 14 and Fig. The processes shown in Figure 15 may have the effect of discharging static electricity that may have built up on the wafer 100 as a result of previous processing steps, thereby preventing or substantially reducing the number of defects formed by the discharge of static electricity from the wafer 100. In some examples, the third cleaning process 68 may be performed at room temperature (e.g., approximately 25 degrees Celsius).

[0031] Fig. 16 shows a fourth cleaning process 80 according to an embodiment, which is performed on the wafer 100. In the fourth cleaning process 80, the first solution 82 used in the first cleaning process 62 is reapplied to the wafer 100. In particular, the conduit 74 of the carrier 70 directs the first solution 82 to the back surface of the wafer 100. In addition, the nozzle 78 dispenses the first solution 82 over the front surface of the wafer 100. In some embodiments, the back surface and the front surface of the wafer 100 are exposed to the first solution 82 simultaneously. In the Fig. 16, a spray mechanism 84 other than nozzle 78 may be used in conjunction with nozzle 78 to dispense first solution 82. In some embodiments, first solution 82 may be a mixture comprising water, hydrogen peroxide, and ammonia water, wherein the ammonia water has a concentration between approximately 10 ppm (parts per million) and approximately 500 ppm (parts per million). Additionally or alternatively, the ammonia water may have a temperature between approximately 20 degrees Celsius and approximately 70 degrees Celsius when performing fourth cleaning process 80.

[0032] An effect caused by the Fig. 14 to 16, is that the residue condensate 66 is removed from side walls of the Fig. 13 is substantially removed. Therefore, the presence of fluorocarbon (e.g., CFx ) on the wafer 100 are eliminated or significantly reduced, thereby improving the defect count in the wafer 100. In addition, the Fig. 14 to Fig. 16 can be used with currently available wafer cleaning systems, thus avoiding the need to upgrade or reconfigure existing systems.

[0033] Fig. 17 shows the structure that was prepared according to Fig. 14 to 16. With reference to Fig. 18, a second spacer layer 200 is conformally formed over the target layer 28 and exposed portions of the etch stop layer 26. The second spacer layer 200 may comprise similar materials as the first spacer layer 46 (e.g., in Fig. 3) and can be formed using similar steps as described above with reference to Fig. 3 described.

[0034] With reference to Fig. 19, the second spacer layer 200 is patterned to form second spacers 202 on sidewalls of the target layer 28. In some embodiments, the second spacer layer 200 is patterned using an anisotropic dry etching process to remove horizontal portions of the second spacer layer 200 from a top surface of the target layer 28 and the exposed surfaces of the etch stop layer 26. Portions of the second spacer layer 200 remaining on the sidewalls of the target layer 28 form second spacers 202. The processes used to pattern the second spacer layer 200 may be similar to those described above with reference to Fig. 4 described processes used to pattern the first spacer layer 46.

[0035] With reference to Fig. 20, the target layer 28 will be removed, for example, using a process described above in Fig. 5 and Fig. 6, which describe the removal of the intermediate mandrels 36A and 36B. The process for removing the target layer 28 leaves the second spacers 202 above the etch stop layer 26, as shown in Fig. 20. From this step, the structure of the second spacers 202 can be transferred to the substrate 120 using the etch stop layer 26 to form semiconductor fins. Fig. 20 shows an area 204 and Fig. Figures 21 to 27 show an enlarged view of area 204.

[0036] With reference to Fig. 21, the oxide layer 26c of the etch stop layer 26 is formed using the second spacers 202 as a mask, e.g., using similar processes as described above with reference to Fig. 7, where the second mask layer 34 is patterned. The result of etching the oxide layer 26c is that the pad nitride layer 26b of the etch stop layer 26 is exposed, as shown in Fig. 21. With reference to Fig. 22, the second spacers 202 may be selectively removed, for example using one or more suitable etching processes described with reference to Fig. 7 and Fig. 8, in which the first spacers 48 are selectively removed, have been described.

[0037] With reference to Fig. 23, the pad nitride layer 26b of the etch stop layer 26 is then etched using the oxide layer 26c as a mask, e.g., using processes described above with reference to Fig. 9, in which the first mask layer 32 is patterned. In some embodiments, such as the one shown in Fig. 23, the oxide layer 26c is removed, for example, using a dry etching process, wherein etching process gases O2, CO2, C x H y F z , Ar, N2, H2, the like or a combination thereof.

[0038] With reference to Fig. 24, the structure of the pad nitride layer 26b is then formed using similar processes as described above with reference to Fig. 7, in which the second mask layer 34 is patterned, are transferred to the pad oxide layer 26a and the substrate 120 to form semiconductor fins 206.

[0039] Fig. 25 illustrates the filling of dielectric materials. According to some embodiments, a liner oxide 208 is formed on the sidewalls of the semiconductor fins 206. The liner oxide 208 may be a conformal layer having horizontal portions and vertical portions whose thicknesses are close to each other. The liner oxide 208 may be a thermal oxide having a thickness between approximately 1 nm and approximately 10 nm, according to some embodiments. According to one embodiment of the present disclosure, the liner oxide 208 is formed, for example, using in-situ steam generation (ISSG), wherein the water vapor or a composite gas of hydrogen (H2) and oxygen (O2) is used to oxidize the semiconductor fins 206 and the substrate 120. According to still other embodiments, the liner oxide 208 is deposited using a deposition technique, such asa subatmospheric chemical vapor deposition (SACVD).

[0040] Fig. 25 also illustrates the deposition / formation of the dielectric material 210. The dielectric material 210 covers the pad nitride layer 26b, the pad oxide layer 26a, the semiconductor fins 206, and the liner oxide 208. The method for forming the dielectric material 210 may be selected from flowable chemical vapor deposition (FCVD), CVD, ALD, and the like. A treatment may be performed to harden the dielectric material 210. The resulting dielectric material 210 may, for example, comprise silicon oxide.

[0041] A planarization, such as chemical mechanical polishing (CMP), is then performed as in Fig. 26. In this way, STI regions 212 are formed, comprising the liner oxide 208 and remaining portions of the dielectric material 210. The pad nitride layer 26b may be used as the CMP stop layer, and therefore, the upper surface of the pad nitride layer 26b is substantially flush with the upper surface of the STI regions 212.

[0042] In subsequent process steps, the pad nitride layer 26b and the pad oxide layer 26a are removed. Next, the STI regions 212 are recessed, as shown in Fig. 27. The upper portions of the semiconductor fins 206 protrude higher than the upper surfaces of the remaining STI regions 212 to form protruding semiconductor fins 214. The resulting structure is shown in Fig.27. According to some embodiments of the present disclosure, the recessing of the STI regions 212 is performed using a dry etching process in which the process gases comprising NH3 and HF3 are used. According to alternative embodiments of the present disclosure, the recessing of the STI regions 212 is performed using a wet etching process in which the etchant solution is a dilute HF solution. After the STI regions 212 have been recessed to form the semiconductor fins 214, the semiconductor fins 214 are subjected to several process steps, where the process steps may include well implantations, forming gate stacks, forming source / drain, and forming replacement gates, thereby forming FinFETs.It should be noted that the described embodiments in which FinFETs are formed are merely examples; other embodiments of the present disclosure contemplate forming other semiconductor features in substrate 120.

Claims

[1] Method comprising: Forming a patterned etching mask (32) over a target layer (28) over a front side of a wafer (100), Structuring the target layer (28) using the structured etching mask (32) as a mask to form a structured target layer (28) and to create a residue layer (60) on sidewalls of the structured target layer (28) and the structured etching mask (32), Performing a first cleaning process (62) on the structured etching mask (32) and the structured target layer (28), wherein the first cleaning process (62) comprises a first solution, wherein the first cleaning process (62) removes a substantial portion of the residue layer (60) on the structured etching mask (32) and the structured target layer (28), wherein portions of the residue layer (60) remain on sidewalls of the structured etching mask (32) and the structured target layer (28), Performing a second cleaning process (64) to remove the patterned etch mask (32) and form an exposed patterned target layer (28), wherein the second cleaning process (64) comprises a second solution, wherein the second cleaning process (64) causes the remaining residue layer (60) to aggregate on sidewalls of the patterned target layer (28) and form a residue condensate (66) on sidewalls of the patterned target layer (28), Performing a third cleaning process (68) on the exposed structured target layer (28); and Performing a fourth cleaning process (80) on the exposed structured target layer (28), wherein the fourth cleaning process (80) comprises the first solution, wherein the third cleaning process (68) and the fourth cleaning process (80) remove the residual condensate (66) from the sidewalls of the structured target layer (28). [2] The method according to claim 1, wherein the first solution comprises at least one of water, hydrogen peroxide and ammonia water. [3] A method according to claim 1 or 2, wherein the second solution comprises phosphoric acid. [4] The process of claim 3, wherein the phosphoric acid has a concentration of between 80 wt% and 90 wt%. [5] Method according to one of the preceding claims, wherein the second cleaning process (64) is carried out at a temperature in a range between 100 degrees Celsius and 200 degrees Celsius. [6] A method according to any one of the preceding claims, wherein the residue layer (60) comprises a fluorocarbon compound. [7] The method of any preceding claim, wherein performing the third cleaning process (68) on the exposed structured target layer (28) comprises exposing the exposed structured target layer (28) to deionized water. [8] The method of claim 7, wherein the deionized water has carbon dioxide therein. [9] The method of any preceding claim, wherein performing the fourth cleaning process (80) on the exposed patterned target layer (28) comprises dispensing the first solution at a temperature between about 20 degrees Celsius and about 70 degrees Celsius. [10] The method of any preceding claim, wherein the third cleaning process (68) and the fourth cleaning process (80) are applied to a front side of the wafer (100) and a back side of the wafer (100).

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