Source and drain epitaxy redesign

Abstract

A method for laterally etching an epitaxial layer, the method comprising: Forming (510) a plurality of fins (110, 115) on a substrate (160), each of the plurality of fins having a first width (125); Forming source / drain regions (120) on the plurality of fins, wherein the source / drain regions (120) are formed on two fins each, and wherein each source / drain region (120) has a second width (150) in a common direction with the first width and a height (155); selectively etching the source / drain regions (120) to reduce the second width of the source / drain regions (150); and Growing (530) an epitaxial depletion layer over the source / drain regions (120), wherein the selective etching comprises an in-situ etch with hydrochloric acid,HCl, germane,GeH4, and chlorine,Cl2, and wherein a flow rate for HCl is 40 to 1000 sccm, a flow rate for GeH4 is 0 to 1000 sccm, and a flow rate for Cl2 is 0 to 100 sccm.

Description

BACKGROUND

[0001] Epitaxial silicon-germanium layers formed on the source / drain terminals of a fin field-effect transistor (FINFET) can electrically short in high-density regions of a chip where the fin pitch is narrow. As a result, these electrical shorts can lead to FINFET performance degradation and wafer yield loss.

[0002] US 2015 / 021,4051A1 relates to a semiconductor device comprising a substrate having an active rib extending in a first direction and a plurality of gate structures on the active rib, each of the gate structures extending in a second direction substantially perpendicular to the first direction.

[0003] US 2016 / 0126093A1 relates to a method for processing a substrate in a processing chamber comprising forming an epitaxial film over a semiconductor fin formed on the substrate, the epitaxial film having a top surface with a first facet and a second facet.

[0004] US 2017 / 0077300A1 relates to a semiconductor device comprising a substrate having a plurality of semiconductor fins with at least one first insulation structure arranged between the semiconductor fins and at least two second insulation structures, wherein the semiconductor fins are arranged between the second insulation structures and the second insulation structures extend further into the substrate than the first insulation structure.

[0005] US 2014 / 0 252489A1 relates to a method for forming a device comprising forming a fin in a substrate and etching away the fin to create a source / drain recess, as well as forming a plurality of source / drain layers in the source / drain recess.

[0006] US 2013 / 0001705 A1 relates to an integrated circuit structure having isolation regions with top surfaces; and a fin field effect transistor (FinFET) comprising a semiconductor fin over and adjacent to the isolation regions and a gate dielectric on a top surface and on the sidewalls of the semiconductor fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present disclosure can best be understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. The Fig. 1 shows a cross-sectional view of an epitaxially grown silicon-germanium source or drain region of a two-fin structure according to some embodiments. The Fig. 2 shows a cross-sectional view of a two-fin structure after an exemplary etching process according to some embodiments. The Fig. 3 shows a cross-sectional view of a pair of single fin structures with epitaxially grown source / drain terminals according to some embodiments. The Fig. 4 shows a cross-sectional view of single fin structures after an exemplary lateral etching process according to some embodiments. The Fig. 5 shows a flow diagram of an exemplary silicon germanium source / drain manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for implementing various characteristic features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples.For example, the formation of a first characteristic feature over a second characteristic feature in the description that follows may include embodiments in which the first and second characteristic features are formed in direct contact and may also include embodiments in which additional characteristic features may be formed between the first and second characteristic features such that the first and second characteristic features are not in direct contact. Furthermore, throughout the present disclosure, reference numbers and / or letters may be repeated in various examples. This repetition, as such, does not dictate any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "below," "under," "lower," "over," "upper," and the like may be used herein for convenience of description to describe an element or the relationship of a characteristic feature to another element(s) or characteristic feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operating in addition to the orientation illustrated in the figures. The device may be oriented in other ways (rotated 90 degrees or in any other orientations), and spatially relative descriptions used herein may be equally interpreted accordingly.

[0010] The term "nominal," as used herein, refers to a desired or target value of a characteristic or parameter for a component or process operation, established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​is typically attributable to slight variations in manufacturing processes or tolerances. Unless otherwise defined, the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0011] With advances in semiconductor manufacturing, smaller critical dimensions (KD) and higher-density regions with smaller pitch geometries are required. However, in high-density regions of a chip, including, for example, fin-field-effect transistor (FINFET) structures, smaller pitch geometries can be challenging. For example, the fin pitch of FINFET structures can pose challenges for source / drain (S / D) formation for closely spaced individual fin structures. For closely spaced fins (e.g., with a pitch of less than 60 nm between FINFET structures), an epitaxial silicon germanium (SiGe) S / D of one fin can electrically short to the SiGe S / D of an adjacent fin. This undesirable condition leads to wafer yield loss.

[0012] The present disclosure is directed to a lateral in-situ etching process that "prunes" the sides of epitaxially grown SiGe S / D regions to minimize or prevent electrical shorts without limiting FINFET performance. According to some embodiments, the lateral etching process can be tailored to reduce the width of the SiGe S / D region without significantly affecting the S / D height. Furthermore, in some embodiments, the height and dopant concentrations of the SiGe S / D can be adjusted accordingly to compensate for the width reduction, such that there is minimal or no performance penalty.

[0013] Depending on the chip design, different fin designs can be used, with each fin design having a different fin pitch or spacing. For example, the chip may include regions with single-fin structures that include single S / D structures or regions with dual-fin structures that may include fused S / D regions. Furthermore, each chip region may have a different fin pitch and therefore a different susceptibility to S / D shorts. Because the growth of SiGe S / D regions during the chip fabrication process is a global process and not local to each fin (e.g., using an independent processing step for each fin), changes in the SiGe S / D growth process can affect all regions of the chip. Therefore, monitoring dense regions of the chip that have a tight fin pitch is necessary.Areas with narrow fin pitch can be considered "weak spots" or vulnerable areas of the chip. The following description discusses two example fin structures: (i) a dual-fin structure and (ii) a single-fin structure.

[0014] Fig. 1 shows a cross-sectional view of an exemplary two-fin structure 100. Fins 110 and 115 share a p-type SiGe S / D region 120. The p-type S / D region 120 may have a high concentration of holes (majority carriers) due to a hole-donor dopant such as boron (B). In some embodiments, two S / D regions are fused in the SiGe S / D region 120, with each S / D region being grown individually on fins 110 and 115. In some embodiments, the SiGe S / D region 120 may have a hexagon-like shape of Fig. 1. In some embodiments, the fin pitch 125 may be between 10 and 40 nm. The S / D region 120 has a top surface 130 and a pair of side surfaces 135 and 140. An angle 145 is formed between the side surfaces 140 and 135, which may range from about 45° to 65°, depending on some embodiments. The SiGe S / D region 120 has a width 150 and a height 155, both of which may be optimized for device performance. In some embodiments, the width 150 may be 50 to 90 nm and the height 155 may be 40 to 80 nm. As one of ordinary skill in the art will understand, these dimensions are not limiting.

[0015] Furthermore, the two-fin structure 100 includes a substrate 160. In some embodiments, the substrate 160 may be a bare semiconductor wafer or a top layer of a semiconductor on an insulator (SOI) wafer. By way of example and not limitation, a semiconductor substrate may be made of silicon or another elemental semiconductor. For example, the elemental semiconductor may be (i) germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP), or (iv) any combination thereof.Furthermore, fins 110 and 115 may be made of the same material as semiconductor substrate 160 or a different material. For example, and not by way of limitation, fins 110 and 115 may be made of silicon.

[0016] Fins 110 and 115 of structure 100 are electrically isolated from each other by a flat-trend insulation (STI) layer 165. As one of ordinary skill in the art would understand, STI layer 165 may be composed of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable dielectric material with suitable gap-filling properties. STI layer 165 may be formed after fin formation on substrate 160, but before formation of S / D region 120. For example, the space between the fins may be filled with dielectric material, followed by partial chemical mechanical planarization (CMP) and etching back the dielectric material to expose fins 110 and 115. As one of ordinary skill in the art would understand, other manufacturing techniques for forming the STI layer 165 are possible.Furthermore, the STI layer 165 may be a multi-layer structure comprising more than one layer of the above materials.

[0017] In some embodiments, the p-type SiGe S / D region 120 may be an epitaxial stack comprising two or more epitaxial layers grown sequentially and having different germanium (Ge) atomic percentages and B dopant concentrations. For example, and not by way of limitation, the first layer may have a Ge atomic percentage ranging from 0 to 40% and a B dopant concentration ranging from 5×10 19 up to 1×10 21 atoms / cm 3 The second epitaxial layer may have a Ge atomic percentage in the range of 20 to 80% and a B dopant concentration in the range of 3×10 20 up to 5×10 21 atoms / cm 3Finally, the third epitaxial layer is a capping layer that has similar Ge atomic percentages and B dopant concentrations as the first layer (e.g., 0 to 40% Ge and 5×10 19 ) to 1×10 21 atoms / cm 3 B dopant). The thickness of these layers may vary depending on the device performance requirements. For example, the first epitaxial layer may have a thickness in the range between 10 and 20 nm, the second epitaxial layer may have a thickness in the range between 30 and 60 nm, and the third epitaxial layer (cap layer) may have a thickness in the range between 0 and 10 nm. In some embodiments, the SiGe S / D region 120 may have the hexagon-like shape of Fig. 1, which is attributable to the two fused "diamond-shaped" S / D regions, each of which is grown on fins 110 and 115. As one of ordinary skill in the art would understand, the SiGe S / D width 150 can be monitored by an inline measurement determination.

[0018] In some embodiments, the SiGe epitaxial growth process may be performed at high wafer temperatures in the range of 450 to 740°C. During epitaxial growth, the process pressure may range from 133.322 to 13332.2 Pa (1 to 100 Torr), and the reactant gases may include silane (SiH4), disilane (Si2H6), germanium (GeH4), diborane (B2H6), hydrochloric acid (HCl), and hydrogen (H2), or nitrogen (N2), or argon (Ar). As one of ordinary skill in the art would understand, the above-mentioned gas ranges and types are exemplary and are not intended to be limiting. The shape and size of the SiGe S / D region 120 may depend on the growth conditions of each individual epitaxial layer (e.g., gas flows, wafer temperature, and process pressure).

[0019] Fig. 2 shows a cross-sectional view of an exemplary two-fin structure 200. In some embodiments, the structure 200 shows a resulting two-fin structure after an exemplary etching process has been performed on the structure 100. In some embodiments, the exemplary etching process is a selective lateral etch for the SiGe S / D region 120. For example, the etching process may selectively remove SiGe material from the side surfaces 135 and 140 along the x-direction to restore the original S / D width 150 of Fig. 1. As in Fig. 2, the x-direction coincides with the direction of the plane (110) which is parallel to the surface of the wafer and in a common direction with the width of the fin 205, and the y-direction coincides with the direction of the plane (100) which is perpendicular to the surface of the wafer.

[0020] In some embodiments, the height 155 and the B dopant concentrations can be adjusted to compensate for the lateral SiGe material removal during the etching process. These adjustments can ensure that the final electrical properties of the SiGe S / D region 120 meet the design requirements. For example, the height 155 can increase when a lateral etch is performed in the SiGe S / D region 120. Adjusting the height 155 is based on the amount of material removed during the lateral etching process. In some embodiments, the adjustment of the height 155 can be in the range of 5 to 20 nm. In some embodiments, the B dopant concentration for the second epitaxial layer can be adjusted for similar reasons as the adjustment of the height 155. For example, the B dopant concentration range can be from 3×10 20 -5×10 21 atoms / cm 3 to 1×10 20-3×10 21 atoms / cm 3 The height and dopant adjustments can be made during the growth of the second epitaxial layer. As one of ordinary skill in the art would understand, these adjustments are made before the selective etching process, and furthermore, the adjustment ranges mentioned above are only examples and are not intended to be limiting.

[0021] The top surface 130 may be etched during the lateral etching process, and the height 155 may be reduced. The height loss at the S / D region may range from 0 to 5 nm, depending on some embodiments. This may translate into a height reduction of 12.50% for an S / D region of 40 nm height or a height reduction of 6.25% for an S / D region of 80 nm height. Due to the directional selectivity of the lateral etching process, a final angle 210 may be wider than the original angle 145 of the structure 100, and consequently, the S / D width 205 is reduced compared to the original S / D width 150 of the structure 100. In some embodiments, the angle 210 may be in the range of 55° to 180° and the width reduction may be up to 20 nm (e.g., 10 nm from each side).

[0022] In some embodiments, the lateral etching process is an in-situ process. For example, the in-situ process can be performed in the same cluster tool or epitaxial growth reactor without vacuum breakage. As one of ordinary skill in the art would understand, vacuum breakage occurs when a wafer exits the cluster tool or reactor and is exposed to a cleanroom environment, such as during wafer transfer to a wafer carrier.

[0023] In-situ processing can be advantageous for several reasons. For example, an in-situ process does not impact the throughput through the cluster tool as much as an ex-situ process, which requires a vacuum break, such as a wafer transfer to a carrier and subsequent transfer to another cluster tool or reactor. The in-situ process also ensures better process and particle control than the ex-situ process. For example, and not by way of limitation, the lateral etching process can be performed after the formation of the second epitaxial SiGe layer, but before the formation of the third epitaxial layer (cap layer). Furthermore, the SiGe growth and subsequent etching can be followed by another cycle of SiGe growth and etching, if necessary. For example, if the fin pitch is less than 50 nm, a third SiGe growth (e.g.similar to the second SiGe growth in terms of Ge atomic percentage and B concentration), and a second lateral etch may be required. After the formation of the third SiGe layer, the capping layer is formed on top (e.g., a fourth epitaxial SiGe layer).

[0024] In some embodiments, the etch chemistry may include HCl, GeH4, and chlorine (Cl2). As one of ordinary skill in the art would understand, these gases may be introduced as a gas mixture or individually during the selective etching process. For example, and not by way of limitation, the flow rates of each of the above-mentioned gases may range from 40 to 1000 sccm for HCl, 0 to 1000 sccm for GeH4, and 0 to 100 sccm for Cl2. In some embodiments, the wafer temperature during the lateral etching process may range between 450 and 800°C, and the etch time may range from 5 to 1200 seconds. As one of ordinary skill in the art would understand, these ranges are only examples, and other ranges are possible.

[0025] In some embodiments, the lateral etch selectivity can be adjusted by the etch gas flows and the wafer temperature. The etch rate and directional selectivity can also depend on the B dopant and the Ge atomic percentage, according to some embodiments. Any or all combinations of wafer temperature, etch gas flows, and dopant concentrations can be used to tailor the etch process and optimize directional selectivity. In general, higher process temperatures, higher Ge atomic percentages, and higher gas flow rates favor lateral etch selectivity along the (110) plane (fin width direction).

[0026] Fig. 3 shows a cross-sectional view of another exemplary two-fin structure 300. In some embodiments, fins 110 and 115 may have a fin pitch 310 of less than 60 nm. In structure 300, fin 110 includes a "diamond-shaped" SiGe S / D region 320, and fin 120 includes a "diamond-shaped" SiGe S / D region 330, as shown in Fig. 3. Both SiGe S / D regions 320 and 330 are grown to have a nominally equal width 340 and a nominally equal height 350. In some embodiments, the width 340 is about 40 nm and the height 350 is about 60 nm. However, these dimensions and shapes are only examples and are not intended to be limiting, as they are determined by the FINFET performance and can be adjusted accordingly depending on the FINFET electrical characteristics. Similar to the structures 100 and 200 in Fig. 1 and 2, respectively, the structure 300 is located on the substrate 160, where the fins 110 and 115 are insulated with the STI layer 165. The side surfaces of the SiGe S / D regions 320 and 330 form an angle 360. In some embodiments, the angle 360 ​​may be in the range of 45° to 65°.

[0027] Due to the fin pitch geometry of structure 300 (e.g., less than 60 nm), the SiGe S / D regions 320 and 330 are at risk of being in physical (and electrical) contact at the end of the epitaxial SiGe growth process. This undesirable situation can lead to an electrical short circuit between neighboring FINFETs. To overcome this undesirable situation, a lateral in-situ etch can be performed to reduce the width 340 of each SiGe S / D region 320 and 330.

[0028] Due to the variability in fin width and height caused by process and condition variations, not all wafers require the same amount of etching. Therefore, to account for these variations, different etching conditions are applied to different wafers. The selection of the etching process for each wafer is accomplished through a process known as the "feedback process." As anyone of ordinary skill in the art would understand, the feedback process uses information from a critical parameter obtained by inline measurement determination (typically performed after the main process operation) to provide feedback to the process tool of the main process operation. The process tool can make process adjustments based on the feedback.For example, if the measured parameter is near or outside the manufacturing specification limits, a process setting is recalled, and wafers entering the main process workflow receive the process setting. The process settings can be made automatically without operator intervention through an automated feedback loop.

[0029] Process settings are important for processes that shift slightly over time or suffer from intrinsic variation, and therefore process adjustments may be necessary to protect product quality. For example, after the SiGe S / D process, each wafer receives an S / D width measurement before moving to the next processing operation. The measured SiGe S / D width is then fed back to the SiGe process tool, and the next incoming wafer receives the etch process parameters based on the previously measured wafer.

[0030] Fig. 4 shows a cross-sectional view of an exemplary two-fin structure 400. In some embodiments, structure 400 shows a resulting two-fin structure after a selective lateral etch has been performed on structure 300. In some embodiments, a final SiGe S / D width 310 may be narrower compared to the original SiGe S / D width 340. This is achieved by laterally removing the x-direction epitaxial SiGe material from both SiGe S / D regions 320 and 330. According to some embodiments, the x-direction coincides with the (110) in-plane direction or the fin width direction, and the y-direction coincides with the (100) in-plane direction or the fin height direction. Due to the lateral etching process, a final angle 420 is wider than the original angle 360. In some embodiments, the S / D regions 320 and 330 have a “longitudinal” diamond shape, as in Fig. 4. In some embodiments, the angle 420 may range from 55° to about 180°. In some embodiments, the amount of etching may vary from 0 to 20 nm. Ideally, due to the directional selectivity of the etching process, the height 350 should not be affected by the selective etching. However, a height loss of 0 to 5 nm is possible, which can be converted into a height reduction of 8.33% for an S / D of 60 nm.

[0031] As mentioned above, to ensure that the electrical properties of the FINFET are not compromised, the height 350 and the B-dopant concentration must be adjusted accordingly. The height 350 adjustment is based on the amount of material removed during the lateral etch process and, therefore, on the final S / D width. In some embodiments, the height adjustment may be in the range of 5 to 20 nm. In some embodiments, the B-dopant concentration for the second epitaxial layer may be adjusted for similar reasons as the height 350 adjustment. For example, the B-dopant concentration range may be from 3×10 20 -5×10 21 atoms / cm 3 to 1×10 20 -3×10 21 atoms / cm 3The height and dopant adjustments can be made during epitaxial layer growth. As someone with ordinary technical knowledge would understand, these settings are only examples and are not intended to be limiting.

[0032] As one of ordinary skill in the art would understand, structures 300 and 100 may be subjected to the same lateral etch, and structures 400 and 200 may be the resulting respective structures after the lateral etch. Furthermore, according to some embodiments, the process changes are intended to be applied to all SiGe S / D regions of the chip.

[0033] Fig. 5 shows a flow diagram of an exemplary SiGe S / D manufacturing process 500 employing a lateral in-situ etch. The lateral etch may selectively remove SiGe material from side surfaces of the S / D regions and reduce the S / D width according to some embodiments. As one of ordinary skill in the art would understand, other manufacturing operations may be performed between the various operations of the manufacturing process 500 and have been omitted for clarity only. This SiGe S / D manufacturing process is not limited to the exemplary manufacturing process 500.

[0034] The exemplary manufacturing method 500 begins with operation 510 and the formation of a plurality of fins on the substrate. Each of the fins has a top surface and a pair of opposing side surfaces. In some embodiments, the substrate may be a bare semiconductor wafer or the top layer of a semiconductor on an insulator (SOI) wafer. As one of ordinary skill in the art would understand, a semiconductor substrate may be made of silicon or another elemental semiconductor. The elemental semiconductor may be, for example, (i) germanium, (ii) a compound semiconductor, including silicon carbide, GaAs, GaP, InP, InAs, and / or InSb, (iii) an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or (iv) any combination thereof.

[0035] Furthermore, the fins may be made of the same material as the semiconductor substrate or a different material. For example, and not by way of limitation, the fins may be made of silicon. Furthermore, the fins may have different pitches in different areas of the wafer (e.g., one fin pitch used for logic FINFETs and a different fin pitch used for SRAM FINFETs). The fins may also have different configurations or arrangements on a chip; for example, the fins may be part of a large array of single-fin structures or part of islands of dual-fin structures. As someone of ordinary skill in the art would understand, these fin configurations and arrangements are examples and are not intended to be limiting.

[0036] The fins are electrically insulated from each other with an STI layer. As one of ordinary skill in the art would understand, the STI layer may be composed of silicon oxide, silicon nitride, silicon oxynitride, FSG, a low-k dielectric material, or any other suitable dielectric material with suitable gap-filling properties, or any combination thereof. The STI layer may be formed after the fins. For example, the space between the fins may be filled with dielectric material, followed by a partial CMP and an etch-back process, which may selectively cut the STI and expose a portion of the fin sidewalls. The partial CMP process may remove the STI until the top surface of the fins is exposed. The etch-back process may selectively cut the STI below the level of the top surface of the fins.As one of ordinary skill in the art would understand, other manufacturing techniques for forming the STI layer are possible. For example, and not by way of limitation, the STI layer may be a stack of more than one dielectric layer.

[0037] In an exemplary manufacturing method 500, operation 515 proceeds to form S / D regions on the fins, growing a first epitaxial SiGe layer over the top surfaces and a portion of the side surfaces of the plurality of fins. The epitaxial growth process, similar to the S / D region layers (the first, second, and capping layers), is performed at high wafer temperatures (e.g., 450°C to 740°C). During epitaxial growth, the process pressure may range between 133.322 to 13332.2 Pa (1 and 100 Torr). The reactant gases may include silane (SiH4), disilane (Si2H6), germane (GeH4), diborane (B2H6), and hydrochloric acid (HCl). The reactant gases may also include hydrogen (H2) or nitrogen (N2) or argon (Ar).

[0038] In some embodiments, the first epitaxial SiGe layer may have a Ge atomic percentage ranging from 0 to 40% and a B dopant concentration ranging from 5×10 19 up to 1×10 21 atoms / cm 3 In some embodiments, the first epitaxial layer may have a thickness in the range between 10 and 20 nm. As one of ordinary skill in the art would understand, the above-mentioned ranges are not intended to be limiting.

[0039] In an exemplary manufacturing method 500, operation 520 continues, wherein a second epitaxial SiGe layer is grown over the first epitaxial SiGe layer. In some embodiments, the second epitaxial SiGe layer may have a Ge atomic percentage between 20 and 80% and a dopant concentration in the range of 1×10 20 up to 3×10 21 atoms / cm 3In some embodiments, the thickness of the second epitaxial layer may be in the range of 30 to 60 nm. As one of ordinary skill in the art would understand, the above-mentioned ranges are not intended to be limiting.

[0040] Depending on the fin spacing and the design plan, the S / D regions of adjacent fins may be allowed to merge. For example, in structure 100 of Fig. 1 allows the S / D regions of fins 110 and 115 to merge and form the common SiGe S / D region 120. Conversely, in a single fin structure 300 of the Fig. 3, the SiGe S / D regions 320 and 330 are not fused. Both single fin and dual fin structures have a fin pitch below 60 nm. However, a dual fin structure (e.g., structure 100) can have a smaller pitch than a single fin structure (e.g., structure 300). In other words, the pitch is 125 nm in Fig. 1 less than the distance 310 in Fig. 3. In some embodiments, the pitch 125 may be less than 40 nm; for example, the pitch 125 may be between 10 and 40 nm.

[0041] In operation 525, an exemplary etching process for etching a portion of the pair of side surfaces of the second epitaxial SiGe layer is introduced. In some embodiments, the etching process may be a lateral etching process, which may be an in-situ process. For example, the etching process may be performed in the same cluster tool or in the epitaxial growth reactor without a vacuum break. This may be advantageous for several reasons. For example, the in-situ process does not impact tool throughput as much as an ex-situ process, which requires a vacuum break or additional equipment. Furthermore, the in-situ process ensures better operation and particle control than the ex-situ process.

[0042] In some embodiments, the lateral etching process may be performed after the formation of the second epitaxial SiGe layer but before the formation of the epitaxial capping layer. Furthermore, the SiGe growth and subsequent etching may be followed by another cycle of SiGe growth and etching, if necessary. For example, for smaller fin pitch dimensions (e.g., less than 50 nm), a third SiGe growth (e.g., similar to the second SiGe growth in terms of Ge atomic percentage and B concentration) may be performed, and a second lateral etch may be required. After the formation of the third SiGe layer, the capping layer (e.g., a fourth epitaxial SiGe layer) is formed thereon.

[0043] In some embodiments, the etch chemistry may include HCl, GeH4, and Cl2. As one of ordinary skill in the art would understand, these gases may be introduced as a mixture or individually. Furthermore, other gas combinations may be possible. By way of example and not limitation, the flows for each of the above-mentioned gases may range from 40 to 1000 sccm for HCl, 0 to 1000 sccm for GeH4, and 0 to 100 sccm for Cl2. In some embodiments, the wafer temperature during the lateral etch process may range from 450 to 800°C, while the etch time may range from 5 to 1200 seconds. As one of ordinary skill in the art would understand, these ranges are only examples and are not intended to be limiting.

[0044] In some embodiments, the etching process has a high selectivity for the x-direction or along the (110) plane, which is parallel to the wafer surface. Consequently, the etching rate along the y-direction (e.g., perpendicular to the wafer surface and along the (100) plane) is nominally zero or insignificant. For example, the height loss can be limited to 5 nm or less. As one of ordinary skill in the art would understand, the lateral etch selectivity can be tuned by etching process parameters such as gas flow rates and wafer temperature. The etching rate and lateral selectivity may also depend on the B and Ge atomic percentages for the second epitaxial SiGe layer and the first epitaxial SiGe layer.Any or all combinations of wafer temperature, etch gas flow rates, Ge atomic percentages, and B dopant concentrations can be used to tailor the final etch process and optimize lateral selectivity. In some embodiments, higher process temperatures, higher Ge atomic percentages, and higher gas flow rates can favor lateral etch selectivity along the (110) plane, which is the fin width direction (x-direction).

[0045] For example, in Fig. 1, the selective etching process removes material from the SiGe S / D side surfaces 135 and 140 along the x-direction, along the plane (110), without substantially etching the upper surface 130. Therefore, the height loss during the lateral etching process can be in the range of 0 to 5 nm. Consequently, after etching and with reference to the Fig. 2 the final angle 210 of SiGe-S / D 120 wider than the original angle 145 in Fig. 1. Also, the S / D width 205 is reduced compared to the original S / D width 150. In some embodiments, the angle 210 may range between 55° and about 180°.

[0046] In a similar way, the Fig. 4 an exemplary two-fin structure 400, which may be the result of a lateral process performed on the structure 300 of Fig. 3 according to some embodiments. As one of ordinary skill in the art would understand, the final SiGe S / D width 400 may be smaller than the original SiGe S / D width 340 of the Fig.3. Due to the lateral etching process, the final angle 420 is also wider than the original angle 360. In some embodiments, the angle 420 may range from 55° to about 180°. In some embodiments, the lateral etch amount may vary from 0 to 20 nm. Furthermore, due to the lateral selectivity of the etching process, the height 350 is not significantly affected by the etch. For example, the S / D height loss may range from 0 to 5 nm.

[0047] As mentioned above, to minimize the FINFET performance degradation due to the volume change of the S / D region after etching, the height and B dopant concentrations can be adjusted accordingly. For example, a height adjustment can be in the range of 5 to 20 nm, and the B dopant concentration range can be from 3×10 20 -5×10 21 atoms / cm 3 up to 1×10 20 -3×10 21 atoms / cm 3Both settings can be made during the growth of the second epitaxial layer. As anyone with ordinary technical knowledge would understand, these settings are made before the selective etching process. The setting ranges mentioned above are only examples and are not intended to be limiting.

[0048] During operation 530, an epitaxial depletion SiGe layer is grown over the second epitaxial SiGe layer. In some embodiments, the epitaxial depletion SiGe layer is similar to the first epitaxial SiGe layer in terms of Ge atomic percentage and B dopant concentrations, for example, 0 to 40% for Ge and 5×10 19 up to 1×10 21 atoms / cm 3 for the B dopant concentration. In some embodiments, the thickness of the epitaxial depletion SiGe layer may range from 0 to 10 nm.

[0049] The present disclosure is directed to an in-situ etching process by which SiGe S / D regions between two adjacent fins of FINFET structures are laterally etched. The lateral etching is performed along the in-plane direction (110) or the fin width direction (x-direction). The lateral etching process can be integrated into the epitaxial growth process of the SiGe S / D regions. For example, the lateral etching process can be an in-situ process. To compensate for SiGe material loss on the S / D regions, the initial height and B dopant concentrations of the SiGe S / D regions can be adjusted to prevent FINFET performance degradation. Due to the lateral in-situ etching process, the S / D regions of adjacent fins can be better insulated, and electrical short circuits can be prevented.

[0050] The etching process may be configured to have high selectivity along the (110) plane, thus reducing the width of the SiGe S / D regions without significantly affecting the height of the S / D regions. The lateral selectivity of the etching process may be tailored by critical process parameters such as gas flow rates and wafer temperatures. The selectivity may also depend on the Ge atomic percentage and the B dopant concentrations of the second and first epitaxial SiGe layers. Furthermore, successive cycles of epitaxial SiGe growth and selective lateral etching may be required for smaller fin pitch dimensions (e.g., fin pitches of less than 50 nm) according to some embodiments.As one of ordinary skill in the art would understand, the present disclosure can be extended to other applications requiring selective etching of SiGe materials, such as microelectromechanical systems (MEMS) and 3D integrated circuits.

[0051] In some embodiments, a method for laterally etching an epitaxial layer includes a plurality of fins formed on a substrate, each fin having a first width. Source / drain regions are formed on the plurality of fins, and each source / drain region has a second width in a common direction with the first width of the fin and a height. The source / drain regions are selectively etched to reduce the second width of the source / drain regions. An epitaxial depletion layer is grown over the source / drain regions.

[0052] In some embodiments, a method for laterally etching an epitaxial layer includes a plurality of fins formed on a substrate, each fin having a top surface, sidewall surfaces, and a first width. A source / drain region having a height is formed by growing a first epitaxial layer over the top surface and a portion of the sidewall surfaces of each fin. Further growing a second epitaxial layer over the first epitaxial layer, where the second epitaxial layer has a second width in a common direction with the first width of the fin. The second epitaxial layer is selectively etched for a predetermined period of time to reduce the second width of the second epitaxial layer.A third epitaxial layer is grown over the second epitaxial layer, where the third epitaxial layer has a third width aligned with the second width of the second epitaxial layer.

[0053] In some embodiments, a method for laterally etching an epitaxial layer comprises an epitaxial stack having a second epitaxial layer over a first epitaxial layer, and wherein the epitaxial stack has a height along the plane (100) and a first width along the plane (110). A portion of the epitaxial stack is selectively etched to reduce the first width along the plane (110). A third epitaxial layer is grown over the epitaxial stack such that the third epitaxial layer has a second width along the plane (110).

[0054] The above outlines features of embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

[1] A method for laterally etching an epitaxial layer, the method comprising: Forming (510) a plurality of fins (110, 115) on a substrate (160), each of the plurality of fins having a first width (125); Forming source / drain regions (120) on the plurality of fins, wherein the source / drain regions (120) are formed on two fins each, and wherein each source / drain region (120) has a second width (150) in a common direction with the first width and a height (155); selectively etching the source / drain regions (120) to reduce the second width of the source / drain regions (150); and Growing (530) an epitaxial depletion layer over the source / drain regions (120), wherein the selective etching comprises an in-situ etch with hydrochloric acid,HCl, germane,GeH4, and chlorine,Cl2, and wherein a flow rate for HCl is 40 to 1000 sccm, a flow rate for GeH4 is 0 to 1000 sccm, and a flow rate for Cl2 is 0 to 100 sccm. [2] The method of claim 1, wherein the height of each of the source / drain regions (120) is between 40 and 80 nm. [3] The method of claim 1 or 2, wherein the in-situ etching is carried out at a process temperature between 450 and 800 °C. [4] The method of any preceding claim, wherein the in-situ etching reduces the height of the source / drain regions (120) by 0 to 5 nm. [5] The method of any preceding claim, wherein forming the source / drain regions (120) comprises: Growing a first epitaxial layer (120) over each of the plurality of fins (110, 115); and Growing (515) a second epitaxial layer (120) over the first epitaxial layer. [6] The method of claim 5, wherein growing the first epitaxial layer (120) comprises growing a silicon-germanium epitaxial layer having a germanium atomic percentage between 0 and 40%, a boron dopant concentration between 5×10 19 and 1×10 21 atoms / cm 3 and a thickness between 10 and 20 nm. [7] The method of claim 5 or 6, wherein growing (520) the second epitaxial layer (120) comprises growing an epitaxial silicon-germanium layer having a germanium atomic percentage between 20 and 80%, a boron dopant concentration between 1×10 20 and 3×10 21 atoms / cm 3 and a thickness between 30 and 60 nm. [8] The method of any preceding claim, wherein growing (530) the epitaxial capping layer (120) comprises growing an epitaxial silicon-germanium layer having a germanium atomic percentage between 0 and 40%, a boron dopant concentration between 5×10 19 and 1×10 21 atoms / cm 3 and a thickness between 10 and 20 nm. [9] A method for laterally etching an epitaxial layer (120), the method comprising: Forming (510) a plurality of fins (110, 115) on a substrate (160), each of the plurality of fins having a top surface (130), sidewall surfaces (135, 140), and a first width (150); and Forming a source / drain region (120), wherein the source / drain region has a height (155), and wherein forming the source / drain region comprises: growing (515) a first epitaxial layer over the top surface and over a portion of the sidewall surfaces of each fin (110, 115); growing (520) a second epitaxial layer over the first epitaxial layer, the second epitaxial layer having a second width in a common direction with the first width; selectively etching (525) the second epitaxial layer for a predetermined period of time to reduce the second width of the second epitaxial layer; Growing a third epitaxial layer over the second epitaxial layer, the third epitaxial layer having a third width aligned with the second width of the second epitaxial layer; selectively etching the third epitaxial layer for another predetermined period of time to reduce the third width of the third epitaxial layer; Growing a fourth epitaxial layer over the third epitaxial layer; and wherein the selective etching of the second epitaxial layer increases an angle (145) formed by a pair of side surfaces of the S / D region from a first range between 45° and 65° to a second range (210) between 55° and 180°, wherein the selective etching of the second epitaxial layer comprises in-situ etching of the second epitaxial layer at a temperature between 450 and 800°C with hydrochloric acid, HCl, germane, GeH4, and chlorine, Cl2, and wherein the in-situ etching comprises introducing the HCl, the GeH4, and Cl2 to form a mixture. [10] The method of claim 9, wherein the in-situ etching reduces the height of the source / drain region (120) by 0 to 5 nm. [11] A method for laterally etching an epitaxial layer, the method comprising: Forming (520) an epitaxial stack having a second epitaxial layer over a first epitaxial layer, the epitaxial stack having a height (155) along a plane and a first width (150) along a plane; selectively etching a portion of the epitaxial stack to reduce the first width (150) along the plane; and Growing a third epitaxial layer over the epitaxial stack, the third epitaxial layer having a second width (205) along the plane; wherein the selective etching comprises reducing the height of the epitaxial stack by less than 5 nm, wherein the selective etching comprises an in-situ etch with hydrochloric acid, HCl, germane, GeH4, and chlorine, Cl2, and wherein a flow rate for HCl is 40 to 1000 sccm, a flow rate for GeH4 is 0 to 1000 sccm, and a flow rate for Cl2 is 0 to 100 sccm. [12] The method of claim 11, further comprising: prior to forming the epitaxial stack, forming a plurality of fins (110, 115) on a substrate (160), each of the plurality of fins (110, 115) having an epitaxial stack formed thereon. [13] The method of claim 11 or 12, wherein the selective etching comprises an in-situ etching carried out at a process temperature between 450 and 800 °C. [14] A method according to any one of the preceding claims 11 to 13, further comprising: selectively etching a portion of the third epitaxial layer to reduce the second width (205) of the third epitaxial layer along the plane (110); and Growing a fourth epitaxial layer over the third epitaxial layer.

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