IGBT with fully depletable n- and p-channel regions and processes

Abstract

A power semiconductor device (1) comprising a semiconductor body (10) coupled to a first load connection structure (11) and a second load connection structure (12), wherein the semiconductor body (10) is configured to conduct a load current (15) and comprises a drift region (100) of a first conductivity type, wherein the power semiconductor device (1) comprises a plurality of cells (14), each cell (14) comprising: - a first mesa (101) contained in a first cell portion (141), the first mesa (101) including: a first terminal region of the first conductivity type (1011) electrically connected to the first load terminal structure (11), and a first channel region (1012) coupled to the drift region (100), the first mesa (101) having a total extension (DX13) of less than 100 nm in a lateral direction (X) perpendicular to a vertical direction (Z) of the load current portion (151) within the first mesa (101); - a second mesa (102) contained in a second cell portion (142), the second mesa (102) including: a second terminal region of a second conductivity type (1021) electrically connected to the first load terminal structure (11), and a second channel region (1022) coupled to the drift region (100); - a trench structure (17) including a control electrode structure (13) for controlling the load current at least by means of an inversion channel in the first channel region (1012); - a guiding zone (1023) of the second conductivity type arranged below the second channel region (1022) while being spatially offset from both the first and second channel regions (1012, 1022) along the vertical direction (Z), wherein the guiding zone (1023) laterally overlaps the second mesa (102) and extends laterally towards the first mesa (101) while not laterally overlapping therewith, and wherein the guiding zone (1023) is separated from the second load connection structure (12) at least by means of a region of the first conductivity type.

Description

TECHNICAL FIELD

[0001] This description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, this description relates to embodiments of an IGBT with fully depletable n- and p-channel regions and to embodiments of a corresponding manufacturing method. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, depend on semiconductor devices. Insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, are used for a wide variety of applications, including switches in power supplies and power converters.

[0003] It is a general goal to minimize losses that occur in semiconductor devices, where losses are essentially caused by conduction losses and / or switching losses.

[0004] For example, a power semiconductor device comprises a plurality of MOS control heads, wherein each control head may have at least one control electrode and a source region and a channel region arranged adjacent thereto.

[0005] In order to place the power semiconductor device into a conducting state during which a load current can be conducted in a forward direction, the control electrode can be supplied with a control signal having a voltage within a first range such that a load current path is induced within the channel region.

[0006] In order to put the power semiconductor device into an off-state, during which a forward voltage applied to load terminals of the semiconductor device can be blocked and a flow of the load current in the forward direction is prevented, the control electrode can be supplied with the control signal having a voltage within a second range that is different from the first range, so that the load current path in the channel region is cut off. The forward voltage can then induce a depletion region at a junction formed by a change between the channel region and a drift region of the power semiconductor device, wherein the depletion region is also referred to as a "space charge region" and can extend mainly into the drift region of the semiconductor device. In this context, the channel region is often also referred to as a "body region" in which the load current path, e.g.An inversion channel through which a control signal can be induced to place the semiconductor device in the conducting state. Without the load current path in the channel region, the channel region can form a reverse junction with the drift region.

[0007] In order to keep losses of the power semiconductor device low, a charge carrier density within a semiconductor body of the power semiconductor device may need to be controlled in an appropriate manner.

[0008] Furthermore, although high switching speeds may result in low losses, some applications may require that the rate of change of load current and / or voltage over time within the power semiconductor device, such as a rate of change of voltage during a turn-on or turn-off operation (also referred to as "dU / dt" or "dV / dt", respectively), does not exceed a predetermined maximum.

[0009] Therefore, it may be desirable to provide a power semiconductor device that provides low conduction losses and low switching losses and at the same time easy controllability so as to ensure that a rate of change in voltage during a turn-on operation or a turn-off operation does not exceed a predetermined maximum.

[0010] An IGBT with a nanostructure is known from the documents DE 10 2016 112 017 A1 and DE 10 2016 112 020 A1, which had not yet been published on the filing date of the present application, as well as from the previously published document DE 10 2015 117 994 A1. SUMMARY

[0011] According to one embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body being configured to conduct a load current and comprising a drift region of a first conductivity type, the power semiconductor device comprising a plurality of cells. Each cell comprises: a first mesa contained within a first cell portion, the first mesa including: a first terminal region of the first conductivity type electrically connected to the first load terminal structure, and a first channel region coupled to the drift region, the first mesa having a total extension of less than 100 nm in a lateral direction perpendicular to a vertical direction of the load current portion within the first mesa;a second mesa included in a second cell portion, the second mesa including: a second terminal region of a second conductivity type electrically connected to the first load terminal structure, and a second channel region coupled to the drift region; a trench structure including a control electrode structure for controlling the load current at least by means of an inversion channel in the first channel region; a guiding zone of the second conductivity type disposed below the second channel region while being spatially offset from both the first and second channel regions along the vertical direction, the guiding zone laterally overlapping the second mesa and extending laterally toward the first mesa while laterally not overlapping it, and the guiding zone being separated from the second load terminal structure at least by means of a region of the first conductivity type.

[0012] According to another embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body being configured to conduct a load current and comprising a drift region of a first conductivity type, the power semiconductor device comprising a plurality of cells. Each cell comprises: a first mesa contained within a first cell portion, the first mesa including: a first terminal region of the first conductivity type electrically connected to the first load terminal structure and a first channel region coupled to the drift region;a second mesa included in a second cell portion, the second mesa including: a second terminal region of a second conductivity type electrically connected to the first load terminal structure, and a second channel region coupled to the drift region; a trench structure including a control electrode structure for controlling the load current at least by means of an inversion channel in the first channel region; a guiding zone of the second conductivity type arranged below the second channel region, the guiding zone laterally overlapping the second mesa and extending laterally toward the first mesa while not laterally overlapping it, and the guiding zone being separated from the second load terminal structure at least by means of a region of the first conductivity type;a barrier zone of the first conductivity type arranged between the guiding zone and the trench structure, the barrier zone having a dopant concentration at least twice as high as the dopant concentration of the drift region;

[0013] According to yet another embodiment, a method for manufacturing a power semiconductor device is presented. The power semiconductor device comprises a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body being configured to conduct a load current and comprising a drift region of a first conductivity type, the power semiconductor device comprising a plurality of cells.Each cell comprises: a first mesa included in a first cell portion, the first mesa including a first terminal region of the first conductivity type electrically connected to the first load terminal structure, and a first channel region coupled to the drift region; a second mesa included in a second cell portion, the second mesa including a second terminal region of a second conductivity type electrically connected to the first load terminal structure, and a second channel region coupled to the drift region; a trench structure including a control electrode structure for controlling the load current at least by means of an inversion channel in the first channel region. The method comprises: a) providing the first mesa with a total extension of less than 100 nm in a lateral direction perpendicular to a vertical direction of the load current portion within the first mesa; and providing a guiding zone of the second conductivity type disposed below the second channel region while being spatially offset from both the first and second channel regions along the vertical direction, wherein the guiding zone laterally overlaps the second mesa and extends laterally toward the first mesa while not laterally overlapping it, and wherein the guiding zone is separated from the second load connection structure at least by means of a region of the first conductivity type; or b) providing a guiding zone of the second conductivity type arranged below the second channel region, wherein the guiding zone laterally overlaps the second mesa and extends laterally toward the first mesa while not laterally overlapping it, and wherein the guiding zone is separated from the second load connection structure at least by a region of the first conductivity type; and providing a barrier zone of the first conductivity type arranged between the guiding zone and the trench structure, wherein the barrier zone has a dopant concentration at least twice as high as the dopant concentration of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The parts in the figures are not necessarily to scale, emphasis being placed instead on illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: Fig. 1A-B each schematically illustrate a portion of a horizontal projection of a power semiconductor device according to some embodiments; Fig. 2A-B each schematically illustrate a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 3A-B each schematically illustrate a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 4 schematically illustrates a distribution of a charge carrier concentration in a semiconductor body of a power semiconductor device according to one or more embodiments; Fig. 5A schematically illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 5B-C each schematically illustrate a portion of a horizontal projection of a power semiconductor device according to some embodiments; Fig. 6 schematically illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 7A-B each schematically illustrate a portion of a vertical cross-section of a power semiconductor device according to some embodiments; Fig. 8A-D each schematically illustrate a portion of a vertical cross-section of a power semiconductor device according to some embodiments; and Fig. 9-17 each schematically illustrate a portion of a vertical cross-section of a power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0015] In describing the figures, directional terminology such as "above," "below," "below," "in front," "behind," "back," "leading," "hanging," "over," etc., may be used with reference to the orientation of the figures being described. Because portions of embodiments may be positioned in a variety of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting.

[0016] The term "horizontal" as used in this specification may describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or a semiconductor region, such as the semiconductor body mentioned below. This may be, for example, the surface of a semiconductor wafer or a die. Both the first lateral direction X and the second lateral direction Y mentioned below may, for example, be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0017] The term "vertical" as used in this description may describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal of the surface of the semiconductor wafer. The extension direction Z mentioned below may, for example, be a vertical direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. Therefore, the extension direction Z is also referred to herein as the vertical direction Z.

[0018] However, it should be understood that the embodiments of power semiconductor devices described below may have a lateral configuration or a vertical configuration.

[0019] In this specification, n-doped is referred to as a "first conductivity type," whereas p-doped is referred to as a "second conductivity type." Alternatively, reversed doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0020] Furthermore, the term "dopant concentration" within this description may refer to an average dopant concentration, a mean dopant concentration, or a surface charge carrier concentration of a specific semiconductor region / zone / section / layer. Accordingly, for example, a statement that a specific semiconductor region has a certain dopant concentration that is comparatively higher or lower than a dopant concentration of another semiconductor region may indicate that the corresponding mean dopant concentrations of the semiconductor regions differ from one another.

[0021] In the context of the present description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe that a low-resistance electrical connection or a low-resistance current path exists between two regions, sections, zones, portions, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and a portion or part of a semiconductor device. Furthermore, the term "in contact" in the context of the present description is intended to describe that a direct physical connection exists between two elements of the respective semiconductor device; e.g., a junction between two elements in contact with each other may not involve any further intermediate element or the like.

[0022] The term "power semiconductor device" as used in this specification is intended to describe a single-chip semiconductor device with high voltage blocking and / or high current-carrying capabilities. In other words, such a power semiconductor device is configured for a high load current, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or for high voltages, typically above 5 V, or above 15 V, or more typically 400 V, and e.g., up to several thousand volts.

[0023] For example, the term “power semiconductor device” as used in this specification does not refer to logic semiconductor devices used, for example, for storing data, computing data, and / or other types of semiconductor-based data processing.

[0024] Accordingly, specific embodiments described in this specification relate, among other things, to a power semiconductor device (hereinafter also simply referred to as "semiconductor device" or "device") that can be used within a power converter or power supply, e.g., for converting a first power signal into a second power signal that is different from the first power signal. For example, for this purpose, the power semiconductor device may comprise one or more power semiconductor cells, such as a monolithically integrated transistor cell, a monolithically integrated diode cell, and / or a monolithically integrated IGBT cell, and / or a monolithically integrated MOS-gated diode (MGD) cell, and / or a monolithically integrated MOSFET cell, and / or derivatives thereof.Such diode cells and / or such transistor cells may be integrated in a semiconductor chip, wherein a number of such chips may be integrated in a power semiconductor module, such as an IGBT module.

[0025] According to all embodiments described herein, the power semiconductor device may have an IGBT configuration.

[0026] Fig. 1A schematically and exemplarily illustrates a portion of a horizontal projection of a power semiconductor device 1 according to one or more embodiments. Also Fig. 1B schematically and exemplarily illustrates a portion of a horizontal projection of a power semiconductor device 1 according to one or more other embodiments. Both in Fig. 1A as well as Fig. 1B, the horizontal projection may be parallel to the plane defined by the first lateral direction X and the second lateral direction Y. The components of the semiconductor device 1 may each extend along the extension direction Z, which may be perpendicular to both the first lateral direction X and the second lateral direction Y.

[0027] The semiconductor device 1 may include an active cell array 16 including one or more active cells 14, e.g., MOS (Metal Oxide Semiconductor) cells, which are referred to simply as "cells" 14 hereinafter. The number of cells 14 is greater than, e.g., one hundred or even greater than one thousand or more. For example, the semiconductor device 1 may include the active cell array 16 with a cell array area of ​​1 mm * 1 mm or more, and may include, e.g., approximately 200 to 1000 cells 14 within such a cell array area, e.g., with a cell pitch of 1 to 5 µm. The active cell array 16 may be configured to conduct a total load current, wherein the total load current may be greater than 1 A, greater than 10 A, or even greater than 100 A. In the following, the total load current is also simply referred to as “load current”.

[0028] The active cell array 16 can be surrounded by an edge termination zone 18 of the semiconductor device 1. For example, the edge termination zone 18 does not contain any active cells. The edge termination zone 18 can be terminated by an edge 19, which can be created, for example, by dicing a chip from a wafer.

[0029] Furthermore, the active cell array 16 or the active cell array 16 and the edge termination zone 18 may be configured to block a voltage of at least 20 V, of at least 100 V, of at least 400 V or of at least 1000 V.

[0030] As shown schematically in Fig. 1A, the cells 14 may have a stripe configuration. Accordingly, each of the cells 14 and at least some of the components they may include may extend along substantially the entire active cell array 16 along the first lateral direction X or the second lateral direction Y (as illustrated), e.g., defining a transition region between the active cell array 16 and the edge termination zone 18.

[0031] In another embodiment, shown schematically in Fig. 1B, the cells 14 may have a needle configuration (also referred to as a "columnar configuration") whose total lateral dimensions along both the first lateral direction X and the second lateral direction Y are only a fraction of the total lateral dimensions along the first lateral direction X and the second lateral direction Y of the active cell array 16. For example, the total lateral dimension of a respective needle cell is less than 1% of the total dimension of the active cell array 16 along the first lateral direction X or the second lateral direction Y. Further, optional aspects of a needle cell and a stripe cell are explained below.

[0032] In another embodiment, the active cell array 16 may include both types of cells 14, e.g., one or more cells 14 having a stripe configuration and one or more cells 14 having a needle configuration, or e.g., one or more cells 14 having stripe configurations with different dimensions in the second lateral direction Y.

[0033] Both the active cell array 16 and the edge termination region 18 may be formed at least partially within a common semiconductor body 10 of the device 1. The semiconductor body 10 may be configured to carry the entire load current, which may be controlled, for example, by means of the cells 14, as described in more detail below.

[0034] In one embodiment, the semiconductor device 1 is a bipolar power semiconductor device 1. Accordingly, the total load current within the semiconductor body 10 can be represented by a first load current formed by first charge carriers of the first conductivity type and by a second load current formed by second charge carriers of the second conductivity type complementary to the first conductivity type. For example, the first charge carriers are electrons, and the second charge carriers are holes.

[0035] Now with regard to Fig. 2A, which schematically and exemplarily illustrates a portion of a vertical cross-section of the semiconductor device 1 according to one or more embodiments, the semiconductor device 1 may further comprise a first load terminal structure 11 and a second load terminal structure 12. For example, the first load terminal structure 11 is arranged separately from the second load terminal structure 12. The semiconductor body 10 may be coupled to both the first load terminal structure 11 and the second load terminal structure 12 and may be configured to receive the entire load current 15 (also referred to as "load current") via the first load terminal structure 11 and output the entire load current 15 via the second load terminal structure 12 and / or vice versa.

[0036] The semiconductor device 1 may have a vertical structure, according to which, for example, the first load connection structure 11 is arranged on a front side of the semiconductor device 1 and the second load connection structure 12 is arranged on a rear side of the semiconductor device 1. In another embodiment, the semiconductor device 1 may have a lateral structure, according to which, for example, both the first load connection structure 11 and the second load connection structure 12 are arranged on the same side of the semiconductor device 1.

[0037] For example, the first load connection structure 11 comprises a first metallization, e.g., a front-side metallization, and the second load connection structure 12 may comprise a second metallization, e.g., a back-side metallization. Furthermore, the first load connection structure 11 and / or the second load connection structure may comprise a diffusion barrier (not illustrated).

[0038] Throughout the present description, the direction of the total load current 15 is expressed in the conventional manner, i.e., as a flow direction of positive charge carriers, such as holes, and / or as a direction opposite to a flow of negative charge carriers, such as electrons. A forward direction of the total load current 15 may, for example, point from the second load terminal structure 12 to the first load terminal structure 11.

[0039] As explained above, the total load current 15 may comprise a movement of charge carriers of the first conductivity type, e.g., an electron movement or an electron current, and a movement of charge carriers of the second conductivity type, e.g., a hole movement or a hole current. Accordingly, the movement direction of the charge carriers of the second conductivity type may be parallel to the technical (conventional) direction of the total load current 15, whereas the movement direction of the charge carriers of the first conductivity type may be antiparallel to the direction of the load current 15. The sum of a charge movement of the first conductivity type and the second conductivity type may form the total load current 15 conducted by the semiconductor body 10.

[0040] A first charge carrier of the first conductivity type, e.g., an electron, moving from the first load connection structure 11 to the second load connection structure 12 or vice versa, may recombine with a second charge carrier of the complementary type, e.g., the second conductivity type, e.g., a hole, on its way through the semiconductor body 10. For example, in the vicinity of the first load connection structure 11, the entire load current 15 in the forward direction may largely or even entirely consist of a movement of charge carriers of the first conductivity type (e.g., electrons) moving toward the second load connection structure 12, whereas in the vicinity of the second load connection structure 12 (compare third connection region 104), the entire load current 15 in the forward direction may largely or even entirely consist of a movement of charge carriers of a second conductivity type (e.g.,holes) moving toward the first load terminal structure 11. The electrons and holes may recombine within the semiconductor body 10. However, within a drift region 100 of the semiconductor body 10, substantially no or only little recombination may occur according to one or more embodiments. According to one embodiment, an ambipolar lifetime of the first and second charge carrier types, i.e., the time until the density of charge carriers is reduced to a value of 1 / e ≈ 37% of its initial value, is more than, for example, 1 µs, more than 10 µs, more than 30 µs, or more than 70 µs.

[0041] Furthermore, the movement of charge carriers of the first conductivity type may include or consist of a first drift movement, e.g., an electron drift movement, and a first diffusion movement, e.g., an electron diffusion movement. In simplified terms, the entire movement of charge carriers of the first conductivity type will result in a first load current 151.

[0042] Furthermore, the movement of charge carriers of the second conductivity type may include or consist of a second drift movement, e.g., a hole drift movement, and a second diffusion movement, e.g., a hole diffusion movement. By analogy, the total movement of charge carriers of the second conductivity type will result in a second load current 152.

[0043] Accordingly, in the conducting state of the semiconductor device 1, the entire load current 15 can be conducted through the semiconductor body 10, wherein at each cross-section through the semiconductor body 10 separating the first load contact structure 11 from the second load contact structure 12, the entire load current 15 can consist of the first load current 151 flowing through the cross-section, which can be an electron current, and the second load current 152 flowing through the cross-section, which can be a hole current. At each cross-section, the sum of the magnitudes of the first load current 151 and the second load current 152 can be equal to the magnitude of the entire load current 15, wherein the cross-sections can be perpendicular to the direction of the entire load current 15. For example, the entire load current 15 during the conducting state can be dominated by the first load current 151, i.e., the first load current 151 can be substantially larger than the second load current 152, e.g.more than 75%, more than 80%, or even more than 90% of the total load current. During a transition from the blocking state to the conducting state or during a transition from the conducting state to the blocking state, ie, during switching, the second load current 152 may represent a higher proportion of the total load current 15, ie, the second load current 152 may even be greater than the first load current 151.

[0044] To control the total load current 15, the semiconductor device 1 may further comprise a control electrode structure 13. For example, the semiconductor device 1 may be configured to be set to the off-state or the conducting state by means of the control electrode structure 13.

[0045] In one embodiment, to place the semiconductor device 1 in a conducting state during which the entire load current 15 can be conducted in the forward direction, the control electrode structure 13 can be supplied with a control signal having a voltage within a first range. To place the semiconductor device 1 in a blocking state during which a forward voltage can be blocked and flow of the load current 15 in the forward direction is prevented, the control electrode structure 13 can be supplied with the control signal having a voltage within a second range that is different from the first range.

[0046] In one embodiment, the control signal may be provided by applying a voltage between the control electrode structure 13 and the first load terminal structure 11 and / or by providing a voltage between the control electrode structure 13 and the second load terminal structure 12.

[0047] For example, the control electrode structure 13 may be implemented at least partially within the cells 14, as schematically shown in Fig. 2A-3B. Furthermore, the cells 14 may be implemented at least partially within the semiconductor body 10. The cells 14 may form a part of the semiconductor body 10.

[0048] In one embodiment, the cells 14 may include at least a first cell portion 141 and at least a second cell portion 142. The second cell portion 142 may be different and arranged separately from the first cell portion 141.

[0049] Both the first cell part 141 and the second cell part 142 may be electrically connected to the first load connection structure 11 on one side and may be electrically coupled to the semiconductor drift region 100 (here also simply referred to as “drift region”) of the semiconductor body 10 on the other side.

[0050] The drift region 100 is a region of the first conductivity type. For example, the drift region 100 exhibits a concentration of dopants of the first conductivity type within the range of 10 12 cm -3 up to 10 18 cm -3 , e.g. 10 13 cm -3 up to 10 15 cm -3 , e.g. within the range of 2*10 13 cm -3 up to 2*10 14 cm -3The drift region 100 may further comprise dopants of the second conductivity type. For example, the comparatively high dopant concentrations may be applicable if the semiconductor device 1 has a compensation structure (also referred to as a superjunction structure). In this case, locally high concentrations of dopants of the first and second conductivity types may occur. However, if the first and second dopant concentrations are integrated in the drift region 100 in, e.g., a horizontal plane, e.g., substantially parallel to the first load terminal structure 11 or the second load terminal structure 12, the resulting integrated dopant concentration may be significantly lower, e.g., at least by a factor of 3, a factor of 5, or a factor of 10, than the larger of the individual dopant concentrations of the first and / or second conductivity types.Such a locally high dopant concentration may be supportive for discharging charge carriers from the semiconductor body 10, e.g., during turn-off, and may accordingly lead to reduced turn-off losses and / or faster turn-off.

[0051] In one embodiment, the first cell portion 141 is configured to control the first load current 151, and the second cell portion 142 is configured to control the second load current 152. For example, the first cell portion 141 is configured to prevent the second load current 152 from passing through the first cell portion 141. Furthermore, the second cell portion 142 may be configured to prevent the second load current 152 from passing through the second cell portion 152, e.g., if the semiconductor device 1 is in a conducting state.

[0052] The first cell portion 141 may accordingly be a unipolar cell configured to control charge carriers of the first conductivity type, and the second cell portion 142 may be a unipolar cell configured to control charge carriers of the second conductivity type.

[0053] In one embodiment, the semiconductor device 1 may be configured to divide the total load current 15 conducted through the semiconductor body 10 into the first load current 151 and the second load current 152 by means of the first cell part 141 and the second cell part 142, which may form an interface between the first load terminal structure 11 and a part of the semiconductor body 10, e.g., the drift region 100. Accordingly, in the path of the total load current 15 between the drift region 100 of the semiconductor body 10 and the first load terminal structure 11, the first load current 151 may traverse the first cell part 141, e.g., if the semiconductor device 1 is in a conducting state, and may, e.g., if the semiconductor device 1 is in a conducting state. For example, when the semiconductor device 1 is switched from the conducting state to the blocking state, the second load current 152 may pass through the second cell portion 142, as described in more detail below.

[0054] With reference to Fig. 3A and Fig. 3B will explain exemplary aspects of cells 14.

[0055] Fig. 3A and Fig. 3B schematically and exemplarily illustrate sections of a vertical cross-section of the semiconductor device 1 according to one or more embodiments. The general configuration of the semiconductor device 1 according to the embodiment of Fig. 3A-B may be identical to or similar to the general configuration of the semiconductor device 1 according to the embodiments of Fig. 1A, Fig. 1 B and Fig. 2A, Fig. 2B. Thus, what was stated above with regard to the Fig. 1A to 2B, equally for the embodiment of Fig. 3A and Fig. 3B apply unless otherwise stated.

[0056] In one embodiment, the control signal provided to the control electrode structure 13 comprises a first control signal and a second control signal. The first control signal may be provided for controlling the first cell portion 141, and the second control signal may be provided for controlling the second cell portion 142. In one embodiment, the first control signal is identical to the second control signal. In another embodiment, the first control signal is different from the second control signal. The control signal may be provided from outside the semiconductor device 1, e.g., by a driver (not illustrated) configured to generate the first control signal and the second control signal. In another embodiment, the first control signal and / or the second control signal may be generated or provided by an internal signal or by an internal potential of the semiconductor device 1.

[0057] The control electrode structure 13 may be contained within a trench structure 17. Furthermore, the control electrode structure 13 may include one or more first control electrodes 131 and / or one or more second control electrodes 132. For example, each of the one or more first control electrodes 131 and / or the one or more second control electrodes 132 is a trench electrode, as shown in Fig. 3A-B is illustrated.

[0058] The first cell portion 141 may include one or more of the first control electrodes 131, which may be configured to receive the first control signal. The first control electrodes 131 may be insulated from the semiconductor body 10 by an isolation structure 133. The isolation structure 133 may form the trench structure 17.

[0059] The second cell portion 142 may include one or more of the second control electrodes 132, which may be configured to receive the second control signal. The second control electrodes 132 may also be insulated from the semiconductor body 10 by means of the insulation structure 133.

[0060] The material and dimensions of the one or more first control electrodes 131 may be identical to or different from the material and dimensions of the one or more second control electrodes 132.

[0061] Furthermore, it is already understood at this point that the control electrodes 131 and 132, in contrast to the exemplary schematic representations in Fig. 3A, 3B, 5A, 8A-D, 11, 13, and 17 may also be arranged in contact with each other according to one or more embodiments, thereby forming a monolithic control electrode used to control both the first cell portion 141 and the second cell portion 142. In other words, the control electrodes 131 and 132 may, in one embodiment, be respective sections of a common control electrode (see Fig. 6, Fig. 7, Fig. 9, Fig. 10, Fig. 12, Fig. 13 (compare dashed line), 15 and 16).

[0062] The insulation structure 133 can accordingly accommodate the control electrode structure 13. Furthermore, one, several, or each of the first control electrode(s) 131 and the second control electrode(s) 132 can be electrically insulated from both the first load terminal structure 11 and the second load terminal structure 12.

[0063] In one embodiment, the first cell portion 141 includes a first mesa 101 implemented at least partially as a part of the semiconductor body 10. Furthermore, the second cell portion 142 may include a second mesa 102 implemented at least partially as a part of the semiconductor body 10. For example, both the first mesa 101 and the second mesa 102 are electrically connected to the first load terminal structure 11. The second mesa 102 may be arranged different from and separate from the first mesa 101.

[0064] The first mesa 101 and the second mesa 102 may be spatially delimited by the isolation structure 133. Example specifications of the spatial dimensions of the mesa 101 and 102 and their components are described with reference to Fig. 5. At the same time, the insulation structure 133 can accommodate the first control electrode(s) 131 and the second control electrode(s) 132.

[0065] The first mesa 101 may include a first connection region 1011 electrically connected to the first load connection structure 11. The first connection region 1011 may be a first semiconductor connection region. For example, the first connection region 1011 is of the first conductivity type and comprises, for example, dopants of the first conductivity type with a dopant concentration in the range of 10 19 cm -3 up to 10 22 cm -3 , e.g. 10 20 cm -3 up to 5*10 21 cm -3 For example, the first connection area 1011 is an n +-region. Accordingly, a dopant concentration of the first terminal region 1011 may be at least two orders of magnitude (corresponding to a factor of 100) greater than the dopant concentration of the drift region 100. In one embodiment, the first terminal region 1011 is a doped semiconductor region that has been additionally silicided. For example, a silicide is provided in the first terminal region 1011. Furthermore, such a silicided first terminal region 1011 may have a common extension region along the vertical direction Z with the first control electrode 131. For example, such a silicided first terminal region 1011 could also be referred to as a "metal source." At a transition from the silicided first terminal region 1011 to a first channel region 1012 (explained in more detail below) of the first mesa 101, a doping peak may be present, e.g., an n + -doping tip.

[0066] The second mesa 102 may include a second connection region 1021 electrically connected to the first load connection structure 11. The second connection region 1021 may be a second semiconductor connection region. For example, the second connection region 1021 is of the second conductivity type and comprises, for example, dopants of the second conductivity type with a dopant concentration in the range of 10 18 cm -3 up to 10 22 cm -3 , e.g. 10 19 cm -3 up to 10 21 cm -3 For example, the second access area 1021 is a p +-region. Accordingly, a dopant concentration of the second terminal region 1021 may be at least two orders of magnitude higher than the dopant concentration of the drift region 100. In one embodiment, the second terminal region 1021 is a doped semiconductor region that has been additionally silicided. For example, a silicide is provided in the second terminal region 1021. Furthermore, such a silicided second terminal region 1021 may have a common extension region along the vertical direction Z with the second control electrode 132. At a transition from the silicided second terminal region 1021 to a second channel region 1022 (explained in more detail below) of the second mesa 102, a doping peak may be present, e.g., a p + -doping tip.

[0067] The first mesa 101 may further include a first channel region 1012 in contact with the first terminal region 1011. The first channel region 1012 may be a first semiconductor channel region. For example, the first channel region 1012 is of the second conductivity type and comprises, for example, dopants of the second conductivity type with a dopant concentration in the range of up to 10 19 cm -3 , e.g. 10 11 cm -3 up to 10 18 cm -3 , e.g. in the range of 10 14 cm -3 up to 10 18 cm -3 For example, the first channel area 1012 is a p-area or a p - -region. In another embodiment, the first channel region comprises 1012 dopants of the first conductivity type, e.g., with a dopant concentration in the range of up to 10 19 cm -3 , e.g. 10 11 cm -3 up to 10 18 cm -3, e.g. in the range of 10 13 cm -3 up to 10 17 cm -3 .

[0068] For example, the first channel region 1012 may be coupled to the semiconductor drift region 100.

[0069] In one embodiment, at least the first channel region 1012 may separate the first connection region 1011 from the semiconductor drift region 100. Furthermore, the first channel region 1012 may be an electrically floating region. For example, the first channel region 1012 is not in contact with the first load connection structure 11, but is separated therefrom by the first connection region 1011. In another embodiment, the first channel region 1012 is electrically connected to the first load connection structure 11.

[0070] The second mesa 102 may further include a second channel region 1022 in contact with the second terminal region 1021. The second channel region 1022 may be a second semiconductor channel region. For example, the second channel region 1022 is of the second conductivity type and comprises, for example, dopants of the second conductivity type with a dopant concentration in the range of up to 10 19 cm -3 , e.g. 10 11 cm -3 up to 10 18 cm -3 , e.g. in the range of 10 14 cm -3 up to 10 18 cm -3 For example, the second channel region 1022 is a p-type region. In another embodiment, the second channel region 1022 comprises dopants of the first conductivity type, e.g., having a dopant concentration in the range of up to 10 19 cm -3 , e.g. 10 11 cm -3 up to 10 18 cm -3 , e.g. in the range of 10 13cm -3 up to 10 17 cm -3 .

[0071] For example, the second channel region 1022 may be coupled to the semiconductor drift region 100.

[0072] Furthermore, at least the second channel region 1022 may separate the second connection region 1021 from the semiconductor drift region 100. Furthermore, the second channel region 1022 may be an electrically floating region, wherein the second channel region 1022 may be coupled to the drift region 100 (e.g., by means of a barrier zone 105, which is mentioned further below) or may even be in contact with the drift region 100. For example, the second channel region 1022 is not in contact with the first load connection structure 11, but is separated therefrom by the second connection region 1021.In another example, the second channel region 1022 may be of the same conductivity type as the second terminal region 1021, and the second channel region 1022 is only temporarily brought into an insulating or floating state by applying a suitable work function of the material of the second control electrode 132 or a suitable electrical potential to the second control electrode 132.

[0073] The first mesa 101 may be a first semiconductor mesa, and the second mesa 102 may be a second semiconductor mesa. It is understood that along the second lateral direction Y, the first mesa 101 may become the second mesa 102 (or the third mesa 103, mentioned below) and vice versa; that is, the mesa may change its configuration along the second lateral direction Y. At the transition between the active cell array and the edge termination region 18, a means for electrically contacting the mesa (regardless of its type (101, 102, or 103)) may be omitted.

[0074] In one embodiment, the first terminal region 1011 and / or the second terminal region 1022 may comprise a metal.

[0075] For example, the first connection region 1011 contributes to a certain proportion of the total volume of the first mesa 101, e.g., within the range of up to 75%, e.g., 10% to 75%, e.g., in the range of 20% to 50%. The first channel region 1012 may contribute to a different proportion of the total volume of the first mesa 101, e.g., within the range of up to 10% to 90%, e.g., 25% to 90%, e.g., in the range of 25% to 75%.

[0076] The second connection region 1021 may contribute to a certain proportion of the total volume of the second mesa 102, e.g., within the range of up to 75%, e.g., 10% to 75%, e.g., in the range of 20% to 50%. The second channel region 1022 may contribute to a different proportion of the total volume of the second mesa 102, e.g., within the range of 10% to 90%, e.g., 25% to 90%, e.g., in the range of 25% to 75%.

[0077] In one embodiment, the first cell portion 141 including the first mesa 101 is configured to completely deplete the first channel region 1012 of mobile charge carriers of the second conductivity type in the conducting state of the semiconductor device 1.

[0078] Furthermore, the second cell part 142 including the second mesa 102 may be configured to completely deplete the second channel region 1022 of mobile charge carriers of the second conductivity type in the conducting state of the semiconductor device 1.

[0079] In the conducting state, as exemplified in Fig. 3B, the semiconductor device 1 may be configured to split the path of the total load current 15 into at least two separate paths, the first of which is taken by the first load current 151 and traverses the first mesa 101 including the first channel region 1012, which may be completely depleted of mobile charge carriers of the second conductivity type, and the second of which is taken by the second load current 152 and traverses neither the second mesa 102 including the second channel region 1022, which may be completely depleted of mobile charge carriers of the second conductivity type, nor the first mesa 101 including the first channel region 1012, which may also be completely depleted of mobile charge carriers of the second conductivity type.Instead, the second cell portion 142 may be configured to block a flow of the second load current 152 through the second mesa 102, thereby preventing mobile charge carriers of the second conductivity type from leaving the semiconductor body 10 during the conducting state of the semiconductor device 1. In other words, the magnitude of the second load current 152 within both the first mesa 101 and the second mesa 102 may be substantially zero during the conducting state according to one embodiment. According to another embodiment, a certain proportion of the load current of up to 30%, or up to 20%, or up to 10% may be conducted by the second load current 152, which may traverse the first mesa 101 and / or the second mesa 102.

[0080] In the following, the term "fully depleted channel region" shall describe a channel region that is completely or at least predominantly depleted of mobile charge carriers of the second conductivity type, whereby mobile charge carriers of the first conductivity type may still be present to a significant extent in the fully depleted channel region. The same definition applies to the term "fully depletable channel region."

[0081] For example, in the steady-state conducting operating state, the fully depleted first channel region 1012 includes no or almost no mobile charge carriers of the second conductivity type, or at least no density of mobile charge carriers of the second conductivity type above a leakage current level, or at least an average density of mobile charge carriers of the second conductivity type that is lower than 10% of the average density of mobile charge carriers of the first conductivity type in the first channel region 1012.

[0082] Furthermore, in one embodiment, the fully depleted second channel region 1022 includes, for example, in the steady-state blocking operating state, no or almost no mobile charge carriers of the first conductivity type, or at least no density of mobile charge carriers of the first conductivity type above a leakage current level, or at least an average density of mobile charge carriers of the first conductivity type that is lower than 10% of the average density of mobile charge carriers of the second conductivity type in the second channel region 1022.

[0083] Accordingly, according to one embodiment, the channel regions 1012 and 1022 are fully depleted regions in a conducting state of the semiconductor device 1.

[0084] For example, the channel regions 1012 and 1022 are completely depleted. This can be achieved, for example, by selecting materials for the control electrodes 131 and 132 that result in work functions of the control electrodes 131, 132 that may be different from those of the channel regions 1012 and / or 1022. Additionally or alternatively, this can be achieved by setting the control electrodes 131 and 132 to an appropriate electrical potential with respect to, for example, the electrical potential of the first load terminal structure 11.Accordingly, in one embodiment, complete depletion of the channel regions 1012, 1022 may be achieved due to a difference between the work function(s) of one or both of the control electrodes 131, 132 on the one hand and the work function(s) of one or both of the channel regions 1012, 1022 on the other hand and due to setting one or both of the control electrodes 131, 132 to a defined electrical potential.

[0085] According to an embodiment described herein, in order to achieve the fully depleted channel regions 1012 and 1022, the lateral dimensions may be limited in the first lateral direction X, which will be described in more detail later.

[0086] For example, if the semiconductor device 1 is set to the conducting state, e.g., by applying a voltage within the first range between each of the control electrodes 131 and 132 on one side and the first load terminal structure 11 on the other side (e.g., the electrical potential of each of the control electrodes 131 and 132 may be greater than the electrical potential of the first load terminal structure 11), the channel regions 1012 and 1022 may be completely depleted of mobile charge carriers of the second conductivity type. There may then be significantly fewer mobile charge carriers of the second conductivity type, e.g., holes, in the first channel region 1012 compared to a state in which no positive voltage is applied. And there may then also be significantly fewer mobile charge carriers of the second conductivity type, e.g., holes, in the second channel region 1022.For example, the phrase “significantly fewer mobile charge carriers” in this specification is intended to describe that the amount of mobile charge carriers of the respective conductivity type is less than 10% of the mobile charge carriers of the other conductivity type.

[0087] According to one embodiment, the semiconductor device 1 is configured to completely deplete the first channel region 1012 of charge carriers of the second conductivity type if a voltage applied between the first control electrode 131 and the first load connection structure 11 is within the first range, e.g., within a range from -1 V to +3 V. According to another embodiment, the semiconductor device 1 is configured to completely deplete the first channel region 1012 if a voltage is applied between the first control electrode 131 and the first load connection structure 11 that generates an electric field within a first range, e.g.,within a range of -3 MV / cm to +10 MV / cm, or within a range of -2 MV / cm to +6 MV / cm, or within a range of -1 MV / cm to +4 MV / cm, wherein the electric field is present within the isolation structure 133 located between the first mesa 101 and the first control electrode 131. The same may apply analogously to the second channel region 1022.

[0088] For example, in an off-state of the semiconductor device 1, only one current path for the second load current 152 exists in at least one of the channel regions 1012 and 1022, e.g., only in the channel region 1022, thus accordingly allowing an eventual leakage current to pass through. In the off-state, the semiconductor device 1 may be configured to build up a space charge region in the drift region 100 to enable a more positive voltage at the second load terminal structure 12 with respect to the first load terminal structure 11, referred to herein as a forward voltage, with no load current flowing between the first load terminal 11 and the second load terminal 12 except for small leakage currents.

[0089] To switch the semiconductor device 1 from the conducting state to the off-state, a voltage within a second range, which is different from the first range, may be applied between the first control electrode 131 and the first load terminal structure 11, such that the load current path in the first channel region 1012 is cut off. For example, the second range may range from, for example, 1 V to a specific negative voltage value, e.g., -3 V, if the load current path to be cut off in the first channel region 1012 is an electron current path. Accordingly, the second range may range from, for example, -1 V to a specific positive voltage value, e.g., +3 V, if the load current path to be cut off in the first channel region 1012 is a hole current path.According to one embodiment, the semiconductor device 1 is configured to be switched from the conducting state to the off-state if a voltage applied between the first control electrode 131 and the first load terminal structure 11 causes an electric field within a second range, e.g., within a range of +3 MV / cm to -10 MV / cm, or within a range of 2 MV / cm to -6 MV / cm, or within a range of 1 MV / cm to -4 MV / cm, wherein the electric field is present within the isolation structure 133 located between the first mesa 101 and the first control electrode 131. The same voltage, or a different voltage in the second range, or a still different voltage may also be applied between the second control electrode 132 and the first load terminal structure 11.Then, an accumulation channel of mobile charge carriers of the second conductivity type can be induced in the second channel region 1022. Furthermore, in one embodiment, the second channel region 1022 forms a conductive connection to the first load connection structure 11 due to dopants of the second conductivity type, if the same voltage or a different voltage in the second region or a still different voltage can also be applied between the second control electrode 132 and the first load connection structure 11. In this embodiment, the accumulation channel of mobile charge carriers of the second conductivity type is not necessary for current transport. For example, the accumulation channel can promote a movement of the second charge carriers of the second conductivity type out of the semiconductor body 10 toward the first load connection structure 11.This can contribute to a rapid reduction of the total charge carrier concentration in the semiconductor body 10 during switching off of the semiconductor device 1.

[0090] To switch the semiconductor device 1 from the off-state to the conducting state, a voltage may be applied within the first region between the first control electrode 131 and the first load terminal structure 11, as described above. A current path for mobile charge carriers of the first conductivity type may then be induced in the first channel region 1012 by forming a conductive channel, e.g., by forming an inversion channel. The conductive channel may extend over the entire first channel region 1012 along the vertical direction Z. In one variant, the conductive channel may also extend over the entire first channel region 1012 along the first lateral direction X and / or the second lateral direction Y.At the same time, the first channel region 1012 may be completely depleted of mobile charge carriers of the second conductivity type due to the voltage lying within the first range, such that a flow of mobile charge carriers of the second conductivity through the first channel region 1012 between the semiconductor body 10 and the first load connection structure 11 is greatly reduced or prevented. The same voltage or a different voltage in the first range or a still different voltage may be further applied between the second control electrode 132 and the first load connection structure 11. The second channel region 1022 may then be completely depleted of mobile charge carriers of the second conductivity type, such that a flow of mobile charge carriers of the second conductivity through the second channel region 1022 between the semiconductor body 10 and the first load connection structure 11 is reduced or prevented.

[0091] The semiconductor body 10 may further comprise a third connection region 104 electrically connected to the second load connection structure 12 and coupled to the drift region 100. The third connection region 104 may be a third semiconductor connection region. For example, the third connection region 104 comprises a first emitter of the second conductivity type electrically connected to the second load connection structure 12 and / or a second emitter with dopants of the first conductivity type electrically connected to the second load connection structure 12, e.g., so-called n-type short circuits (if the first conductivity type is n) to implement reverse conductivity of the semiconductor device 1.

[0092] Furthermore, the third terminal region 104 may comprise a buffer region, also known as a field stop region, which may be of the same conductivity type as the drift region 100, e.g., of the first conductivity type, but may have a higher dopant concentration compared to the dopant concentration of the drift region 100. However, because these exemplary configurations of the third terminal region 104 are generally known to a person skilled in the art, particularly in the context of IGBT configurations, the first emitter, the second emitter, and the buffer region are neither in Fig. 3A-B illustrates and explains in more detail here.

[0093] As explained above, the semiconductor body 10 may be configured to conduct the entire load current 15 in the forward direction between the load terminal structures 11 and 12. For this purpose, the first control electrode 131 may be configured, in response to receiving the first control signal, to induce an inversion channel for conducting a portion of the first load current 151 within the first channel region 1012. For example, the semiconductor device 1 may be configured, in response to receiving the first control signal, to completely deplete the first channel region 1012 of mobile charge carriers of the second conductivity type. Accordingly, the semiconductor device 1 may be further configured, in response to receiving the second control signal, to completely deplete the second channel region 1022 of mobile charge carriers of the second conductivity type.

[0094] According to one embodiment, the first load terminal structure 11 is an emitter terminal (also referred to as a "source terminal"), the second load terminal structure 12 is a collector terminal (also referred to as a "drain terminal"), and the control electrode structure 13 is electrically connected to a gate terminal structure (not illustrated). For example, the first terminal region 1011 of the first mesa 101 may therefore be a source region, e.g., a semiconductor source region.

[0095] For example, in order to set the semiconductor device 1 into a conducting state during which the entire load current 15 between the load terminal structures 11, 12 can be conducted in a forward direction, the first control electrode 131 can be supplied with the first control signal having a voltage within a first range, such that an inversion channel is induced within a first channel region 1012. For example, the voltage is applied between the first control electrode 131 and the first load terminal structure 11. In one embodiment, the electrical potential of the first control electrode 131 is greater than the electrical potential of the first load terminal structure 11 if the applied voltage is within the first range.

[0096] To put the semiconductor device 1 into an off-state in which a voltage applied between the second load terminal structure 12 and the first load terminal structure 11 can be blocked in the forward direction and a flow of the load current 15 in the forward direction is prevented, the first control electrode 131 can be supplied with the control signal having a voltage within the second range that is different from the first range, so that a depletion region is induced, e.g., at a junction between the first channel region 1012 and the drift region 100. For example, the voltage is applied between the first load terminal structure 11 and the first control electrode 131. In one embodiment, the electrical potential of the first control electrode 131 is equal to or lower than the electrical potential of the first load terminal structure 11 if the applied voltage is within the second range.

[0097] According to the foregoing, one embodiment of the operation and configuration of the semiconductor device 1 can be summarized as follows. The semiconductor device 1 can be configured to be set to the conducting state by providing the control signal with a voltage within the first range. In response to receiving such a control signal, the first cell portion 141 can be configured to induce an inversion channel within the first channel region 1012 such that the first load current 151 of first charge carriers of the first conductivity type can traverse the first mesa 101. At the same time, the first cell portion can be configured to completely deplete the first channel region 1012 of charge carriers of the second conductivity type and, accordingly, drastically reduce or prevent a flow of the second load current 152 within the first mesa 101.Furthermore, in response to receiving such a control signal, the second cell portion 142 may be configured to completely deplete the second channel region 1022 of charge carriers of the second conductivity type and accordingly prevent a flow of both the first load current 151 and the second load current 152 within the second mesa 102. Accordingly, during the conducting state, the total load current within the cell portions 141 and 142 may be at least dominated by, or even solely represented by, the first load current 151 because the second load current 152 within the cell portions 141 and 142 is substantially zero. To switch the semiconductor device 1 from the conducting state to the off-state, the control signal may be provided with a voltage within the second range, which is different from the first range.In response to receiving such a control signal, the semiconductor device 1 may be configured to cause a movement of mobile charge carriers out of the semiconductor body 10. For this purpose, the first cell portion 141 may be configured to cut off the first load current 151 within the first mesa 101 by dissolving the inversion channel. At the same time as or shortly before cutting off the first load current 151 within the first mesa 101, the second cell portion 142 may be configured to induce a conductive channel within the second channel region 1022, thereby enabling a flow of the second load current 152 within the second mesa.In fact, such a second load current 152 can be considered a charge carrier removal (or drain) current, since it causes the semiconductor body 10 to reduce the concentration of charge carriers of the second conductivity type or even to become depleted of second charge carriers of the second conductivity type. Accordingly, the total load current 15 within the cell portions 141 and 142, i.e., the total load current 15 in the vicinity of the first load terminal structure 11, may be dominated by, or even substantially represented by, the second load current 152 within the second cell portion 142 during turn-off.

[0098] Fig. 4 schematically illustrates exemplary distributions of charge carrier concentrations in the semiconductor body 10 of the semiconductor device 1 when in the conducting state, according to one or more embodiments. The dashed line exemplifies the distribution of the concentration (CC) of charge carriers of the first conductivity type, e.g., electrons, along the vertical direction Z, and the dotted line exemplifies the distribution of the concentration (CC) of charge carriers of the second conductivity type, e.g., holes, along the vertical direction Z. As illustrated, in the vicinity of the first load terminal structure 11, e.g., within the cell parts 141 and 142, the concentration of charge carriers of the first conductivity type may be higher than the concentration of charge carriers of the second conductivity type, e.g.,for reasons explained in the previous paragraph and because doping regions in cell parts 141 and 142 may contribute to the curves.

[0099] Along the extension of the semiconductor body 10 in the vertical direction Z, e.g., within the drift region 100, the concentration of charge carriers of the first conductivity type may be substantially equal to the concentration of charge carriers of the second conductivity type, e.g., due to the physical requirement of charge neutrality, which may be established within the electron-hole plasma inside the drift region 100.

[0100] In the vicinity of the second load connection structure 12, the concentration of charge carriers of the second conductivity type may be significantly higher compared to the concentration of charge carriers of the first conductivity type, e.g., because charge carriers of the first conductivity type may continuously move from the semiconductor body 10 to the second load connection structure 12, and wherein charge carriers of the second conductivity type may continuously be pumped into the drift region 100 from the first emitter, which may be contained within the third connection region 104 electrically connected to the second load connection structure 12, wherein the first emitter may comprise dopants of the second conductivity type. According to another embodiment, which is described in Fig. 4, in the vicinity of the second load terminal structure 12, the density of charge carriers of the first conductivity type may also be much higher in a region close to a doping region of the first conductivity type, e.g., to implement reverse conductivity of the semiconductor device 1, as previously indicated. Differences in the densities of charge carriers of the first and second conductivity types may occur in a region of a buffer or field stop region.

[0101] For example, the semiconductor device 1 may be configured to have within the semiconductor body 10, e.g., within the drift region 100, a total concentration of charge carriers greater than 10 16 cm -3 or even larger than 10 17 cm -3 or even larger than 2*10 17 cm -3Such a high concentration of charge carriers may make it possible to achieve a comparatively low on-state voltage during the conducting state, ie a voltage between the first load terminal structure 11 and the second load terminal structure 12 of less than 1 V, less than 0.9 V or even less than 0.8 V at a rated load current or at a load current density flowing through a horizontal cross-section of the semiconductor device of at least 100 A / cm 2and at approximately 20°C. The on-state voltage may be substantially caused by a pn junction in proximity to the second load terminal structure 12. Accordingly, the drop in the on-state voltage may be asymmetrically distributed along the distance between the first load terminal structure 11 and the second load terminal structure 12, e.g., due to the main voltage change occurring in proximity to the second load terminal structure 12 and a negligible voltage change occurring in proximity to the first load terminal structure 11. For example, if the semiconductor body is primarily based on silicon (Si), an on-state voltage of significantly less than 0.7 V may hardly be achieved.

[0102] With reference to Fig. 5A, some exemplary spatial dimensions of the first cell portion 141 and the second cell portion 142 will be explained. Before giving specific values, it should be understood that each cell 14 (including the first cell portion 141 and the second cell portion 142) may have either a stripe configuration or a needle configuration, as described with reference to Fig. 1A was declared.

[0103] In the first case (“strips”), as shown schematically in Fig. 5B (not to scale!), both the first mesa 101 and the second mesa 102 may have the shape of a fin, having a total lateral extent along one lateral direction (e.g., Y) that is at least a multiple of the total lateral extent in the other lateral direction (e.g., X). For example, the fin-shaped mesas 101 and 102 may extend substantially along the entire active cell array 16 in one lateral direction.

[0104] In the second case (“needle”), as shown schematically in Fig. 5C (not to scale!), both the first mesa 101 and the second mesa 102 may have the shape of a wire. For example, the mesas 101 and 102 may each have a circular or rectangular cross-section parallel to a horizontal plane and may each be completely surrounded by the insulation structure 133.

[0105] Accordingly, according to the schematic diagram in Fig. For example, in the embodiment illustrated in Figure 5A, cell portions 141 and 142 may have a needle configuration or a strip configuration. In another embodiment, the first cell portion 141 may have a strip configuration and the second cell portion 142 may have a needle configuration, or vice versa.

[0106] In one embodiment, the first connection region 1011 and the second connection region 1021 each extend from their respective contact with the first load connection structure 11 at the level Z0 (which may be 0 nm) along the vertical direction Z to a level Z12 and a level Z22, respectively, which may be within the range of 30 nm to 500 nm, within the range of 50 nm to 400 nm, or within the range of 50 nm to 300 nm, respectively. The levels Z12 and Z22 may be substantially identical to each other. Accordingly, the first connection region 1011 may have a total extension DZ13 along the vertical direction Z within the range of 30 nm to 500 nm, within the range of 50 nm to 400 nm, or within the range of 50 nm to 300 nm, and the second connection region 1021 may have a total extension DZ23 in the vertical direction substantially identical to DZ13.

[0107] Furthermore, the first channel region 1012 and the second channel region 1022 may each extend from the contact with the first terminal region 1011 at the plane Z12 and from the contact with the second terminal region 1021 at the plane Z22, respectively, along the vertical direction Z to a plane Z13 and to a plane Z23, respectively, which may each be within the range of 50 nm to 700 nm, within the range of 60 nm to 550 nm, or within the range of 100 nm to 400 nm. The planes Z13 and Z23 may be identical to each other. Accordingly, the first channel region 1012 along the vertical direction Z may have a total extension DZ14 within the range of 50 nm to 700 nm, within the range of 80 nm to 550 nm, or within the range of 150 nm to 400 nm, and the second channel region 1022 may have a total extension DZ24 in the vertical direction substantially identical to DZ14.

[0108] The first control electrode 131 and the second control electrode 132 may be spaced apart from the first load connection structure 11 along the vertical direction Z by a distance DZ11 and DZ21, respectively, which may be equal to DZ11. Accordingly, the distances DZ11 and DZ21 may be identical to the thickness of the portion of the isolation structure 133 that isolates the control electrodes 131 and 132 from the first load connection structure 11 along the vertical direction Z. Both DZ11 and DZ21 may be within the range of 10 nm to 490 nm, within the range of 20 nm to 180 nm, or within the range of 30 nm to 250 nm. In other words, the first control electrode 131 may have a proximal end located at a plane Z11 corresponding to DZ11 in magnitude, and the second control electrode 132 may have a proximal end located at a plane Z11 corresponding to DZ21 in magnitude.

[0109] In one embodiment, the first control electrode 131 may have a total extension DZ15 along the vertical direction Z that is greater than the total extension DZ14 of the first channel region 1012, and may be arranged to have a common extension area along the vertical direction Z with the first channel region 1012 that is greater than 100% of the total extension DZ14 of the first channel region 1012, as schematically shown in Fig. 5A. Accordingly, the total extension DZ15 of the first control electrode 131 may be at least a factor of 1.1 of DZ14, a factor of 1.3 of DZ14, or even a factor of 1.5 of DZ14. Opposite the vertical direction Z, there may be an overlap DZ12 within the range from 10 nm to 490 nm, within the range from 20 nm to 380 nm, or within the range from 50 nm to 250 nm, which at the same time may be a common extension range with the first connection region 1011. The first control electrode 131 may have an overlap DZ16 in the vertical direction Z within the range of 10 nm to 490 nm, within the range of 20 nm to 380 nm, or within the range of 30 nm to 250 nm, which at the same time may be a common extension region with the drift region 100.Furthermore, the first control electrode 131 may have a distal end at a plane Z14 that is spaced from a distal end of the isolation structure 133 at a plane Z15 by a distance DZ17 that may be within the range of 60 nm to 1200 nm, within the range of 100 nm to 900 nm, or within the range of 200 nm to 650 nm.

[0110] What was stated above with respect to the extent and arrangement of the first control electrode 131 along the vertical direction Z may equally apply to the second control electrode 132 and its relative position with respect to the second channel region 1022. Accordingly, the values ​​of DZ25 may be within the same range as DZ15, the values ​​of DZ21 may be within the same range as DZ11, the values ​​of DZ22 may be within the same range as DZ12, and the values ​​of DZ26 may be within the same range as DZ16. Furthermore, the second control electrode 132 may have a distal end at plane Z24 that is spaced from a distal end of the isolation structure 133 at plane Z25 by a distance DZ27, wherein the values ​​of DZ27 may be within the same range as DZ17.

[0111] The upper and lower vertical ends of the first control electrode 131 (Z11, Z14) and the second control electrode 132 (Z21, Z24) may be specified only in the vicinity of or adjacent to the first channel region 1012 and the second channel region 1022, as indicated above. Further in the first lateral direction X, away from the first channel region 1012 or the second channel region 1022, the upper and / or lower vertical ends of the control electrodes 131, 132 may differ. The upper ends (compare reference numeral Z11' in Fig. 6) can, for example, even be located above position Z0 or below position Z0. The lower ends Z14 and Z24 can, for example, even be located below position Z15 or above position Z15. It is clear that, regardless of the chosen spatial dimensions, the first control electrode 131 and the second control electrode 132 are still electrically isolated from the first load connection structure 11 and the drift region 100 according to one embodiment.

[0112] Along the first lateral direction X, the first control electrode 131 may be spaced from the first channel region 1021 by a distance DX12, which may be within the range of 1 nm to 100 nm, within the range of 2 nm to 50 nm, or within the range of 3 nm to 20 nm. The distance DX12 may be identical to a thickness of the isolation structure 133 that isolates the first control electrode 131 from the first mesa 101 along the first lateral direction X. Accordingly, along the first lateral direction X, the second control electrode 132 may be spaced from the second channel region 1022 by a distance DX22, which may be within the range of 1 nm to 100 nm, within the range of 2 nm to 50 nm, or within the range of 3 nm to 20 nm. The distance DX22 may be identical to a thickness of the isolation structure 133 that isolates the second control electrode 132 from the second mesa 102 along the first lateral direction X.

[0113] The thickness DX11 of the first control electrode 131 along the first lateral direction X may be within the range of 10 nm to 10,000 nm, within the range of 50 nm to 7,000 nm, or within the range of 100 nm to 5,000 nm. The thickness DX21 of the second control electrode 132 along the first lateral direction X may be in the same range as the thickness DX11 or in another of the ranges described above with respect to the thickness DX11. As mentioned above, the control electrodes 131 and 132 may be located in contrast to the exemplary schematic representation in Fig. 5A according to one or more embodiments are in contact with each other (ie, in Fig. 5A, X16 would be equal to X21), forming a common control electrode that can be used to control both the first cell portion 141 and the second cell portion 142.

[0114] In the embodiment according to Fig. 5A, the cells 14 may have a needle configuration or a strip configuration, as explained above. For example, in the first case (“needle”), the cells 14 may each have a radially symmetric structure, for example, and the portion of the vertical cross section may be Fig. 5A actually shows only a single first control electrode 131, which, for example, has a cylindrical shape, and a single second control electrode 132, which, for example, also has a cylindrical shape, covering the first mesa 101 and the second mesa 102, respectively. In this case, both the first lateral direction X and the second lateral direction Y denote a radial direction. Furthermore, the needle cells could also have a rectangular cross-section, e.g., with rounded corners, or an elliptical cross-section parallel to the YX plane. In the second case (“strip”), the first cell part 141 can comprise a monolithic first control electrode 131 flanking the first mesa 101 only on one lateral side, and correspondingly, the second cell part 142 can also comprise a monolithic second control electrode 131 flanking the second mesa 102 only on one lateral side. In another embodiment, as in Fig. 5A, the first control electrode 131 may be a multi-part, e.g., a two-part, first electrode 131 and the second control electrode 132 may also be a multi-part, e.g., a two-part, second electrode 132. For example, according to the embodiment of Fig. 5A, if the cells 14 have a stripe configuration, the first control electrode 131 may be a two-part first control electrode 131 arranged mirror-symmetrically along the first lateral direction X with respect to the first mesa 101, and the second control electrode 132 may be a two-part second control electrode 132 arranged mirror-symmetrically along the first lateral direction X with respect to the second mesa 101. Accordingly, what was stated above with respect to the dimensions DX11, DX21 and DX12, DX22 may equally apply to the dimensions DX14, DX24 and DX15, DX25 shown in Fig. 5A apply.

[0115] As explained above, the spatial dimensions of the mesas 101 and 102 and their components may each be limited by the isolation structure 133. The total extension Z15 of both the first mesa 101 and the second mesa 102 parallel to the path of the first load current 151 and the second load current 152, respectively, which may be parallel to the vertical direction Z, may be at least a multiple of the respective total extensions DX13, DX23 perpendicular to the load current paths, e.g., in the first lateral direction X and / or the second lateral direction Y.

[0116] For example, the width DX13 of the first channel region 1012 of the first mesa 101 in a direction perpendicular to the course of the first load current 151 within the first mesa 101, e.g., in a direction perpendicular to the vertical direction Z, e.g., in the first lateral direction X, may be less than 100 nm, less than 60 nm, or even less than 40 nm over a distance in a direction of the first load current 151 within the first mesa 101, e.g., along a direction parallel to the vertical direction Z, which is at least three times DX13. For example, the first channel region 1012 may have a width of DX13 that is less than 100 nm along at least 300 nm in the vertical direction Z, a width of DX13 that is less than 60 nm along at least 180 nm in the vertical direction Z, or a width of DX13 that is less than 40 nm along at least 120 nm in the vertical direction Z. Fig. 5A shows the first mesa 101 with substantially parallel sidewalls. In contrast, the first mesa 101 may also have partially or fully tapered sidewalls, e.g., with a lateral width DX13 that is up to 50% larger at the vertical position Z13 than DX13 at the vertical position Z12. The extension of the first channel region 1012 along the vertical direction Z DZ14 may be related to the larger or smaller value of DX13.

[0117] Analogously, the width DX23 of the second channel region 1022 of the second mesa 102 in a direction perpendicular to the course of the second load current 152 within the second mesa 102, e.g., in a direction perpendicular to the vertical direction Z, e.g., in the first lateral direction X, may be less than 100 nm, less than 60 nm, or even less than 40 nm over a distance in a direction of the second load current 152 within the second mesa 102, e.g., along a direction parallel to the vertical direction Z, which is at least three times DX23. For example, the second channel region 1022 may have a width of DX23 that is less than 100 nm along at least 300 nm in the vertical direction Z, a width of DX23 that is less than 60 nm along at least 180 nm in the vertical direction Z, or a width of DX23 that is less than 40 nm along at least 120 nm in the vertical direction Z. Fig. 5A shows the second mesa 102 with substantially parallel sidewalls. In contrast, the second mesa 102 may also have partially or fully tapered sidewalls, e.g., with a lateral width DX23 that is up to 50% larger at the vertical position Z23 than DX23 at the vertical position Z22. The extension of the second channel region 1022 along the vertical direction Z DZ24 may be related to the larger or smaller value of DX23.

[0118] It is understood that the isolation structure 133, in contrast to the schematic representation in Fig. 5A does not necessarily have to extend at least as far in the vertical direction Z as the first control electrode 131 along the entire distance DX30 between the first mesa 101 and the second mesa 102, but may extend less in the vertical direction Z, e.g. in the same range as the entire extension of the first connection region 1011 or the entire extension of the second connection region 1021 in the vertical direction Z (DZ13, DZ23 in Fig. 5A), e.g., along at least 80% of the distance DX30 between the first mesa 101 and the second mesa 102.

[0119] The distance between the first cell part 141 and the second cell part 142 along the first lateral direction X or the second lateral direction Y, hereinafter also referred to as “intracell pitch” DX40, can be within the range of 100 nm to 15000 nm, within the range of 300 nm to 10000 nm or within the range of 500 nm to 8000 nm.

[0120] In one embodiment, the first mesa 101 is dimensioned according to the following equation (1), which is presented below: DX13≤2*Wmax; Wmax=4*ε*k*T*ln(NAni)q2*NA

[0121] Accordingly, in one embodiment, DX13, i.e., the width of the first channel region 1011, is equal to or less than twice a maximum width Wmax along at least 80%, at least 90%, or along at least 95%, or even along at least 99% of the total extension of the first mesa 101 in the vertical direction Z, wherein the maximum width Wmax is determined according to equation (1) presented above, where: ε dielectric constant of the material of the first channel region 1012; k Boltzmann constant; T temperature; In denotes the natural logarithm; N A Dopant concentration of the material of the first channel region 1012; n i intrinsic charge carrier concentration; and q elementary charge.

[0122] In one embodiment, the second mesa 102 is dimensioned accordingly, ie DX23 is equal to or smaller than twice a maximum width Wmax along at least 80%, at least 90% or along at least 95% or even along at least 99% of the total extension of the first mesa 101 in the vertical direction Z, wherein the maximum width Wmax is determined with values ​​that apply to the second channel region 1022.

[0123] In another embodiment, the second mesa 102 may have a width DX23 that is significantly greater than the width DX13 of the first mesa 101, e.g., at least twice as large or even at least ten times larger than DX13.

[0124] For example, DX13 (and optionally DX23) is within a range of 15 nm to 100 nm, where both the dopant concentration of the first channel region 1012 and the dopant concentration of the second channel region 1022 are greater than 8*10 18 cm -3are.

[0125] Accordingly, in one embodiment, each of the first connection region 1011, the first channel region 1012, the second connection region 1021, and the second channel region 1022 may accordingly represent a nanometer-scale structure having a spatial dimension in the first lateral direction X and / or the second lateral direction Y and / or the vertical direction Z of less than 100 nm. In one embodiment, the at least one direction along which the respective region has an extension of less than 100 nm is perpendicular to the direction of the applicable load current conducted within the respective region.

[0126] Reference is now made to the embodiments of the power semiconductor device 1 shown in Fig. 6 and Fig. 7A are illustrated schematically and by way of example:

[0127] The power semiconductor device 1 comprises the semiconductor body 10, which is coupled to the first load connection structure 11 and the second load connection structure 12, as explained above. The semiconductor body 10 is configured to conduct the load current (see reference numeral 15 in the previous drawings) and comprises the drift region 100 of the first conductivity type, as explained above. The power semiconductor device 1 includes the plurality of cells 14. The cells 14 may be configured identically, and a portion of a cell 14 is in Fig. 6. Accordingly, each cell 14 comprises the first mesa 101 contained in the first cell portion 141, wherein the first mesa 101 includes the first connection region of the first conductivity type 1011 electrically connected to the first load connection structure 11, and the first channel region 1012 coupled to the drift region 100, wherein optionally the first mesa 101 has a total extension (compare reference numeral DX13) of less than 100 nm in the first lateral direction X perpendicular to the vertical direction Z of the load current portion within the first mesa 101, as explained above. For example, a first contact plug 111 may be used to establish an electrical connection between the first load connection structure 11 and the first connection region 1011.For example, the insulation structure 133 may be at least partially covered with a liner 113 in the area where the first contact plug 111 is to be provided, as illustrated.

[0128] Each cell 14 further comprises the second mesa 102 contained in the second cell portion 142, wherein the second mesa 102 includes the second terminal region 1021 of the second conductivity type and electrically connected to the first load terminal structure 11, and the second channel region 1022 coupled to the drift region 100, as explained above. For example, a second contact plug 112 may be used to establish an electrical connection between the first load terminal structure 11 and the second terminal region 1021. For example, the insulation structure 133 may be partially covered with the liner 113 in the region where the second contact plug 112 is to be provided, as illustrated.

[0129] Each cell 14 further comprises the trench structure 17, including the control electrode structure 13 (e.g., implemented as the common / first control electrode 131) for controlling the load current at least by means of the inversion channel in the first channel region 1012, as explained above.

[0130] According to one embodiment, each cell 14 further comprises a guiding zone 1023 of the second conductivity type arranged below the second channel region 1022, wherein the guiding zone 1023 laterally overlaps with the second mesa 102 and extends laterally towards the first mesa 101 while not laterally overlapping therewith, as shown in both Fig. 6 as well as Fig. 7A is illustrated.

[0131] For example, the guidance zone 1023 may completely overlap with the second mesa 102, e.g., along both the first lateral direction X and the second lateral direction Y.

[0132] In one embodiment, it may also be possible for the guiding zone 1023 to at least partially laterally overlap with the first mesa 101, e.g., in a portion of the edge termination zone 18 and / or within a portion of the active cell array 16. In one embodiment, there is no lateral overlap between the guiding zone 1023 and the first mesas 101 for at least 80% of the active cell array 16. In the remaining 20% ​​of the active cell array 16, there may (or may not) be a lateral overlap between the guiding zone 1023 and the first mesas 101. For example, the ratio between the portions of the active cell field may not be 80% to 20%, but may be 90% to 10% or, for example, 95% to 5% (i.e., in 95% of the active cell field there is no lateral overlap between the guide zone 1023 and the first mesas 101).

[0133] Furthermore, in one embodiment, there is a complete lateral overlap between the guiding zone 1023 and the second mesas 102 for at least 80% of the active cell array 16. In the remaining 20% ​​of the active cell array 16, there may (or may not) be a lateral overlap between the guiding zone 1023 and the second mesas 102. For example, the ratio between the active cell array portions may not be 80% to 20%, but may be, for example, 90% to 10% or 95% to 5% (i.e., in 95% of the active cell array, there is a lateral overlap between the guiding zone 1023 and the second mesas 102).

[0134] Furthermore, in one embodiment, for at least 80% of the active cell array 16, there is a lateral overlap between the guiding zone 1023 and at least 30% of the total extents of the first control electrodes 131 in the first lateral extent X. In the remaining 20% ​​of the active cell array 16, there may (or may not) be a lateral overlap between the guiding zone 1023 and the first control electrodes 131. For example, the ratio between the active cell array portions may not be 80% to 20%, but may be, for example, 90% to 10% or 95% to 5% (i.e., in 95% of the active cell array, there is no lateral overlap between the guiding zone 1023 and the first mesa 101).

[0135] In an embodiment as in Fig. 6, the guiding zone 1023 is arranged below the second channel region 1022 while being spatially offset from both the first and second channel regions 1012, 1022 along the vertical direction Z. Additionally or alternatively, each cell 14 may, in an embodiment as shown in Fig. 7A, further comprise a barrier zone 105 of the first conductivity type arranged between the guiding zone 1023 and the trench structure 17, wherein the barrier zone 105 optionally has a dopant concentration at least twice as large as the dopant concentration of the drift region 100.

[0136] The guide zone 1023 may have a dopant concentration of at least 10 15 cm -3 , of at least 10 16 cm -3 or at least 2*10 17 cm -3In one embodiment, the dopant concentration of the guiding zone 1023 is at least as large as a total concentration of charge carriers present in the drift region 100 during the conducting state of the device 1, e.g., at least 2*10 17 cm -3The dopant concentration of the guiding zone 1023 may, for example, vary along the vertical direction Z and / or the first lateral direction X. For example, a maximum dopant concentration may be present within an inner part (with respect to the vertical direction Z), e.g., within an upper inner part. Furthermore, the dopant concentration may decrease along the direction toward the first mesa 101. The dopant concentration may be asymmetric with respect to the vertical direction Z and may, for example, have a deeper trailing characteristic in the direction toward the second load terminal structure 12 compared to the direction toward the first load terminal structure 11; i.e.,the decrease in the dopant concentration of the guiding zone 1023 may be present for a longer distance toward the second load connection structure 12 compared to a decrease in the dopant concentration of the guiding zone 1023 along a distance toward the first load connection structure 11.

[0137] For example, the guiding zone 1023 is neither electrically connected to the first load connection structure 11 nor to the second load connection structure 12. For example, the guiding zone 1023 is separated from the second load connection structure 12 by at least a portion of the drift region 100.

[0138] Furthermore, the guiding zone 1023 may be separated from the second channel region 1022 by means of a semiconductor part of the first conductivity type, e.g., by a portion of the drift region 100 and / or a portion of the barrier zone 105.

[0139] In one embodiment, a minimum distance along the vertical direction Z between the second channel region 1022 and the guiding zone 1023 is at least 50 nm, at least 100 nm, or at least 250 nm.

[0140] In one embodiment, a maximum distance along the vertical direction Z between the second channel region 1022 and the guiding zone 1023 is at most 3000 nm, at most 1500 nm, or at most 500 nm.

[0141] Therefore, the guide zone 1023 may be separated from the second channel region 1022 by a distance between the minimum distance and the maximum distance mentioned above.

[0142] Furthermore, a minimum distance DXmin along the first lateral direction X between the guide zone 1023 and the first mesa 101 is at least 100 nm. However, according to one embodiment, this distance is not greater than 1000 nm or not greater than 500 nm.

[0143] However, as indicated above, although the guiding zones 1023 within the active cell array 16 are typically separated from the second channel regions 1022 by semiconductor portions of the first conductivity type, it may be appropriate to provide at least one (not illustrated) path of the second conductivity type between one of the guiding zones and the first load terminal structure 11 within the edge termination zone 18.

[0144] The barrier zone 105 may laterally overlap (partially or completely) with both the first mesa 101 and the second mesa 102. Accordingly, the channel region 1012 of the first mesa 101 and the channel region 1022 of the second mesa 102 may be interconnected within the semiconductor body 10 by means of: a) a first path of the first conductivity type, e.g. formed by means of the barrier zone 105 and / or by means of a portion of the drift region 100; and b) a second path with an npn configuration, which is formed by the barrier zone 105 (or a portion of the drift region 100) and by the guide zone 1023 (which forms the p-part of the npn configuration of the second path).

[0145] As in both Fig. 6 and 7A and explained above, the control electrode structure 13 may include the first control electrode 131 within the trench structure 17. The first control electrode 131 may be configured in such a way that it can control both the inversion channel within the first channel region 1012 and the accumulation channel within the second channel region 1022. If the first control electrode 131 is configured in such a way, it may therefore also be referred to as a common control electrode 131.

[0146] In one embodiment, the guiding zone 1023 laterally overlaps with the first (common) control electrode 131 along the first lateral direction X for at least 60% or for at least 80% of the total lateral extent of the first control electrode 131 in this first lateral direction X. Accordingly, a significant lateral overlap is formed between the first (common) control electrode 131 and the guiding zone 1023. For example, the guiding zone 1023 may thereby be configured to shield the first (common) control electrode 131 from an electrical potential within the drift region 100, thereby reducing unwanted capacitive coupling. This may result in improved controllability of a switching operation.According to one embodiment, the first (common) control electrode 131 may simultaneously or alternatively have an unshielded lower portion that does not have a lateral overlap with the guiding zone 1023. e.g., such an unshielded region of the first (common) control electrode 131 is smaller than 40% or 20% of the total lateral extent of the first control extent of the first control electrode 131 in the first lateral direction X. According to another embodiment, the unshielded lower portion of the first control electrode 131 is shorter than 1000 nm or shorter than 500 nm in the first lateral direction. For example, the unshielded lower portion of the first control electrode 131 is the lower portion of the first control electrode 131 that is closest to the first mesa 101.

[0147] The trench structure 17, which houses the first (common) control electrode 131, may include a first trench sidewall 171 adjacent to the first mesa 101, a second trench sidewall 172 adjacent to the second mesa 102, and a trench bottom 175 between the first trench sidewall 171 and the second trench sidewall 172. The first (common) control electrode 131 may extend approximately from the first sidewall 171 to approximately the second trench sidewall 172, wherein the first (common) control electrode 131 does not contact either the first mesa 101 or the second mesa 102, but is electrically insulated from them by means of the isolation structure 133.

[0148] For example, the trench bottom 175 abuts either the drift region 100 or, if present, the barrier zone 105, which may have a significantly increased dopant concentration compared to the drift region dopant concentration.

[0149] For example, providing the barrier zone 105 may be appropriate if the first control electrode 131 extends substantially from the first trench sidewall 171 to the second trench sidewall 172, i.e., if the first control electrode 131 is the common control electrode for both the first mesa 101 and the second mesa 102. Then, an unwanted capacitive coupling between the semiconductor body 10 and the first (common) control electrode 131 may be avoided by means of the barrier zone 105 and may be even more effectively avoided by means of a barrier subzone 1052 (see more detailed explanation below). If, in another embodiment, the control electrode structure 13 includes separate control electrodes 131 and 132 for the first mesa 101 and the second mesa 102, and if, for example, the two control electrodes 131 and 132 are separated from each other by means of the isolation structure 133 (as exemplarily shown in Fig. 3A-B, Fig. 5A, Fig. 9 and Fig. 17), the barrier zone 105 can also be omitted.

[0150] In an embodiment as in Fig. 7B, a first thickness along the first lateral direction X of the isolation structure 133 between the first trench sidewall 171 and the first control electrode 131 is less than one half of a second thickness along the vertical direction Z of the isolation structure 133 between the trench bottom 175 and the first control electrode 131. Therefore, the isolation structure 133 may have a greater thickness at the trench bottom 175 compared to the region at the first trench sidewall 171. For example, in a transition sub-region 174 of the trench structure 17, the trench bottom 175 and the first trench sidewall 171 merge into one another, and the thickness of the isolation structure 133 increases, e.g., gradually, from the first thickness to the second thickness.

[0151] For example, the second thickness is even larger than twice the first thickness, e.g., at least three times as large or even larger than four times the first thickness.

[0152] According to one embodiment, the thickness of the insulation structure 133 along the entire extent of the first control electrode 131 along the first lateral direction X outside the transition sub-region 174 may be at least the second thickness. For example, the comparatively thick insulator (e.g., an oxide) at the trench bottom 175 may allow for reducing undesired capacitive coupling between the semiconductor body 10 and the first control electrode 131. It may further be appropriate to limit the second thickness; e.g., with regard to controllability, it may be appropriate to configure the second thickness no greater than 100 times the first thickness, e.g., less than 50 times, less than 20 times, or less than 10 times the first thickness.

[0153] It is understood that such a transitional sub-area 174 (e.g. as in Fig. 7B) also in the schematically shown Fig. 6 and that the transition sub-region 174 can also be implemented at a transition between the trench bottom 175 and the second trench sidewall 172.

[0154] For example, a gradual increase in the thickness of the insulation structure 133 in the transition sub-region(s) 174 may result in a more robust operating behavior of the power semiconductor device 1, since an unwanted influence of potential local increases in the electric field strength at or in the vicinity of the transition sub-region(s) 174 may be avoided.

[0155] In addition or alternatively to the transition subregion 174 described above, the first mesa 101 may have a mesa opening with a width at least twice as large as its entire extension (compare reference numeral DX13) in the first lateral direction X. For example, the width of the mesa opening of the first mesa 101 is defined by the distance in the first lateral direction X between two adjacent trench bottoms 175 of the trench structure 17. Accordingly, although the first mesa 101 may have its width along the first lateral direction X of no more than 100 nm in a portion of the first mesa 101 that completely overlaps with the first control electrode 131 along the vertical direction Z, such a maximum width at the mesa opening may be increased, e.g., by at least a factor of two.

[0156] For example, the mesa opening is formed by a corresponding curved profile of the insulation structure 133; e.g., a radius defining the mesa opening is at least three times, at least five times, or at least ten times the first thickness of the insulation structure 133 mentioned above.

[0157] According to one embodiment, the second mesa 102 may also have a corresponding mesa opening with a width at least twice as large as its entire extension (see reference numeral DX23) in the first lateral direction X. According to another embodiment, the second mesa 102 may also have an opening formed by a corresponding curved profile of the isolation structure 133; e.g., a radius defining the mesa opening is at least three times, at least five times, or at least ten times the first thickness of the isolation structure 133 mentioned above.

[0158] As already stated above, the barrier zone 105 may be provided between the guiding zone 1023 and the second channel region 1022. For example, the barrier zone 105 may comprise the barrier subzone 1052 in contact with the trench bottom 175, wherein the barrier subzone 1052 has a dopant concentration at least as large as the dopant concentration of the drift region 100. The dopant concentration of the barrier subzone 1052 may be greater than twice the dopant concentration of the drift region 100; e.g., the dopant concentration of the barrier subzone 1052 may be greater than 50 times, greater than 500 times, or 2000 times the dopant concentration of the drift region 100. For example, the dopant concentration of the barrier subzone 1052 may be at least 10 17 cm -3Furthermore, the barrier subzone 1052 may have a greater dopant concentration than the remaining part of the barrier zone 105, i.e., the part of the barrier zone 105 that is not the subzone 1052. Furthermore, the barrier subzone 1052 may be located in contact with the trench bottom 175 within the transition subregion 174. Accordingly, a semiconductor region of the first conductivity type with a significantly increased dopant concentration may be arranged in the transition subregion 174 of the trench structure 17.

[0159] For example, the barrier subzone 1052 is configured to prevent charge carriers of the second conductivity type from approaching the trench bottom 175. For example, this enables the reduction of undesired capacitive coupling between the first control electrode 131 and the semiconductor body 10.

[0160] In one embodiment, the barrier subzone 1052 has a thickness of less than 100 nm. Although the barrier zone 105 may laterally completely overlap with both the first mesa 101 and the second mesa 102, in one embodiment, the barrier subzone 1052 terminates at the transition subregions 174, ie, in the region where the trench bottom 175 merges with the first trench sidewall 171, and / or in the region where the trench bottom 175 merges with the second trench sidewall 172.

[0161] The barrier zone 105 may not only be arranged between the guide zone 1023 and the trench bottom 175, but may also extend further laterally, e.g., such that it laterally completely overlaps with the first mesa 101, as schematically shown in Fig. 7A and Fig. 7B. However, in one embodiment, the barrier zone 105 does not extend further along the vertical direction Z compared to the guide zone 1023.

[0162] For example, the barrier subzone 1052 covers the trench bottom 175. In another embodiment, the barrier subzone 1052 may even laterally overlap at least partially with the first mesa 101. Or, as illustrated in most of the drawings, at least the barrier zone 105 may laterally overlap at least partially with the first mesa 101. For example, by providing an increased dopant concentration of dopants of the first conductivity type in the region below the first mesa 101, charge carriers of the second conductivity type may be prevented from approaching the region directly below the first mesa 101.

[0163] For example, a change along the vertical direction Z between the barrier zone 105 and the guiding zone 1023 forms an upper pn junction 1051 and a change along the vertical direction Z between the guiding zone 1023 and the drift region 100 forms a lower pn junction 1001. For example, the distance along the vertical direction Z between the trench bottom 175 and the upper pn junction 1051 is at least 50 nm and not more than 500 nm, wherein depending on the configuration of the trench structure 17, such a distance may be considerably larger (compare, for example, Fig. 9). Therefore, in one embodiment, the guiding zone 1023 does not contact the trench structure 17, but is separated therefrom by a semiconductor region of the first conductivity type, e.g., by the barrier zone 105. Furthermore, the distance between the two pn junctions 1051 and 1001, i.e., the maximum thickness of the guiding zone 1023 along the vertical direction Z, may be within the range of 300 nm to 5000 nm. However, as will become apparent from the explanations below, such a maximum thickness may vary along the first lateral direction X. Regardless of whether the thickness varies or not, the maximum thickness of the guiding zone 1023 along the vertical direction Z may in any case be less than one-tenth of the total extension of the semiconductor body 10 along the vertical direction Z.

[0164] For example, the maximum thickness of the guide zone 1023 along the vertical direction Z may in any case be within the range of a factor of 0.5 to 10 of the total extent of the first mesa 101 along the vertical direction Z.

[0165] As explained above, the guiding zone 1023 may be separated from the second channel region 1022 by a semiconductor part of the first conductivity type, e.g., by a portion of the drift region 100 and / or a portion of the barrier region 105. The second channel region 1022 may form a pn junction with the semiconductor part of the first conductivity type, and the exemplary minimum distances and maximum distances between the guiding zone 1023 and the second channel region 1022 along the vertical direction Z, as mentioned above, may be the minimum distances and maximum distances between the pn junction 1051 and the pn junction formed between the second channel region 1022 and at least the semiconductor part of the first conductivity type (by a portion of the drift region 100 and / or a portion of the barrier region 105).

[0166] For example, the thickness of the guide zone 1023 can be adjusted with respect to the thickness shown schematically and by way of example in Fig. 15, the distance between the bottom of the trench structure 175 and the guiding region 1023 may decrease by a factor of at least two as it extends laterally toward the first mesa 101. Furthermore, the distance between the bottom of the trench structure 175 and the guiding region 1023 may remain substantially constant as the guiding region 1023 extends laterally toward the first mesa 101 and decreases in thickness. For example, the distance between the trench bottom 175 and the top pn junction 1051 does not change as the guiding region 1023 extends toward the first mesa 101. However, the distance between the two pn junctions 1051 and 1001 may decrease as the guiding region 1023 extends toward the first mesa 101.

[0167] For example, such a decrease in thickness forms a bulge-like portion of the guide zone 1023, which may enable better control of the lateral end of the guide zone 1023 in the lateral direction toward the first mesa 101, or an opening DXmin of the guide zone 1023 under the first mesa 101, as described above.

[0168] Such an exemplary shape of the guide zone 1023 is also possible if the control electrode structure 13 includes the separate first and second control electrodes 131 and 132, as in Fig. 17 is shown.

[0169] As already stated above, the guiding zone 1023 can provide improved controllability of switching operations of the power semiconductor device 1.

[0170] For example, a connection between the second channel region 1022 and the guiding zone 1023 exhibits a first electrical conductivity during a first operating state (e.g., the conducting state) of the power semiconductor device 1 and a second electrical conductivity during a second operating state (e.g., the off-state) of the power semiconductor device 1. The second electrical conductivity may be greater than the first electrical conductivity by a factor of at least ten. Accordingly, the current flow through the second channel region 1022, e.g., at least during a transition from the conducting state to the off-state of the power semiconductor device 1, may be greater by a factor of at least ten than the current flow through the second channel region 1022 during a conducting state of the power semiconductor device. For example, the dissipation of charge carriers of the second conductivity type (e.g.,of the second load current 152) shortly before and / or during a switch-off operation and / or during the blocking state of the power semiconductor device 1.

[0171] For example, during the transition from the first operating state to the second operating state, the electrical potential of the guiding zone 1023 deviates from the electrical potential of the first load terminal structure 11 by at most 3 V, by at most 1.5 V, or even by less than 0.5 V. In one embodiment, this voltage difference is caused along the path between the upper pn junction 1051 and the second channel region 1022.

[0172] Furthermore, in one example, during the off-state of the power semiconductor device 1 and / or during a transition from the conducting state to the off-state, the guiding zone 1023 is configured to guide charge carriers of the second conductivity type and / or an electrical potential that differs from the electrical potential of the second channel region 1022 by at least 50 mV and less than 3 V along a path between the first mesa 101 and the second mesa 102. This voltage range may also be selected differently depending on the application, e.g., it may be within 50 mV to 3 V, or within 100 mV to 1.5 V, or within 150 mV to 500 mV. Again, in one embodiment, this voltage difference is caused along the path between the upper pn junction 1051 and the second channel region 1022, which may be completely formed by a semiconductor part of the first conductivity type, e.g.,through a portion of the drift region 100 and / or a portion of the barrier zone 105, as explained above.

[0173] With regard to all embodiments described above, it is understood that both the first channel region 1012 and the second channel region 1022 may be of the second conductivity type. Accordingly, both the first channel region 1012 and the second channel region 1022 may form a respective pn junction with a semiconductor region of the first conductivity type arranged thereunder, e.g., either with the drift region 100 or with the barrier zone 105.

[0174] As indicated above, the control electrode structure 13 may comprise a separate control electrode for each cell portion 141 and 142. For example, as shown in Fig. 8A-D, respectively, the first control electrode 131 is associated with the first mesa 101, and the second control electrode 132 is associated with the second mesa 102. The control electrodes 131 and 132 may not only be arranged separately from each other, but may also differ from each other in a relative position to the associated mesa 101 / 102 and / or in a dimension and / or in a material. The first control electrode 131 is configured to control at least the first mesa 101, and the second control electrode 132 is configured to control at least the second mesa 102.

[0175] For example, according to the schematic in Fig. 8A, the control electrodes 131 and 132 are arranged separately from each other, but do not differ in terms of relative position with respect to the associated mesa 101 / 102. For example, this may result in a symmetrical arrangement of the first cell part 141 and the second cell part 142 within the cell. The control electrodes 131 and 132 may be separated from each other by means of the isolation structure 133. The guiding zone 1023 may, for example, completely overlap with the second control electrode 132 associated with the second mesa 102 and, for example, only partially overlap with the first control electrode 131 associated with the first mesa 101 in the first lateral direction X. If present, the barrier subzone 1052 may laterally overlap with the two control electrodes 131, 132 in the first lateral direction X.

[0176] As also stated above, both control electrodes 131, 132 can be supplied with the identical control signal; for example, the first control electrode 131 can be electrically connected to the second control electrode 132. In another embodiment, the control electrodes 131 and 132 are electrically isolated from each other and can therefore be supplied with individual control signals, e.g., a driver (not shown) is configured to supply the first control signal to the first control electrode 131 and a second control signal to the second control electrode 132. The latter variant can provide a more flexible control scheme, but also requires a corresponding driver configuration.

[0177] In a further embodiment, the first control electrode 131 and the second control electrode 132 can be connected to each other by means of a defined ohmic resistance. A single control signal can then be delivered to both electrodes, wherein such a single control signal can cause a dynamic voltage difference between the first control electrode 131 and the second control electrode 132 during switching and the same voltage at both electrodes during a static on-state (also referred to herein as a conducting state) and a static off-state (also referred to herein as a blocking state).

[0178] According to one embodiment, the second mesa 102 exhibits a larger total extension area along the first lateral direction X (i.e., a larger width) compared to the first mesa 101. This optional aspect is also described in Fig. 8A and Fig. 8C, wherein the width of the second mesas 102 may, for example, be greater than twice the width of the first mesa 101. According to another embodiment, and as schematically illustrated in Fig. 8D, the second mesa 102 may have a smaller total extension area along the first lateral direction X (i.e., a smaller width) compared to the first mesa 101. Optionally, the first mesa 101 may also have a contact doping part 1019, which is indicated by the dotted line in Fig. 8D is shown.

[0179] As in Fig. 8B-D, providing the separate control electrodes 131 and 132 may enable a design of the cell 14 according to an asymmetric design. For example, the first control electrode 131 or the second control electrode 132 may extend further along the vertical direction Z compared to the other control electrode. For example, this may allow the first mesa 101 to have a different overall extension along the vertical direction Z compared to the second mesa 102, e.g., a shorter (compare Fig. 8A).

[0180] For example, the control electrode that is arranged deeper compared to the other control electrode may have a larger overall extent along the first lateral direction X. For example, the barrier subzone 1052, if present, laterally overlaps only with the control electrode that is arranged deeper than the other. Forming the trench 17 for the first control electrode 131 and the second control electrode 132 (with, e.g., different spatial configurations) may include one or more dry etching processes (e.g., RIE: Reactive Ion Etch), wherein the etching speed in the vertical direction Z may depend on the opening of a mask that defines the width of the trench 17. Accordingly, openings of different widths may result in trenches etched to different depths, with larger mask openings leading to deeper trenches, as shown in Fig. 8B-C is shown.

[0181] According to the schematic and exemplary in Fig. 11A-B, the trench structure 17 may further include a source electrode 1150 that is electrically isolated from the control electrode structure 13 (e.g., from both the first control electrode 131 and the second control electrode 132) and electrically connected to the first load connection structure 11 by means of a further contact plug 115. As shown in Fig. 11A, the further plug 115 may form part of the source electrode 1150. For example, the source electrode 1150 is implemented as a trench electrode. For example, it may be arranged between the first control electrode 131 and the second control electrode 132. In one embodiment, the source electrode 1150 laterally overlaps with the guiding zone 1023, wherein the isolation structure 133 may have a minimum thickness dZZ of at least 50 nm in a region where such an overlap exists.

[0182] For example, the distance between the source electrode 115 and the trench bottom 175 is greater than the distance between the first control electrode 131 and the trench bottom 175. In one embodiment, the source electrode 115 laterally overlaps along its entire extent with the guiding zone 1023 in the first lateral direction X. If present, the source electrode 115 may further laterally overlap along its entire extent with the barrier zone 105 in the first lateral direction X or, if present, with the barrier sub-zone 1052 in the first lateral direction X.

[0183] In one embodiment, a trench electrode structure as shown in Fig. 11B, the isolation structure 133 may be laterally structured to obtain the first control electrode 131, the control electrode 132 (both having the functionalities as described above), and the source electrode 1150, which may be electrically connected to the first load connection structure 11 (compare contact plug 115). For example, the isolation structure 133 may have the minimum thickness dZZ between the source electrode 1150 and the trench bottom 175 of at least twice the thickness, or three times the thickness, or four times the thickness of the isolation structure 133 in the first lateral direction between one of the first control electrode 131 (or the second control electrode 132) and the first mesa 101 (or the second mesa 102); e.g., at least twice the above-mentioned first thickness.

[0184] In yet another embodiment, the electrode 1150 is not electrically connected to the first load connection structure 11, but to a different electrical potential, or the electrode 1150 is electrically potential-free.

[0185] According to one embodiment, each cell 14 may include more than one first mesa 101 and / or more than one second mesa 102. For example, with reference to Fig. 12, the number of second mesas 102 contained in each cell 14 may be greater than the number of first mesas 101. For example, each cell 14 comprises only one first mesa 101 and two or more second mesas 102. For example, in such a case, the guide zone 1023 overlaps laterally along the first lateral direction X with each of the second mesas 102, as in Fig. 11. Furthermore, the barrier zone 105, if present, may comprise more than one barrier subzone 1052, e.g., below each trench bottom 175. For example, no lateral overlap is formed between the barrier subzones 1052 and the first and second mesas 101, 102.

[0186] For example, the ratio between the number of first mesas 101 and the number of second mesas 102 can be selected depending on the desired switching behavior. If, for example, a faster turn-off process is desired, the number of second mesas 102 can be increased.

[0187] To control the second mesa 102, the separate second control electrode 132 may be provided within the trench structure 17. However, as explained above, it should be noted that the second control electrode 132 does not necessarily have to be electrically isolated from the first control electrode 131.

[0188] The example in Fig. 12 shows the additional second mesa 102, which is controlled from one side by the first control electrode 131 and from the other side by the second control electrode 132. The additional second mesa 102 may (if the control electrodes 131 and 132 are configured differently and / or supplied with different control signals) have a different control characteristic than the second mesa 102, which is controlled exclusively by means of two second control electrodes 132 (one on each side). However, as indicated by the dashed line, the (common) control electrode 131 on the left side of the additional second mesa 102 could be separated into the first control electrode 131 for controlling the first mesa 101 and the second control electrode 132 for controlling the additional second mesa 102 in the same way as the second mesa 102. The control electrode separation can be achieved at least by providing a dummy mesa, as described with reference to Fig. 13-14 is explained in more detail.

[0189] However, as explained above, operation of the power semiconductor device can still be controlled by a single control signal delivered to the control electrode structure 13, regardless of the final spatial separation of the control electrodes 131, 132. For example, the second control electrode 132 can be electrically connected to the first control electrode 131 or coupled thereto by means of a defined ohmic resistance.

[0190] According to one embodiment, each cell 14 may comprise a third cell portion 143, e.g., between the first cell portion 141 and the second cell portion 142, as shown in Fig. 13. For example, the third cell portion 143 may include a third mesa 103. The third mesa 103 may be laterally delimited by third trench sidewalls 173 of the trench structure 17. The third mesa 103 may, for example, have the same spatial dimensions as the first mesa 101 or the second mesa 102. For example, the third mesa 103 is a dummy mesa, i.e., a mesa configured not to conduct any load current or any portion thereof. For this purpose, the third mesa 103 is, for example, not electrically connected to the first load terminal structure 11. As shown, no contact plug is provided that would establish an electrical connection between the third mesa 103 and the first load terminal structure 11. Additionally or alternatively, a transition between the third mesa 103 and the first load terminal structure 11 may be configured not to provide a conductive path for a load current portion; e.g., B.Instead, the transition between the third mesa 103 and the first load connection structure 11 may be configured to provide electrical isolation.

[0191] For example, the third mesa 103 is completely filled with a semiconductor material of the first or second conductivity type. If present, the barrier zone 105 may extend into the third mesa 103, as shown in Fig. 13 is illustrated.

[0192] As a dummy mesa, there is no need to control the third mesa 103. Nevertheless, the control electrode structure 13 may also extend into the vicinity of the third mesa 103, e.g., for process consistency and / or symmetry reasons, e.g., by means of one or more additional third electrodes 134, 134' or (as indicated by the dotted line) through a portion of a respective first (common) control electrode 131. Therefore, for example, each cell 14 may comprise two first control electrodes 131, one of which is associated with both the first mesa 101 and the third mesa 103, and the other is associated with both the second mesa 102 and the third mesa 103. The third electrodes 134, 134' may alternatively be electrically connected to the first control electrodes 131 and / or the second control electrodes 132 and / or the first load connection structure 11.

[0193] Additionally or alternatively, the third mesa 103 can be used to separate the control electrode structure 13, e.g., into the first control electrode 131 and the second control electrode 132, which can also be described with reference to Fig. 14 is explained in more detail.

[0194] For example, the guidance zone 1023 also overlaps laterally with the third mesa 103 along the first lateral direction X, so that it approaches, for example, the first mesa 101, but without laterally overlapping it, as explained above. Regarding the multiple barrier subzones 1052 that may be optionally provided, reference is made to the explanations above, which apply analogously to the Fig. 13 illustrated embodiment may apply.

[0195] For example, the ratio between the number of first mesas 101, the number of second mesas 102, and the number of third mesas 103 in each cell can be selected independently of a desired capacitive behavior of the device 1. Equipping each or some of the cells 14 with the third mesa 103 can make it possible to adjust a capacitance of the device, e.g., the capacitances or the ratio of the capacitances between the first control electrode 131, the second control electrode 132, and the third electrodes 134, 134' with respect to the first load connection structure 11 and the second load connection structure 12.

[0196] With reference to Fig. 14, another embodiment of the cell 14 will be explained. As illustrated, the cell 14 may comprise two first cell parts 141 and two second cell parts 142, wherein the two first cell parts 141 and the two second cell parts 142 may be separated by one (or more) third cell parts 143. The cell parts 141, 142, and 143 may be configured in a manner as explained by way of example with reference to the previous drawings. In this embodiment, both pairs of the first mesa 101 and the second mesa 102 are controlled by means of the respective first (common) control electrode 131. The central third cell part 143 with the third (dummy) mesa 103 separates the central first mesa 101 and the central second mesa 102 from each other. For example, each cell part 141, 142 and 143 shows the same total extent in the first lateral direction X.

[0197] According to one embodiment, the distance along the first lateral direction X between the first mesa 101 and the second mesa 102 is greater than the distance between the first mesa 101 and the third mesa 103. For example, the distance along the first lateral direction between the first mesa 101 and the second mesa 102 is twice the distance between the first mesa 101 and the third mesa 103. Analogously, the distance along the first lateral direction X between the first mesa 101 and the second mesa 102 may also be twice the distance between the second mesa 102 and the third mesa 103. The lateral widths in the first lateral direction X of the first mesa 101, the second mesa 102, and the third mesa 103 may be substantially the same, e.g., by using the same process technology.However, for example, the third mesa 103, when implemented as a dummy mesa, may have a different (e.g., larger or smaller) width compared to the first mesa 101 and / or the second mesa 102. According to one embodiment, the lateral width of the third mesa 103 may be larger than the first mesa 101 or the second mesa 102 by a factor of, e.g., ten or more.

[0198] If several first and / or second and / or third cell parts 141, 142, 143 are present, each cell 14 can accordingly also comprise several guide zones 1023, as in Fig. 14. Although the barrier zone 105 may be a contiguous zone shared by several or all cells 14 of the active cell array 16, the different guiding zones 1023 may be separated from each other. In another embodiment, it is possible, for example, for the different guiding zones 1023 to merge somewhere in the semiconductor body 10, e.g., within the edge termination zone 18. The semiconductor portion separating adjacent guiding zones 1023 may laterally overlap the first mesas 101 and may be filled by the portion of the drift region 100 and / or a portion of the barrier zone 105, as already explained in more detail above.

[0199] If a plurality of first and / or second and / or third cell portions 141, 142, 143 are present, and if each cell 14 therefore comprises two or more first mesas 101, it may further be possible to associate a first of the first mesas 101 with the first control electrode 131 and to associate a second of the first mesas 101 with the second control electrode 132. This optional aspect provides the possibility of controlling a first portion of the plurality of first mesas 101 differently from a second portion of the plurality of first mesas 101. For example, the third cell portion 143, including the third mesa 103, may be used to separate the control electrode structure 13 accordingly. In another embodiment, it may be desirable to control all first mesas 101 by means of control electrodes that are electrically connected to one another, e.g., only by means of the first control electrodes 131, as shown in Fig. 14 is illustrated.

[0200] According to all embodiments described herein, the cutoff voltage of the accumulation channel in the second channel region 1022 may be greater than the cutoff voltage of the inversion channel in the first channel region 1012. For example, the difference between the cutoff voltages may be at least 0.2 V. In one embodiment, the cutoff voltage of the inversion channel is less than 0.8 V, and the cutoff voltage of the accumulation channel is greater than 1.0 V.

[0201] Generally speaking, the difference in the blocking voltages may enable achieving a more flexible control of the device 1, e.g. of the second channel region 1022, e.g. during the conducting state of the semiconductor device 1, e.g. in a manner that prevents charge carriers of the second conductivity type from leaving the semiconductor body 10 via the second mesa 102 of the second cell part 142 during the conducting state, and / or in a manner that allows charge carriers of the second conductivity type to be drained from the semiconductor body 10 via the second mesa 102 of the second cell part 142 shortly before switching the semiconductor device 1 to the blocking state.

[0202] Some exemplary ways to achieve such a difference between the blocking voltages are described in more detail below:

[0203] In an embodiment as exemplified in the preceding drawings, for example in Fig. 3A, 3B, 5A, 8A-D, 11, 13, and 17, the semiconductor device 1 may include the first control electrode 131 and the second control electrode 132, wherein the first control electrode 131 is configured to induce the inversion channel within the first channel region 1012, wherein the isolation structure 133 may isolate the first control electrode 131 from the first mesa 101. The second control electrode 132 may be configured to induce the accumulation channel, wherein the isolation structure 133 further isolates the second control electrode 132 from the second mesa 102. The first control electrode 131 and the second control electrode 132 may be arranged separately from each other, as illustrated in the aforementioned drawings. For example, the material of the first control electrode 131 may differ from the material of the second control electrode 132 so as to achieve or contribute to the difference between the blocking voltages.For this purpose, the first control electrode 131 may have a work function that is different from the work function of the second control electrode 132. The difference between the work functions may, for example, be at least 0.4 eV. For example, the second control electrode 132 may have a work function of less than 4.5 eV and the first control electrode 131 may have a work function of more than, for example, 4.9 eV. For example, to achieve a difference between the work functions, in one embodiment the first control electrode 131 comprises a polycrystalline semiconductor material with dopants of the second conductivity type and / or a metal silicide (such as PtSi2 or MoSi2) and / or a metal nitride (such as WN). Xor TiN) and / or nickel and / or palladium and / or iridium and / or platinum and / or gold; and the second control electrode 132 comprises a polycrystalline semiconductor material with dopants of the first conductivity type and / or a metal silicide (such as TiSi2, TaSi2, or NbSi2) and / or a metal nitride (such as TaN or TiN) and / or aluminum and / or titanium and / or magnesium and / or scandium and / or yttrium and / or rubidium and / or selenium and / or strontium. The work function of TiN as a gate electrode can be adjusted by a surface treatment at the transition zone to the gate dielectric, making it useful for both the first and second control electrodes 131, 132.Although the two control electrodes 131 and 132 may be arranged separately and provided with different work functions, it is understood that, according to one or more embodiments, the two control electrodes 131 and 132 may be electrically connected to each other and, accordingly, receive the same control signal. For example, contrary to the suggestion, it is understood by the schematic illustration in some drawings, e.g., in . Fig. 3A, Fig. 3B, Fig. 5A and Fig. 6, that the two control electrodes 131 and 132 do not necessarily have to be electrically isolated from each other.

[0204] In a further embodiment, either in addition to or as an alternative to providing the two separate control electrodes 131 and 132 with different work functions, the difference between the blocking voltages can also be effected or achieved by providing the first control electrode 131 with a work function greater than the work function of the first channel region 1012. Furthermore, in addition to or as an alternative thereto, the second control electrode 132 can be provided with a work function that is smaller than the work function of the second channel region 1022. Both the first channel region 1012 and the second channel region 1022 can comprise a monocrystalline semiconductor material with dopants of the second conductivity type and / or a titanium nitride (TiN). For example, both the first channel region 1012 and the second channel region 1022 can have a work function within a range of 4.6 eV to 5.0 eV.

[0205] In yet another embodiment, the difference between the blocking voltages may also be achieved by providing both the first channel region 1012 and the second channel region 1022 with dopants of the second conductivity type, wherein the dopant concentration of the first channel region 1012 may be smaller than the dopant concentration of the second channel region 1022 by a factor of at least 2, a factor of 3, or a factor of 5. For example, in this embodiment, with different dopant concentrations in the channel regions 1012 and 1022, the effective thickness, e.g., in the first lateral direction X (compare, e.g., DX12, DX14 in Fig. 5A), the isolation structure 133 isolating the first control electrode 131 from the first channel region 1012, identical to the effective thickness, e.g., in the first lateral direction X (compare, e.g., DX22, DX24 in Fig. 5A), the isolation structure 133, which isolates the second control electrode 132 from the second channel region 1022. Furthermore, in this embodiment, the first control electrode 131 and the second control electrode 132 may be identical in material and / or spatial dimensions, or the first mesa 101 and the second mesa 102 may be controlled by a common control electrode.

[0206] According to yet another example, the difference between the blocking voltages may also be effected by providing the isolation structure 133 such that the effective thickness, e.g., in the first lateral direction X (compare e.g., DX12, DX14 in Fig. 5A), the insulation structure 133, which isolates the first control electrode 131 from the first channel region 1012, by a factor of at least 20% or at least 30% or at least 50% smaller than the effective thickness, e.g., in the first lateral direction X (compare, e.g., DX22, DX24 in Fig. 5A), the insulation structure 133 that isolates the second control electrode 132 from the second channel region 1022. Accordingly, a variation in the thickness may accordingly vary the respective blocking voltages of the inversion channel and the accumulation channel. Here, the comparison of the “effective thicknesses” may mean comparing the product of the dielectric constant of the dielectric used for the insulation structure 133 that isolates the first control electrode 131 from the first channel region 1012, multiplied by its thickness, with the product of the dielectric constant of the dielectric used for the insulation structure 133 that isolates the second control electrode 132 from the second channel region 1022, multiplied by its thickness. If the dielectrics are made of the same material, e.g., silicon dioxide, this is reduced to a comparison of the respective thicknesses. If, for example,the dielectric used for the isolation structure 133 isolating the first control electrode 131 from the first channel region 1012 has a higher dielectric constant, the thickness may even be the same as or even larger than that for isolating the second control electrode 132 from the second channel region 1022.

[0207] According to yet another example, the difference between the blocking voltages may be achieved by providing a different density of interfacial charges of the isolation structure 133, such that the interfacial charge of, e.g., the isolation structure 133 isolating the first control electrode 131 from the first channel region 1012 is a factor of at least 20%, or at least 30%, or at least 50% more positive than the interfacial charge of, e.g., the isolation structure 133 isolating the second control electrode 132 from the second channel region 1022. Different interfacial charges may, e.g., be achieved by different materials for both isolation structures 133 in the first channel region 1012 and the second channel region 1022, e.g. B. using a silicon nitride or a nitride silicon oxide as dielectric in the first channel region 1012 and a silicon dioxide in the second channel region 1022.

[0208] It is understood that the first mesa 101 and the second mesa 102 may be controlled by a single control signal according to one or more embodiments. For this purpose, two separately arranged control electrodes 131 and 132 may be provided, as illustrated by way of example in some of the drawings, and the two separately arranged control electrodes 131 and 132 may be electrically connected to each other. According to another embodiment, as illustrated by way of example in some of the drawings, both the first mesa 101 and the second mesa 102 may be controlled by a common control electrode, which is also referred to in the foregoing as the first control electrode 131, which may, for example, be monolithically integrated within the trench structure 17.Accordingly, it is understood that the difference in blocking voltages does not necessarily require two separate control electrodes for controlling the first mesa 101 and the second mesa 102.

[0209] As exemplified in Fig. 9, it is further understood that the insulation structure 133 does not necessarily extend at least as far in the vertical direction Z as the first control electrode 131 along the entire distance (compare DX30 in Fig. 5A) between the first mesa 101 and the second mesa 102, but may extend less in the vertical direction Z, e.g. in the same area as the entire extent of the first connection region 1011 or the entire extent of the second connection region 1021 in the vertical direction Z (compare DZ13, DZ23 in Fig. 5A), e.g., along at least 80% of the distance between the first mesa 101 and the second mesa 102. For example, the first control electrode 131, if implemented as a common control electrode, may have a U-shaped vertical cross-section. In another embodiment, as schematically and exemplarily shown in Fig. 10, the first control electrode 131 may be implemented as a block having a substantially constant total extension in the vertical direction Z along at least, for example, 80% of the distance between the first mesa 101 and the second mesa 102.

[0210] An exemplary method for operating such a power semiconductor device (which provides an inversion channel and an accumulation channel with different blocking voltages) is described in the German patent application DE 10 2016 112 017 A1.

[0211] A method for manufacturing a power semiconductor device is also presented here. According to some embodiments, the power semiconductor device to be manufactured comprises a semiconductor body to be coupled to a first load connection structure and a second load connection structure, wherein the semiconductor body is configured to conduct a load current and comprises a drift region of a first conductivity type, wherein the power semiconductor device comprises a plurality of cells.Each cell comprises: a first mesa included in a first cell portion, the first mesa including a first terminal region of the first conductivity type electrically connected to the first load terminal structure, and a first channel region coupled to the drift region; a second mesa included in a second cell portion, the second mesa including a second terminal region of a second conductivity type electrically connected to the first load terminal structure, and a second channel region coupled to the drift region; a trench structure including a control electrode structure for controlling the load current at least by means of an inversion channel in the first channel region. The method comprises: a) providing the first mesa with a total extension of less than 100 nm in a lateral direction perpendicular to a vertical direction of the load current path within the first mesa; and providing a guiding zone of the second conductivity type arranged below the second channel region while being spatially offset from both the first and second channel regions along the vertical direction, wherein the guiding zone laterally overlaps with the second mesa and extends laterally toward the first mesa while not laterally overlapping therewith, and wherein the guiding zone is separated from the second load connection structure at least by means of a region of the first conductivity type; or b) providing a guiding zone of the second conductivity type arranged below the second channel region, wherein the guiding zone laterally overlaps the second mesa and extends laterally toward the first mesa while not laterally overlapping it, and wherein the guiding zone is separated from the second load connection structure at least by a region of the first conductivity type; and providing a barrier zone of the first conductivity type arranged between the guiding zone and the trench structure, wherein the barrier zone has a dopant concentration at least twice as high as the dopant concentration of the drift region.

[0212] The methods described above may also include, at least partially before or after providing the guide zone, pre-processing and / or post-processing of the semiconductor body such that it has the configuration described above.

[0213] Embodiments of the methods correspond to the embodiments of the power semiconductor device explained with reference to the drawings. Accordingly, reference is made to the foregoing.

[0214] According to one embodiment of the method as described in Fig. 16, a spacer element 21 may be inserted within the scope of providing the guide zone 1023. For example, providing the guide zone 1023 may include one or more implantation processing steps, e.g., by a first guide sub-zone 1023a and a second guide sub-zone 1023b, as shown in Fig.16. Providing the barrier zone 105 may also include one or more implantation processing steps. For example, the spacer element 21 is removed after the first guiding sub-zone region 1023a has been provided and, e.g., before the barrier zone 105 is provided. A lateral distance DF1 between the first mesa 101 and the first guiding sub-zone 1023a may be provided by a lateral thickness DS of the spacer element 21 at the sidewall of the first mesa 101, which locally masks an ion implantation step at the position of the first mesa 101. Due to lateral roaming of the implanted ions, the lateral distance DF1 is smaller than the lateral thickness DS of the spacer element 21. Accordingly, a lateral distance DF2 may be provided between the second mesa 102 and the first guiding sub-zone 1023a.The energy of the implanted ions may be configured in such a way that they overcome a vertical thickness DV1 of the horizontal part of the spacer element 21, reaching the semiconductor body 10. However, the energy of the implanted ions may be too low to overcome a larger vertical thickness DV2 of the spacer element 21 at the first mesa 101 and the second mesa 102, resulting in a substantial blockage of the ion implantation at the position of the first mesa 101 and the second mesa 102. For example, the isolation structure 133 and the control electrode structure 13 with the trench structure 17 are formed thereafter. The second guiding sub-zone 1023b may be provided either earlier or later in the processing using, e.g., ion implantation steps in combination with conventional patterning with lithographic masks. The first guiding sub-zone 1023a and the second guiding sub-zone 1023b may, for example, be formed. B.can be realized by implanting boron or BF2 ions at different energies if the dopants of the second conductivity type are acceptors.

[0215] For example, providing the guide zone 1023 and / or the barrier zone 105 (optionally including one or more barrier subzones 1052) may be performed according to a self-aligned processing step as described in detail above.

[0216] Embodiments relating to a power semiconductor device and methods for manufacturing a power semiconductor device have been explained above. These embodiments are based, for example, on silicon (Si). Accordingly, a monocrystalline semiconductor region / zone / section / layer of embodiments may be a monocrystalline Si region or a monocrystalline Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.

[0217] It is understood, however, that the semiconductor regions / zones / portions / layers may be made of any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few.The aforementioned semiconductor materials are also called "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaNN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (Si). x C 1-x ) and silicon-SiGe heterojunction semiconductor materials. Currently, Si, SiC, GaAs, and GaN materials are mainly used for power semiconductor device applications.

[0218] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used for convenience of description to describe the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the corresponding device in addition to those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Throughout the description, like terms refer to like elements.

[0219] As used herein, the terms “comprising,” “containing,” “including,” “comprising,” “having,” and the like are open-ended terms that indicate the presence of the stated elements or features but do not exclude additional elements or features.

Claims

[1] A power semiconductor device (1) comprising a semiconductor body (10) coupled to a first load connection structure (11) and a second load connection structure (12), wherein the semiconductor body (10) is configured to conduct a load current (15) and comprises a drift region (100) of a first conductivity type, wherein the power semiconductor device (1) comprises a plurality of cells (14), each cell (14) comprising: - a first mesa (101) contained in a first cell portion (141), the first mesa (101) including: a first terminal region of the first conductivity type (1011) electrically connected to the first load terminal structure (11), and a first channel region (1012) coupled to the drift region (100), the first mesa (101) having a total extension (DX13) of less than 100 nm in a lateral direction (X) perpendicular to a vertical direction (Z) of the load current portion (151) within the first mesa (101); - a second mesa (102) contained in a second cell portion (142), the second mesa (102) including: a second terminal region of a second conductivity type (1021) electrically connected to the first load terminal structure (11), and a second channel region (1022) coupled to the drift region (100); - a trench structure (17) including a control electrode structure (13) for controlling the load current at least by means of an inversion channel in the first channel region (1012); - a guiding zone (1023) of the second conductivity type arranged below the second channel region (1022) while being spatially offset from both the first and second channel regions (1012, 1022) along the vertical direction (Z), wherein the guiding zone (1023) laterally overlaps the second mesa (102) and extends laterally towards the first mesa (101) while not laterally overlapping therewith, and wherein the guiding zone (1023) is separated from the second load connection structure (12) at least by means of a region of the first conductivity type. [2] The power semiconductor device (1) according to claim 1, further comprising a barrier region of the first conductivity type (105), wherein the barrier region (105) is arranged between the guide region (1023) and the trench structure (17). [3] Power semiconductor device (1) according to claim 2, wherein the barrier zone (105) has a dopant concentration at least twice as large as the dopant concentration of the drift region (100). [4] A power semiconductor device (1) comprising a semiconductor body (10) coupled to a first load connection structure (11) and a second load connection structure (12), wherein the semiconductor body (10) is configured to conduct a load current (15) and comprises a drift region (100) of a first conductivity type, wherein the power semiconductor device (1) comprises a plurality of cells (14), each cell (14) comprising: - a first mesa (101) contained in a first cell portion (141), the first mesa (101) including: a first terminal region of the first conductivity type (1011) electrically connected to the first load terminal structure (11), and a first channel region (1012) coupled to the drift region (100); - a second mesa (102) contained in a second cell portion (142), the second mesa (102) including: a second terminal region of a second conductivity type (1021) electrically connected to the first load terminal structure (11), and a second channel region (1022) coupled to the drift region (100); - a trench structure (17) including a control electrode structure (13) for controlling the load current at least by means of an inversion channel in the first channel region (1012); - a guiding zone (1023) of the second conductivity type arranged below the second channel region (1022), wherein the guiding zone (1023) laterally overlaps the second mesa (102) and extends laterally towards the first mesa (101) while not laterally overlapping therewith, and wherein the guiding zone (1023) is separated from the second load connection structure (12) at least by means of a region of the first conductivity type; - a barrier zone of the first conductivity type (105) arranged between the guide zone (1023) and the trench structure (17), wherein the barrier zone (105) has a dopant concentration at least twice as high as the dopant concentration of the drift region (100). [5] The power semiconductor device (1) according to claim 4, wherein the guiding zone (1023) is spatially offset from both the first and the second channel region (1022) along the vertical direction (Z) and / or wherein the first mesa (101) has a total extension (DX13) of less than 100 nm in a lateral direction (X) perpendicular to a vertical direction (Z) of the load current part (151) within the first mesa (101). [6] Power semiconductor device (1) according to one of the preceding claims, wherein the guide zone (1023) has a dopant concentration of at least 10 15 cm -3 and / or wherein the region of the first conductivity type separating the guide zone (1023) from the second load connection structure (12) is the drift region (100). [7] The power semiconductor device (1) according to any one of the preceding claims, wherein the control electrode structure (13) includes a first control electrode (131) configured to control both the inversion channel in the first channel region (1012) and an accumulation channel in the second channel region (1022), and wherein the guiding zone (1023) laterally overlaps with the first control electrode (131) along the lateral direction (X) for at least 60% of the total lateral extent of the first control electrode (131). [8] Power semiconductor device (1) according to one of the preceding claims, wherein the trench structure (17) comprises a first trench sidewall (171) adjoining the first mesa (101), a second trench sidewall (172) adjoining the second mesa (102), and a trench bottom (175) between the first trench sidewall (171) and the second trench sidewall (172), wherein optionally the trench bottom (175) adjoins the barrier zone (105). [9] The power semiconductor device (1) according to claim 8, further comprising an isolation structure (133) isolating the control electrode structure (13) within the trench structure (17), and wherein a first thickness along the lateral direction (X) of the isolation structure (133) between the first trench sidewall (171) and the control electrode structure (13) is less than one half of a second thickness along the vertical direction (Z) of the isolation structure (133) between the trench bottom (175) and the control electrode structure (13). [10] Power semiconductor device (1) according to claim 9, wherein within a transition sub-region (174) of the trench structure (17), the trench bottom (175) and the first trench sidewall (171) merge into one another and the thickness of the insulation structure (133) increases from the first thickness to the second thickness. [11] Power semiconductor device (1) according to claim 2 or 4 and according to claim 8, wherein the barrier zone (105) comprises a barrier sub-zone (1052) in contact with the trench bottom (175), the barrier sub-zone (1052) having a dopant concentration at least as large as the dopant concentration of the drift region (100). [12] Power semiconductor device (1) according to claims 10 and 11, wherein the barrier sub-zone (1052) contacts the trench bottom (175) within the transition sub-region (174). [13] Power semiconductor device (1) according to one of the preceding claims, wherein the first mesa (101) has a mesa opening with a width at least twice as large as the total extension (DX13) of the first mesa (101) in the lateral direction (X). [14] Power semiconductor device (1) according to one of the preceding claims, wherein the thickness of the guiding zone (1023) decreases by a factor of at least two as it extends laterally towards the first mesa (101), and optionally wherein the distance between the trench structure (17) and the guiding zone (1023) remains substantially constant as the guiding zone (1023) extends laterally towards the first mesa (101). [15] Power semiconductor device (1) according to one of the preceding claims, wherein a maximum thickness of the guide zone (1023) along the vertical direction (Z) is less than one tenth of the total extension of the semiconductor body (10) along the vertical direction (Z). [16] Power semiconductor device (1) according to claim 2 or 4 and optionally a further one of the preceding claims, wherein at least the barrier zone (105) separates the second channel region (1022) and the guide zone (1023) from each other. [17] Power semiconductor device (1) according to one of the preceding claims, wherein a connection between the second channel region (1022) and the guide zone (1023) has a first electrical conductivity during a first operating state of the power semiconductor device (1) and a second electrical conductivity during a second operating state, wherein the second electrical conductivity is greater than the first electrical conductivity by a factor of at least ten. [18] Power semiconductor device (1) according to claim 17, wherein the electrical potential of the guide zone (1023) deviates from the electrical potential of the first load connection structure (11) by at most 3 V during the transition from the first operating state to the second operating state. [19] Power semiconductor device (1) according to one of the preceding claims, wherein the guiding zone (1023) is configured to guide charge carriers of the second conductivity type along a path between the first mesa (101) and the second mesa (102) during a blocking state of the power semiconductor device (1) and / or during a transition from a conducting state to the blocking state. [20] Power semiconductor device (1) according to one of the preceding claims, wherein both the first channel region (1012) and the second channel region (1022) are of the second conductivity type. [21] A method for manufacturing a power semiconductor device (1) comprising a semiconductor body (10) coupled to a first load connection structure (11) and a second load connection structure (12), the semiconductor body (10) being configured to conduct a load current (15) and comprising a drift region (100) of a first conductivity type, the power semiconductor device (1) comprising a plurality of cells (14), each cell (14) comprising: a first mesa (101) contained in a first cell part (141), the first mesa (101) comprising: a first connection region of the first conductivity type (1011) electrically connected to the first load connection structure (11), and a first channel region (1012) coupled to the drift region (100);a second mesa (102) contained in a second cell portion (142), the second mesa (102) including: a second terminal region of the second conductivity type (1021) electrically connected to the first load terminal structure (11), and a second channel region (1022) coupled to the drift region (100); and a trench structure (17) including a control electrode structure (13) for controlling the load current at least by means of an inversion channel in the first channel region (1012); the method comprising: a) providing the first mesa (101) with a total extension (DX13) of less than 100 nm in a lateral direction (X) perpendicular to a vertical direction (Z) of the load current path (151) within the first mesa (101); and providing a guiding zone (1023) of a second conductivity type arranged below the second channel region (1022) while being spatially offset from both the first and second channel regions (1012, 1022) along the vertical direction (Z), wherein the guiding zone (1023) laterally overlaps the second mesa (102) and extends laterally toward the first mesa (101) while not laterally overlapping it, and wherein the guiding zone (1023) is separated from the second load connection structure (12) at least by means of a region of the first conductivity type; or b) providing a guiding zone (1023) of a second conductivity type arranged below the second channel region (1022), wherein the guiding zone (1023) laterally overlaps the second mesa (102) and extends laterally toward the first mesa (101) while not laterally overlapping therewith, and wherein the guiding zone (1023) is separated from the second load connection structure (12) at least by means of a region of the first conductivity type; and providing a barrier zone of the first conductivity type (105) arranged between the guiding zone (1023) and the trench structure (17), wherein the barrier zone (105) has a dopant concentration at least twice as high as the dopant concentration of the drift region (100).

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