Circuit and method for providing an output signal

Abstract

Output circuit (100) having the following features: an output transistor (110) configured to provide an output signal; a gate switch (130) configured to decouple a gate of the output transistor (110) from other components of the output circuit (100) when there is a drop in a supply voltage of the output circuit (100), wherein, when the gate of the output transistor (110) is decoupled, a charge at the gate in a capacitor (C GS ), which is inherent in the gate of the output transistor (110), is maintained; and a reset controller (170) configured to reset the output signal after a predetermined reset time has elapsed after the gate switch (130) decouples the gate of the output transistor (110).

Description

The present disclosure is directed to improving robustness of electromagnetic compatibility (EMF) of a 3-wire sensor output signal. Class A functionality at the output is ensured when the integrated circuit (IC) is subjected to either conducted or coupled pulses at the supply (e.g., direct capacitive coupling (DKK)), inductive transients (e.g., radio frequency immunity (RI 130)), or short supply drops below a reset level.One approach to improving EMF robustness uses an external storage capacitor that powers the IC during EMF pulses. A disadvantage of this approach is that it requires an additional bond pad and an external passive component.Another approach uses a relatively large integrated capacitor to power output circuitry. A power management loss circuit configuration detects a power supply voltage drop and outputs a latch signal for controlling the logic circuit configuration. During power loss, the capacitor is decoupled from the supply line using a diode / switch and a voltage stored on the capacitor supplies power to the output circuitry. A disadvantage of this approach is that it requires a relatively large integrated capacitor to power the entire output circuitry. This drawback becomes even more significant at higher temperatures where additional leakage results in a relatively fast loss of stored voltage, which determines substantial drifting of output sensor parameters such as output voltage saturation. In addition, using a large capacitor to ensure good performance at high temperatures results in slow discharge of the capacitor at lower temperatures when power is turned off.DE 10 2014 001 749 A1 relates to a protective device for a power supply. The protection device includes an under voltage detection circuit for monitoring the power supply and detects variations in the power supply. A gate disconnection circuit is configured to disconnect the terminal of the gate driver from the power supply when the under voltage detection circuit detects a variation in the power supply. A voltage at the terminal of the gate driver is maintained in a preselected range when the gate is cut off.US 2015 / 0 098 160 A1 relates to a protection circuit and a gate driver circuit arrangement. The protection circuit serves to protect a p-type back-to-back MOS switch. The circuit receives an input driver signal and provides a driver output signal to common gates of the p-type back-to-back MOS switch. The circuit includes a driver signal isolation switch for isolating the common gate of the p-type back-to-back MOS switch from the received input driver signal when the voltage of the common gates is greater than the supply voltage of the circuit. The circuit further includes a gate-source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate when a voltage received at the common sources is greater than a reference voltage Vref.The object of the present invention is to provide an output circuit, a circuit and a method for operating an output circuit with improved characteristics.This object is achieved by an output circuit according to independent claims 1 and 13, a circuit according to claim 14 and / or a method according to independent claims 15 and 20.All embodiments and examples of the description which do not fall within the scope of the claims are not part of the invention and serve only as comparative examples and for illustration purposes.According to an embodiment, an output circuit may comprise the following features: an output transistor configured to provide an output signal; a gate switch configured to decouple a gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit, wherein, when the gate of the output transistor is decoupled, a charge is maintained at the gate in a capacitor that is inherently in the gate of the output transistor, and a reset controller configured to reset the output signal after a predetermined reset time has elapsed after the gate switch decouples the gate of the output transistor.According to a further embodiment, the output circuit may further comprise a charge pump configured to provide a local supply voltage for controlling the gate switch during a normal operating mode, wherein the local supply voltage is greater than the supply voltage.According to a further embodiment, the output circuit may further comprise a chip reset circuit coupled to the output of the charge pump and configured to drive the charge pump output to ground during the decrease of the supply voltage.According to another embodiment, the reset controller may be further configured to output a reset signal to pull down the gate of the output transistor after a predetermined reset time has elapsed.According to another embodiment, the reset controller may be configured to output the reset signal in response to receiving a resistor-capacitor (RC) timing signal.According to another embodiment, the reset controller may include: a reset controller output transistor configured to output the reset signal; a capacitor configured to store a threshold voltage; and a discharge switch configured to turn on in response to receiving the RC timing signal to couple the capacitor to a gate of the reset controller output transistor.According to yet another embodiment, the output circuit may further include: a passive pull-down circuit coupled to the gate switch and configured to drive the gate switch to ground during the decrease of the supply voltage.According to a further embodiment, the output circuit may further comprise the following feature: an edge control which is connected between a signal input of the output circuit and the gate and is configured to carry out a current charge and discharge at the gate.According to a further embodiment, the edge controller may comprise: a first current source connected between a supply and the gate and configured to perform current charging on the gate when the signal input to the output circuit is high; and a second current source connected between ground and the gate and configured to perform current discharging on the gate when the signal input to the output circuit is low.According to another embodiment, the output circuit may further include: a hard-on switch connected between a regulated supply voltage and the gate and configured to be closed when a signal input to the output circuit is high; and a hard-off switch connected between ground and the gate and configured to be closed when the signal input to the output circuit is low.According to a further embodiment, the output circuit may further comprise: an inversion protection transistor connected between an output node of the output circuit and the output transistor and configured to prevent an inversion current at the output node.According to a further exemplary embodiment, the output circuit can be designed to receive a sensor signal and to output the output signal.According to another embodiment, a circuit may comprise: the above-mentioned output circuit; and a memory configured to store an RC time constant provided by a resistor and a capacitor within the circuit.According to an embodiment, an output circuit may comprise: an output transistor configured to provide an output signal; a gate switch configured to decouple a gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge is maintained at the gate in a capacitor that is inherently in the gate of the output transistor, and a reset controller configured to output a reset signal to pull down the gate of the output transistor after a predetermined reset time has elapsed.According to another embodiment, a method of operating an output circuit may include the steps of: providing an output signal through an output transistor; decoupling a gate of the output transistor from other components of the output circuit through a gate switch when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge is maintained at the gate in a capacitor that is inherently in the gate of the output transistor, and resetting the output signal through a reset control after a predetermined reset time has elapsed after decoupling the gate of the output transistor.According to a further embodiment, the method may further comprise the step of: providing a local supply voltage for controlling the gate switch during a normal operating mode by a charge pump, wherein the local supply voltage is greater than the supply voltage.According to another embodiment, the method may further include the step of: outputting a reset signal by a reset controller to pull down the gate of the output transistor after a predetermined reset time has elapsed.According to a further embodiment, the method may further comprise the step of: driving the gate switch by a passive pull-down circuit coupled to the gate switch during the return of the supply voltage to ground.According to a further embodiment, the method may further comprise the step of: charging and discharging the gate with current by an edge controller connected between a signal input of the output circuit and the gate.According to another embodiment, a method of operating an output circuit may include the steps of: providing an output signal through an output transistor; decoupling a gate of the output transistor from other components of the output circuit through a gate switch when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge is maintained at the gate in a capacitor that is inherently in the gate of the output transistor; and outputting a reset signal through a reset controller to pull down the gate of the output transistor after a predetermined reset time has elapsed.Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the attached drawings. The following are shown: FIG. 1 illustrates a sensor output signal for improved electromagnetic compatibility (EMF) robustness, in accordance with aspects of the disclosure; FIG. 2 is a timing diagram for an initial frozen state, in accordance with aspects of the disclosure; FIG. 3 illustrates a microinterrupt reset controller according to aspects of the disclosure; FIG. 4 is a timing diagram for a predefined reset time, in accordance with aspects of the disclosure; FIG. 5 illustrates an output system in accordance with aspects of the disclosure; and FIG. 6 is a flow diagram of a method in accordance with aspects of the disclosure.The present disclosure is directed to an output circuit including an output transistor configured to provide an output signal and a gate switch configured to decouple the gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit. When the gate of the output transistor is decoupled, charge is maintained at the gate in a capacitor that is inherently in the gate of the output transistor. The output circuit thus disconnects the gate of the output transistor, thereby ensuring a low leakage path.In addition, a charge pump may supply a voltage to the gate switch, so that the gate switch need only be a small, low-leakage switch. In addition, a reset controller may provide a defined time for resetting the state of the output signal regardless of a temperature.FIG. 1 illustrates an output circuit 100 for improved robustness of electromagnetic compatibility (EMF) in accordance with aspects of the disclosure.A sensor, such as a camshaft magnetic sensor, has three pins - supply, ground and output. An output signal at the output pin is high or low depending on a magnetic signal applied to the sensor. During an EMF perturbation, the sensor output circuit 100 disconnects a gate of an output transistor 110, providing a frozen output. An EMF fault is sometimes referred to herein as a "microinterrupt.". A "frozen output" is present when a state of the output signal is maintained for a period of time after a decrease in a supply voltage caused by an EMF disturbance.The output circuit 100 is configured to receive an input signal and output the output signal. The input and output signals could be from a sensor, although the disclosure is not limited in this respect.The output circuit 100 includes an output transistor 110, an inversion protection transistor 120, a gate switch 130, an edge controller 140, hard on / off (hard on / off) switches 150, a charge pump 160, a reset controller 170, and a passive pulldown circuit 180.To classify the sensor output circuit 100, FIG. 1 shows a supply comparator 10 and a chip reset circuit 60. the supply comparator 10 is configured to detect when a supply voltage falls below a predefined threshold and output a micro-break detection signal for decoupling the gate of the output transistor 110 from the rest of the circuit configuration. The chip reset element 60 is configured to reset the charge pump 160.The output transistor 110 is configured to provide the output signal. Switching the output transistor 110 to an on state results in the sensor output signal being low because the sensor output is coupled to ground. Switching the output transistor 110 to an off state results in the sensor output signal being high because the sensor output is decoupled from ground.The output transistor 110 has an inherent storage capacitor C GS between its gate and source. Normally, this inherent capacitor C GS is undesirable. During the microinterrupt, however, the sensor output state is stored in this inherent capacitor C GS. This is in contrast to previous solutions where the sensor output state is stored in a separate capacitor connected in parallel with the output transistor 110. Since the output circuit 100 of this disclosure uses the inherent capacitor, no separate capacitor is required.The reverse protection transistor 120 is connected between an output node of the output circuit 100 and the output transistor 110, and is configured to prevent a reverse current. In particular, the reverse protection transistor 120 prevents large output currents in a case of a negative voltage at the sensor output by preventing a large current flow to the drain of the output transistor 110. The reverse current could be limited to a range of, for example, mA to prevent any deleterious effects.The output transistor 110 and the reverse protection transistor 120 are connected anti-serially. In the exemplary implementation, output transistor 110 is an enhancement mode NMOS transistor, i.e., is on at a positive gate voltage, and reverse protection transistor 120 is an depletion mode NMOS, i.e., is always on, although the disclosure is not limited to this particular design.The gate switch 130 is configured to decouple the gate of the output transistor 110 from other components of the output circuit 100 when there is a decrease in the supply voltage of the output circuit 100. These other components are the components in the figure that are to the left of the gate switch 130, i.e., the edge controller 140 and the hard on / off switches 150. When the gate of output transistor 110 is decoupled, charge is maintained at the gate in capacitor C GS which is inherently in the gate of output transistor 110.The edge controller 140 is connected between a signal input (digital sensor signal) of the output circuit 100 and the gate of the output transistor 110 and configured to ensure controlled current charging and discharging of the gate of the output transistor 110. The edge controller 140 includes a first current source 140- 1 and a second current source 140- 2. The first current source 140- 1 is connected between a supply V reg and the gate, and is configured to charge the gate with current when the signal input to the output circuit is high. The second current source 140- 2 is connected between ground and the gate, and is configured to perform current discharge of the gate when the signal input to the output circuit is low.The hard on / off switch circuit 150 is configured to ensure greater robustness of the output state during fast low-energy pulses (e.g., DCC) by providing a low-resistance path to the supply lines. The hard on / off switch circuit 150 includes a hard on switch 150- 1 and a hard off switch 150- 2. The hard-on switch 150- 1 is connected between the supply V reg and the gate, and is configured to be closed when a signal input to the output circuit is high. The hard-off switch 150- 2 is connected between ground and the gate and is configured to be closed when the signal input to the output circuit is low.The charge pump 160 is configured to provide a local supply voltage VDDL for controlling the gate switch 130 during a normal operating mode. The local supply voltage VDDL is greater than the supply voltage of the output circuit 100. The charge pump 160 is configured to increase the voltage level at the gate switch 130 to minimize the size and therefore leakage of the output switch 130. To obtain a low on-resistance (Ron) and low leakage at the gate switch 130, the driver signal of the switch is increased by the charge pump 160.The reset controller 170 is coupled to the gate of the output transistor 110. When there is a decrease in the supply voltage (i.e., a micro-break), the reset controller 170 is configured to reset the output signal after a predetermined reset time has elapsed after the gate switch 130 decouples the gate of the output transistor 110. Specifically, the reset controller 170 is configured to output a reset signal in response to receiving a resistor-capacitor (RC) time signal to pull down the gate of the output transistor 110 after a predetermined reset time has elapsed. If only the gate switch 130 were present without the reset controller 170, there would be different behaviors at different temperatures due to leakage, which can discharge the gate of the output transistor 110 and cause the state of the output signal to go high. A high temperature is a worst case. At room temperature there is relatively little leakage. The reset time provided by an RC time constant of the RC time signal should be independent of temperature.The passive pull-down circuit 180 is coupled to the gate switch 130 and is configured to drive the gate switch 130 to ground during the decrease of the supply voltage.During normal operation, when there is a sufficiently high supply voltage, the charge pump 160 is on, providing a higher voltage than the supply voltage. The voltage provided could be twice the supply voltage, for example.In the case of a supply voltage decrease, the supply comparator 10 detects the micro-interruption and outputs the micro-interruption detection signal. The microinterrupt detection signal is transmitted through a level shifter within the charge pump 160 to turn off the gate switch 130. In this manner, the gate of output transistor 110 is isolated from the remainder of the circuitry (e.g., hard on / off switch 150 and edge controller 140). The chip reset signal transmitted by the chip reset circuit 60 turns off the clock signals provided to the charge pump and discharges the charge pump output capacitor. The passive pull-down circuit 180, combined with the small size of the low leakage gate switch 130, maintains the output voltage level for a duration of, for example, up to 100 μs. The frozen output is temperature dependent, i.e. a duration of about 100 μs could be seconds or minutes due to the exponential property of leaking at lower temperatures. The reset controller 170 provides a maximum frozen state reset time. Based on this feature, retention of frozen output despite the temperature value is ensured. Even at lower temperatures, a reset in the range of hundreds of microseconds is triggered, providing predictable integrated circuit performance.FIG. 2 illustrates a timing diagram 200 for an initial frozen state, in accordance with aspects of the disclosure.The timing diagram shows a magnetic signal applied to a magnetic sensor, the supply voltage signal, the micro-break detection signal, and the output signal of the sensor. The output signal is based on the magnetic signal.If the supply signal decreases due to an EMF disturbance (i.e., a micro-break) that is not associated with the magnetic signal and the sensor output signal, the output circuit cannot provide signal processing. During this time, the information at the output is retained in the inherent capacitor C GS of the output transistor 110. The sensor output signal (low or high) is frozen for the microinterrupt time. During the microinterruption, there is a slight increase in sensor output due to leaks. When the power supply signal subsequently goes high, the signal processing is continued.FIG. 3 illustrates a micro-interrupt reset controller 300 in accordance with aspects of the disclosure. The microinterrupt reset controller 300 is the reset controller 170 of FIG. 1.The example reset controller 300 includes a reset controller output transistor 310, a capacitor 330, and a charge switch 320, among other elements. The micro-interrupt reset controller 300 is operable without a supply because the capacitor 330 stores a charge and then discharges it to allow the reset controller 300 to operate for a period of time without the supply.Specifically, the reset controller 300 ensures a constant reset time despite a temperature value. During normal operation (i.e., appropriate supply voltage), a PMOS threshold voltage level is stored on capacitor 330 by switch 320. The RC_Time signal is high and the output transistor 310 of this circuit is off.When there is a decrease in the supply voltage, switch 320 turns off decoupling capacitor 330 from the circuitry shown to the left of switch 320. The RC_Time signal is provided by RC circuitry (not shown) and the RC time constant defines a reliable reset time for the output transistor 310. When the RC_Time signal transitions from high to low, the output transistor 310 is turned on by coupling its gate to the voltage stored on the capacitor 330, and the gate of the output transistor 310 is pulled high. Consequently, the output state is reset to high.This reset controller 300 is merely exemplary. The other elements do not pertain to this disclosure and should be understood by one of ordinary skill in the art. The descriptions thereof are therefore omitted for the sake of brevity.FIG. 4 illustrates a timing diagram 400 for a predefined reset time, in accordance with aspects of the disclosure.Timing diagram 400 shows a supply voltage signal, a micro-interrupt detection signal, an RC time signal, a reset threshold signal, a micro-interrupt reset signal, and the sensor output signal.When the supply comparator 10 detects a micro-break in the supply voltage, the micro-break detection signal from the supply comparator 10 goes low. The micro interrupt reset signal of the reset controller 170 goes low after a predetermined time based on an RC time constant, that is, when the RC time signal becomes smaller than a reset threshold level. The chip reset circuit 60 then outputs a chip reset signal to cause the VDDL voltage of the charge pump 60 to short to low. The microinterrupt is indicated by dashed lines in the sensor output signal. After the reset time has elapsed and the microinterrupt reset signal goes low, the sensor output signal is reset to high.FIG. 5 illustrates an output system 500 in accordance with aspects of the disclosure.The system 500 includes a sensor 20 (e.g., Hall sensor), a chopper / analog-to-digital converter 30, a switching level calculation circuit 40, the supply comparator 10 of FIG. 1, the output circuit 100 of FIG. 1, and an information memory 50 (i.e., memory).The sensor 20 in this example is configured to output an analog voltage signal proportional to the magnetic field strength. The chopper / ADC 30 is configured to convert the analog signal to a digital signal. The supply comparator 10 is configured to compare the digital signal with a threshold provided by the switching level calculation circuit 40 to determine whether the digital signal is in a high state or a low state.The information memory 50 is configured to store digital information such as a threshold for the supply comparator 10, the RC time constant of the RC time signal, and the output state of the sensor 20, so that in the case of a decrease in the supply voltage or an EMF fault, the output state of the sensor 20 is maintained. The information storage 50 is a memory that can be any known volatile and / or nonvolatile memory.FIG. 6 illustrates a flowchart 600 of a method in accordance with aspects of the disclosure.In step 610, an output signal is provided by an output transistor 110.In step 620, a gate of the output transistor 110 is decoupled from other components of an output circuit 100 by a gate switch 130 if a decrease in a supply voltage of the output circuit 100 is present. When the gate of output transistor 110 is decoupled, charge is maintained at the gate in a capacitor C GS that is inherently in the gate of the output transistor.The subject matter of this disclosure is applicable not only to microinterruptions, but also to any disturbances when the supply voltage is near or below zero. When the supply voltage decreases, the state of the output signal should be maintained for a period of time.The output circuit 100 of this disclosure ensures EMF robustness for the sensor output signal. Class A functionality is ensured by the proposed system while allowing guaranteed reset time of the output. For this improved robustness, there is no need for integration of area-consuming passive components.Numerous other exemplary embodiments are likewise possible. These include embodiments that have fewer, additional, and / or different components, steps, features, tasks, advantages, and benefits. These also include embodiments in which the components and / or steps are arranged and / or ordered differently. For example, any signal discussed herein could be scaled, buffered, scaled, and buffered, converted to another state (e.g., voltage, current, charge, time, etc.), or converted to another state (e.g., from HIGH to LOW and LOW to HIGH) without materially changing the underlying control method. In addition, bipolar transistors (e.g., PNP or NPN) may be used instead of MOS transistors. A PNP could be used in place of an NPN and a PMOS could be used in place of an NMOS.For purposes of this explanation, the terms "circuit" and "circuitry" are intended to be understood as circuit(s), processor(s), logic, or a combination thereof. For example, a circuit may include analog circuitry, digital circuitry, state machine logic, other structural electronic hardware, or a combination thereof.While the foregoing has been described in connection with an exemplary embodiment, it is to be understood that the term "exemplary" is intended to be merely an example, rather than the best or optimum. Accordingly, the disclosure is intended to cover alternatives, modifications, and equivalents that may be included within the scope of the disclosure.Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternative and / or equivalent implementations could be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the specific embodiments discussed herein.

Claims

An output circuit (100) comprising: an output transistor (110) configured to provide an output signal; a gate switch (130) configured to decouple a gate of the output transistor (110) from other components of the output circuit (100) when there is a decrease in a supply voltage of the output circuit (100), wherein when the gate of the output transistor (110) is decoupled, a charge is maintained at the gate in a capacitor (C GS), which is inherently in the gate of the output transistor (110); and a reset controller (170) configured to reset the output signal after a predetermined reset time has elapsed after the gate switch (130) decouples the gate of the output transistor (110).The output circuit (100) of claim 1, further comprising: a charge pump (160) configured to provide a local supply voltage (V DDL) for controlling the gate switch (130) during a normal operation mode, wherein the local supply voltage is greater than the supply voltage.The output circuit (100) of claim 2, further comprising: a chip reset circuit (60) coupled to the output of the charge pump (160) and configured to drive the charge pump output to ground during the decrease of the supply voltage.The output circuit (100) according to any one of claims 1 to 3, wherein the reset controller (170) is further configured to output a reset signal to pull down the gate of the output transistor (110) after a predetermined reset time has elapsed.The output circuit (100) of claim 4, wherein the reset controller (170) is configured to output the reset signal in response to receiving a resistor-capacitor (RC) time signal.The output circuit (100) of claim 5, wherein the reset controller (170) comprises: a reset controller output transistor (310) configured to output the reset signal; a capacitor (330) configured to store a threshold voltage; and a discharge switch configured to turn on in response to receiving the RC timing signal to couple the capacitor (330) to a gate of the reset controller output transistor (310).The output circuit (100) of any of claims 1 to 6, further comprising: a passive pull-down circuit (180) coupled to the gate switch (130) and configured to drive the gate switch (130) to ground during the decrease of the supply voltage.The output circuit (100) according to any one of claims 1 to 7, further comprising: a slope controller (140) connected between a signal input of the output circuit (100) and the gate and configured to perform current charging and discharging on the gate.The output circuit (100) of claim 8, wherein the edge controller (140) comprises: a first current source (140-1) connected between a supply and the gate and configured to perform current charging on the gate when the signal input to the output circuit is high; and a second current source (140-2) connected between ground and the gate and configured to perform current discharging on the gate when the signal input to the output circuit is low.The output circuit (100) according to any one of claims 1 to 9, further comprising: a hard-on switch (150-1) connected between a regulated supply voltage and the gate and configured to be closed when a signal input to the output circuit is high; and a hard-off switch (150-2) connected between ground and the gate and configured to be closed when the signal input to the output circuit is low.The output circuit (100) of any of claims 1 to 10, further comprising: an inverting protection transistor (120) connected between an output node of the output circuit (100) and the output transistor (110) and configured to prevent an inverting current at the output node.Output circuit (100) according to one of Claims 1 to 11, wherein the output circuit (100) is designed to receive a sensor signal and to output the output signal.An output circuit (100) comprising: an output transistor (110) configured to provide an output signal; a gate switch (130) configured to decouple a gate of the output transistor (110) from other components of the output circuit (100) when there is a decrease in a supply voltage of the output circuit (100), wherein when the gate of the output transistor (110) is decoupled, a charge is maintained at the gate in a capacitor (C GS), which is inherently in the gate of the output transistor (110), and a reset controller (170) configured to output a reset signal to pull down the gate of the output transistor (110) after a predetermined reset time has elapsed.A circuit (500) comprising: the output circuit (100) according to any one of claims 1 to 13; and a memory (50) configured to store an RC time constant provided by a resistor and a capacitor within the circuit.A method (600) of operating an output circuit (100), the method comprising the steps of: providing (610) an output signal through an output transistor (110); and decoupling (620) a gate of the output transistor (110) from other components of the output circuit (100) through a gate switch (130) when there is a decrease in a supply voltage of the output circuit (100), wherein when the gate of the output transistor (110) is decoupled, a charge is maintained at the gate in a capacitor (CGS) inherent in the gate of the output transistor (110), and resetting the output signal through a reset controller (170) after a predetermined reset time has elapsed after decoupling the gate of the output transistor (110).The method (600) of claim 15, further comprising the step of: providing a local supply voltage for controlling the gate switch (130) by a charge pump (160) during a normal operating mode, wherein the local supply voltage is greater than the supply voltage.The method (600) according to any of claims 15 or 16, further comprising the step of: outputting, by a reset controller (170), a reset signal to pull down the gate of the output transistor (110) after a predetermined reset time has elapsed.The method (600) of any of claims 15 to 17, further comprising the step of: driving the gate switch (130) through a passive pulldown circuit (180) coupled to the gate switch (130) during the power supply voltage return to ground.The method (600) according to any of claims 15 to 18, further comprising the step of: charging and discharging the gate with current by an edge controller (140) connected between a signal input of the output circuit (100) and the gate.A method (600) of operating an output circuit (100), the method comprising the steps of: providing (610) an output signal through an output transistor (110); decoupling (620) a gate of the output transistor (110) from other components of the output circuit (100) through a gate switch (130) when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor (110) is decoupled, a charge at the gate is retained in a capacitor (C GS), which is inherently in the gate of the output transistor (110); and outputting a reset signal through a reset controller (170) to pull down the gate of the output transistor (110) after a predetermined reset time has elapsed.

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