METHOD FOR ADJUSTING A NEGATIVE CAPACITY IN GATE ELECTRODE STRUCTURES

Abstract

Procedure, comprehensive: a formation of a negative capacitor region (130NC; 230NC; 330NC) of a gate electrode structure (130; 230; 330) of a transistor element (150; 2250; 350), adjacent and capacitively coupled to a potential-free electrode region (130F; 230F; 330F) of the gate electrode structure (130; 230; 330); and Setting a negative capacitance of the negative capacitor region (130NC; 230NC; 330NC) by independently setting an effective capacitive area (130A; 230A; 330A) of a dielectric material (137; 237; 337) of the negative capacitor region (130NC; 230NC; 330NC) and a thickness (137T; 237T; 337T) of the dielectric material (137; 237; 337) with forming a side wall spacer (136; 236; 336) with a specified thickness (136W; 236W; 336W) in an opening (130O; 230O; 330O) which is an electrode material of the potential-free electrode region (130F; 230F; 330F) exposes, and a formation of the dielectric material (137; 237; 337) of the negative capacitor area (130NC; 230NC; 330NC) on the side wall spacer (136; 236; 336) which has the specified thickness (136W; 236W; 336W), and on a bottom of the opening (130O; 230O; 330O) such that a size of the opening (130O; 230O; 330O) is reduced, and further comprising filling the reduced-size opening (130O; 230O; 330O) with an electrode material (138, 139; 238, 239; 338, 339) of the negative capacitor region (130NC; 230NC; 330NC) after forming the dielectric material (137; 237; 337).

Claims

[1] Method comprising: forming a negative capacitor region (130NC; 230NC; 330NC) of a gate electrode structure (130; 230; 330) of a transistor element (150; 2250; 350), adjacent to and capacitively coupled to a floating electrode region (130F; 230F; 330F) of the gate electrode structure (130; 230; 330); and adjusting a negative capacitance of the negative capacitor region (130NC; 230NC; 330NC) by independently adjusting an effective capacitive area (130A; 230A; 330A) of a dielectric material (137; 237; 337) of the negative capacitor region (130NC; 230NC; 330NC) and a thickness (137T; 237T; 337T) of the dielectric material (137; 237; 337) with forming a sidewall spacer (136; 236; 336) with a specified thickness (136W; 236W; 336W) in an opening (130O; 230O; 330O) containing an electrode material of the potential-free electrode region (130F; 230F; 330F), and forming the dielectric material (137; 237; 337) of the negative capacitor region (130NC; 230NC; 330NC) on the sidewall spacer (136; 236; 336) having the specified thickness (136W; 236W; 336W) and on a bottom of the opening (130O; 230O; 330O) such that a size of the opening (130O; 230O; 330O) is reduced, and further comprising filling the reduced size opening (130O; 230O; 330O) with an electrode material (138, 139; 238, 239; 338, 339) of the negative capacitor region (130NC; 230NC; 330NC) after forming the dielectric material (137; 237; 337). [2] The method of claim 1, wherein independently adjusting the effective capacitive area (130A; 230A; 330A) of the dielectric material (137; 237; 337) of the negative capacitor region (130A; 230A; 330A) and the thickness (137T; 237T; 337T) comprises forming a sidewall spacer (136; 236; 336) having a specified thickness (136W; 236W; 336W) selectively on sidewalls of an opening (130O; 230O; 330O) exposing an electrode material of the floating electrode region (130F; 230F; 330F) such that a width of the opening (130O; 230O; 330O) is reduced, and Forming the dielectric material of the negative capacitor region (130NC; 230NC; 330NC) such that it extends to a predetermined height in the reduced-width opening (130O; 230O; 330O). [3] The method of claim 2, wherein forming the dielectric material (137; 237; 337) comprises filling the reduced width opening (130O; 230O; 330O) from bottom to top with the dielectric material (137; 237; 337) and removing a portion of the dielectric material (137; 237; 337) above the predetermined height. [4] The method of claim 3, further comprising removing a portion of the sidewall spacer (136; 236; 336) above the predetermined height. [5] The method of claim 2, further comprising forming an electrode material of the negative capacitor region (130NC; 230NC; 330NC) on the dielectric material (137; 237; 337). [6] The method of claim 1, wherein independently adjusting the effective capacitive area (130A; 230A; 330A) of the dielectric material (137; 237; 337) of the negative capacitor region (137; 237; 337) and the thickness comprises: forming an upper electrode material on sidewalls of an opening (130O; 230O; 330O) exposing a lower electrode material of the floating electrode region (130F; 230F; 330F) to reduce a size of the opening (130O; 230O; 330O), the upper electrode material extending to a predefined height; and forming a layer of the dielectric material (137; 237; 337) having the predetermined thickness in the reduced size opening (130O; 230O; 330O). [7] The method of claim 6, further comprising forming an electrode material of the negative capacitor region (130NC; 230NC; 330NC) on the layer of dielectric material (137; 237; 337). [8] The method of claim 1, further comprising replacing a portion of the negative capacitor region (130NC; 230NC; 330NC) with a dielectric capping material. [9] The method of claim 1, wherein the dielectric material (137; 237; 337) is manufactured to have ferroelectric behavior. [10] A method comprising: performing at least one first manufacturing process for adjusting an effective capacitive surface (130A; 230A; 330A) of a first and a second region of a gate electrode structure (130; 230; 330) of a transistor element (150; 250; 350), wherein the first and the second region are capacitively coupled to one another; performing at least one second manufacturing process for producing a dielectric material (137; 237; 337) of a predefined thickness, wherein an area of ​​the dielectric material (137; 237; 337) corresponds to the predetermined thickness of the effective capacitive surface (130A; 230A; 330A); and forming an opening (130O; 230O; 330O) in a dielectric interlayer material such that an electrode material of the first region of the gate electrode structure (130; 230; 330) is exposed; wherein performing at least a first manufacturing process comprises forming a dielectric sidewall spacer (136; 236; 336) on sidewalls of the opening (130O; 230O; 330O) such that a width of the opening (130O; 230O; 330O) is reduced to a first width, and wherein the at least one second manufacturing process comprises depositing the dielectric material (137; 237; 337) with the predefined thickness such that the first width of the opening (130O; 230O; 330O) is reduced to a second non-zero width. [11] The method of claim 10, wherein the dielectric material (137; 237; 337) comprises a ferroelectric material such that a negative capacitance is imparted to the second region of the gate electrode structure (130; 230; 330).

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