Multiple structuring method

Abstract

Multiple structuring process, comprising: Forming a dummy layer (30) over a substrate (20), the dummy layer (30) having a cut (32) therein, wherein a layer underlying and contacting the dummy layer (30) is a tetraethylorthosilicate, TEOS, layer; Forming a first sacrificial layer (34) over the dummy layer (30), wherein at least a portion of the first sacrificial layer (34) is disposed in the recess (32), and wherein the first sacrificial layer (34) is a layer of an oxide material and the oxide material is a polymer; Forming a second sacrificial layer (36) over the first sacrificial layer (34), wherein the second sacrificial layer (36) is a SiOC layer; Structuring the second sacrificial layer (36) to have a first structure; Structuring the first sacrificial layer (34) to have the first structure using the first structure of the second sacrificial layer (36); Removing the second sacrificial layer (36), wherein removing the second sacrificial layer (36) comprises etching the second sacrificial layer (36) using a combination of N2 gas, Ar gas, H2 gas, CF4 gas and CHF3 gas in a ratio of the flow volume velocities in a range of: 20 sccm to 100 sccm : 10 sccm to 100 sccm : 70 sccm to 200 sccm : 30 sccm to 150 sccm : 5 sccm to 80 sccm = N2:Ar:H2:CF4:CHF3; Forming a second structure in the first sacrificial layer (34) after removing the second sacrificial layer (36), comprising changing a dimension of the first structure of the first sacrificial layer (34); Structuring the dummy layer (30) using the second structure of the first sacrificial layer (34); Forming mask sections (44) along corresponding sidewalls of the patterned dummy layer (30); and Using the mask portions (44) to form a mask, the mask to be used during etching of a layer of the substrate (20).

Description

BACKGROUND

[0001] Double patterning is a lithography technology developed to improve element density in integrated circuits. Typically, lithography is used to form integrated circuit elements on wafers. Lithography involves applying a photoresist and defining patterns in the photoresist. The patterns in the photoresist are first defined in a lithography mask and realized either through the transparent or opaque areas of the lithography mask. The patterns in the lithography mask are transferred to the photoresist by irradiation using the lithography mask, followed by development of the photoresist. The patterns in the patterned photoresist are then transferred to the fabricated elements, which are formed on a wafer.

[0002] Various techniques have been developed to realize double or multiple patterning. One technique is a lithography-etch-lithography-etch (LELE) technique. In an LELE technique, a structure is generally divided into several parts to be realized, applying several lithography steps, each followed by etching steps. Another technique is a self-alignment technique. In a self-alignment technique, a structure is generally formed by forming a mandrel and spacers on sidewalls of the mandrel, where the spacers are the structure to be formed in the underlying substrate. The goal of these techniques is to reduce the width between adjacent elements, thereby increasing density.

[0003] US 2015 / 0140811 A1 discloses a method for patterning a semiconductor device. A photoresist with a light-sensitive layer is patterned using a photolithography process, wherein the patterned cover layer contains an opening.

[0004] US 2007 / 0161255 A1 discloses a method for processing a substrate in which a second resist material is formed from a first resist feature having a greater width than the second resist material.

[0005] US 2015 / 0064918 A1 discloses a method for controllable lateral etching of dielectrics during polymerization of fluorocarbon plasmas. DEMOLITION

[0006] The present invention is defined by the independent claims. Specific embodiments are defined by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when taken in conjunction with the accompanying figures. It should be noted that, in accordance with common practice in the art, various elements are not drawn to scale. Indeed, the dimensions of the various elements may be arbitrarily exaggerated or reduced for the purpose of clarity of description. Fig. 1A, Fig. 1B, Fig. 2A, Fig. 2B, Fig. 3A, Fig. 3B, Fig. 4A, Fig. 4B, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A and Fig. 13B are views of intermediate structures during respective stages of a method for forming conductive elements in a dielectric layer, for example, using a self-aligned double patterning technique, according to some embodiments. Fig. 14A and Fig. 14B is a flow diagram of a method for forming conductive elements in a dielectric layer, for example, using a self-aligned double patterning technique, according to some embodiments. DETAILED DESCRIPTION

[0008] In the following disclosure, many different embodiments or examples of implementing various features of the subject invention are presented. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for the purpose of simplification and clarity and does not, as such, determine any relationship between the various embodiments and / or configurations described.

[0009] Furthermore, for ease of description, spatial relationship terms such as "below," "under," "lower," "above," "above," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The devices may be differently oriented (rotated 90 degrees or have other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0010] Some embodiments described herein generally relate to one or more methods for patterning one or more layers on a semiconductor substrate and / or the semiconductor substrate itself. In general, a step of changing (e.g., reducing or trimming) a dimension of features on a patterned bottom layer may be performed, as described in more detail below. By changing the dimensions on the patterned bottom layer, a photoresist may maintain a higher aspect ratio, which in turn may enable more robust processing, thereby avoiding photoresist disintegration. Furthermore, by changing the dimensions on the patterned bottom layer, various other layers may be better protected from etching processes that might otherwise cause anomalies in structures or other features.

[0011] Some embodiments described herein are in the context of self-aligned double patterning (SADP). Other embodiments may be applied in other contexts, e.g., self-aligned quadruple patterning (SAQP) or other patterning techniques. Various multi-patterning technologies have been developed to exceed the physical resolutions achievable by conventional lithography. For example, self-aligned double patterning may be applied to create features with dimensions and sizes smaller than the physical resolution of conventional lithography. This may enable smaller devices and increased on-chip density.

[0012] Some variations of the exemplary methods and structures are described. Those skilled in the art will readily recognize other modifications that may be made and may be contemplated within the scope of other embodiments. Although method embodiments are described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than described herein.

[0013] Fig. 1A-B to 13A-B illustrate intermediate structures during respective stages of an exemplary method for forming conductive elements in a dielectric layer, for example, using a self-aligned double patterning technique, according to some embodiments. These figures show xyz axes to facilitate understanding of various viewing points in the figures. Also shown are Fig. 14a and Fig. 14b is a flowchart of the exemplary method for forming conductive elements in a dielectric layer, for example, using a self-aligned double patterning technique, according to some embodiments.

[0014] Fig. 1A and Fig. 1B illustrates an intermediate structure during processing. Fig. Figure 1A illustrates a cross-sectional view of the intermediate structure. Fig. 1B illustrates a top view of the Fig. 1A, where the cross section of the Fig. 1A is located on line AA. The intermediate structure comprises a semiconductor substrate 20. The semiconductor substrate 20 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. In general, an SOI substrate comprises a layer of semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, e.g., a multilayer substrate or a gradient substrate, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate may include silicon (Si); germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. Furthermore, the semiconductor substrate 20 is not limited to any particular size, shape, or materials. The semiconductor substrate 20 may be a round / circular substrate having a diameter of 200 mm, 300 mm, 450 mm, or other diameters. The semiconductor substrate 20 may also be any polygonal, square, rectangular, curved, or other non-circular workpiece, e.g., a polygonal glass substrate.

[0015] Above the semiconductor substrate 20 is a dielectric layer 22. The dielectric layer 22 may be located directly on the semiconductor substrate 20, or any number of other materials may be disposed between the dielectric layer 22 and the semiconductor substrate 20. For example, the dielectric layer 22 may be or comprise an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). For example, the dielectric layer 22 may be or comprise a low-k dielectric having a k value of less than about 4.0, e.g., about 2.0 or even less. In some examples, the dielectric layer 22 is or comprises phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y, spin-on glass, spin-on polymers, silicon-carbon material, a compound thereof, a composite thereof, or a combination thereof. The dielectric layer 22 may be deposited by chemical vapor deposition (CVD), e.g., plasma enhanced CVD (PECVD) or flowable CVD (FCVD); spin coating, or another deposition technique. In some examples, chemical mechanical planarization (CMP) or another planarization process may be performed to planarize the top surface of the dielectric layer 22. The dielectric layer 22 may, for example, have a thickness in a range of about 30 nm to about 70 nm.

[0016] Further, although not illustrated, an etch stop layer may be disposed in or beneath and adjacent to the dielectric layer 22. In general, an etch stop layer may provide a mechanism to halt an etch process when, for example, contacts or vias are being formed. An etch stop layer may be formed from a dielectric material having a different etch selectivity than adjacent layers, e.g., the dielectric layer 22. The etch stop layer may have a different etch selectivity and thus may be an etch stop for the etch process used to form recesses and / or openings in the dielectric layer 22 for conductive elements, as described herein. The etch stop layer may be conformally deposited over the semiconductor substrate 20 (and / or any intervening structures and layers formed thereover).The etch stop layer may comprise or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, the like, or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique.

[0017] Various devices may be located on the semiconductor substrate 20, which may be and / or become connected by the dielectric layer 22 and / or other dielectric layers. For example, the semiconductor substrate 20 may include field-effect transistors (FETs), e.g., fin FETs (FinFETs), planar FETs, vertical gate all-around FETs (VGAA FETs), horizontal gate all-around FETs (HGAA FETs), or the like; diodes; capacitors; inductors; and other devices. The devices may, for example, be formed entirely within the semiconductor substrate 20, in a portion of the semiconductor substrate and a portion of one or more overlying layers, and / or entirely within one or more overlying layers 20. The patterning described herein may be applied during processing, for example, to connect the devices to form an integrated circuit.The integrated circuit can be any circuit, e.g. for an application-specific integrated circuit (ASIC), a processor, a memory or another circuit.

[0018] As in Fig. 1A and Fig. 1B and in Operation 102 of the Fig. 14A, a mask stack is formed over the dielectric layer 22. The mask stack includes a first mask sublayer 24, a second mask sublayer 26, and a third mask sublayer 28. In other examples, the mask stack may be or include one layer or any number of different layers. The first mask sublayer 24 is located over the dielectric layer 22. The second mask sublayer 26 is located over the first mask sublayer 24. The third mask sublayer 28 is located over the second mask sublayer 26.

[0019] The first mask sublayer 24 may be or comprise an anti-reflective coating (ARC), e.g., a nitrogen-free anti-reflective coating (NFARC) (e.g., a silicon-rich oxide (SRO)), and may be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or another deposition technique. The first mask sublayer 24 may, for example, have a thickness in a range of about 2 nm to about 15 nm. The second mask sublayer 26 may be or comprise a nitride layer, e.g., titanium nitride (TiN), silicon nitride (SiN), tantalum nitride (TaN), the like, or a combination thereof, and may be formed by CVD, PVD, ALD, or another deposition technique. The second mask sublayer 26 may, for example, have a thickness in a range of approximately 20 nm to approximately 50 nm. The third mask sublayer 28 may be an oxide layer, e.g.B. Tetraethylorthosilicate (TEOS), the like, or a combination thereof, and can be formed by CVD, PVD, ALD, or another deposition technique. The third mask sublayer 28 can, for example, have a thickness in a range of about 10 nm to about 50 nm.

[0020] As in Fig. 1A and Fig. 1B and in Operation 104 of the Fig. 14A, a dummy mask layer 30 having a notch 32 is formed over the mask stack (e.g., over the third mask sublayer 28). The dummy mask layer 30 may be or comprise a silicon layer, e.g., an amorphous silicon layer, the like, or a combination thereof. The dummy mask layer 30 may be formed by CVD, PVD, ALD, or another deposition technique. The dummy mask layer 30 may, for example, have a thickness in a range from about 30 nm to about 70 nm.

[0021] The recess 32 (e.g., or opening) is formed through the dummy mask layer 30. The recess 32 may be formed by a suitable lithography technique and etching. For example, a photoresist may be formed on the dummy mask layer 30, e.g., by spin coating, and patterned by exposing the photoresist to light using a suitable photomask. Exposed or unexposed portions of the photoresist may then be removed, depending on whether a positive or negative resist is used. The pattern of the photoresist may then be transferred to the dummy mask layer 30, e.g., by a suitable etching process. The etching process may include reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic.The photoresist is then removed, for example, using an ashing and / or wet lift-off process. As will be apparent from the following figures and the description, the notch 32 corresponds to a region where some conductive elements formed in the dielectric layer 22 and laterally intersecting the notch 32 become discontinuous in the corresponding y-directions.

[0022] In the following figures, the semiconductor substrate 20, the dielectric layer 22, and the AA line may be omitted to prevent elements illustrated in these figures from becoming difficult to recognize. Those skilled in the art will readily understand that the semiconductor substrate 20 and the dielectric layer 22 are nevertheless present in the structures illustrated in these figures and will readily recognize the reference point of the AA line in these figures.

[0023] Fig. 2A and Fig. 2B illustrate the intermediate structure of the Fig. 1A and Fig. 1B after further processing. Fig. 2A and Fig. 2B illustrate a cross-sectional view and a top view, respectively, as in Fig. 1A and Fig. 1B. In Fig. 2A and Fig. 2B and Operation 106 of the Fig. 14A, a lower layer 34 (e.g., a sacrificial layer) is formed over the dummy mask layer 30 and in the trench 32. The lower layer 34 may be or include a hard mask material, e.g., a carbonaceous material, and may be formed by spin coating, CVD, PVD, ALD, or another deposition technique. In one example, the lower layer is a polymer material, e.g., an oxide, formed by spin coating. In some examples, the lower layer 34 may be planarized after it is deposited, e.g., by CMP or another planarization technique. The lower layer 34 may, for example, have a thickness (e.g., in a region outside the trench 34) in a range of about 20 nm to about 150 nm.

[0024] Furthermore, Fig. 2A and Fig. 2B and Operation 108 of the Fig. 14A, a middle layer 36 (e.g., a sacrificial layer) is formed over the lower layer 34. The middle layer 36 may be or include another mask material, e.g., a carbonaceous material such as silicon oxycarbide (SiOC), and may be formed by CVD, PVD, ALD, or another deposition technique. In one example, the middle layer 36 is SiOC. The middle layer 36 may, for example, have a thickness in a range of about 10 nm to about 40 nm.

[0025] Furthermore, Fig. 2A and Fig. 2B and Operation 110 of the Fig. 14A, a photoresist 38 is formed over the middle layer 36, e.g., by spin coating, and is patterned by exposing the photoresist 38 to light using a suitable photomask. Exposed or unexposed portions of the photoresist may then be removed, depending on whether a positive or negative resist is used. Patterned line photoresist portions 38a-38e remain over the middle layer 36. Areas where portions of the photoresist 38 have been removed form line regions 40a-40d that expose corresponding portions of the middle layer 36. The line regions 40a-40d may each have a spacing (e.g., a dimension in an x-direction between adjacent patterned line photoresist portions 38a-38e), for example, in a range of about 10 nm to about 80 nm.The patterned line photoresist portions 38a-38e may each have an aspect ratio sufficient to resist disintegration of the patterned line photoresist portions 38a-38e during one or more subsequent etching processes. Each of the patterned line photoresist portions 38a-38e may have a height H and a width W, as illustrated for the patterned line photoresist portion 38b, and may further have an aspect ratio (e.g., of the height H to the width W) less than or equal to about 5.5, e.g., in a range of about 0.1 to about 5.

[0026] Fig. 3A and Fig. 3B illustrate the intermediate structure of the Fig. 2A and Fig. 2B after further processing. Fig. 3A and Fig. 3B illustrate a cross-sectional view and a top view, respectively, as in Fig. 2A and Fig. 2B. In Fig. 3A and Fig. 3B and Operation 112 of the Fig. 14A, an etching process is performed that transfers the pattern of the patterned line photoresist portions 38a-38e to the underlying middle layer 36. Areas where portions of the middle layer 36 have been removed similarly include line portions 40a-40d, which expose corresponding portions of the lower layer 34. The etching process may be any suitable etching process, such as RIE, NBE, the like, or a combination thereof. During this etching process, the patterned line photoresist portions 38a to 38e may each have an aspect ratio small enough to resist disintegration, e.g., an aspect ratio less than or equal to about 5.5, e.g., in a range of about 0.1 to about 5. Subsequently, the photoresist 38 (e.g., the photoresist portions 38a to 38e) may be removed, for example, in an ashing or wet lift-off process.

[0027] Fig. 4A and Fig. 4B illustrate the intermediate structure of the Fig. 3A and Fig. 3B after further processing. Fig. 4A and Fig. 4B illustrate a cross-sectional view and a top view, respectively, as in Fig. 3A and Fig. 3B. In Fig. 4A and Fig. 4B and Operation 114 of the Fig. 14A, an etching process is performed which transfers the pattern of the patterned middle layer 36 to the underlying lower layer 34. Regions where portions of the middle layer 36 have been removed similarly comprise the conductive portions 40a-40d, which expose corresponding portions of the dummy mask layer 30 and / or a portion of the lower layer 34 disposed in the recess 32. The etching process may be any suitable etching process, such as RIE, NBE, the like, or a combination thereof. The etching process may be controlled, e.g., timed, so that the portion of the lower layer 34 disposed in the recess 32 remains while portions of the dummy mask layer 30 are exposed, although the portion of the lower layer 34 disposed in the recess 32 may be etched to a depth below a top surface of the dummy mask layer 30.

[0028] Fig. 5A and Fig. 5B illustrate the intermediate structure of the Fig. 4A and Fig. 4B after further processing. Fig. 5A and Fig. 5B illustrate a cross-sectional view and a top view, respectively, as in Fig. 4A and Fig. 4B. In Fig. 5A and Fig. 5B and Operation 116 of the Fig. 14A, an etching process is performed that removes the patterned middle layer 36. The etching process may be any suitable etching process that is selective for etching the material of the patterned middle layer. For example, the etching process may be a plasma-based etch, such as an RIE, the like, or a combination thereof. In some examples, the etching process does not significantly etch the patterned bottom layer 34 and a portion of the bottom layer 34 disposed in the recess 32. In some examples, a selectivity ratio of the etching process between the middle layer 36 and the bottom layer 34 may be greater than one, greater than about ten, greater than about fifty (e.g., infinity), or other selectivities.In some examples, a ratio of the selectivity of the etching process between the middle layer 36 and the third mask sublayer 28 may be more than two, more than four, more than ten, more than one hundred, or have other selectivities.

[0029] In one example, the middle layer 36 is SiOC; the bottom layer 34 is a polymer oxide; the dummy mask layer 30 is amorphous silicon; and the third mask sublayer 28 is TEOS. In this example, a plasma etch may be used to remove the patterned middle layer 36. The plasma etch may include a combination of nitrogen (N2) gas, argon (Ar) gas, hydrogen (H2) gas, carbon tetrafluoride (CF4) gas, and fluoroform (CHF3) gas. For example, a ratio of the flow volume velocities of the gases in the combination may be in the ranges of (20 standard cubic centimeters per minute (sccm) to 100 sccm): (10 sccm to 100 sccm): (70 sccm to 200 sccm): (30 sccm to 150 sccm): (5 sccm to 80 sccm) (N2:Ar:H2:CF4:CHF3). In some embodiments, a ratio of volume velocities of N2:Ar:H2:(CF4+CHF3) is about 1:1:2:3.In this example, using this plasma etching, the etch rate of the middle layer 36 may be approximately 2.6 nm / s (26 angstroms per second (Å / s)); the etch rate of the bottom layer 34 may be approximately -112.7 pm / s (-1.127 Å / s); and the etch rate of the third mask sublayer 28 may be approximately 1.2573 nm / s (12.573 angstroms per second (Å / s)). Thus, in this example, the etch selectivity of the middle layer 36 relative to the bottom layer 34 may be high, e.g., infinity, and the etch selectivity of the middle layer 36 relative to the third mask sublayer 28 may be high, e.g., approximately 2.07.Therefore, in this example, if the portion of the lower layer 34 has been removed and / or has experienced some loss in the trench 32, the third mask sublayer 28 may not be significantly etched because the etch selectivity between the middle layer 36 and the third mask sublayer 28 during plasma etching may be higher than in other processes.

[0030] Fig. 6A and Fig. 6B illustrate the intermediate structure of the Fig. 5A and Fig. 5B after further processing. Fig. 6A and Fig. 6B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 5A and Fig. 5B. In Fig. 6A and Fig. 6B and Operation 118 of the Fig. 14A, dimensions of elements of the intermediate structure are changed. For example, an isotropic etch, which may be a plasma etch, may be performed which is selective for the material of the patterned lower layer 34 and which etches horizontal and vertical surfaces of the patterned lower layer 34 at substantially equal rates. Accordingly, in the illustrated example, corresponding lateral dimensions (e.g., in an x-direction) of patterned portions of the lower layer 34 may be reduced (e.g., trimmed) by twice a first dimension D1. Accordingly, when the lateral dimensions of the patterned portions of the lower layer 34 are reduced, corresponding lateral dimensions of the conduction regions 40a to 40d are increased by twice the first dimension D1 to obtain modified conduction regions 40a' to 40d' having a second dimension D2.The second dimension D2 is a distance between facing sidewalls of adjacent patterned portions of the lower layer 34. The first dimension D1 may, in some examples, be in a range from about 0.5 nm to about 3 nm, and the second dimension D2 may, in some examples, be in a range from about 1 nm to about 6 nm.

[0031] In addition, the portion of the lower layer 34 disposed in the recess 32 may be etched vertically by the first dimension D1. A top surface of the portion of the lower layer 34 disposed in the recess 32 may have a step difference D3 relative to a top surface of the dummy mask layer 30 that is greater than or equal to the first dimension D1. For example, if the portion of the lower layer 34 disposed in the recess 32 is etched vertically by the first dimension D1 during the etching process of the Fig. 4A to 4B and / or 5A to 5B has experienced some loss, the step difference D3 may be higher than the first dimension D1. In one example, where the lower layer 34 is a polymer oxide, a plasma etching process for the isotropic etching may be used, and the plasma etching may include a combination of oxygen (O2) gas, nitrogen (N2) gas, chlorine (Cl2) gas, and hydrogen bromide (HBr) gas in a ratio of 2:1:1:1 (O2:N2:Cl2:HBr). Other etching processes with different etch chemistries may also be used.

[0032] Fig. 7A and Fig. 7B illustrate the intermediate structure of the Fig. 6A and Fig. 6B after further processing. Fig. 7A and Fig. 7B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 6A and Fig. 6B. In Fig. 7A and Fig. 7B and Operation 120 of the Fig. 14B, an etching process is performed, which transfers the pattern of the patterned lower layer 34 to the underlying dummy mask layer 30 to form dummy mask lines 30a to 30e (see subsequent figures). Regions where portions of the dummy mask layer 30 have been removed similarly comprise the modified line regions 40a' to 40d', with the accommodation of the portion of the lower layer 34 that was disposed in the recess 32, exposing corresponding portions of the mask stack (e.g., the third mask sublayer 28) and / or the portion of the lower layer 34 that was disposed in the recess 32. The etching process may be any suitable etching process, such as RIE, NBE, the like, or a combination thereof.

[0033] Fig. 8A and Fig. 8B illustrate the intermediate structure of the Fig. 7A and Fig. 7B after further processing. Fig. 8A and Fig. 8B illustrate a cross-sectional view and a top view, respectively, as in Fig. 7A and Fig. 7B. In Fig. 8A and Fig. 8B and Operation 122 of the Fig. 14B, an ashing and / or etching process selective to the material of the lower layer 34 is performed to remove the remaining portions of the lower layer 34. The ashing and / or etching process may be a plasma-based process.

[0034] The dummy mask lines 30a to 30e (e.g., mandrels) remain above the mask stack. As illustrated, the dummy mask lines 30a to 30e extend longitudinally along y-directions. As a result of the cut 32 through the dummy mask layer 30, one or more dummy mask lines may be discontinuous in the longitudinal direction. For example, a first portion of a second dummy mask line 30b1 and a second portion of the second dummy mask line 30b2 do not extend through the cross-section represented by the line AA and in Fig. 8A. Thus, the second dummy mask line 30b is discontinuous. Similarly, for example, a first portion of a third dummy mask line 30c1 and a second portion of the third dummy mask line 30c2 do not extend through the cross section represented by line AA and shown in Fig. 8A. Thus, the second dummy mask line 30c is discontinuous. The first portions of the second and third dummy mask lines 30b1 and 30c1 are in the cross section of the Fig. 8A is shown in dashed lines to illustrate this discontinuity.

[0035] Fig. 9A and Fig. 9B illustrate the intermediate structure of the Fig. 8A and Fig. 8B after further processing. Fig. 9A and Fig. 9B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 8A and Fig. 8B. In Fig. 9A and Fig. 9B and Operation 124 of the Fig. 14B, a spacer layer 42 is formed on the dummy mask lines 30a to 30e and above the mask stack. The spacer layer 42 is conformally formed on the dummy mask lines 30a to 30e. The spacer layer 42 may be, for example, titanium oxide, a nitride such as silicon nitride, or another acceptable material, and may be formed by CVD, ALD, or another deposition technique. The spacer layer 42 may, for example, have a thickness in a range of about 5 nm to about 30 nm.

[0036] As already described, in the illustrated example, the notch 32 through the dummy mask layer 30 causes the second dummy mask line 30b and the third dummy mask line 30c to be discontinuous. Furthermore, the notch 32 forms respective sidewalls of the first and second portions of the second and third dummy mask lines 30b1, 30b2, 30c1, and 30c2 in an xz plane. For example, when a distance between sidewalls in the corresponding xz-planes of the first and second portions of the second dummy mask line 30b1 and 30b2 is less than or equal to twice a thickness of the spacer layer 42, the spacer layer 42 may merge between the first and second portions of the second dummy mask line 30b1 and 30b2 due to the formation of the spacer layer 42 at the sidewalls in the xz-planes, which is represented by a merging region 42b in Fig. 9A. Similarly, if a distance between sidewalls in the xz-planes of the first and second portions of the third dummy mask line 30c1 and 30c2 is, for example, less than or equal to twice a thickness of the spacer layer 42, the spacer layer 42 may merge between the first and second portions of the third dummy mask line 30c1 and 30c2, which may be defined by a merging region 42c in Fig. 9A is illustrated.

[0037] Fig. 10A and Fig. 10B illustrate the intermediate structure of the Fig. 9A and Fig. 9B after further processing. Fig. 10A and Fig. 10B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 9A and Fig. 9B. In Fig. 10A and Fig. 10B and Operation 126 of the Fig. 14B, an anisotropic etching process is performed, whereby lateral portions of the spacer layer 42 may be largely removed to form mask portions 44. The mask portions 44 remain after the anisotropic etching on sidewalls (e.g., in xz-planes and yz-planes) of the dummy mask lines 30a to 30e. Furthermore, the anisotropic etching exposes upper surfaces of the dummy mask lines 30a to 30e, and portions of the mask stack (e.g., the third mask sublayer 28) between the mask portions 44 that are not covered by a dummy mask line are also exposed. The anisotropic etching process may be any etching process, e.g., an RIE, NBE, the like, or a combination thereof.

[0038] Fig. 11A and Fig. 11B illustrate the intermediate structure of the Fig. 10A and Fig. 10B after further processing. Fig. 11A and Fig. 11B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 10A and Fig. 10B. In Fig. 11A and Fig. 11B and Operation 128 of the Fig. 14B, the dummy mask lines 30a to 30e are removed. The dummy mask lines 30a to 30e may be removed by a suitable etching process that is selective for the material of the dummy mask lines 30a to 30e, e.g., a wet etching process or a plasma-based etching process.

[0039] Fig. 12A and Fig. 12B illustrate the intermediate structure of the Fig. 11A and Fig. 11B after further processing. Fig. 12A and Fig. 12B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 11A and Fig. 11B. In Fig. 12A and Fig. 12B and Operation 130 of the Fig. 14B, the pattern of the mask portions 44 is transferred to the mask stack (e.g., the third mask sublayer 28, the second mask sublayer 26, and the first mask sublayer 24) and into the dielectric layer 22 to form recesses and / or openings in the dielectric layer 22. To form the recesses and / or openings in the dielectric layer 22, one or more etching techniques may be applied. For example, due to the different etch selectivities between the mask sublayers 28, 26, and 24 of the mask stack and the dielectric layer 22, a different etch chemistry may be used to transfer the pattern of the mask portions 44 to a different layer or sublayer.In some cases, the etching process used to etch into the dielectric layer 22 may further etch the dielectric layer 22, for example, until the etching process reaches an etch stop layer beneath and adjacent to the dielectric layer 22, as previously indicated. Although the mask portions 44 in . Fig. 12A and Fig. 12B are illustrated as remaining above the mask stack, the mask portions 44 and / or portions of the mask stack may be at least partially consumed by various etching processes applied in transferring the pattern of the mask portions 44 to the dielectric layer 22.

[0040] Fig. 13A and Fig. 13B illustrate the intermediate structure of the Fig. 12A and Fig. 12B after further processing. Fig. 13A and Fig. 13B illustrate a cross-sectional view and a plan view, respectively, as in Fig. 12A and Fig. 12B. In Fig. 13A and Fig. 13B and Operation 132 of the Fig. 14B, conductive portions 50 are formed in the dielectric layer 22. For example, a barrier layer, e.g., titanium nitride, tantalum nitride, or the like, may be deposited conformally in the recesses and / or openings (e.g., along sidewalls and bottom surfaces) in the dielectric layer 22, and a conductive material, e.g., a metal such as copper, tungsten, aluminum, gold, silver, an alloy thereof, the like, or a combination thereof, may be deposited on the barrier layer. The barrier layer may be deposited by any suitable deposition technique, e.g., ALD, CVD, the like, or a combination thereof, and the conductive material may also be deposited by a suitable deposition technique, e.g., PVD, CVD, ALD, the like, or a combination thereof. Any excess barrier layer and / or conductive material may be removed, e.g.,by a CMP to planarize upper surfaces of the barrier layer and the conductive material so that they are coplanar with the upper surface of the dielectric layer 22. If any of the mask portions 44 and the mask stack remain when the barrier layer and / or the conductive material are deposited, the CMP may also remove the mask portions 44 and the mask stack. After the CMP, conductive elements 50 remain, and the conductive elements may be or include conductive lines (e.g., metal lines), conductive vias, and / or conductive contacts. Although in . Fig. 13A, the semiconductor substrate 20 is located under the dielectric layer 22.

[0041] One or more additional dielectric layers may be formed over the dielectric layer 22. Each of the one or more additional dielectric layers may have various conductive elements formed therein, where the conductive elements may further connect devices formed on the semiconductor substrate 20 to form the integrated circuit. These conductive elements may be formed via patterning, as described above for patterning the dielectric layer 22, or via other patterning techniques. Patterning as described herein and / or patterning within the scope of various embodiments may be applied to each interlayer dielectric (ILD) layer and intermetallization dielectric (IMD) layer in the integrated circuit.In addition, some embodiments may be realized in the context of any suitable multi-patterning, e.g., self-aligned quadruple patterning (SAQP).

[0042] Although some embodiments described herein are related to the formation of conductive elements 50 in the dielectric layer 22, some embodiments implementing aspects described herein may be applied to form structures in the semiconductor substrate 20. Example structures may include fins or isolation zone definitions. These structures may be used to form devices on the semiconductor substrate 20. For example, the mask stack (e.g., the first mask sublayer 24, the second mask sublayer 26, and the third mask sublayer 28) may be formed directly on the semiconductor substrate 20 or formed with other layers therebetween. The mask stack may be patterned as described herein, and the mask stack may be used to pattern the semiconductor substrate 20, for example, with fins.The fins may be included in the active regions of FinFETs for some devices formed on the semiconductor substrate 20, in some examples.

[0043] Advantages may be obtained by some embodiments. In some examples, conductive lines (e.g., metal lines) with line cuts or discontinuities with small element sizes and / or small separation distances may be obtained. Furthermore, for example, by changing dimensions of the patterned lower layer 34 in the method as described in Fig. 6A and Fig.6B, for example, in contrast to earlier in the process, a risk of patterned elements falling apart, e.g., the photoresist portions 38a to 38e falling apart, may be reduced or eliminated. A falling apart of patterned elements could lead to pattern anomalies (e.g., a wavy line or a broken line) in the dielectric layer 22, and by reducing a risk of patterned elements falling apart, occurrences of pattern anomalies in the dielectric layer 22 may be reduced or eliminated. Also, the unintentional undercutting or underetching of a layer, e.g., in the zone where the notch 32 was formed, may be avoided in the process of forming the mask portions 44 when applying some etching methods described herein, and in other etching methods within the scope of the present disclosure.By increasing etch selectivities when etching different layers, inadvertent undercutting or underetching of a layer can be prevented. Some embodiments may be particularly advantageous at smaller technology nodes, e.g., 7 nm, 5 nm, and below, to enable more robust processing at these smaller technology nodes.

[0044] One embodiment is a multiple patterning method. A dummy layer is formed over a substrate. The dummy layer has a notch therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the notch. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. After removing the second sacrificial layer, a second pattern is formed in the first sacrificial layer, comprising changing a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned.Mask sections are formed along corresponding sidewalls of the patterned dummy layer. The mask sections are used to form a mask, and the mask is to be used during the etching of a layer of the substrate.

[0045] Another embodiment is a self-aligned multi-patterning process. A dummy layer is formed over a dielectric layer, and the dummy layer has a trench therein. The dielectric layer is disposed over a substrate. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the trench. A patterned second sacrificial layer is formed over the first sacrificial layer. Using the patterned second sacrificial layer, the first sacrificial layer is patterned. The patterned second sacrificial layer is removed, comprising etching the patterned second sacrificial layer.The etching of the patterned second sacrificial layer has a first etch selectivity ratio between the patterned second sacrificial layer and the first sacrificial layer that is higher than 10, and the etching of the patterned second sacrificial layer has a second etch selectivity ratio between the patterned second sacrificial layer and a layer underlying and contacting the dummy layer that is higher than 2. After removing the patterned second sacrificial layer, corresponding lateral dimensions of portions of the patterned first sacrificial layer are reduced. After reducing the corresponding lateral dimensions, the dummy layer is patterned using the patterned first sacrificial layer. Mask portions are formed along corresponding sidewalls of the patterned dummy layer.The mask sections are used to form a mask, and the mask is to be used during etching in the dielectric layer.

[0046] Another embodiment is a self-aligned multi-patterning method. A mask stack is formed over a dielectric layer, and the dielectric layer is disposed over a semiconductor substrate. A dummy layer is formed over the mask stack, and the dummy layer has a cut therein. A first sacrificial layer is formed over the dummy layer, and a cut portion of the first sacrificial layer is disposed in the cut. A patterned second sacrificial layer is formed over the first sacrificial layer. Using the patterned second sacrificial layer, the first sacrificial layer is patterned. The patterned second sacrificial layer is removed, comprising etching the patterned second sacrificial layer.The etching of the patterned second sacrificial layer has a first etch selectivity ratio between the patterned second sacrificial layer and the first sacrificial layer that is higher than 10, and the etching of the patterned second sacrificial layer has a second etch selectivity ratio between the patterned second sacrificial layer and a layer of the mask stack contacting the dummy layer that is higher than 2. After removing the patterned second sacrificial layer, the patterned first sacrificial layer is isotropically etched. After isotropically etching the patterned first sacrificial layer, at least a portion of the cut portion of the first sacrificial layer remains in the cut, and the patterned first sacrificial layer comprises the at least existing portion of the cut portion.After isotropic etching of the patterned first sacrificial layer, the dummy layer is patterned using the patterned first sacrificial layer. Mask sections are formed along corresponding sidewalls of the patterned dummy layer. Using the mask sections, a mask is formed from the mask stack, and the mask is to be used during etching in the dielectric layer.

Claims

[1] Multiple structuring process, comprising: Forming a dummy layer (30) over a substrate (20), the dummy layer (30) having a cut (32) therein, wherein a layer underlying and contacting the dummy layer (30) is a tetraethylorthosilicate, TEOS, layer; Forming a first sacrificial layer (34) over the dummy layer (30), wherein at least a portion of the first sacrificial layer (34) is disposed in the recess (32), and wherein the first sacrificial layer (34) is a layer of an oxide material and the oxide material is a polymer; Forming a second sacrificial layer (36) over the first sacrificial layer (34), wherein the second sacrificial layer (36) is a SiOC layer; Structuring the second sacrificial layer (36) to have a first structure; Structuring the first sacrificial layer (34) to have the first structure using the first structure of the second sacrificial layer (36); Removing the second sacrificial layer (36), wherein removing the second sacrificial layer (36) comprises etching the second sacrificial layer (36) using a combination of N2 gas, Ar gas, H2 gas, CF4 gas and CHF3 gas in a ratio of the flow volume velocities in a range of: 20 sccm to 100 sccm : 10 sccm to 100 sccm : 70 sccm to 200 sccm : 30 sccm to 150 sccm : 5 sccm to 80 sccm = N2:Ar:H2:CF4:CHF3; Forming a second structure in the first sacrificial layer (34) after removing the second sacrificial layer (36), comprising changing a dimension of the first structure of the first sacrificial layer (34); Structuring the dummy layer (30) using the second structure of the first sacrificial layer (34); Forming mask sections (44) along corresponding sidewalls of the patterned dummy layer (30); and Using the mask portions (44) to form a mask, the mask to be used during etching of a layer of the substrate (20). [2] The multiple patterning method according to claim 1, further comprising: Forming at least one mask layer (24, 26, 28) over the layer of the substrate (20), wherein the dummy layer (30) is formed over the at least one mask layer (24, 26, 28); Forming the mask from the at least one mask layer (24, 26, 28) using the mask sections (44); and Etching the layer of the substrate (20) using the mask. [3] The multiple patterning method of claim 1 or 2, wherein changing the dimension of the first pattern of the first sacrificial layer (34) comprises increasing a lateral distance between adjacent portions of the first sacrificial layer (34) and decreasing a lateral dimension of at least a portion of the first sacrificial layer (34). [4] A multiple patterning method according to any one of the preceding claims, wherein changing the dimension of the first pattern of the first sacrificial layer (34) comprises performing an isotropic etching process. [5] A multiple patterning method according to any one of the preceding claims, wherein forming the mask portions (44) along the respective sidewalls of the patterned dummy layer (30) comprises: shape-adapted deposition of a spacer layer (42) along the structured dummy layer (30); and anisotropic etching of the spacer layer (42). [6] The multiple patterning method of any preceding claim, wherein removing the second sacrificial layer (36) comprises etching the second sacrificial layer (36), the etching having an etch selectivity ratio between the second sacrificial layer (36) and the first sacrificial layer (34) that is higher than 10. [7] The multiple patterning method according to any one of the preceding claims, wherein removing the second sacrificial layer (36) comprises etching the second sacrificial layer (36), the etching having an etch selectivity ratio between the second sacrificial layer (36) and a layer underlying and contacting the dummy layer (30) that is higher than 2. [8] The multiple patterning method of any preceding claim, wherein: wherein patterning the first sacrificial layer (34) comprises controlling an etching process such that the portion of the first sacrificial layer (34) disposed in the recess (32) remains. [9] Multiple structuring method according to one of the preceding claims, further comprising: Etching the layer of the substrate (20) to form at least recesses using the mask; Forming respective conductive lines in the at least one recesses, wherein at least one of the conductive lines crosses a zone corresponding to the notch (32) in the dummy layer (30), wherein the at least one of the conductive lines is discontinuous at the zone. [10] Self-aligned multi-patterning method comprising: Forming a dummy layer (30) over a dielectric layer (22), the dummy layer (30) having a cut (32) therein, the dielectric layer (22) being over a substrate (20); Forming a first sacrificial layer (34) over the dummy layer (30), wherein at least a portion of the first sacrificial layer (34) is disposed in the recess (32), wherein the first sacrificial layer (34) is a layer of an oxide material, wherein the oxide material is a polymer; Forming a patterned second sacrificial layer (36) over the first sacrificial layer (34), wherein the patterned second sacrificial layer (36) is a SiOC layer; Structuring the first sacrificial layer (34) using the structured second sacrificial layer (36); Removing the structured second sacrificial layer (36), comprising etching the structured second sacrificial layer (36), wherein the etching of the structured second sacrificial layer (36) has an etch selectivity ratio between the structured second sacrificial layer (36) and the first sacrificial layer (34) that is higher than 10, wherein the etching of the structured second sacrificial layer (36) has an etch selectivity ratio between the structured second sacrificial layer (36) and a layer that lies beneath and contacts the dummy layer (30) that is higher than 2, wherein the layer that lies beneath and contacts the dummy layer (30) is a tetraethylorthosilicate, TEOS, layer, and wherein, in the etching of the structured second sacrificial layer (36), a combination of N2 gas, Ar gas, H2 gas,CF4 gas and CHF3 gas in a ratio of flow volume velocities in a range of: 20 sccm to 100 sccm : 10 sccm to 100 sccm : 70 sccm to 200 sccm : 30 sccm to 150 sccm : 5 sccm to 80 sccm = N2:Ar:H2:CF4:CHF3 is used;, Reducing corresponding lateral dimensions of portions of the patterned first sacrificial layer (34) after removing the patterned second sacrificial layer (36); Structuring the dummy layer (30) using the structured first sacrificial layer (34) after reducing the corresponding lateral dimensions; forming mask sections along corresponding sidewalls of the structured dummy layer (30); and Using the mask portions (44) to form a mask, the mask to be used during etching in the dielectric layer (22). [11] The self-aligned multi-patterning method according to claim 10, further comprising: Forming a mask stack over the dielectric layer (22), wherein the dummy layer (30) is formed over the mask stack; Forming the mask from the mask stack using the mask sections (44); and Etching the dielectric layer (22) using the mask. [12] The self-alignment multi-patterning method according to claim 10 or 11, wherein forming the mask portions (44) along the respective sidewalls of the patterned dummy layer (30) comprises: shape-adapted deposition of a spacer layer (42) along the structured dummy layer (30); and anisotropic etching of the spacer layer (42). [13] The self-aligned multi-patterning method of any one of the preceding claims 10 to 12, wherein patterning the first sacrificial layer (34) comprises controlling an etching process such that the portion of the first sacrificial layer (34) disposed in the recess (32) remains. [14] Self-aligned multi-patterning method according to one of the preceding claims 10 to 13, further comprising: Etching in the dielectric layer (22) to form at least recesses using the mask; Forming respective conductive lines in the at least one recesses, wherein at least one of the conductive lines crosses a zone corresponding to the notch (32) in the dummy layer (30), wherein the at least one of the conductive lines is discontinuous at the zone. [15] The self-aligned multi-patterning method of any one of the preceding claims 10 to 14, wherein reducing the respective lateral dimensions of the portions of the patterned first sacrificial layer (34) comprises isotropic etching of the patterned first sacrificial layer (34). [16] Self-aligned double patterning method comprising: Forming a mask stack over a dielectric layer (22), wherein the dielectric layer (22) is located over a semiconductor substrate (20); Forming a dummy layer (30) over the mask stack, the dummy layer (30) having a notch (32) therein; Forming a first sacrificial layer (34) over the dummy layer (30), wherein a cut portion of the first sacrificial layer (34) is disposed in the cut (32), and wherein the first sacrificial layer (34) is a layer of an oxide material, the oxide material being a polymer; Forming a patterned second sacrificial layer (36) over the first sacrificial layer (34), the patterned second sacrificial layer (36) being a SiOC layer; Structuring the first sacrificial layer (34) using the structured second sacrificial layer (36); Removing the structured second sacrificial layer (36), comprising etching the structured second sacrificial layer (36), wherein the etching of the structured second sacrificial layer (36) has a first etch selectivity ratio between the structured second sacrificial layer (36) and the first sacrificial layer (34) that is higher than 10, wherein the etching of the structured second sacrificial layer (36) has a second etch selectivity ratio between the structured second sacrificial layer (36) and a layer of the mask stack that contacts the dummy layer (30) that is higher than 2, wherein the layer of the mask stack that contacts the dummy layer (30) is a tetraethylorthosilicate, TEOS, layer, and wherein, in the etching of the structured second sacrificial layer (36), a combination of N2 gas, Ar gas, H2 gas,CF4 gas and CHF3 gas are used in a ratio of flow volume velocities in a range of 20 sccm to 100 sccm : 10 sccm to 100 sccm : 70 sccm to 200 sccm : 30 sccm to 150 sccm : 5 sccm to 80 sccm = N2:Ar:H2:CF4:CHF3;, isotropic etching of the structured first sacrificial layer (34) after removing the structured second sacrificial layer (36), wherein after isotropic etching of the structured first sacrificial layer (34) at least a portion of the cut portion of the first sacrificial layer (34) remains in the cut (32), wherein the structured first sacrificial layer (34) comprises at least the portion of the cut portion; Structuring the dummy layer (30) using the structured first sacrificial layer (34) after isotropic etching of the structured first sacrificial layer (34); forming mask sections along corresponding sidewalls of the structured dummy layer (30); and Forming a mask from the mask stack using the mask sections (44), the mask to be used during etching in the dielectric layer (22). [17] The self-alignment double patterning method of claim 16, wherein forming the mask portions (44) along the respective sidewalls of the patterned dummy layer (30) comprises: shape-adapted deposition of a spacer layer (42) along the structured dummy layer (30); and anisotropic etching of the spacer layer (42). [18] The self-aligned double patterning method of claim 16 or 17, wherein patterning the first sacrificial layer (34) comprises controlling an etching process such that the portion of the first sacrificial layer (34) disposed in the recess (32) remains. [19] Self-aligned double patterning method according to one of the preceding claims 16 to 18, wherein: the layer of the mask stack that contacts the dummy layer (30) is a tetraethylorthosilicate, TEOS, layer; and is not etched through the TEOS layer before the mask is formed. [20] The self-aligned double patterning method according to any one of the preceding claims 16 to 19, wherein the patterned second sacrificial layer (36) comprises separate line portions (40a) of the patterned second sacrificial layer (36).

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