Silicon carbide semiconductor device with trench-gate structure and a source region in an upper area of ​​a mesa section.

Abstract

Semiconductor device comprising: trench-gate structures (150) extending from a front face into a silicon carbide region (100); a source region (110) formed in an upper region of a mesa section (180) of the silicon carbide region (100) between the trench-gate structures (150); and a gate-controlled channel region (120) in the mesa section (180), wherein the gate-controlled channel region (120) is adjacent to the source region (110) and is configured to deplete completely within absolute maximum nominal values ​​of the semiconductor device (500), wherein i) the gate-controlled channel region (120) forms a first junction (j1) with the source region (110) and the first junction (j1) is an n+ / n junction or a p+ / p junction; orii) the gate-controlled channel region (120) forms a first transition (j1) with the source region (110) and the first transition (j1) is an n+ / i transition or a p+ / i transition;oriii) the gate-controlled channel region (120) forms a first transition (j1) with the source region (110) and the first transition (j1) is a pn transition, wherein an upper limit of a width of the mesa section (180) is defined by a depletion width Wdep as follows: Wdep=4εSiCε0kTln(NA / ni)e2NA where εSiC is the relative permittivity of the silicon carbide region (100), ε0 is the vacuum permittivity, e is the elementary charge, ni is the intrinsic carrier density of SiC, NA is the doping concentration in the gate-controlled channel region (120), and T is the temperature.

Description

BACKGROUNDIn vertical power semiconductor devices, a load current flows between a first surface on a front side and a second surface on the back side of a semiconductor die. Since the field strength of a dielectric breakdown in silicon carbide is significantly higher than in silicon, silicon carbide semiconductor devices having the same voltage blocking capability may be significantly thinner than equivalent silicon devices. Consequently, silicon carbide semiconductor devices may combine high breakdown voltages of more than 600 V with a significantly lower on-resistance RDSonthan their counterparts of silicon. Due to a comparatively thin drift zone, the comparatively low charge carrier mobility in the channel region predominates in the on-resistance of vertical silicon carbide devices at least for voltage classes with reverse voltages of up to 1200 V. Reference is made by way of example to the disclosure content in the publications DE 10 2014 119 465 B3 and U.S. Pat. No. 7,265,415 B2.There is a need for vertical semiconductor devices that combine high dielectric breakdown field strength materials with a low RDSon.SUMMARYThe invention is defined in claim 1. Further developments are the subject matter of the dependent patent claims. Embodiments of the present disclosure relate to a semiconductor device including trench gate structures extending from a front side into a silicon carbide region. A source region is formed in an upper region of a mesa portion of the silicon carbide region between the trench gate structures. In the mesa portion, a gate-controlled channel region adjoins the source region. The gated channel region is configured to fully depletion within absolute maximum ratings of the semiconductor device.Further embodiments are described in the claims and in the following detailed description. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the present embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate the present embodiments and together with the description serve to explain principles of the embodiments. Other embodiments and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. FIG. 1A is a schematic horizontal cross-sectional view of a portion of a vertical power semiconductor device having trench gate structures, a vertical channel and a fully depleted channel region, according to an embodiment. FIG. 1B is a schematic vertical cross-sectional view of the semiconductor device portion of FIG. 1A along a line B-B. FIG. 2A is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment with respect to a JFET structure below the trench gate structures. FIG. 2B is a schematic vertical cross-sectional view of the semiconductor device portion of FIG. 2A along a line B-B. FIG. 3A is a schematic vertical cross-sectional view of a portion of a semiconductor device including a JFET structure according to an embodiment regarding an electrical connection between a JFET structure and a source terminal. FIG. 3B is a schematic horizontal cross-sectional view of the semiconductor device portion of FIG. 3A along a line B-B in a plane of the JFET structure. FIG. 4A is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment with respect to a lightly doped channel region of the conductivity type of a drift zone and further with respect to vertically recessed stripe-shaped trench gate structures and stripe-shaped counter-doped regions extending orthogonally to the trench gate structures. FIG. 4B is a schematic horizontal cross-sectional view of the semiconductor device portion of FIG. 4A along a line B-B in a plane of the counter doped regions. FIG. 4C is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment with respect to p-doped mesa regions connecting a JFET structure to a source electrode. FIG. 4D is a schematic horizontal cross-sectional view of the semiconductor device portion of FIG. 4C along a line D-D in a plane of the counter doped regions. FIG. 5A is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment with respect to an intrinsic channel region and further with respect to laterally recessed upper portions of trench gate structures. FIG. 5B is a schematic horizontal cross-sectional view of the semiconductor device portion of FIG. 5A along a line B-B in a plane of gate controlled channel regions. FIG. 6A is a schematic horizontal cross-sectional view of a portion of a vertical power semiconductor device according to an embodiment with respect to contact plugs (JFET) structure. FIG. 6B is a schematic vertical cross-sectional view of the semiconductor device portion of FIG. 6A along a line B-B. FIG. 7A is a schematic horizontal cross-sectional view of a portion of a vertical power semiconductor device according to an embodiment with respect to a lightly doped channel region of the complementary conductivity type of a drift zone and further with respect to vertically recessed trench gate structures in combination with channel contact regions. FIG. 7B is a schematic vertical cross-sectional view of the semiconductor device portion of FIG. 7A along a line B-B.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used in or in conjunction with other embodiments to arrive at yet another embodiment. The present disclosure is intended to encompass such modifications and variations. The examples are described by means of a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are denoted by the same reference numerals in the different drawings, unless stated otherwise.The terms "have," "include," "comprise," "have," and the like are open ended terms, and the terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features. The indefinite articles and the definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.The term "electrically connected" describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" includes that one or more intervening elements suitable for signal transmission may be present between the electrically coupled elements, for example elements that may be controlled to temporarily provide a low impedance connection in a first state and a high impedance electrical decoupling in a second state.The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n -" means a doping concentration lower than the doping concentration of an "n" doping region, while an "n +" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.FIGS. 1A and 1B show a vertical semiconductor device 500 having a plurality of field effect transistor cells TC electrically connected in parallel, wherein a load current flows through two opposing main surfaces of the semiconductor device 500. In the transistor cells TC, the load current flow in field effect induced channels ("gated channels") is directed along a direction orthogonal to the main surfaces.The semiconductor device 500 may be or include, for example, an IGFET (insulated gate field effect transistor), for example a MOSFET (metal oxide semiconductor FET) in the usual sense including FETs with metal gates as well as FETs with gates of a semiconductor material, an IGBT (insulated gate bipolar transistor) or an MCD (MOS controlled diode).The transistor cells TC are formed along a first surface 101 at a front side of a silicon carbide portion 100 based on, for example, 2H-SiC (2H-polytype SiC), 6H-SIC or 15R-SiC. According to an embodiment, the semiconductor material may be silicon carbide of the 4H polytype (4H-SiC).The first surface 101 may be inclined to a principal crystal plane by an angle α to the axis, the absolute value of which may be at least 2° and at most 12°, e.g. about 4°, wherein the first surface 101 may be planar or may comprise parallel first surface portions which are displaced with respect to each other and inclined by the angle α to the axis to a horizontal central plane, and second surface portions which are inclined to the first surface portions and connect the first surface portions, such that a cross-sectional line of the first surface 101 approximates a sawtooth line. In the following, the term first surface 101 shall be understood as a horizontal planar surface or as the central plane of a toothed surface.A normal 104 to a planar first surface 101 or to a central plane of a toothed first surface 101 defines a vertical direction. Directions parallel to the planar first surface 101 or the central plane of a serrated first surface 101 are horizontal directions, and hereinafter referred to also as lateral directions.The silicon carbide portion 100 comprises a drift structure 130 formed between the transistor cells TC and a second surface 102 of the silicon carbide portion 100 at a back side, wherein the second surface 102 is parallel to the first surface 101. The drift structure 130 may include a highly doped base region 139 directly adjoining the second surface 102 and a weakly doped drift zone 131 between the transistor cells TC and the highly doped base region 139.Gate controlled channel regions 120, which have the same conductivity type as the drift zone 131, the complementary conductivity type or which may be intrinsic, vertically separate the drift zone 131 from source regions 110, which may extend from the first surface 101 into the silicon carbide region 100 and which have the conductivity type of the drift zone 131.The gated channel regions 120 directly adjoin the source regions 110 and may directly adjoin the drift structure 130. The interfaces between the gated channel regions 120 and the source regions 110 form first junctions j 1 between semiconductor materials having different doping and substantially equal band gaps, wherein a possible band gap difference mainly results from the different doping. The interfaces between the gated channel regions 120 and the drift structure 130, e.g. with the drift zone 131, may form second junctions j 2 between semiconductor materials having different doping and equal band gaps. The first and second junctions j 1, j 2 may be pn junctions or unipolar junctions, e.g. n - / n-type or p - / p-type junctions. The first and second junctions j 1, j 2 are horizontal and predominantly parallel to the first surface 101.The source regions 110 and the gated channel regions 120 are electrically connected to a first load terminal L 1 directly or via a low impedance path, wherein the first load terminal L 1 may be the anode terminal of an MCD, the source terminal of an IGFET or the emitter terminal of an IGBT.If the gated channel regions 120 have the same conductivity type as the source regions 110, the gated channel regions 120 are connected to the first load terminal L 1 through the source regions 110. Otherwise, an electrical connection between the gated channel regions 120 and the first load terminal L 1 may comprise a highly doped channel region of the conductivity type of the gated channel region 120.The drift structure 130 is electrically connected or coupled to a second load terminal L 2, which may be the cathode terminal of an MCD, the drain terminal of an IGFET or the collector terminal of an IGBT.Trench gate structures 150 extend from the first surface 101 into the silicon carbide region 100. The trench gate structures 150 may be stripes extending along a first horizontal direction 191, wherein the trench gate structures 150 sequentially alternate with mesa portions 180 of the silicon carbide portion 100 along a second horizontal direction 192 orthogonal to the first horizontal direction 191. The mesa sections 180 comprise the source regions 110 and the gated channel regions 120, wherein the source regions 110 are formed in upper regions of the mesa sections 180 along the first surface 101.The trench gate structures 150 include a conductive gate electrode 155 and a gate dielectric 159 dielectrically isolating the gate electrode 155 from the silicon carbide region 100. The gate electrode 155 may be electrically connected to a gate terminal G and may include highly doped polycrystalline silicon, nickel, platinum and / or gold. According to an embodiment, the gate electrode 155 is made of or contains a material combination having a work function in a range of 5.0 eV to 5.5 eV, e.g. about 5.25 eV, e.g. highly p-doped polycrystalline silicon.The gate dielectric 159 may isolate the gate electrode 155 from the mesa portions 180 or may completely isolate the gate electrode 155 from the silicon carbide region 100. The gate dielectric 159 may include, for example, at least one of deposited silicon oxide, thermal silicon oxide, silicon oxynitride, and silicon nitride. A first thickness d 1 of the gate dielectric 159 may be in a range from 3 nm to 20 nm, e.g. from 3 nm to 10 nm. According to other embodiments, the trench gate structures 150 may include one or more isolation dielectrics having a layer configuration and / or a layer thickness different from the gate dielectric 159, wherein the one or more isolation dielectrics may isolate the gate electrode 155 from the source region 110 and / or may be formed along a bottom of the trench gate structures 150.Along the second horizontal direction 192, the trench gate structures 150 may be arranged at regular intervals, wherein a center-to-center distance p 1 between adjacent trench gate structures 150 may be in a range from 100 nm to 5 μm, for example from 0.5 μm to 5 μm.Sidewalls of the mesa sections 180 may be at least approximately vertical to the first surface 101 or may be inclined to the normal 104 by an inclination angle greater than 0°. The mesa sidewalls may be parallel to each other or may taper as the distance from the first surface 101 increases and may be parallel to principal crystal planes or may be inclined to all principal crystal planes. For example, both mesa sidewalls may be parallel to (-1100) and (1-100) crystal planes or parallel to (11-20) and (-1-120) crystal planes. According to another embodiment, one of the mesa sidewalls may be parallel to the (11-20) crystal plane and the other mesa sidewall may be inclined to the first mesa sidewall.A first mesa width w 1 of the mesa sections 180 along the second horizontal direction 192 may be at most 50 nm, e.g. at most 40 nm or at most 30 nm. A vertical extension v 1 of the trench gate structures 150 may be in a range from (3*w1+3*d 1) to (20*w1+20*dl), wherein w 1 is the first mesa width and d 1 is the first thickness of the gate dielectric 159. For example, a vertical extension v 1 of the trench gate trenches 150 may be in a range from 0.1 μm to 5 μm, e.g. from 0.3 μm to 2 μm.A distance between the first and second junctions j 1, j 2 may be less than a vertical distance between a bottom of the trench gate structures 150 and the first junction j 1, such that the second junctions j 1 are formed between adjacent trench gate structures 150.The first mesa width w 1 of the mesa sections 180 along the second horizontal direction 192, a dopant concentration in the gated channel regions 120 and a material configuration of the trench gate structures 150 are selected such that for a first gate-source voltage VGS 1 within the absolute maximum ratings of the semiconductor device 500, the gated channel regions 120 are fully depleted ("fully depleted") of mobile charge carriers and such that for a positive second gate-source voltage VGS 2 within the absolute maximum ratings of the semiconductor device 500, the electric fields induced from opposite sides in the mesa sections 180 interact in a manner such that a bulk channel of charge carriers corresponding to the conductivity type of the source regions 110 is formed in the mesa sections 180.The absolute maximum ratings define a set of values of operating and ambient conditions applicable to any semiconductor device of a specific type as defined by its published specification data which should not be exceeded under the worst possible conditions.Instead of two spatially separated inversion layers along the interfaces to the trench gate structures 150 as in comparatively wide mesa structures, a single bulk channel is formed in each mesa section 180 at the second gate-source voltage VGS 2, wherein the bulk channel contains a charge carrier flow at least in a central region of the respective mesa section 180.In the case of an n-type source region 110, electrons form the bulk channel, and the gated channel regions 120 may be completely inversion ("volume inverted") or may be completely accumulation ("volume accumulated"), depending on the doping of the channel region 120. Where two maxima of a charge carrier density appear near the two mesa sidewalls in wide mesa structures, a single maximum of mobile charge carriers occurs near the center of the mesa section 180 in the case of a bulk channel.A mesa portion 180 is "fully inverted" or "volume inverted" if at least a portion of the mesa portion 180 is inverted from one adjacent trench gate structure 150 to the other adjacent trench gate structure 150. The phrase "completely in inversion" and "volume inverted" may include that end portions of mesa portion 180 are not completely in inversion. A transistor cell TC showing complete inversion in the sense defined above is of the volume inversion type.Electrons also form the bulk channel in the case of n-type source region 110 and n-type gate controlled channel regions 120. Formation of the bulk channels in the mesa sections 180 may begin at the center of each mesa section 180.Transistor cells with bulk channels provide minority charge carriers with significantly higher mobility in the on state of the semiconductor device 500. Provided instead of two separate, comparatively thin inversion layers along the trench gate structures 150, the entire mesa cross-section for the charge carrier flow results in a lower channel on-resistance. Since a high portion of the minority charge carriers flow at a distance from the trench gate structures 150, interfacial states and surface induced scattering effects along the gate dielectric 159 have only a small adverse influence on the charge carrier flow in the mesa portions 180.In the following, the operation mode of the semiconductor device 500 will be discussed in more detail with reference to n-channel transistor cells TC having an n-type source region 110 and an n-type drift zone 131. The gated channel regions 120 may be intrinsic, lightly p-doped, or lightly n-doped.The gate-source voltage VGSis defined as the electric potential difference applied between the gate electrode 155 and the source region 110 by an external voltage source. The applied gate voltage VGSadds to the built-in voltage V BI, which results from different work functions of the trench gate structures 150 and the gated channel regions 120. Fixed charge carriers located in the gate dielectric 159 and / or at the interface of the gate dielectric 159 may contribute to the built-in voltage V BI. The built-in voltage V BI causes, in the absence of an externally applied gate voltage VGS, i.e. for VGS=0V, depletion zones to extend laterally from the interfaces between the mesa portions 180 and the trench gate structures 150 into the intermediate gated channel regions 120, even if the channel region 120 has a doping of the same type as the drift zone 131.According to an embodiment, a first mesa width w 1, a dopant concentration N ch in the gated channel regions 120 and a material configuration of the trench gate structures 150 are selected such that for VGS=0 V the depletion zones extending from opposing trench gate structures 150 in the intermediate mesa portion 180 overlap and the gated channel regions 120 are completely depleted of mobile charge carriers.As the gate voltage VGSincreases, the electrostatic potential in the mesa portion 180 increases smoothly. At a gate voltage VGS larger than a threshold voltage Vth, a bulk channel is formed. In the case of p-type gate controlled channel regions 120, a volume inversion may become effective and form minority charge carriers gate controlled channels having a lateral width equal to the mesa width mw. In the case of n-type gate controlled channel regions 120, formation of bulk channels may begin at the center of the mesa portions 180. In the case of n-type gate controlled channel regions 120, volume accumulation may become effective and form electron gate controlled channels having a lateral width equal to the mesa width mw. The threshold voltage Vth is given by, among other things, the work functions of a gate electrode 155 and a gated channel region 120 and may be in a range of 0.2 V to 6 V, e.g., in a range of 0.3 V to 1.5 V.According to an embodiment, the silicon carbide portion 100 is one of 4H-SiC and 6H-SiC, the first mesa width w 1 is at most 50 nm, e.g. at most 40 nm or less than 30 nm, and an acceptor concentration N A in the gated channel region 120 is at most 1E 17 1 / cm 3, at most 1E 16 1 / cm 3 or at most 1E 15 1 / cm 3.The vertical charge carrier flow controlled by the gated channels vertically passes the drift zone 131 and reaches the second surface 102 at the back side of the silicon carbide portion 100.Equation (1) yields the width W dep of a depletion zone as a function of a surface potential ψ S and an acceptor concentration N A in the gated channel region 120:In Equation (1), ε SiC is the relative permittivity of the silicon carbide portion 100, e.g., ε SiC9,7, is ε 0 the vacuum permittivity is 8.85×10 -14 As / Vcm, and e is the elemental charge 1.6×10 -19 As. In inversion, the surface potential ψ S becomes equal to twice the bulk potential ψ b.In equation (2), k is the Boltzmann constant 1.38066×10 -23 J / K, T is the thermodynamic temperature, e.g., 300 K, Ln is the natural logarithm, and n i is the intrinsic carrier concentration at the thermodynamic temperature T. The intrinsic carrier density n i of SiC is about 1E-07 1 / cm 3 in 4H-SiC, and in 6H-SiC, about 1E-05 1 / cm 3. Equation (3) combines equations (1) and (2) and yields the depletion zone width W dep at V GS= 0.The depletion width Wdep inherently gives the upper limit for the first mesa width w 1 as a function of material properties, temperature, and acceptor concentration N A in the gated channel region 120.Table 1 below provides maximum values for the first mesa width w1for three different acceptor concentrations N A1, N A2 and N A3, with N A1= 1 E15 1 / cm 3, N A2= 1 E16 1 / cm 3 and N A3= 1 E17 1 / cm 3 for 4H-SiC and 6H-SiC. Table 1 Table 14H-SiC1677,59 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm542,42 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm175,22 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm6H-SiC1596,21 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm517,23 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm167,41 nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nmFor a given first mesa width w1and for a given net acceptor concentration N A the bulk potential and a voltage drop across the gate dielectric 159 are selected to achieve a threshold voltage Vthin a range of 2.5 V to 6 V, the threshold voltage Vthbeing given by equation (4).In Equation (4), V fb is the flat-band voltage (Flat-band voltage) given by the difference in work function between a gate electrode 155 and the gated channel region 120, and C GD is the capacitance of the gate dielectric 159. Table 2 below gives the bulk potential ψ b in volts for dopant levels N A1, N A2 and N A3 in 4H-SiC and 6H-SiC. Table 2 Table 24H-SiC2,622,742,866H-SiC2,382,502, 62For example, a p-type polycrystalline silicon gate electrode 155 may have a work function of 5.25 eV. The work function for n-type 4H-SiC may be 3.4 eV. The resulting flat band voltage V fb is about 1.85 V. According to equation (4), a flat band voltage V fb of 1.85 V results in a threshold voltage V th of about 4 V.If acceptor doping is omitted in the gated channel regions 120, i.e., for N A= 0, equation (4) reduces to equation (5):Without an address doping of the gated channel region 120, the threshold voltage becomes independent of the thickness of the gate dielectric 159, such that a first thickness d 1 of the gate dielectric 159 may be selected to adjust the voltage blocking capability of the semiconductor device 500.FIGS. 2A and 2B show a semiconductor device 500 including JFET structures with junction channel regions 132 in a vertical projection of the mesa portions 180.The JFET structures include counter-doped regions 160 between a bottom of the trench gate structures 150 and the drift zone 131. The JFET structures further include junction channel regions 132 between adjacent counter doped regions 160, the junction channel regions 132 being part of the drift structure 130. The transition channel regions 132 and the gated channel regions 120 form approximately vertical transitions. A minimum width w 2 of the transition channel regions 132 may be equal to or greater than the first mesa width w 1.A surface charge in the counter doped regions 160 may be in a range of 2E13 1 / cm 2 to 4E13 1 / cm 2 wherein a net net dopant concentration in the counter doped regions 160 may be in a range of 1E16 1 / cm 3 to 1E18 1 / cm 3, e.g. in a range of 5E16 1 / cm 3 to 5E17 1 / cm 3.The counter doped regions 160 and the junction channel regions 132 form additional pn junctions pnx. The counter-doped regions 160 may be electrically connected to the first load terminal L 1 (not shown in FIG. 2B ) or may be electrically connected to another, non-potential-free or potential-afflicted structure, the electrical potential of which may be fixed or may be switchable between at least two different potentials. Consequently, the additional pn junctions pnx may be reverse biased in a blocking state of the semiconductor device 500. Under reverse bias, depletion zones extend laterally from the vertical regions of the additional pn junctions pnx into the junction channel regions 132 and support the voltage blocking capability of the semiconductor device 500.A vertical extension v 2 of the counter-doped regions 160 may be sufficiently large to reduce the electric field strength effective at the bottom of the trench gate structures 150 to below the breakdown field strength of the gate dielectric 159, e.g. to at most 1 MV / cm. Equation (6) yields dE / dz, which indicates the change of an electric field strength per vertical unit length of a distance to the bottom of the trench gate structure 150, as a function of the relative permittivity ε SiC of the silicon carbide portion 100, the vacuum permittivity ε 0, the elemental charge e and the dopant concentration Ncd in the counter-doped regions.With ε SiC= 9,7, ε 0= 8,85 × 10 -14 As / Vcm, e = 1.6 × 10 -19 As and Ncd = 1E17 1 / cm 3 dE / dz is 1.8 MV / cm * 1 / μm. In other words, the electric field reduces by 1.8 MV / cm per 1 μm vertical extension of the counter-doped regions 160. For example, counter-doped regions 160 having a vertical extension v 2 of 1.5 μm reduce the electric field strength at the bottom of the trench gate structures 150 from 3.0 MV / cm to 0.3 MV / cm. The counter doped regions 160 may effectively shield the trench gate structures 150 and the gate dielectric 159 from the potential applied to the base region 139.The counter doped regions 160 may be formed by epitaxy. For example, an n-type precursor drift zone may be formed by epitaxy, trenches may be etched into the precursor drift zone and refilled by epitaxy, wherein in situ doping during epitaxy provides pillar-like counter doped p-type regions 160 having straight, approximately vertical sidewalls, and wherein remains of the precursor drift zone between adjacent p-type pillars form the junction channel regions 132. Alternatively or additionally, forming the counter doped regions 160 may include ion implantation using temporary implantation masks and / or gate trenches used as precursor structures of the trench gate structures 150.The semiconductor device 500 of FIGS. 3A and 3B is an IGFET and includes further details regarding the counter doped regions 160 and regarding load electrodes at the front side and at the back side of the silicon carbide portion 100.At the front side, the trench gate structures 150 include an upper dielectric 210 separating the gate electrode 155 from a first load electrode 310, which may form or may be electrically connected or coupled to a source terminal S. An upper surface of the trench gate structures 150 is recessed with respect to the first surface 101 of the silicon carbide portion 100. A source contact structure 315 fills the recess and directly adjoins sidewalls of the upper portion of the mesa sections 180 including the source regions 110.A second load electrode 320 may directly adjoin the second surface 102 and the base region 139. The second load electrode 320 may form or may be electrically connected to a drain terminal D.The counter doped regions 160 may be formed by epitaxy or ion implantation as described above, wherein the low diffusion coefficients of dopants in SiC may result in counter doped regions 160 that exhibit a mussel-like cross-section as the distance to the second surface 102 decreases as illustrated in FIG. 3A.The counter doped regions 160 may be electrically connected to the first load electrode 310. The gated channel regions 120 may have the same conductivity type and dopant concentration as the drift zone 131, such that no significant transition occurs between the first junction j 1 and the base region 139.The counter doped regions 160 may form stripes, wherein, according to FIG. 3B, the stripe shaped counter doped regions 160 may extend parallel to stripe shaped trench gate structures 150 extending along a first horizontal direction 191.FIGS. 4A and 4B show counter-doped regions 160 having a first portion 161 directly adjoining the trench gate structures 150 and having a second portion 162 directly adjoining the first portion 161 on the side oriented towards the second surface 102. The second portion 162 may be formed by epitaxy and / or ion implantation as described with respect to FIGS. 2A and 2B. The first portion 161 may be formed by ion implantation using gate trenches temporarily formed as precursor structures of the trench gate structures 150, wherein a lateral extension w 3 of the first portions 161 may be defined by a temporary spacer formed along vertical sidewalls of the gate trenches.At the front side, the trench gate structures 150 may be fully recessed below the first surface 101 such that after forming the upper dielectric 210, the source regions 110 protrude from a plane defined by the upper surface of the upper dielectric 210 such that source contact structures 315 laterally embed exposed portions of the source regions 110.In the gated channel regions 120, a net dopant concentration may be lower than in the transition channel regions 132 such that unipolar second n -- / n -- type junctions j 2 form in the mesa portions 180 between adjacent trench gate structures 150.The counter doped regions 160 may form stripes, wherein, according to FIG. 4B, at least the second portions 162 of the stripe shaped counter doped regions 160 which may result from ion implantation using an implantation mask and / or from epitaxial filling of trenches formed in an epitaxial layer may be inclined, e.g. orthogonal to the stripe shaped trench gate structures 150 extending along a first horizontal direction 191.A center-to-center distance p 2 of the second portions 162 is decoupled from the center-to-center distance p 1 of the trench gate structures 150. Decoupling the design parameters for the second portions 162 and the trench gate structures 150 allows for greater design flexibility and relaxes alignment processes.FIGS. 4C and 4D show an electrical connection between the first load electrode 310 and the counter doped regions 160 via p doped regions of the mesa portions 180.The counter doped regions 160 may be coupled to the source contact structures 315 via highly p-doped contact regions 110 aand p-doped mesa regions 120 aas shown in FIG. 4C, wherein the p-doped mesa regions 120 aand p-doped contact regions 110 amay be selectively formed in the vertical projection of the second portions 162 of the counter doped regions 160. Alternatively, the counter-doped regions 160 may be coupled to the source contact structures 315 via p-doped contact regions 110 aand p-type channels induced in a gated n-type channel region 120.FIGS. 5A and 5B show intrinsic gate controlled channel regions 120. Source contact structures 315 extend between upper regions of the trench gate structures 150 and upper regions of the mesa sections 180, such that the source contact structures 315 extend on two opposite sides of the upper regions of the mesa sections 180 including the source regions 110.The trench gate structures 150 may form a grid horizontally embedding the mesa portion 180 on all lateral sides. A second mesa width w 4 of the mesa portion 180 orthogonal to the first mesa width w 1 may be within the same order of magnitude as the first mesa width w 1. For example, the second mesa width w 4 is at most twice the first mesa width w 1. A horizontal cross-sectional area of the mesa section 180 may be a polygon, e.g. a quadrilateral, a hexagon or an octave with or without beveled or rounded corners, an oval or an ellipse, e.g. a circle.In FIGS. 6A to 6B, a second thickness d 2 of a separation dielectric 158 separating the gate electrode 155 from counter doped regions 160 at the bottom of the trench gate structures 150 is greater than the first thickness d 1 of the gate dielectric 159 between the gate electrode 155 and the mesa portion 180. For example, the second thickness d 2 of the separation dielectric 158 may be at least 150% of the first thickness d 1 of the gate dielectric 159, e.g. at least 50 nm.Additional contact structures 360 may extend from the first load electrode 310 into the silicon carbide region 100, wherein the additional contact structures 360 may directly adjoin the counter-doped regions 160. The additional contact structures 360 may be formed exclusively at one or both ends of the striped trench gate structures 150 in a connection region of the semiconductor device 500 outside a transistor cell region.According to the illustrative embodiment, the trench gate structures 150 and the additional contact structures 360 may alternate along the first horizontal direction 191, wherein a first contact insulator 251 may laterally separate the additional contact structure 360 from the mesa portion 180 and a second contact insulator 252 may separate the additional contact structure 360 from the gate electrode 155.The additional contact structure 360 may have a same layer and material configuration as the gate electrode 155 or may include materials also included in the first load electrode 310. For example, the additional contact structure 360 may include a silicide region 361 along the interface to the silicon carbide region 100, a metal liner 362 including at least one of titanium or tantalum, and a tungsten fill 363. Alternatively, the additional contact structure 360 may be formed of or may include a highly doped polycrystalline silicon.The gated channel regions 120 of the semiconductor device 500 of FIGS. 7A to 7B are a p-type, wherein the first and second junctions j 1, j 2 are pn junctions.Body contact regions 129 may extend from the first surface 101 into the silicon carbide region 100, wherein the body contact regions 129 directly adjoin the gated channel regions 120. The body contact regions 129 may be formed exclusively at one or both ends of each stripe-shaped mesa portion 180 in a connection region of the semiconductor device 500 outside a transistor cell region.According to the illustrated embodiment, the source regions 110 and the body contact regions 129 alternate along the first horizontal direction 191, wherein the first load electrode 310 alternately forms low-ohmic contacts with both the source regions 110 and the body contact regions 129. The body contact regions 129 may alternate with additional contact structures 360 along the second horizontal direction 192.Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that a variety of alternative and / or equivalent configurations may be utilized for the specific embodiments shown and described without departing from the scope of the present invention. This application is therefore intended to cover any adaptations or variations of the specific embodiments discussed herein.

Claims

A semiconductor device comprising: trench gate structures (150) extending from a front side into a silicon carbide region (100); a source region (110) formed in an upper region of a mesa portion (180) of the silicon carbide region (100) between the trench gate structures (150); and a gate controlled channel region (120) in the mesa portion (180), wherein the gate controlled channel region (120) borders the source region (110) and is configured to fully de-mininate within absolute maximum ratings of the semiconductor device (500), wherein i) the gate controlled channel region (120) forms a first junction (j1) with the source region (110) and the first junction (j1) is an n + / n junction or a p + / p junction; or ii) the gated channel region (120) forming a first junction (j1) with the source region (110) and the first junction (j1) is an n + / i-junction or a p + / i-junction; or iii) the gated channel region (120) forms a first junction (j1) with the source region (110) and the first junction (j1) is a pn-junction, wherein an upper limit of a width of the mesa portion (180) by a depletion width W dep is set as follows: W d e p = 4 ε S i C ε 0 k T ln (N A / n i ) e 2 N A where ε SiC is the relative permittivity of the silicon carbide region (100), ε 0 is the vacuum permittivity, e is the elemental charge, n i is the intrinsic carrier density of SiC, N A is the doping concentration in the gated channel region (120), and T is the temperature.The semiconductor device according to the preceding claim, wherein the gated channel region (120) separates the source region (110) from a drift structure (130), wherein the gated channel region (120) forms a second junction (j2) with the drift structure (130) and the second junction (j2) is an n - / n-junction or an i / n -- junction or a pn-junction.The semiconductor device according to claim 2, wherein the second junction (j2) is formed in the mesa portion (180).The semiconductor device of any of claims 1 to 3, further comprising: counter doped regions (160) between the trench gate structures (150) and a backside of the silicon carbide portion (100) opposite the front side, wherein the counter doped regions (160) form additional pn junctions (pnx) with a drift structure (130) adjoining the gated channel region (120).The semiconductor device of claim 4, wherein the drift structure (130) comprises a junction channel region (132) directly adjacent to the gated channel region (120) between the counter doped regions (160).The semiconductor device according to claim 5, wherein a horizontal minimum width (w2) of the junction channel region (132) is equal to or greater than a horizontal first mesa width (w1) of the mesa portion (180).The semiconductor device of any of claims 4 to 6, wherein the counter doped regions (160) directly adjoin the trench gate structures (150).The semiconductor device of any of claims 4 to 7, wherein the trench gate structures (150) are stripes extending along a first horizontal direction (191), and wherein the counter doped regions (160) are stripes extending parallel to the trench gate structures (150).The semiconductor device according to any of claims 4 to 7, wherein the trench gate structures (150) are stripes extending along a first horizontal direction (191), and wherein the counter doped regions (160) include stripe shaped second portions (162) extending along a second horizontal direction (192) orthogonal to the first horizontal direction (191).The semiconductor device according to any one of claims 4 to 7, wherein the trench gate structures (150) form a horizontal grid with the mesa portion (180) formed in a mesh of the horizontal grid.The semiconductor device of any of claims 4 to 10, wherein the trench gate structures (150) comprise a conductive gate electrode (155), a gate dielectric (159) separating the gate electrode (155) from the mesa portion (180), and a separation dielectric (158) separating the gate electrode (155) from the counter doped regions (160), wherein a second thickness (d2) of the separation dielectric (158) is greater than a first thickness (d1) of the gate dielectric (159).The semiconductor device according to any one of claims 1 to 11, wherein a first mesa width (w1) of the mesa portion (180) along the first horizontal direction (191) is at most 50 nm.The semiconductor device according to any one of claims 1 to 12, further comprising: a source contact structure (315) forming a low impedance interface with the source region (110) and directly adjoining a sidewall of the source region (110), wherein the sidewall is inclined to a horizontal plane.The semiconductor device of claim 13, wherein the source contact structure (315) laterally separates a top region of the mesa portion (180) from a top region of the trench gate structures (150).

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