Semiconductor package with a cavity

Abstract

Semiconductor packages, including: a first die which has a first and a second side wall, a first cavity having a first and a second side wall, each of which has a first dielectric material, a second dielectric material that directly contacts the first and second sidewalls of the first die, wherein the first and second dielectric materials have different material compositions, a first layer on the first die, which has a first metal compound and a third dielectric material, wherein (a) a first horizontal axis parallel to an upper surface of the first die and intersecting the first and second sidewalls of the first die, the first and second sidewalls of the first cavity and the second dielectric material, but not intersecting the first layer, and (b) a second horizontal axis intersecting the first metal compound and the third dielectric material.

Description

Technical field

[0001] Embodiments of the invention relate to electronic housings. background

[0002] Electronic products come in many forms. Mobile computing nodes include smartphones, tablet computers, and nodes integrated into the Internet of Things (IoT), which involves the networking of physical devices, media (also referred to as "connected devices" and "smart devices"), buildings, and other units embedded with electronics, software, sensors, actuators, and network connectivity, enabling these objects to collect and exchange data. Such computing nodes are typically small, with a trend toward progressively smaller sizes. This reduction in physical footprint involves the use of thin processors or unpackaged chips housed within thin packages.

[0003] Documents US 2007 / 0096292 A1, US 2016 / 0204067 A1 and US 2015 / 0262902 A1 describe known semiconductor devices. Brief description of the drawings

[0004] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the detailed description below of one or more exemplary embodiments, and the corresponding figures. Where deemed appropriate, reference designations have been repeated in the figures to indicate corresponding or analogous elements. Fig. Figure 1 shows an embodiment of a housing with a cavity for an unpacked chip. Fig. Figure 2 shows an embodiment of a housing with two cavities for two cubes or uncased chips. Although Fig. Figure 2 shows two cavities and two unpacked chips; other embodiments may have three or more cavities and unpacked chips. Fig. Figures 3(A) to (K) show a method for forming a housing in one embodiment. Fig. Figure 4 shows a method for forming a housing in one embodiment. Fig. Figure 5 shows a package-on-package (PoP) system in one embodiment. Fig. 6, Fig. 7 and Fig. 8 exhibit systems that accommodate embodiments. Detailed description

[0005] Reference is now made to the drawings, where identical structures may be provided with the same additional reference designations. To more clearly illustrate the structures of different embodiments, the drawings included here are schematic representations of semiconductor / circuit structures. Therefore, the actual appearance of the manufactured integrated circuit structures, for example in a micrograph, may differ, although it still incorporates the claimed structures of the depicted embodiments. Furthermore, the drawings may only show those structures that are useful for understanding the depicted embodiments. Additional structures known in the art may have been omitted to maintain the clarity of the drawings. For example, not every layer (e.g.,The barrier layer, nucleation layer, and etch stop layer of a semiconductor device are shown. Furthermore, connections may not be perfectly aligned in the figures, and other details may be omitted if the figure's focus is elsewhere, such as the presence of cavity 204' in [figure number]. Fig. 2 in contrast to the concrete design of connections in layer 209. Furthermore, not every step is included for processes, such as processes 300 and 400 in Fig. Figures 3(A) to (K) and 4 show that “one embodiment,” “different embodiments,” and the like indicate that the embodiment(s) described so may have certain features, structures, or properties, but that not every embodiment necessarily has to have those particular features, structures, or properties. Some embodiments may have some, some, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate that reference is being made to different instances of the same object. Such adjectives do not imply that the objects described so must be in a given sequence, whether temporal, spatial, hierarchical, or otherwise.“Connected” can indicate that elements are in direct physical or electrical contact with each other, and “coupled” can indicate that elements work together or interact with each other, but that they may or may not be in direct physical or electrical contact.

[0006] The applicant recognizes that certain problems must be overcome in the pursuit of a thinner enclosure. For example, "fan-out" enclosure systems present a key challenge.

[0007] In particular, fan-out wafer-level packaging (FOWLP) is a packaging technology that promotes package miniaturization. A technological aspect of FOWLP involves forming a reconfigured overmolded wafer combined with a thin-film redistribution layer (RDL). FOWLP improves high-frequency (RF) performance due to its implementation of comparatively shorter connections, including a direct connection to an integrated circuit (e.g., a printed circuit board) using thin-film metallization instead of wire bonds or flip-chip contact bumps, and lower parasitic effects.

[0008] The applicant has found that many fan-out packaging processes involve a "chip-first" packaging process at the wafer level. This involves taking a "proven-free" chip that has already been inspected and then placing the unpackaged chip into the initial stages of the packaging process. That unpackaged chip is then subjected to heat and stress as the process progresses to form a package. The heat and stress result in the loss of many proven-free chips, causing financial damage to chip and package manufacturers. In fact, the risks to the proven-free chip are not limited to heat and stress but generally include any processing errors during packaging that result in the loss of the proven-free chip as well as the loss of the entire package, which has a significant impact on costs.

[0009] However, the embodiments discussed here feature a low z-height (measured perpendicular to the horizontal principal plane in which the chip lies), high density, a coreless package architecture, and a "chip-last" package approach (where the proven-free chip is inserted into a cavity of the package much later in the package formation process), thereby reducing the risk of loss and lowering manufacturing costs. Such embodiments are suitable for package-on-package (PoP) and multi-chip package systems.

[0010] In particular, one embodiment of the "chip-last" approach involves inserting the unpackaged chip relatively later in the process, while first-level connections (through which the chip is coupled, for example, to another package of a PoP system) are fabricated relatively early in the process. The approach uses a removable material (e.g., a film) that creates a placeholder for an unpackaged chip. This placeholder can take the form of a cavity containing the removable sacrificial material. The sacrificial material is picked up early in the process and then removed later, at which point it is replaced by a demonstrably defect-free chip.

[0011] Fig. Figures 3(A) to (K) show a method 300 for forming a housing in one embodiment. Fig. Figure 4 shows a method 400 for forming an enclosure in one embodiment. These figures will now be discussed and describe a process sequence with peelable core panels that leads to the enclosure with a coreless architecture. Processes 300 and 400 are not identical and show how certain process steps can be optional and / or how the sequence of certain operational steps can be varied in different embodiments.

[0012] First, a peelable core panel is provided. Such a panel can contain Prepreg 350 (resin-impregnated fibers) and copper (Cu) 351. (See Fig. 3(A) and Fig. 4, Element 401). The core can comprise a variety of adhesive-based (inorganic / organic) cores, vacuum-based cores, thermally detachable cores, and the like. In one embodiment, this is performed at the panel level, not the wafer level (although in other embodiments it can be performed at the wafer level).

[0013] Secondly, a removable / sacrificial film 352 is applied to the core using a stencil, mask, or the like. (See Fig. 3(A) and Fig. 4, Element 403). Material 352 acts as a placeholder for the unpackaged chip, which will later replace Material 352 in the process. The placeholder material is then covered with a dielectric, such as a buildup material (BU) (e.g., ABF film), a solder mask material (SR material), an underfill material, and / or a film-like mold material 307 (depending on the package curvature requirements), so that Material 352 is flush with the placeholder material. (See Fig. 3(B) and Fig. 4, Element 404).

[0014] In one phase, the laminated material 307 can be drilled with a laser to create a PoP connection. This can be done early in the process (e.g., soon after the phase in Fig. 3(B)) or later in the process ((see Fig. 3(H)). The ability to laser-drill the 307 material and plate the connections opens up the possibility of achieving a closer spacing. For example, the through-hole drilling and electroplating processes in substrate fabrication are mature and can control the spacing by adjusting process conditions, tool sets, and the like. In fact, the PoP connections can be formed before the 307 material is applied. (See Fig. 4, Element 402). If, for example, a closer spacing is required, the PoP connections can be plated onto the core, and then the material 352 can be layered over the PoP connections, for example, using a lithographic through-hole plating process. Furthermore, the PoP connections can be separated after core separation ( Fig. 4, Fig. 409). See, for example, Process 300.

[0015] In the context of lithographic through-hole plating (LiV), LiV is a process that helps reduce fine traces and spacing, as well as the distances between features. This approach relies on plating the required features first and then applying a dielectric, rather than drilling through the dielectric and plating the vias and copper features. Embodiments that use LiV alignment to contact points (instead of laser-drilled via alignment) exhibit tighter alignment (as opposed to laser drilling), and consequently, the spacing is smaller due to a lower alignment target.

[0016] After the material 307 has been applied (e.g., laminated) over the removable film 352, first-level interconnects (FLI) 353 are created. (See Fig. 3(C) and Fig. 4, Element 405). The FLI can be formed using various techniques, which vary depending on the platform requirements of electrolytic Cu applications (eCu), thick Ni plating, Sn plating, and the like. After the FLI have been formed, the solder mask 354 is flush laminated using vacuum lamination. (See Fig. 3D and Fig. 4, Element 406).

[0017] BU layers are then formed, for example, using semi-additive processing, LiV, subtractive etching processes, laser direct imaging (LDI), and the like. (See Fig. 3(E) and Fig. 4, Element 407). These processes are repeated depending on the desired number of BU layers. A semi-additive process can provide a thin layer of copper on a surface. A reverse mask is then applied in some embodiments. Additional copper is then plated onto the surface in unmasked areas. Tin-lead or other surface platings are then applied. The mask is removed, and a short etching step removes the now exposed original copper laminate from the surface, thereby isolating the individual connections. BU layers feature a dielectric 311 and connections 310. The connection 310 may include vias, such asVias that are completely filled with metal (as opposed to vias where the sidewalls are lined with metal, but the via is not completely filled with metal between opposing sidewalls of the via).

[0018] Next, openings for second-level interconnects (SLI) are created in a similar way to FLI creation. (See Fig. 3(F) and Fig. 4, Element 408). SLI openings can be used in this phase ( Fig. 3(F)) are formed, or they can be formed in another embodiment after the attachment of the unpackaged chip and lamination (See Fig. 3(K)).

[0019] Then the peelable core 350 is separated, resulting in two symmetrical stacks of layers. (See Fig. 3(F) and Fig. 4, Element 409). After the core has been separated, the Cu layers 351 are etched back to the BU layers. (See Fig. 3(G) and Fig. 4, Element 410). This exposes the removable material 352, allowing the removable material to be removed. Connections (e.g., PoP contact points) 355 are then plated to the required thickness. (See Fig. 3(H) to (I) and Fig. 4, Element 411). This can provide for an initial drilling of vias within the material 307. PoP contact points are formed in the case of a package that uses a PoP architecture. However, these contact points are not formed in embodiments that use a multi-chip package, where unpackaged chips are connected on a single package (e.g., Fig. 2), possibly not required. Furthermore, depending on the required distance, these contact points and connections for PoP coupling can have laser-drilled vias that are plated (e.g., using SAP) after embedding and encapsulating unpackaged chips (e.g., Fig. 3K), or they can be formed by plating (e.g. LiV), as mentioned above.

[0020] After plating the joints, the removable material 352 is removed. (See Fig. 3(J) and Fig. 4, Element 412). Various techniques can be used to remove the material, depending on its characteristics. The removable materials 352 can, without restriction, include: (1) Removable PET (polyethylene terephthalate) that is initially (e.g. Fig. 3(A)) laser-defined and mechanically removed at the end of the 300 / 400 process, (2) dry film photoresist (DFR) structured / developed to the required dimensions and chemically peeled off at the end of the 300 / 400 process using the DFR peel-off solution, (3) TEMPLOC® adhesive chemical peelable material stencil-printed and removed at the end of the 300 / 400 process using hot water that does not affect / etch the Cu compounds, and (4) a thermal polyethylene terephthalate (PET) release film.

[0021] Upon removal of the removable material 352, a cavity 304 is created in which the unpackaged chip 301 is placed on the substrate panel level (after completion of the FLI contact surface / contact bumps). (See Fig. 3(J) and Fig. 4, Element 413, 414). The ability to place the unpackaged chip within the substrate packaging line represents another advantage that improves throughput as well as handling. After the unpackaged chip is placed, the cavity is filled using BU / SR material 308 or any other required material. For example, at a PoP interface, a capillary underfill (CUF) (which may be a film or liquid) and / or a mold underfill (MUF) (which may be a film or liquid) can be used. The underfill materials can be applied using a vacuum laminator tool. (See Fig. 3(K) and Fig. 4, Element 415). Therefore, in some embodiments no underfilling materials are used, but in other embodiments underfilling materials are used. This essentially eliminates the need for a separate process step of underfilling the unpackaged chip and provides the advantage of higher throughput. After the cavity has been filled, a stiffening element 319 is attached (See Fig. 3(K) and Fig. 4, Element 416) and the package with the unpacked chip 301 can be tested for electrical performance and other specifications.

[0022] The lamination of the BU film, CUF, or MUF can be optimized so that a lower layer of material 308 is located outside the unpackaged chip, as opposed to being on the chip. As referenced in Fig. As mentioned in point 5, this ensures that smaller BGA contact points can be used, thereby reducing the risk of bridging.

[0023] Although the embodiments described here mention the use of a lamination process for applying materials (e.g. dielectric 108), other embodiments are not so restricted and may use compression molding or liquid coating of dielectric materials instead of or in addition to lamination.

[0024] Fig. Figure 1 shows an embodiment of a housing with a cavity for an unpackaged chip. In particular, it features Fig. 1 A semiconductor package 100 comprising: a first unpackaged chip 101 having a first and a second sidewall 102, 103; a first cavity 104 having a first and a second sidewall 105, 106, each of which comprises a first dielectric material 107. The package 100 further comprises a second dielectric material 108 that directly contacts the first and second sidewalls of the first unpackaged chip. The package 100 has a first layer 109 on the first unpackaged chip comprising a first metal compound 110 and a third dielectric material 111. A first horizontal axis 112 cuts the first and second sidewalls 102, 103 of the first unpacked chip, the first and second sidewalls 105, 106 of the first cavity, and the second dielectric material 108, but it does not cut the first layer 109.A second horizontal axis 113 intersects the first metal compound 110 and the third dielectric material 111.

[0025] In one embodiment, the first dielectric material 107 directly contacts the second dielectric material 108 along a seam, and the first horizontal axis 112 intersects the first seam. For example, the first and second dielectric materials are not monolithic to each other (formed or composed of one material without links or seams). As shown below in Fig. As will be addressed in section 4, the first and second dielectric materials are not formed simultaneously and exhibit a seam or link between the two materials, which is not removed in the finished product. This seam can be sidewalls 105, 106 if the first and second dielectric materials 107, 108 are in direct contact with each other.

[0026] In one embodiment, a first vertical axis 117 intersects the first layer 109 and the first unpackaged chip 101. In one embodiment, the first and second sidewalls of the first cavity 105, 106 are substantially parallel to the first vertical axis. However, in another embodiment, the first and second sidewalls of the first cavity are: (a) not parallel to the first vertical axis, (b) not parallel to the first horizontal axis, and (c) tapered. For example, in embodiments where the cavity 104 is drilled (e.g., laser-drilled or otherwise), the sidewalls of the cavity may be tapered, such as along the dashed lines 118. Therefore, if the first and second dielectric materials are in direct contact with each other and the sidewalls of the cavity are tapered, then the seam is also tapered.

[0027] In one embodiment, the first vertical axis 117 intersects the second dielectric material 108. In a specific example, the second dielectric material 108 directly contacts the first unpackaged chip 101 at a position between the first unpackaged chip 101 and the first layer 109. In such a case, the second dielectric material 108 can serve as an underfill for the unpackaged chip 101 and provide support for it, thereby preventing warping. Furthermore, in some embodiments, a stiffening element 119 can be coupled to the unpackaged chip 101 to prevent warping.

[0028] In one embodiment, the first and second dielectric materials have different material compositions. For example, the first dielectric material 107 may comprise a molding compound (e.g., thermosetting epoxy) or a solder resist, while the second dielectric material 108 comprises an underfill material (e.g., an underfill encapsulation material, such as an epoxy). The materials may contain different fillers; for example, one dielectric material may contain silica particles, while another dielectric material may contain filler particles made of a different material. However, in other embodiments, the first and second dielectric materials have essentially the same material compositions.In one embodiment, the third dielectric material 111 has a substantially identical material composition to that of at least one of the first and second dielectric materials. In other embodiments, however, the third dielectric material 111 does not have a substantially identical material composition to that of either the first or the second dielectric material.

[0029] In one embodiment, the first metal connection 110 has a via that is completely filled with at least one metal. This contrasts, for example, with a technology in which only one side wall 114 of the via 110 is plated, but the center 115 of the via 110 does not have a metal conductor. Instead, in one embodiment, the via is "solid" and has one or more metals along the side wall 114 and its center 115.

[0030] In one embodiment, layer 109 forms a redistribution layer (RDL). The lack of an area layout for the unpackaged chip 101 can be addressed by redistributing metal connections with input / output (I / O) nodes on the unpackaged chip. RDLs incorporate metal and dielectric layers (e.g., on an area of ​​a wafer or an unpackaged chip) to redirect the I / O design of the unpackaged chip to a loosely spaced area layout. Such RDLs can include thin-film polymers (B-stage bisbenzocyclobutene (BCB), polyimide (PI), Asahi Glass ALX, epoxy-based polymers, and the like) for the dielectric 111 and metallization (Al or Cu) for conductor tracks and vias 110 to redirect peripheral contacts to an area layout configuration.

[0031] One embodiment comprises at least one solder ball 116, wherein the first layer 109 is located between the at least one solder ball 116 and the first unpackaged chip 101. The solder ball can be used to connect to other circuits, such as those mounted on a printed circuit board coupled to the housing 100.

[0032] The embodiment of Fig. 1 is a coreless package with no silicon core. Furthermore, without a silicon core, no silicon vias (TSVs) are included in such a core. Additionally, no TSVs are present in the first unpackaged chip for embodiments such as package 100, which features a fan-out architecture. Although a silicon core has been mentioned above, the core need not necessarily be a silicon core. For example, the core may be a glass-impregnated prepreg. Therefore, embodiments feature composite laminates based on organic polymers and the like. Some cored embodiments may require through-holes, while coreless embodiments do not have through-holes for connection to the FLI or SLI.

[0033] Fig. Figure 2 shows an embodiment of a housing with two cavities for two unpackaged chips. Although Fig. Figure 2 shows two unpackaged chips; other embodiments may have three or more unpackaged chips. In particular, Figure 2 shows two unpackaged chips. Fig. 2 a semiconductor package 200 comprising: a first unpackaged chip 201 having a first and a second sidewall 202, 203; a first cavity 204 having a first and a second sidewall 205, 206, each of which comprises a first dielectric material 207'. The package 200 further comprises a second dielectric material 208' which directly contacts the first and second sidewalls of the first unpackaged chip 201. The package 200 has a first layer 209 on the first unpackaged chip comprising a first metal compound 210 and a third dielectric material 211. A first horizontal axis 212 cuts the first and second sidewalls 202, 203 of the first unpacked chip, the first and second sidewalls 205, 206 of the first cavity, and the second dielectric material 208', but it does not cut the first layer 209.

[0034] The package 200 further comprises a second unpackaged chip 201', wherein the first horizontal axis 212 intersects the first and second unpackaged chips. The package 200 further comprises a second cavity 204', which has a first and a second sidewall 205', 206', each of which comprises the first dielectric material 207'. The second dielectric material 208' directly contacts the first and second sidewalls 202', 203' of the second unpackaged chip. The first layer 209 is located on the second unpackaged chip 201'. The first horizontal axis 212 intersects the first and second sidewalls 202', 203' of the second unpackaged chip and the first and second sidewalls 205', 206' of the second cavity.

[0035] Fig. Figure 5 shows a package-on-package (PoP) system in one embodiment. Fig. 5 comprises a semiconductor package system comprising: a first package 500, comprising: (a)(i) a first unpackaged chip 501 having a first and a second sidewall 502, 503; (a)(ii) a first cavity 504 having a first and a second sidewall 505, 506, each of which comprises a first dielectric material 507; (a)(iii) a second dielectric material 508 directly contacting the first and second sidewalls of the first unpackaged chip; (a)(iv) a first layer 509 on the first unpackaged chip comprising a first metal compound 510 and a third dielectric material 511. The system further comprises a second package 500' comprising a second unpackaged chip 501'.A first horizontal axis 512 cuts the first and second sidewalls 502, 503 of the first unpacked chip, the first and second sidewalls 505, 506 of the first cavity, and the second dielectric material 508, but it does not cut the first layer or the second unpacked chip. A second horizontal axis 513 cuts the first metal compound 510 and the third dielectric material 511. A vertical axis 517 cuts the first and second unpacked chips. The system includes at least one solder ball 516 that couples the first unpacked chip to the second unpacked chip.

[0036] In one embodiment of the system, a cavity 520 is located between the first and second unpacked chips 500, 500'. The cavity may contain a space, an underfill material, or some other material (i.e., it is not necessarily empty). The cavity has a lower boundary, defined at least partially by an upper surface 521 of the first package, and an opposite second boundary, defined at least partially by a lower surface 522 of the second package. A section 521' of the upper surface of the first package, located directly above the first unpacked chip, is situated at a first distance 523 from the first layer. A second section 521" of the upper surface of the first package, not located directly above the first unpacked chip, is situated at a second distance 523' from the first layer. In one embodiment, the first distance is greater than the second distance.For example, the dielectric material 508 can be coupled to the unpackaged chip 501 and the dielectric 507 in odd planes (e.g., a laminate applied under vacuum conditions). This reduces the distance 524'. Consequently, the diameter of the sphere 516 can be reduced, which not only reduces the distance 524' but also the distance 525.

[0037] In one embodiment, the first vertical axis 517 intersects the first section 521' of the upper surface of the first housing. The first vertical axis does not intersect the second section 521" of the upper surface of the first housing.

[0038] In one embodiment, the first unpackaged chip 501 includes a processor and the second unpackaged chip 501' includes a memory. However, other embodiments are not so restricted and can generally include a first and a second unpackaged chip without any restriction on the functions of those unpackaged chips.

[0039] One embodiment comprises a method comprising: coupling a sacrificial material with a substrate (see, for example, block 403 of Fig. 4); Forming a first dielectric material adjacent to the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material (see, for example, block 404 of Fig. 4); Forming a first layer on the first dielectric material and the sacrificial material, comprising a first metallic compound and a third dielectric material (see, for example, block 407 of Fig. 4); Decoupling the substrate from the first dielectric material and the sacrificial material (see e.g. block 409 of Fig. 4); Removal of the sacrificial material to form an empty cavity whose sidewalls comprise the first dielectric material (see, for example, block 412 of Fig. 4); after removing the sacrificial material to form the empty cavity, inserting a first uncased chip into the empty cavity (see e.g. block 414 of Fig. 4); and forming a second dielectric material between the first dielectric material and the first unpackaged chip, such that the horizontal axis intersects the first and second dielectric materials and the first unpackaged chip (see, for example, block 415 of Fig. 4).

[0040] One embodiment of the foregoing method features the formation of a connection through the first dielectric material (see, for example, Block 402 of Fig. 4), wherein a first vertical axis cuts the connection but does not cut the first unpacked chip after the first unpacked chip has been inserted into the empty cavity.

[0041] One embodiment features the formation of the connection through the first dielectric before the substrate is decoupled from the first dielectric material and the sacrificial material. However, another embodiment features the formation of the connection through the first dielectric after the substrate has been decoupled from the first dielectric material and the sacrificial material.

[0042] The embodiments described here offer many advantages, some of which are discussed below.

[0043] First, these embodiments provide a lower risk of chip loss. They employ a chip-last approach, which, unlike architectures that use chip-first processes, reduces the risk of losing a "proven to be defect-free" chip during packaging. As used here, "chip-last" does not literally mean that the unpackaged chip must be included in the very last step of the packaging process.

[0044] Secondly, embodiments offer lower costs. Embodiments are less expensive than conventional approaches that take place at the wafer level. Embodiments that enable processing at the panel level (which is larger than a wafer) allow for higher throughput in the encapsulation process. The ability to process packages at the panel level (as opposed to the wafer level) is demonstrated, for example, by fully filled via connections in the RDLs and the cavity surrounding the unpackaged chip. Furthermore, lower costs are achieved because the chip-last approach requires fewer carriers for the unpackaged chip compared to chip-first approaches. This saves processing time.Since some embodiments encapsulate the unpackaged chip by means of lamination at a panel level, the lamination also eliminates the need for an additional step of overforming and underfilling the unpackaged chip at a unit level, again saving processing time and materials, thus reducing the overall cost of the package.

[0045] Third, embodiments provide a relatively simpler process. Since overforming and underfilling are eliminated in some embodiments (while other embodiments may still use underfilling), the resulting process is simpler than processes that use overforming and / or underfilling. Consequently, the simpler processes exhibit fewer problems, such as voids in the underfilling material and the like—problems that plague the industry today. This is because lamination (of the first dielectric material 107 and / or the second dielectric material 108) at a panel level can achieve higher vacuum levels (which is required for many lamination techniques), making the lamination process more reliable and reproducible.

[0046] Fourth, embodiments offer higher yield / scalability. For example, since some embodiments provide a symmetrical setup on a single panel level, the number of units per substrate throughput is higher than in a conventional, single-sided wafer-level process (see, for example, the symmetrical setup in [reference]). Fig. 3(F)).

[0047] Fifthly, embodiments exhibit a lower risk of bridging between contact bumps. Lamination (used in some, but not all, embodiments) of the dielectric material allows for better control of the dielectric material thickness. The thickness on the unpackaged chip (e.g., Section 521' of Fig. 5) opposite outside the unpackaged chip (e.g. section 521) of Fig. 5) can be controlled in such a way that the thickness outside the unpackaged chip is lower (see, for example, the non-planar surface 521 of Fig. 5), which allows the size of the connections (e.g., ball grid array (BGA)) of the upper unpackaged chip (e.g., memory chips) to be reduced, and therefore the risk of bridging between such connections is reduced.

[0048] Sixth, embodiments provide a narrower / smaller PoP distance. The PoP distance can be reduced considering the process capability of drilling and plating vias through the dielectric (see, e.g., [reference]). Fig. 3(H)).

[0049] Seventh, embodiments provide warping control. In a conventional forming architecture, it is challenging to reduce high-temperature warping without affecting room-temperature warping of the housing. However, embodiments are able to provide the necessary benefit of both room-temperature and high-temperature warping by using BU dielectrics that act as an adhesive for a stiffening element (e.g., a copper or stainless steel stiffener). Conventional systems require a second adhesive for the stiffener, and this adhesive contributes to warping due to a mismatch of its coefficient of thermal expansion (CTE) with other components in the housing.

[0050] Eighthly, embodiments offer advantages with regard to displacement of the unpackaged chip. Embodiments that include a cavity prevent or at least limit displacement of the unpackaged chip. This addresses a problem that occurs in conventional technologies where an unpackaged chip is overmolded, and consequently, the unpackaged chip shifts from its intended position during overmolding and subsequent curing.

[0051] With reference to Fig. Figure 6 presents a block diagram of an example system with which embodiments can be used. As can be seen, the system 900 can be a smartphone or another communication or IoT (Internet of Things) device. A baseband processor 905 (which may have the housing system of embodiments described herein) is designed to perform various signal processing with respect to communication signals to be sent or received by the system. The baseband processor 905 is in turn coupled with an application processor 910 (which may have the housing system of embodiments described herein), which may be a main CPU of the system for running an operating system (OS) and other system software in addition to user applications, such as social media and multimedia applications, which are known per se.The 910 application processor can also be designed to perform a variety of other computational operations for the device.

[0052] The application processor 910 can, in turn, be coupled with a user interface / display 920 (e.g., a touchscreen display). Furthermore, the application processor 910 can be coupled with a storage system comprising non-volatile memory, namely flash memory 930, and system memory, namely DRAM 935. In some embodiments, the flash memory 930 (which can be contained in a housing configuration described herein) can include a more secure section 932 in which secrets and other sensitive information can be stored. As can further be seen, the application processor 910 is also coupled with a capture device 945, such as one or more image capture devices capable of recording video and / or still images.

[0053] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure memory 942 for storing secure user information. The system 900 may further include a security processor 950 (e.g., a Trusted Platform Module (TPM)) (which may include the thermal management of embodiments described herein) that can be coupled to the application processor 910. A variety of sensors 925, including one or more multi-axis accelerometers, can be coupled to the application processor 910 to enable input of a variety of detected information, such as motion or other environmental information. Furthermore, one or more authentication devices 995 can be used to receive, for example, biometric user input for use in authentication operations.

[0054] As further shown, a contactless near-field communication (NFC) interface 960 is provided, which communicates in an NFC near field via an NFC antenna 965. Although separate antennas are shown, it is understood that in some implementations one antenna or a different set of antennas may be provided to accommodate various wireless functionalities.

[0055] An integrated power management circuit (PMIC) 915 (which may include the thermal management of embodiments described herein) is coupled to the application process 910 to perform platform-level power management. For this purpose, the PMIC 915 can issue power management requests to the application processor 910 so that certain low-power states are entered as desired. Furthermore, based on platform constraints, the PMIC 915 can also control the power levels of other components of the system 900.

[0056] To enable the sending and receiving of communications, such as in one or more IoT networks, various circuits can be coupled between the baseband processor 905 and an antenna 990. Specifically, a high-frequency (HF) receiver 970 and a wireless local area network (WLAN) transceiver 975 can be included. In general, the HF transceiver 970 can be used to wirelessly receive and transmit data and calls according to a given wireless communication protocol, such as a 3G or 4G wireless communication protocol, such as CDMA (code division multiplexing), GSM (global system for mobile communications), LTE (Long Term Evolution), or another protocol.Furthermore, a GPS sensor 980 can be present, providing position information to the security processor 950 for use as described here when context information is required in a pairing process. Other wireless communication capabilities, such as receiving or transmitting radio signals (e.g., AM / FM) and other signals, can also be provided. Additionally, local wireless communication, such as that based on a Bluetooth™ or IEEE 802.11 standard, can be implemented via the WLAN transceiver 975.

[0057] With reference to Fig. Figure 7 shows a block diagram of a system according to another embodiment of the present invention. A multiprocessor system 1000 is a point-to-point interconnect system, such as a server system, and comprises a first processor 1070 (which may have the housing system of embodiments described herein) and a second processor 1080 (which may have the housing system of embodiments described herein) coupled via a point-to-point connection 1050. Each of the processors 1070 and 1080 may be a multi-core processor, such as a SoC, having a first and a second processor core (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many cores may be present in the processors. Furthermore, each of the processors 1070 and 1080 may have a safe machine 1075 and 1085 to perform safe operations, such asTo carry out authentications, IDD network integration, and so on.

[0058] The first processor 1070 also features a memory controller hub (MCH) 1072 and point-to-point (PP) interfaces 1076 and 1078. Similarly, the second processor 1080 features an MCH 1082 and PP interfaces 1086 and 1088. MCHs 1072 and 1082 connect the processors to corresponding memories, namely a memory 1032 and a memory 1034, which can be sections of main memory (e.g., DRAM) located locally on the respective processors (memory and processors can be housed in the package forms described here). The first processor 1070 and the second processor 1080 can each be connected to a chipset 1090 via PP connections 1052 and 1054, respectively. The 1090 chipset features PP interfaces 1094 and 1098.

[0059] Furthermore, the chipset 1090 (which may have the housing system of embodiments described herein) has an interface 1092 for coupling the chipset 1090 to a high-performance graphics engine 1038 via a PP connection 1039. The chipset 1090 can, in turn, be coupled to a first bus 1016 via an interface 1096. Various input / output devices (I / O devices) 1014 can be coupled to the first bus 1016, including a bus bridge 1018 that couples the first bus 1016 to a second bus 1020. Various devices, such as a keyboard and / or mouse 1022, communication devices 1026, and a storage unit 1028, such as non-volatile memory or other mass storage devices, can be coupled to the second bus 1020. As can be seen, in one embodiment a data storage unit 1028 can have a code 1030.As can also be seen, the data storage unit 1028 also has a trusted storage unit 1029 for storing sensitive information that needs to be protected. Furthermore, an audio input and output unit 1024 can be connected to a second bus 1020.

[0060] These embodiments can be used in environments where IoT devices can be portable or other IoT (Internet of Things) devices with a small form factor. With reference to Fig. Figure 8 shows a block diagram of a portable Module 1300 according to another embodiment. In one particular implementation, the Module 1300 may be an Intel® Curie™ module comprising several components arranged within a single small module, which may be implemented as a whole or as part of a portable device. As can be seen, the Module 1300 includes a Core 1310 (which may have the housing system of embodiments described herein). Such a core may be an in-order core of comparatively low complexity, such as one based on an Intel Architecture® Quark™ design. In some embodiments, the Core 1310 may implement a TEE, as described herein. The Core 1310 is coupled with various components comprising a Sensor Hub 1320, which may be designed to work with a variety of Sensors 1380, such as…one or more biometric, motion-environment, or other sensors. A power supply circuit 1330 is present together with a non-volatile memory 1340 (which may include the housing system of embodiments described herein). In one embodiment, this circuit may include a rechargeable battery and a charging circuit, which in one embodiment may wirelessly receive charging power. One or more input / output interfaces (IO interfaces) 1350, such as one or more interfaces compatible with one or more of the USB / SPI / I2C / GPIO protocols, may be present. A wireless transceiver 1390, which may be a Bluetooth™ low-energy or other short-range wireless transceiver, is also present to enable wireless communications as described herein.It is understood that in different implementations, a portable module can take many other forms. Portable and / or IoT devices, compared to a typical general-purpose CPU or GPU, have a small form factor, low power requirements, limited instruction sets, comparatively slow processing throughput, or any of the above.

[0061] The following examples refer to further embodiments.

[0062] Example 1 comprises a semiconductor package comprising: a first unpackaged chip having a first and a second sidewall; a first cavity having a first and a second sidewall, each of which comprises a first dielectric material; a second dielectric material directly contacting the first and second sidewalls of the first unpackaged chip; a first layer on the first unpackaged chip comprising a first metal compound and a third dielectric material; wherein (a) a first horizontal axis intersects the first and second sidewalls of the first unpackaged chip, the first and second sidewalls of the first cavity, and the second dielectric material, but does not intersect the first layer; and (b) a second horizontal axis intersects the first metal compound and the third dielectric material.

[0063] The presence of the cavity may indicate that the housing was formed at the panel level and not at the level of small wafers (e.g., Process 300).

[0064] In various embodiments, the dielectric material can have compositions of different materials. A first dielectric can be A x B 1-x exhibit and another can A x B 1-y exhibiting, where x is not equal to y. Although the preceding example refers to a first and a second dielectric material, this does not preclude a third, a fourth, or more dielectrics.

[0065] Example 2 features the housing according to Example 1, wherein the first dielectric material directly contacts the second dielectric material along a seam and the first horizontal axis intersects the first seam.

[0066] Example 3 features the housing according to Example 2, wherein the first and second dielectric materials have different material compositions.

[0067] For example, dielectric materials can contain polyimide and / or poly(butyl acrylate) (PBA). This contrasts with conventional technologies that can use epoxy-based materials (e.g., ABF).

[0068] Example 4 features the housing according to Example 2, wherein the first and second dielectric materials have essentially the same material compositions.

[0069] Example 5 has the housing according to Example 2, wherein the first metal connection has a via which is completely filled with at least one metal.

[0070] This can indicate that the package was formed at the panel level and not at the level of small wafers (e.g., Process 300). The metal compound may be part of a reinforced liquid layer (RDL). The RDL can be formed from a thin film. A thin film is a layer of material with a thickness ranging from fractions of a nanometer (monolayer) to several micrometers. These films can be formed, for example, using deposition techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0071] For tighter spacing and finer leads / pitches, a LiV process can also be used. An LiV process can provide a via with a less tapered shape. This contrasts with conventional technologies that use a semi-additive process to form vias shaped like truncated cones. Furthermore, connections in conventional RDLs are conformally plated at the wafer level, unlike a fully plated via in a substrate.

[0072] Example 6 has the housing according to Example 5, which includes at least one solder ball, with the first layer being located between the at least one solder ball and the first unhousing chip.

[0073] Example 7 features the package according to Example 5, with a first vertical axis intersecting the first layer and the first unpackaged chip.

[0074] Example 8 features the housing according to Example 7, wherein the first and second side walls of the first cavity are substantially parallel to the first vertical axis.

[0075] Example 9 has the housing according to Example 7, wherein the first and second side walls of the first cavity are: (a) not parallel to the first vertical axis, (b) not parallel to the first horizontal axis, and (c) tapered.

[0076] Example 10 features the housing according to Example 7, with the first vertical axis intersecting the second dielectric material.

[0077] Example 11 has the housing according to Example 10, wherein the second dielectric material directly contacts the first unpacked chip at a position between the first unpacked chip and the first layer.

[0078] Example 12 has the housing according to Example 2, wherein the second dielectric material directly contacts the first unpacked chip at a position between the first unpacked chip and the first layer.

[0079] Example 13 has the housing according to Example 2, wherein the first and second dielectric materials are not monolithic to each other.

[0080] Example 14 features the package of Example 2, which includes a second unpacked chip, with the first horizontal axis intersecting the first and second unpacked chips.

[0081] Example 15 comprises the housing of Example 14, comprising: a second cavity having a first and a second side wall, each of which includes the first dielectric material; the second dielectric material directly contacting the first and second side walls of the second unhoused chip; and the first layer on the second unhoused chip, the first horizontal axis intersecting the first and second side walls of the second unhoused chip and the first and second side walls of the second cavity.

[0082] Example 16 has the housing according to Example 2, where the housing does not have a silicon through-hole (SOH).

[0083] For example, the package can be coreless and can use fan-out traces to avoid the need to arrange a TSV inside the unpackaged chip.

[0084] Fig.17 comprises a semiconductor package system comprising: a first package comprising: (a)(i) a first unpackaged chip having a first and a second sidewall; (a)(ii) a first cavity having a first and a second sidewall, each of which comprises a first dielectric material; (a)(iii) a second dielectric material directly contacting the first and second sidewalls of the first unpackaged chip; (a)(iv) a first layer on the first unpackaged chip comprising a first metal compound and a third dielectric material; and a second package comprising a second unpackaged chip;wherein (b)(i) a first horizontal axis intersects the first and second sidewalls of the first unpacked chip, the first and second sidewalls of the first cavity and the second dielectric material, but does not intersect the first layer and does not intersect the second unpacked chip, (b)(ii) a second horizontal axis intersects the first metal compound and the third dielectric material, and (b)(iii) a vertical axis intersects the first and the second unpacked chip.;

[0085] Example 18 features the system according to Example 17, which includes at least one solder ball coupling the first unpacked chip to the second unpacked chip.

[0086] Example 19 comprises the system of Example 17, comprising: a cavity between the first and second unpacked chips, having a lower boundary defined at least partially by an upper surface of the first package, and an opposite second boundary defined at least partially by a lower surface of the second package; wherein (c)(i) a section of the upper surface of the first package is located directly above the first unpacked chip at a first distance from the first layer, (c)(ii) a second section of the upper surface of the first package, not located directly above the first unpacked chip, is located at a second distance from the first layer, and (c)(iii) the first distance is greater than the second distance.

[0087] Example 20 features the system according to Example 19, wherein: the vertical axis intersects the first section of the upper surface of the first housing; and the vertical axis does not intersect the second section of the upper surface of the first housing.

[0088] Example 21 features the system according to Example 17, wherein the first unpackaged chip has a processor and the second unpackaged chip has a memory.

[0089] Example 22 discloses a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent to the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer on the first dielectric material and the sacrificial material, comprising a first metal compound and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity, the sidewalls of which comprise the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first unpackaged chip into the empty cavity;and forming a second dielectric material between the first dielectric material and the first unpackaged chip, such that the horizontal axis intersects the first and second dielectric materials and the first unpackaged chip.

[0090] In various designs, the cavity can be laser-drilled.

[0091] Example 23 includes the method of Example 22, comprising: forming a junction through the first dielectric material, wherein a first vertical axis cuts the junction but does not cut the first unpacked chip after the first unpacked chip has been inserted into the empty cavity.

[0092] Example 24 demonstrates the procedure of Example 23, comprising: forming the connection through the first dielectric prior to decoupling the substrate from the first dielectric material and the sacrificial material.

[0093] Example 25 demonstrates the procedure according to Example 23, comprising: forming the connection through the first dielectric after decoupling the substrate from the first dielectric material and the sacrificial material.

[0094] Example 26 comprises a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory is contained in the first unpackaged chip and the package according to any one of Examples 1 to 21.

[0095] Example 27 features the housing according to one of Examples 1 to 2 and 5 to 21, wherein the first and second dielectric materials have different material compositions.

[0096] Example 28 features the housing according to one of Examples 1 to 2 and 5 to 21, wherein the first and second dielectric materials have substantially the same material compositions.

[0097] Example 29 has the housing according to one of Examples 1 to 4 and 8 to 21, wherein the first metal connection has a via which is completely filled with at least one metal.

[0098] Example 30 has the housing according to one of Examples 1 to 4 and 8 to 21, which includes at least one solder ball, wherein the first layer is located between the at least one solder ball and the first unhousing chip.

[0099] Example 31 has the package according to one of Examples 1 to 4, 6 and 8 to 21, wherein a first vertical axis intersects the first layer and the first unpackaged chip.

[0100] Example 32 has the housing according to one of Examples 1 to 11 and 12 to 21, wherein the second dielectric material directly contacts the first unpacked chip at a position between the first unpacked chip and the first layer.

[0101] Example 33 has the housing according to one of Examples 1 to 11 and 13 to 21, wherein the second dielectric material directly contacts the first unpacked chip at a position between the first unpacked chip and the first layer.

[0102] Example 34 has the housing according to one of Examples 1 to 12 and 14 to 21, wherein the first and second dielectric materials are not monolithic to each other.

[0103] Example 35 features the package according to one of Examples 1 to 13 and 15 to 21, which includes a second unpacked chip, wherein the first horizontal axis intersects the first and the second unpacked chip.

[0104] Example 36 has the housing according to one of Examples 1 to 15 and 17 to 21, wherein the housing does not have a silicon through-hole (SOH) connection.

[0105] Example 37 comprises the enclosure according to one of Examples 17 to 18 and 20 to 21, comprising: a cavity between the first and the second unenclosed chip, having a lower boundary defined at least partially by an upper surface of the first enclosure, and an opposite second boundary defined at least partially by a lower surface of the second enclosure; wherein (c)(i) a section of the upper surface of the first enclosure is located directly above the first unenclosed chip at a first distance away from the first layer, (c)(ii) a second section of the upper surface of the first enclosure, not located directly above the first unenclosed chip, is located at a second distance away from the first layer, and (c)(iii) the first distance is greater than the second distance.

[0106] Example 38 has the case according to one of Examples 17 to 19 and 21: the first vertical axis intersects the first section of the upper surface of the first case; and the first vertical axis does not intersect the second section of the upper surface of the first case.

[0107] Example 39 features the system according to Example 17, which includes at least one interconnection device that couples the first unpackaged chip to the second unpackaged chip.

[0108] Example 40 has the housing according to Example 5, which includes at least one interconnection device, wherein the first layer is located between the at least one interconnection device and the first unpackaged chip.

[0109] The foregoing description of the embodiments of the invention is presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the exact forms disclosed. The description and the claims below contain terms such as left, right, upper, lower, above, below, top, bottom, first, second, etc., which are used solely for descriptive purposes and are not to be construed as a limitation.For example, terms describing a relative vertical position refer to a situation in which a device side (or active side) of a substrate or integrated circuit represents the "top" face of the substrate; the substrate may actually be in any orientation, such that a "top" face of a substrate may be lower than the "bottom" face in a normal terrestrial frame of reference and still be within the meaning of the term "top". The term "on" as used here (including the claims) does not indicate that a first layer "on" a second layer is directly on top of and in immediate contact with the second layer unless expressly stated; there may be a third layer or some other structure between the first layer and the second layer on top of the first layer.The embodiments of a device or object described herein can be manufactured, used, or shipped in a multitude of positions or orientations. A person skilled in the art in the relevant field will understand that many modifications and variations are possible in light of the foregoing teaching. A person skilled in the art will recognize various equivalent combinations and substitutions for the different components shown in the figures. It is therefore intended that the scope of the invention is not limited to this detailed description, but rather to the accompanying claims.

Claims

[1] Semiconductor package, comprising: a first die having a first and a second sidewall, a first cavity having first and second side walls, each of which comprises a first dielectric material, a second dielectric material directly contacting the first and second sidewalls of the first die, wherein the first and second dielectric materials have different material compositions from each other, a first layer on the first die comprising a first metal interconnect and a third dielectric material, wherein (a) a first horizontal axis is parallel to a top surface of the first die and intersects the first and second sidewalls of the first die, the first and second sidewalls of the first cavity, and the second dielectric material, but does not intersect the first layer, and (b) a second horizontal axis intersects the first metal interconnect and the third dielectric material. [2] The semiconductor package of claim 1, wherein the first dielectric material directly contacts the second dielectric material along a seam and the first horizontal axis intersects the first seam. [3] A semiconductor package according to any one of the preceding claims, wherein the first and second dielectric materials have substantially identical material compositions. [4] Semiconductor package according to one of the preceding claims, wherein the first metal connection comprises a via that is completely filled with at least one metal. [5] The semiconductor package of claim 4, comprising at least one solder ball, wherein the first layer is located between the at least one solder ball and the first die. [6] The semiconductor package of any of claims 4-5, wherein a first vertical axis intersects the first layer and the first die. [7] The semiconductor package of claim 6, wherein the first and second sidewalls of the first cavity are substantially parallel to the first vertical axis. [8] The semiconductor package of any of claims 6-7, wherein the first and second sidewalls of the first cavity are: (a) not parallel to the first vertical axis, (b) not parallel to the first horizontal axis, and (c) tapered. [9] The semiconductor package of any of claims 6-8, wherein the first vertical axis intersects the second dielectric material. [10] The semiconductor package of claim 9, wherein the second dielectric material directly contacts the first die at a position between the first die and the first layer. [11] The semiconductor package of any of claims 2-10, wherein the second dielectric material directly contacts the first die at a position between the first die and the first layer. [12] A semiconductor package according to any one of claims 2-11, wherein the first and second dielectric materials are not monolithic with each other. [13] The semiconductor package of any of claims 2-12, comprising a second die, wherein the first horizontal axis intersects the first and second die. [14] A semiconductor package according to claim 13, comprising: a second cavity having first and second side walls, each of which comprises the first dielectric material, the second dielectric material directly contacting the first and second sidewalls of the second die, and the first layer on the second die, wherein the first horizontal axis intersects the first and second sidewalls of the second die, and the first and second sidewalls of the second cavity. [15] A semiconductor package according to any one of claims 2-14, wherein the package does not have a silicon via (TSV). [16] A semiconductor packaging system comprising: a first package comprising: (a)(i) a first die having first and second sidewalls, (a)(ii) a first cavity having first and second sidewalls, each of which comprises a first dielectric material; (a)(iii) a second dielectric material directly contacting the first and second sidewalls of the first die; (a)(iv) a first layer on the first die comprising a first metal interconnect and a third dielectric material, and a second package having a second die, wherein (b)(i) a first horizontal axis parallel to a top surface of the first die and intersecting the first and second sidewalls of the first die, the first and second sidewalls of the first cavity, and the second dielectric material, but not intersecting the first layer and not intersecting the second die, (b)(ii) a second horizontal axis intersecting the first metal interconnect and the third dielectric material, and (b)(iii) a vertical axis intersecting the first and second die. [17] The semiconductor packaging system of claim 16, comprising at least one solder ball coupling the first die to the second die. [18] A semiconductor packaging system according to any one of claims 16-17, comprising: a cavity between the first and second dies having a lower boundary defined at least in part by a top surface of the first housing and an opposite second boundary defined at least in part by a bottom surface of the second housing, wherein (c)(i) a portion of the top surface of the first package directly above the first die is a first distance away from the first layer, (c)(ii) a second portion of the top surface of the first package not directly above the first die is a second distance away from the first layer, and (c)(iii) the first distance is greater than the second distance. [19] A semiconductor packaging system according to claim 18, wherein: the vertical axis intersects the first portion of the upper surface of the first housing, and the vertical axis does not intersect the second portion of the upper surface of the first housing. [20] The semiconductor packaging system of any of claims 18-19, wherein the first die comprises a processor and the second die comprises a memory. [21] Method comprising: Coupling a sacrificial material with a substrate, Forming a first dielectric material adjacent to the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material, Forming a first layer on the first dielectric material and the sacrificial material, comprising a first metal compound and a third dielectric material, Decoupling the substrate from the first dielectric material and the sacrificial material, Removing the sacrificial material to form an empty cavity whose side walls comprise the first dielectric material, after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity, and Forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis parallel to a top surface of the first die intersects the first and second dielectric materials and the first die, wherein the first and second dielectric materials have different material compositions from each other. [22] The method of claim 21, comprising: forming an interconnect through the first dielectric material, wherein a first vertical axis intersects the interconnect but does not intersect the first die after the first die is inserted into the empty cavity. [23] The method of claim 22, comprising: forming the interconnect through the first dielectric prior to decoupling the substrate from the first dielectric material and the sacrificial material. [24] The method of claim 22 or 23, comprising: forming the connection through the first dielectric after decoupling the substrate from the first dielectric material and the sacrificial material.

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