METAL GATE MODULATION TO IMPROVE THE KICK EFFECT AND METHOD

Abstract

Integrated chip that includes the following: an insulation structure (104) set up within a substrate (102) and having internal surfaces defining one or more divots (108) recessed below a top surface of the insulation structure, and side walls defining an opening (106) that exposes the substrate (102); a source area (124) located within the opening (106); a drain area (126) arranged within the opening (106) and separated from the source area (124) by a channel area (125) along a first direction (128); and a gate structure (110) extending over the channel region (125), the gate structure comprising a first gate electrode region (114) having a first composition of one or more materials, and a second gate electrode region (116) arranged over the one or more divots (108) having a second composition of one or more materials that is different from the first composition of one or more materials; wherein the second gate electrode region (116) comprises a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the third segment of the second gate electrode region (116) are arranged over a first edge of the channel region (125); wherein the second segment and the fourth segment of the second gate electrode region (116) are arranged over a second edge of the channel region (125) opposite the first edge of the channel region; wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) each have a rectangular shape in a top view; wherein the first segment and the second segment of the second gate electrode region (116) are arranged along a first side (110a) of the gate structure (110) near the drain region (126), such that side surfaces of the first segment and the second segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the drain region; wherein the third segment and the fourth segment of the second gate electrode region (116) are arranged along an opposite second side (110b) of the gate structure near the source region (124), such that side surfaces of the third segment and the fourth segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the source region; wherein the first segment is separated from the third segment and the second segment from the fourth segment along the first direction (128) by the first gate electrode region (114); wherein the first segment is separated from the second segment and the third segment from the fourth segment along a second direction (130) perpendicular to the first direction (128) by the first gate electrode region (114); and wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) extend beyond the channel region (125) in the second direction (130).

Description

BACKGROUND

[0001] Modern integrated chips comprise millions or billions of semiconductor components built on a semiconductor substrate (for example, a silicon substrate). To improve the functionality of integrated chips, the semiconductor industry has continuously reduced the size of semiconductor components to create integrated chips with small, densely packed components. By creating integrated chips with small, densely packed components, the speed of the semiconductor components increases, and the power consumption of the components decreases.

[0002] US Patent 2001 / 0002058A1 describes a semiconductor device with a gate electrode formed over an active region and isolation regions to reduce a "hump" below a threshold voltage in a drain current-versus-gate voltage characteristic. The gate electrode comprises a central section and end sections, the end sections being located near interfaces between the active region and isolation regions, and the central section being situated between the end sections. The end sections may be doped differently from the central section to compensate for lower threshold voltages in such regions.

[0003] US Patent 2010 / 0084717A1 describes a semiconductor device with a gate electrode extending over an insulating film and a channel region. The gate electrode exhibits a zone of increased work function over at least part of the interface between the insulating film and the channel region.

[0004] US Patent 2010 / 0044801A1 describes a field-effect transistor with a gate structure comprising a first section over a central part of the channel region and second sections over the channel edges. The first section has a different work function than the second sections of the gate structure, resulting in an increased threshold voltage at the channel edges.

[0005] WO 2016 / 062 358 A1 describes a transistor wherein the gate comprises a layer of a conductive material, and wherein the layer has a recess such that the layer has a greater width near the source and drain than in the middle between the source and drain.

[0006] US 2010 / 0320529A1 describes a method for fabricating an integrated circuit system, comprising: providing a semiconductor substrate with an active region doped with dopants of a first type in a first concentration; forming an isolation region around the active region; forming a parasitic transistor by placing a gate electrode doped with dopants of a second type in a second concentration over the active region and the isolation region; and applying an isolation edge doping with the dopants of the first type in a third concentration greater than or equal to the second concentration to suppress the parasitic transistor.

[0007] US 2012 / 0280291A1 describes a semiconductor device comprising a substrate, an insulating layer over the substrate defining an active region of the substrate, and a gate electrode traversing the active region between a source region and a drain region of the active region. The gate electrode defines at least one gate opening. The at least one gate opening may expose part of a boundary between the active region and the device's insulating layer.

[0008] US 2013 / 0092987A1 describes a MOS transistor formed in an active region of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate containing two lateral regions of the second conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of this disclosure are best understood through the following detailed description, with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. The dimensions of the various features may be arbitrarily enlarged or reduced for the clarity of the discussion. The Fig. Figures 1A-1B illustrate some examples of an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. The Fig. Sections 2A-2B illustrate some exemplary band diagrams corresponding to the transistor component of the Fig. 1A-1B correspond. Fig. 2C illustrates graphs showing some exemplary absolute threshold voltages that apply to the transistor component of the Fig. 1A-1B correspond. The Fig. 3A-3C illustrate some additional examples of an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. The Fig. Figure 4A illustrates a top view showing an embodiment of an integrated chip that includes a gate structure configured to improve component performance. Fig. Figure 4B illustrates a top view showing an alternative example of an integrated chip that includes a gate structure configured to improve component performance. The Fig. 5A-5B illustrate some additional examples of an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. The Fig. Figures 6A to 17 illustrate some examples of cross-sectional and top views corresponding to a method for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. Fig. Figure 18 illustrates a flowchart of some examples of a procedure for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. The Fig. Figures 19A to 28 illustrate cross-sectional and top views corresponding to some alternative examples of a method for forming an integrated chip having a transistor component that includes a gate structure configured to improve component performance. Fig. Figure 29 illustrates a flowchart of some alternative examples of a method for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing various elements of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For instance, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or reference letters in the various examples.This repetition is intended for the sake of simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatial reference terms such as "below," "under," "lower," "above," "above," and the like may be used here to facilitate description and to describe the relationship of one feature or characteristic to one or more other features or characteristics, as illustrated in the figures. The spatial reference terms may be intended to include different orientations of the component during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or to other orientations), and the spatial reference descriptors used here are interpreted accordingly.

[0012] In integrated chips, active components (e.g., MOSFETs, embedded memory components, etc.) are generally mounted on a common semiconductor substrate (e.g., a silicon substrate). However, semiconductor materials can be electrically conductive, so leakage currents can flow between active components located in close proximity within the semiconductor substrate. If such leakage currents are not properly mitigated, cross-coupling between adjacent components can lead to the failure of an integrated chip.

[0013] To prevent leakage currents from flowing between adjacent components, many modern integrated chips employ shallow trench insulation (STI) structures. Typically, STI structures are formed by creating a pad oxide over a substrate, structuring the pad oxide according to a nitride masking layer, etching trenches into the substrate according to the nitride masking layer, filling the trenches with one or more dielectric materials (such as silicon dioxide or silicon nitride), and removing any excess of the dielectric material from over the substrate. STI formation processes may further utilize a wet etching process to remove the nitride masking layer and / or the pad oxide used during the formation of the STI structures.

[0014] During the formation of an STI structure, divots can form within the upper surface of the STI structure (for example, due to the wet etching process used to remove the nitride masking layer and / or pad oxide). A conductive gate material of a transistor device can subsequently fill the divots within the STI structure, causing the conductive gate material to have sharp edges. During operation of the transistor device, these sharp edges can amplify an electric field generated by the gate structure and reduce the device's threshold voltage near the divots, resulting in a problem called kink effect, defined by a double hump in a drain current-to-gate voltage relationship. Kink effect has several negative consequences, including the difficulty of modeling it (for example, during SPICE curve fitting and / or parameter extraction).Furthermore, it was understood that the thermal processes used in several gate-dielectric processes (for example, processes that form different gate dielectrics in different regions of a substrate) can enhance the diffusion of dopants from the substrate (for example, from a well region) into the STI structures, which can result in lower dopant concentrations along the edges of a channel region of a transistor device. These lower dopant concentrations further reduce the threshold voltage along the edges of the channel region, thus making the kink effect more difficult to achieve.

[0015] The present disclosure relates, in several examples, to a transistor device having a gate structure comprising multiple gate electrode regions with different work functions configured to reduce the transistor device's susceptibility to the kink effect, and an associated forming method. The transistor device includes an insulating structure arranged within a substrate. The insulating structure has internal surfaces defining one or more divots recessed beneath a top surface of the insulating structure, and sidewalls defining an opening that exposes the substrate. A source region is arranged within the opening. A drain region is also arranged within the opening and separated from the source region by a channel region. A gate structure extends across the opening between the source region and the drain region.The gate structure comprises a first gate electrode region, which has a first composition of one or more materials, and a second gate electrode region, which has a second composition of one or more materials that differs from the first. The second gate electrode region is positioned over the divots. The different material compositions within the gate structure have different work functions, which can be used to tune the threshold voltage of the transistor device to compensate for the undesirable effect of divots and / or dopant diffusion on the threshold voltage.

[0016] The Fig. Figures 1A-1B illustrate some examples of an integrated chip that has a transistor component comprising a gate structure configured to improve component performance.

[0017] As in a cross-sectional view 100 of the Fig. As shown in Figure 1A, the integrated chip comprises a substrate 102 having internal surfaces that define a trench 103 extending within an upper surface 102u of the substrate 102. An insulating structure 104 (for example, a shallow trench insulating structure - STI) comprising one or more dielectric materials is arranged within the trench 103. The insulating structure 104 includes sidewalls that define an opening 106 exposing the upper surface 102u of the substrate 102. The opening 106 corresponds to an active area (that is, an area of ​​the substrate 102 in which a transistor component is located). The insulating structure 104 further includes surfaces that define one or more divots 108 recessed beneath an uppermost surface of the insulating structure 104. One or more divots 108 can be set up along edges of the insulation structure 104 that are close to the opening 106.

[0018] As shown in the top view 122 of the Fig. As shown in Figure 1B, the isolation structure 104 extends continuously around the opening 106, and one or more divots 108 within the isolation structure 104 surround the opening 106. A source region 124 and a drain region 126 are arranged in the substrate 102 within the opening 106. The source region 124 and the drain region 126 each comprise highly doped regions arranged in the substrate 102. The source region 124 is separated from the drain region 126 along the first direction 128 by a channel region 125. A gate structure 110 extends over the channel region 125 along a second direction 130, which is perpendicular to the first direction 128.

[0019] Referring again to cross-sectional view 100 of the Fig. In 1A, the gate structure 110 is arranged above the substrate 102 and extends beyond opposite edges of the opening 106. The gate structure 110 comprises a gate dielectric 112 arranged above the substrate 102 and a gate electrode 113 separated from the substrate 102 by the gate dielectric 112. A conductive contact 120 is arranged within a dielectric structure 118 (for example, an interlayer dielectric - ILD) above the substrate 102. The conductive contact 120 extends perpendicularly from a top surface of the gate structure 110 to a top surface of the dielectric structure 118.

[0020] The gate electrode 113 comprises a first gate electrode region 114 and a second gate electrode region 116. The first gate electrode region 114 has a first work function, and the second gate electrode region 116 has a second work function that is different from the first (for example, higher). In some examples, the first gate electrode region 114 comprises a first composition of one or more materials that has a first work function, and the second gate electrode region 116 comprises a second composition of one or more materials that is different from the first composition and has the second work function. In some examples, the first composition of one or more materials and the second composition of one or more materials do not comprise the same material.

[0021] In some examples where the transistor component is an NMOS component, the first composition of one or more materials (in the first gate electrode region 114) comprises an n-type gate metal with a first work function, while the second composition of one or more materials (in the second gate electrode region 116) comprises a p-type gate metal with a second work function that is greater than the first work function (in order to increase an absolute value of a threshold voltage below the second gate electrode region 116).In other examples, where the transistor component is a PMOS device, the first composition of one or more materials (in the first gate electrode region 114) comprises a p-type gate metal with a first work function, while the second composition of one or more materials (in the second gate electrode region 116) comprises an n-type gate metal with a second work function that is lower than the first work function (to increase the absolute value of a threshold voltage below the second gate electrode region 116). In some examples, the gate structure 110 may comprise multiple first gate electrode regions and / or multiple second gate electrode regions. In some examples, the gate structure 110 may comprise separate second gate electrode regions 116 arranged on opposite sides of the opening 106 and separated from a first gate electrode region 114.

[0022] As shown in the top view 122 of the Fig. As shown in Figure 1B, the first gate electrode region 114 and the second gate electrode region 116 are positioned directly above the channel region 125. In some examples, the channel region 125 extends continuously from directly below the second gate electrode region 116 to beyond the outer edges of the second gate electrode region 116 along the first direction 128 and along the second direction 130. In other examples, the second gate electrode region 116 extends over a distance Δx across opposite sides of the channel region 125 along the second direction 130.

[0023] During operation, the gate structure 110 is configured to form a conductive channel within the channel region 125 in response to an applied gate voltage. The different work functions of the different gate electrode regions cause charge carriers within the channel region to respond differently to the applied voltage. For example, the higher work function of the second gate electrode region 116 causes the gate electrode 113 to use a higher threshold voltage to form a conductive channel under the second gate electrode region 116 than under the first gate electrode region 114.The higher threshold voltage required to form a conductive channel under the second gate electrode region 116 compensates for a reduction in the threshold voltage caused by one or more divots 108 and / or by diffusion of dopants (for example, boron) from the substrate 102 into the insulation structure 104. By mitigating the effect of one or more divots 108 and / or by diffusion of dopants from the substrate 102 into the insulation structure 104, the performance of the transistor device is improved (for example, the kink effect in the drain current is reduced).

[0024] The Fig. Figures 2A-2B illustrate some exemplary band diagrams along the first gate electrode region and along the second gate electrode region of the integrated chip. Fig. 1A-1B.

[0025] Fig. Figure 2A illustrates some exemplary band diagrams 200 and 202 for an NMOS transistor along the first gate electrode region and along the second gate electrode region of the integrated chip. Fig. 1A-1B.

[0026] As shown in band diagram 200, the gate dielectric 112 forms an energy barrier between the substrate 102 and the first gate electrode region 114. The first composition of one or more materials (for example, an n-metal gate material) gives the first gate electrode region 114 a first work function, which causes an upward bending of the conduction band E. c and of the valence band E v within substrate 102 caused (so that within substrate 102 there is a distance between a vacuum level and E cand / or Ev increases with decreasing distance from the gate dielectric 112). As shown in the band diagram 202, the gate dielectric 112 also forms an energy barrier between the substrate 102 and the second gate electrode region 116. The second composition of one or more materials (for example, a p-metal gate material) imparts a second work function to the second gate electrode region 116. The second work function of the second composition of one or more materials is greater than the first work function of the first composition of one or more materials (that is, the second gate electrode region 116 has a greater work function than the first gate electrode region 114). The greater second work function causes a downward bending of the conduction band E. c and the valence band Ev within substrate 102 (such that within substrate 102 there is a distance between the vacuum level and E cand / or Ev decreases with the decrease of the distance from the gate dielectric 112).

[0027] Fig. Figure 2B illustrates some exemplary band diagrams 204 and 206 for an NMOS transistor along the second gate electrode region and along the second gate electrode region of the integrated chip. Fig. 1A-1B.

[0028] As shown in band diagram 204, the gate dielectric 112 forms an energy barrier between the substrate 102 and the first gate electrode region 114. The first composition of one or more materials (for example, a p-metal gate material) gives the first gate electrode region 114 a first work function, which causes a downward bending of the conduction band E. c and of the valence band Ev within substrate 102 (so that within substrate 102 there is a distance between a vacuum level and E cand / or Ev decreases with decreasing distance from the gate dielectric 112). As shown in the band diagram 206, the gate dielectric 112 also forms an energy barrier between the substrate 102 and the second gate electrode region 116. The second composition of one or more materials (for example, an n-metal gate material) imparts a second work function to the second gate electrode region 116. The second work function of the second composition of one or more materials is lower than the first work function of the first composition of one or more materials (that is, the second gate electrode region 116 has a lower work function than the first gate electrode region 114). The lower second work function can cause an upward bending of the conduction band E. c and of the valence band Ev within substrate 102 cause (so that within substrate 102 there is a distance between the vacuum level and E cand / or Ev increases with decreasing distance from the gate dielectric 112).

[0029] Fig. 2C illustrates some examples of graphs, 208 and 212, which show examples of how different features of the integrated chip affect the absolute threshold voltage (shown along the y-axis) depending on a position within an active area (shown along the x-axis).

[0030] Graph 208 illustrates an example of the effect of divots and / or dopant (for example, boron) diffusion on the absolute threshold voltage. As shown by line 210 of Graph 208, due to one or more divots within the insulation structure and / or dopant diffusion into the insulation structure, the absolute threshold voltage under the second gate electrode region 116 is lower than under the first gate electrode region 114.

[0031] Graph 212 illustrates an example of the effect of the different work functions of the first gate electrode region 114 and the second gate electrode region 116 on the absolute threshold voltage. As shown by line 214 of graph 212, due to the different work functions of the first gate electrode region 114 and the second gate electrode region 116, the gate structure has a higher absolute threshold voltage under the second gate electrode region 116 than under the first gate electrode region 114. In some examples, there is a difference in the absolute threshold voltage AV. TH under the first gate electrode area 114 and under the second gate electrode area 116 in a range of about 0.5 V and about 1.5 V.

[0032] The higher absolute threshold voltage under the second gate electrode region 116 (shown in Graph 212) compensates for the decrease in the absolute threshold caused by the one or more divots and / or by the diffusion of dopants (shown in Graph 208) from the substrate into the insulation structure. By mitigating the effect on the one or more divots or on the diffusion of dopants from the substrate into the insulation structure, the performance of the transistor device is improved (for example, the kink effect in the drain current, caused by the effect of the one or more divots on the electric field generated by the gate structure, is reduced).

[0033] The Fig. 3A-3C illustrate some additional examples of an integrated chip that has a transistor component comprising a gate structure configured to improve component performance.

[0034] As shown in the top view 300 of the Fig. As shown in Figure 3A, the integrated chip has an isolation structure 104 that defines an opening 106 exposing a substrate 102 within an active area. In some examples, the opening 106 can have a substantially rectangular shape. In other examples, the opening 106 can have an alternative shape (for example, a circular shape). A source region 124 is arranged within the opening 106. A drain region 126 is also arranged within the opening 106 at a separate location, and the source region 124 extends along a first direction 128.

[0035] A gate structure 110 extends across the opening 106 along a second direction 130, which is perpendicular to the first direction 128. The gate structure 110 is located between the source region 124 and the drain region 126. The gate structure 110 comprises a first gate electrode region 114 and a second gate electrode region 116. In some examples, the first gate electrode region 114 comprises a continuous segment, while the second gate electrode region 116 may comprise two or more separate and distinct segments. In some examples, the first gate electrode region 114 can include an n-type gate metal (for example, a metal having a work function of less than or equal to about 4.2 eV), while the second gate electrode region 116 can include a p-type metal (for example, a metal having a work function greater than or equal to about 5.0 eV).In some examples, the first gate electrode region 114 may, for example, comprise an n-type metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum silicon nitride, chromium, tungsten, copper, titanium-aluminum, or the like. In some examples, the second gate electrode region 116 may comprise a p-type gate metal such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, or the like.

[0036] In some examples, the first gate electrode region 114 touches the second gate electrode region 116 along the first direction 128 and along a second direction 130 that is perpendicular to the first direction 128. In some examples, the second gate electrode region 116 is located within openings in the first gate electrode region 114. In some such examples, the first gate electrode region 114 extends around a circumference of the gate structure 110, such that the second gate electrode region 116 is completely surrounded by the first gate electrode region 114.

[0037] In some examples, the second gate electrode region 116 can have a first length L1 along the first direction 128 that is smaller than a second length L2 of the gate structure 110 along the first direction 128. In some examples, the second gate electrode region 116 can span one or more divots 108 along the second direction 130 (that is, extend beyond opposite sides of them). For example, the second gate electrode region 116 can extend across a first side of the one or more divots 108 by a first non-zero distance 304 and across a second side of the one or more divots 108 by a second non-zero distance 306. In some examples, the first non-zero distance 304 can be essentially the same as the second non-zero distance 306.In some examples, the first gate electrode region 114 and the second gate electrode region 116 can be essentially symmetrical along a first line extending in the first direction 128, and / or along a second line extending in the second direction 130.

[0038] In some examples, sidewall spacers 302 can be arranged along the outer sidewalls of the gate structure 110. The sidewall spacers 302 comprise one or more dielectric materials. In various examples, the sidewall spacers 302 can, for example, comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide), or the like. In some examples, the gate structure 110 and / or the sidewall spacers 302 can extend along the first direction 128 across the source region 124 and / or the drain region 126.

[0039] Fig. Figure 3B illustrates a cross-sectional view 308 of the integrated chip of the Fig. 3A along the cross-sectional line A-A'.

[0040] As shown in a cross-sectional view 308, the first gate electrode region 114 and the second gate electrode region 116 are separated from the substrate 102 by a gate dielectric 112. In some examples, a well region 310 may be arranged within the substrate 102 below the opening 106. The well region 310 has a doping type that differs from that of the substrate 102. For example, in some examples where the transistor device is an NMOS transistor, the substrate 102 may have p-type doping, the well region 310 may have n-type doping, and the source region 124 and the drain region 126 may have p-type doping.

[0041] The first gate electrode region 114 laterally contacts the second gate electrode region 116, such that the first composition of one or more materials laterally contacts the second composition of one or more materials. The second gate electrode region 116 is located above the one or more divots 108. In some examples, the second composition of one or more materials fills portions of the one or more divots 108 within the insulating structure 104. In such examples, the second composition of one or more materials extends to below a bottom surface of the first composition of one or more materials. In some examples, the second composition of one or more materials directly contacts the surfaces of the insulating structure 104 that define the one or more divots 108.In some examples, the first composition of one or more materials extends from within the one or more divots 108 to above the top surface of the insulation structure 104 and above the gate dielectric 112.

[0042] In some examples, a contact etch stop layer (CESL) 312 can be arranged along sides of the gate structure 110 and the insulation structure 104. In various examples, the CESL 312 can comprise a nitride (for example, silicon nitride), a carbide (for example, silicon carbide), or the like.

[0043] A dielectric structure 118 (for example, an interlayer dielectric layer - ILD) is arranged over the substrate 102. In some examples, the dielectric structure 118 may comprise borosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), or the like. A conductive contact 120 extends perpendicularly through the dielectric structure 118 to the gate structure 110. The conductive contact 120 may comprise tungsten, copper, aluminum-copper, or another conductive material. In some examples, the conductive contact 120 touches the first gate electrode region 114. In such examples, the conductive contact 120 has outermost sidewalls that are offset laterally from the second gate electrode region 116 by a non-zero distance.

[0044] Fig. 3C illustrates a cross-sectional view 314 of the integrated chip of the Fig. 3A along the cross-sectional line B-B'.

[0045] As shown in a cross-sectional view 314, the source region 124 and the drain region 126 are located within the basin region 310 on opposite sides of the gate structure 110. In some examples, source and drain extension regions 316 can project outward from the source region 124 and the drain region 126 to below the sidewall spacers 302 and / or the gate structure 110. In such examples, a channel region 125 extends between the source and drain extension regions 316. In some examples, a silicide layer 318 can be provided on the source region 124 and the drain region 126. In some examples, the silicide layer 318 can, for example, comprise a nickel silicide.

[0046] The Fig. Figure 4A illustrates a top view showing an embodiment of an integrated chip that includes a gate structure configured to improve component performance. Fig. Figure 4B illustrates a top view showing an alternative embodiment of an integrated chip that includes a gate structure configured to improve component performance.

[0047] Referring to the top view 400 of the Fig. In section 4A, the integrated chip comprises an isolation structure 104 that defines an opening 106 exposing the substrate 102. A source region 124 and a drain region 126 are arranged within the opening 106 and separated from each other along a first direction 128. A gate structure 110 extends in a second direction 130 above the opening 106 and between the source region 124 and the drain region 126. The gate structure 110 comprises a first gate electrode region 114 and a second gate electrode region 116. The second gate electrode region 116 comprises a first segment arranged along a first side 110a of the gate structure 110 near the source region 124, and a second segment arranged along an opposite second side 110b of the gate structure 110 near the drain region 126.The second gate electrode region 116 is not continuous between the first side 110a of the gate structure 110 and the second side 110b of the gate structure 110, such that segments of the second gate electrode region 116 along the first direction 128 are separated by the first gate electrode region 114. In some embodiments, the second gate electrode region 116 is symmetrical about a first line that divides the gate structure 110 into two along the first direction 128, and a second line that divides the gate structure 110 into two along the second direction 130.

[0048] Referring to plan view 402 of the Fig. In some examples, the integrated chip 4B comprises a gate structure 110 extending in a second direction 130 across an opening 106 and between a source region 124 and a drain region 126. The gate structure 110 includes a first gate electrode region 114 and a second gate electrode region 116. The second gate electrode region 116 is arranged above one or more divots 108 in the isolation structure 104 and is located along a first side 110a of the gate structure 110 and is separated from an opposite second side 110b of the gate structure 110.

[0049] It has been understood that forming different dielectric gate layers within different regions of an integrated chip can exacerbate the kink effect within transistor devices due to additional etching processes, which can increase the size of divots within insulating structures, and / or additional thermal processes, which can increase dopant diffusion. For example, in some processes used to form multiple dielectric gate layers, a gate oxide can be thermally grown on a substrate (but not on surrounding insulating structures). The gate oxide can then be removed from the substrate in some device regions that use a different dielectric gate layer. This gate oxide removal is achieved through etching, which also affects the insulating structures.Due to over-etching, removing the gate oxide can increase the size of the divots within the isolation structures.

[0050] The Fig. Figures 5A-5B illustrate some examples of an integrated chip that has different dielectric gate layers within different areas.

[0051] The integrated chip comprises a first logic area 502, an embedded memory area 512, and a second logic area 522. Isolation structures 104 are arranged within the substrate 102 within the first logic area 502, the embedded memory area 512, and the second logic area 522. The first logic area 502 includes a high-voltage transistor device configured to provide a higher breakdown voltage than a dual-gate transistor device arranged within the second logic area 522.

[0052] As in a cross-sectional view 500 of the Fig. As shown in Figure 5A, the insulating structure 104 within the first logic area 502 has side walls that define an opening 106 exposing a first surface of the substrate 102. A high-voltage gate electrode 508 is positioned above the opening 106 and separated perpendicularly from the substrate 102 by a dielectric high-voltage gate layer 504 and a dielectric dual-gate layer 506, which has a first dielectric gate layer 506a and a second dielectric gate layer 506b. In some examples, the high-voltage gate electrode 508 is separated perpendicularly from a high-voltage tray 512 located within the substrate 102.

[0053] The high-voltage gate electrode 508 comprises a first gate electrode region 114, which has a first work function, and a second gate electrode region 116, which has a second work function that is greater than the first work function. The second gate electrode region 116 is arranged via divots in the insulating structure 104 and contacts side walls of the first gate electrode region 114. As shown in a top view 530 of the Fig. As shown in Figure 5B, the second gate electrode region 116 is set up directly above one or more divots 108 within the insulation structure 104, and the first gate electrode region 114 continuously surrounds the second gate electrode region 116.

[0054] As in a cross-sectional view 500 of the Fig. As shown in Figure 5A, the insulating structure 104 within the embedded memory area 512 has side walls that define an opening 514 exposing a second surface of the substrate 102. In some examples, a control gate electrode 518 is positioned above the opening 514 and separated from the substrate 102 by the dielectric dual-gate layer 506 and a dielectric charge-trapping structure 516. In some examples, the dielectric charge-trapping structure 516 may include an ONO structure having a nitride layer positioned between a first oxide layer and a second oxide layer. In some examples, the control gate electrode 518 is separated perpendicularly from a control trough 520 located within the substrate 102. As shown in a top view 530 of the Fig. As shown in Figure 5B, the embedded memory region 512 can also include a select-gate electrode 532. The control-gate electrode 518 and the select-gate electrode 532 share a common source / drain region 534. Although the embedded memory region 512 of the Fig. While 5A-5B comprehensively illustrates a SONOS flash storage device, it is clear that the embedded memory area 512 can encompass different types of memory components in other examples. For instance, in other examples, the embedded memory area 512 might encompass a different type of flash storage device, such as a floating-gate flash storage device, a split-gate flash storage device, or the like.

[0055] As in a cross-sectional view 500 of the Fig. As shown in Figure 5A, the insulation structure 104 within the second logic region 522 has side walls that define an opening 524, exposing a third upper surface of the substrate 102. A logic gate electrode 526 is separated perpendicularly from a logic trough region 528 within the substrate 102 by means of the dielectric dual-gate layer 506. As shown in a top view 530 of the Fig. As shown in Figure 5B, the logic gate electrode 526 extends between a source region 536 and a drain region 538, which are located within the opening 524 within the second logic region 522. In some examples, the logic gate electrode 560 may be homogeneous (that is, have the same composition of gate materials throughout the entire gate electrode). In other examples (not shown), the logic gate electrode 526 may comprise a first gate electrode region, which has a first work function, and a second gate electrode region, which has a second work function that is greater than the first work function.

[0056] The Fig. Figures 6A to 17 illustrate some examples of cross-sectional and top views corresponding to a method for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. Although the Fig. Sections 6A to 17, which describe a procedure, make it clear that the structures described in the Fig. The provisions described in sections 6A to 17 are not limited to the procedure, but rather can be independent and separate from the procedure.

[0057] As seen in a top view, 600 of the Fig. 6A and in a cross-sectional view 602 of the Fig. As shown in Figure 6B, an insulation structure 104 is formed within a trench 103 within a substrate 102. The insulation structure 104 defines an opening 106 that exposes the upper surface 102u of the substrate 102. As shown in the top view 600 of the Fig. As shown in Figure 6A, the opening 106 has an essentially rectangular shape. As shown in a cross-sectional view 602 of the Fig. As shown in Figure 6B, the isolation structure 104 is arranged within a trench 103 defined by the inner surfaces of the substrate 102. During the formation of the isolation structures 104, one or more divots 108 can be formed within the isolation structure 104, recessed beneath a top surface of the isolation structure 104. The one or more divots 108 can be arranged along edges of the isolation structure 104 that are close to the opening 106.

[0058] In some examples, the insulating structure 104 can be formed by selectively etching the substrate 102 to create the groove 103. One or more dielectric materials are subsequently formed within the groove 103. In various examples, the substrate 102 can be etched by a wet etchant (for example, hydrofluoric acid, sodium hydroxide, or the like) or a dry etchant (which, for example, contains an etching chemical including fluorine, chlorine, or the like). In various examples, the substrate 102 can be any type of semiconductor material (for example, silicon, SiGe, SOI, etc.), as well as any other type of semiconductor, epitaxial, dielectric, or metal layers bonded to it. In various examples, the one or more dielectric materials can include an oxide, a nitride, a carbide, or the like.

[0059] In some additional examples, the insulating structure 104 can be formed by using a thermal process to form a pad oxide over the substrate 102, followed by the formation of a nitride film over the pad oxide. The nitride film is then patterned (for example, using a photosensitive material such as a photoresist), and the pad oxide and the substrate 102 are patterned according to the nitride film to form the trench 103 within the substrate 102. The trench 103 is then filled with one or more dielectric materials, followed by a planarization process (for example, a chemical-mechanical planarization process) to expose a top surface of the nitride film, and by etching to remove the nitride film.

[0060] As seen in a top view, 700 of the Fig. 7A and in a cross-sectional view 702 of the Fig. As shown in Figure 7B, a gate dielectric 112 is formed over the substrate 102 and within the opening 106. In some examples, the gate dielectric 112 can comprise an oxide (for example, silicon oxide), a nitride (for example, silicon oxynitride), or the like. In some examples, the gate dielectric 112 can be formed by a vapor deposition technique (for example, PVD, CVD, PE-CVD, ALD, etc.). In other examples, the gate dielectric 112 can be formed by a thermal growth process. In some examples, an implantation process can be performed prior to the formation of the gate dielectric 112 to create a trough region (not shown) in the substrate 102. In some examples, a dielectric sacrificial layer (not shown) can be formed over the substrate 102 prior to the implantation process to control the depth of the trough region.The dielectric sacrificial layer is then removed before the formation of the gate dielectric 112.

[0061] In some examples, the gate dielectric 112 can be formed as part of a multiple dielectric gate process, in which different dielectric gate layers are formed within different regions of the substrate 102. In some examples, the multiple dielectric gate process can, for instance, form a high-voltage dielectric gate layer (for example, by a thermal process) over a high-voltage well within the substrate 102. The high-voltage dielectric gate layer can then be removed from one or more regions of a chip (for example, within the region of an embedded memory), and a dual-gate dielectric layer can be placed over a logic well within the substrate 102 (for example, by one or more deposition processes).It was understood that the formation of multiple dielectric gate layers can exacerbate the kink effect within associated transistor devices by increasing the size of one or more divots 108 within the structure 104 (due to the additional etching processes carried out to remove the dielectric gate layers from different areas of the substrate) and / or by increasing dopant diffusion from the substrate 102 to the insulating structure 104 due to additional thermal processes used to form the dielectric gate layers.

[0062] As seen in a top view, 800 of the Fig. 8A and in a cross-sectional view 804 of the Fig. As shown in Figure 8B, a gate sacrificial material 802 is formed over the gate dielectric 112 and over the insulating structure 104. The gate sacrificial material 802 can fill one or more divots 108 within the upper surface of the insulating structure 104. The gate sacrificial material 802 can be formed by a deposition process (for example, CVD, PE-CVD, PVD, or ALD). In some examples, the gate sacrificial material 802 can comprise doped polysilicon. The gate dielectric 112 and the gate sacrificial material 802 are structured to define a gate sacrificial structure that extends over the opening 106 and over the insulating structure 104. In some examples, the gate dielectric 112 and the gate sacrificial material 802 can be structured according to a masking layer (not shown) formed over the gate sacrificial material 802.In various examples, the masking layer can comprise a light-sensitive material (for example, a photoresist) or a hard mask layer.

[0063] In some examples, one or more sidewall spacers 302 can be formed on opposite sides of the gate sacrificial material 802. In some examples, the one or more sidewall spacers 302 can be formed by depositing a spacer material (for example, a nitride or an oxide) on horizontal and vertical surfaces of the gate sacrificial material 802, after which the spacer material is etched to remove it from the horizontal surfaces, thus removing the one or more sidewall spacers 302.

[0064] As seen in a top view of 900 of the Fig. 9A and a cross-sectional view 902 of the Fig. As shown in Figure 9B, a source region 124 and a drain region 126 are formed within the substrate 102 on opposite sides of the gate sacrificial material 802. The source region 124 and the drain region 126 contain a dopant type that is different from the dopant type of the substrate surrounding the source region 124 and the drain region 126. For example, the source region 124 and the drain region 126 can contain a first dopant type (for example, n-type doping) within a substrate 102 or a trough region (not shown) that has a second dopant type (for example, p-type doping).

[0065] In some examples, the source region 124 and the drain region 126 can be formed by an implantation process. This implantation process can be carried out by selectively implanting a dopant 904 into the substrate 102 according to a mask that includes the gate sacrificial material 802 and the sidewall spacers 302. In various examples, the dopant 904 can be a p-type dopant (e.g., boron, gallium, etc.) or an n-type dopant (e.g., phosphorus, arsenic, etc.). In some examples, after implanting the dopant 904 into the substrate 102, a drive-in anneal is performed to distribute the dopant 904 within the substrate 102. In some examples, additional implantation processes can be performed to form source and drain expansion regions within the substrate.In such examples, the additional implantation processes may include angled implantation processes, so that the source and drain extension areas extend below the gate sacrificial material 802.

[0066] As seen in a top view, 1000 of the Fig. 10A and a cross-sectional view 1004 of the Fig. As shown in Figure 10B, a first dielectric layer 1002 (for example, a first interlayer dielectric (ILD) layer) is formed over the substrate 102. The first dielectric layer 1002 covers the gate sacrificial material 802 and the sidewall spacers 302. In various examples, the first dielectric layer 1002 can comprise an oxide, PSG, a low-θ dielectric, or another dielectric and can be formed by a vapor deposition process (for example, CVD, PVD, or ALD).

[0067] As in a top view 1100 of the Fig. 11A and a cross-sectional view 1102 of the Fig. As shown in Figure 11B, a planarization process is performed to remove the first dielectric layer 1002 above the gate sacrificial material 802 and the sidewall spacers 302. The planarization process exposes an upper surface of the gate sacrificial material 802, while leaving a portion of the first dielectric layer laterally surrounding the gate sacrificial material 802 and the sidewall spacers 302. In some examples, the planarization process may include a chemical-mechanical planarization (CMP) process configured to form a substantially planar surface along line 1104.

[0068] As in a top view 1200 of the Fig. 12A and in a cross-sectional view 1208 of the Fig. As shown in Figure 12B, a photosensitive material 1204 is formed over the substrate 102. In some examples, the photosensitive material 1204 can comprise a positive or negative photoresist formed over the substrate 102 by a spin-coating process. The photosensitive material 1204 is selectively exposed to electromagnetic radiation 1210 according to a photomask 1202. The electromagnetic radiation 1210 modifies the solubility of the exposed areas within the photosensitive material 1204 to define soluble regions. The photosensitive material 1204 is then developed to define openings 1206 within the photosensitive material 1204 by removing the soluble regions.

[0069] As in a top view 1300 of the Fig. 13A and in a cross-sectional view 1304 of the Fig. As shown in Figure 13B, portions of the gate sacrificial material 802 located beneath the openings 1206 within the photosensitive material 1204 are selectively removed. These portions of the gate sacrificial material 802 can be removed by selectively exposing the gate sacrificial material 802 to a first etching agent 1306 in accordance with the photosensitive material 1204. The removal of these portions of the gate sacrificial material 802 results in one or more first openings 1302 extending through the gate sacrificial material 802 to the gate dielectric 112 and the insulating structure 104. The one or more first openings 1302 are located above the one or more divots 108. In various examples, the first etchant may comprise a dry etchant containing an etchant chemical that includes a fluorine species (for example, CF4, CHF3, C4F8, etc.) or a wet etchant containing hydrofluoric acid (HF).

[0070] As in a top view 1400 of the Fig. 14A and a cross-sectional view 1402 of the Fig. As shown in Figure 14B, a second composition of one or more materials is formed within the one or more first openings 1302 to form a second gate electrode region 116, which has a second work function. The second gate electrode region 116 laterally contacts the gate sacrificial material 802. In some examples, the second composition of one or more materials can completely fill the one or more first openings 1302. In some examples, the second composition of one or more materials can include a p-type gate metal such as platinum, tungsten nitride, molybdenum nitride, tantalum nitride, nickel, or the like. In several examples, the second composition of one or more materials can be formed by a vapor deposition technique (for example, PVD, CVD, PE-CVD, ALD, etc.).

[0071] As seen in a top view, 1500 of the Fig. 15A and in a cross-sectional view 1504 of the Fig. As shown in Figure 15B, a second part of the sacrificial material 802 is removed. In some examples, the second part of the sacrificial material 802 may be a remnant of the gate sacrificial material 802. The second part of the gate sacrificial material 802 can be removed by exposing the gate sacrificial material 802 to a second etchant 1506. The removal of the second part of the gate sacrificial material 802 results in one or more second openings 1502 extending through the gate sacrificial material 802 to the gate dielectric 112 and the insulating structure 104. In some examples, the one or more second openings 1502 may surround the second gate electrode region 116. In various examples, the second etchant may include a dry etchant containing an etching chemical that includes a type of fluorine (for example, CF4, CHF3, C4F8, etc.) or a wet etchant containing hydrofluoric acid (HF).

[0072] As in a top view 1600 of the Fig. 16A and in a cross-sectional view 1602 of the Fig. As shown in Figure 16B, a first composition of one or more materials is formed within the one or more second openings 1502 to form a gate structure 110 comprising a first gate electrode region 114 and a second gate electrode region 116, which laterally contacts the first gate electrode region 114. The first gate electrode region 114 has a first work function that differs from (for example, is lower than) the second work function of the second gate electrode region 116. In some examples, the first composition of one or more materials may include an n-type gate metal such as aluminum, tantalum, titanium, hafnium, tantalum nitride, or the like. In several examples, the first composition of one or more materials may be formed using a vapor deposition technique (for example, PVD, CVD, PE-CVD, ALD, etc.).

[0073] As in a cross-sectional view 1700 of the Fig. As shown in Figure 17, a second dielectric layer 1702 (for example, a second ILD layer) is formed over the first dielectric layer 1002 and the gate structure 110. A conductive contact 120 is formed within the second dielectric layer 1702. The conductive contact 120 extends from an upper surface of the second dielectric layer 1702 to the gate structure 110. In some examples, the conductive contact 120 can be formed by selectively etching the second dielectric layer 1702 to create an opening 1704. The opening 1704 is then filled with a conductive material to form the conductive contact 120. A planarization process (for example, a chemical-mechanical polishing process) can be carried out after the formation of the conductive material to planarize the upper surfaces of the second dielectric layer 1702 and the conductive contact 120 together.In various examples, the conductive material can include tungsten, copper, aluminum-copper, or another conductive material.

[0074] Fig. Figure 18 illustrates a flowchart of some examples of a process 1800 for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance.

[0075] Although the disclosed procedures (for example, procedures 1800 and 2900) are illustrated and described here as a series of processes or events, it is appreciated that the illustrated sequence of such processes or events is to be interpreted as illustrative. Some processes, for example, may occur in different sequences and / or concurrently with other processes or events separate from those illustrated and / or described here. Furthermore, processes not illustrated may be required to implement one or more aspects or examples of the description. Additionally, one or more of the processes depicted here may be carried out in one or more separate processes and / or stages.

[0076] In 1802, an isolation structure is formed within a substrate. The isolation structure comprises sidewalls that define an opening exposing an upper surface of the substrate, and surfaces that define one or more divots within an upper surface of the isolation structure. Fig. Figures 6A-6B illustrate some examples corresponding to the process of 1802.

[0077] At 1804, a gate sacrificial structure is formed, which has a gate dielectric and a gate sacrificial material that extends across the opening. Fig. Figures 7A-8B illustrate some examples corresponding to the process of 1804.

[0078] At 1806, source and drain regions are formed within the opening on opposite sides of the gate sacrificial structure. Fig. 9A-9B illustrate some examples corresponding to the process of 1806.

[0079] At 1808, a first dielectric layer is formed over the substrate and over the gate sacrificial structure. Fig. 10A-11B illustrate some examples corresponding to the process of 1808.

[0080] At 1810, a portion of the gate sacrificial material above one or more divots is removed to form one or more initial openings extending through the gate sacrificial material. Fig. 12A-12B illustrate some examples corresponding to the process 1810.

[0081] At 1812, a second composition of one or more materials is formed within the one or more first openings. This second composition of one or more materials defines one or more second gate electrode regions, which have a second work function. Fig. 13A-13B illustrate some examples corresponding to the process of 1812.

[0082] At 1814, a remnant of the gate sacrificial material is removed to form one or more secondary openings adjacent to the second gate electrode region. Fig. 14A-14B illustrate some examples corresponding to the process of 1814.

[0083] In 1816, a first composition of one or more materials is formed within one or more second openings in place of the remainder of the gate sacrificial material. This first composition of one or more materials defines one or more first gate electrode regions that have a first work function that differs from (for example, is lower than) the second work function. Fig. 15A-15B illustrate some examples corresponding to the process of 1816.

[0084] At 1818, a second dielectric layer forms above the first and second compositions of one or more materials. Fig. 16A-16B illustrate some examples corresponding to the process of 1818.

[0085] At 1820, a conductive contact is formed within a second dielectric layer. Fig. Figure 17 illustrates some examples corresponding to the process in 1820.

[0086] The Fig. Figures 19A to 28 illustrate cross-sectional and top views corresponding to some alternative examples of a method for forming an integrated chip that has a transistor component comprising a gate structure configured to improve component performance. Although the Fig. As described in sections 19A to 28 with reference to a procedure, it is clear that the structures described in the Fig. The provisions described in sections 19A to 28 are not limited to the procedure, but rather can be independent and separate from the procedure.

[0087] As seen in a top view from 1900, the Fig. 19A and in a cross-sectional view 1904 of the Fig. As shown in Figure 19B, an isolation structure 104 is formed within a trench 103 within a substrate 102. The isolation structure 104 defines a first opening 106a within a first region 1902a, corresponding to a first transistor type (for example, an NMOS transistor), and a second opening 106b within a second region 1902b, corresponding to a second transistor type (for example, a PMOS transistor). The first opening 106a and the second opening 106b expose upper surfaces 102u of the substrate 102. The isolation structure 104 is set up within a trench 103 defined by the inner surfaces of the substrate 102. During the formation of the isolation structure 104, one or more divots 108 can be formed within the isolation structure 104. One or more divots 108 are recessed beneath a top surface of the insulation structure 104.One or more divots 108 can be set up along edges of the isolation structure 104 that are near the first opening 106a and the second opening 106b.

[0088] As seen in a top view from 2000 Fig. 20A and in a cross-sectional view 2002 of the Fig. As shown in Figure 20B, a gate dielectric 112 is formed over the substrate 102 and within the first opening 106a and the second opening 106b.

[0089] As seen in a top view from 2100 Fig. 21A and in a cross-sectional view 2102 of the Fig. As shown in Figure 21B, a gate sacrificial material 802 is formed over the gate dielectric 112 and over the insulating structure 104. The gate sacrificial material 802 is structured to define gate sacrificial structures. In some examples, sidewall spacers 302 can be formed along sides of the gate sacrificial structures.

[0090] A first source region 124a and a first drain region 126a are formed within the substrate 102 on opposite sides of the gate sacrificial material 802 in the first opening 106a. A second source region 124b and a second drain region 126b are formed within the substrate 102 on opposite sides of the gate sacrificial material 802 in the second opening 106b. In some examples, the first source region 124a and the first drain region 126a can be formed by a first implantation process, while the second source region 124b and the second drain region 126b can be formed by a second implantation process. The first implantation process can be carried out, for example, by selectively implanting a first dopant type (which includes, for example, an n-type dopant such as phosphorus, arsenic, etc.) into the substrate 102 according to a first mask covering the second area 1902b.Similarly, the second implantation process can be carried out by selectively implanting a second dopant type (which includes, for example, a p-type dopant such as boron, gallium, etc.) into the substrate 102 according to a second mask covering the first area 1902a.

[0091] As seen in a top view from 2200 Fig. As shown in Figure 22, a first dielectric layer 1002 (for example, a first interlayer dielectric layer - ILD) is formed over the substrate 102. The first dielectric layer 1002 covers the gate sacrificial material 802 and the sidewall spacers 302. A planarization process is performed (along line 2202) to remove the first dielectric layer 1002 over the gate sacrificial material 802 and the sidewall spacers 302.

[0092] As in a cross-sectional view 2300 of the Fig. 23 shows the gate sacrifice material (802 of the Fig. 22) within the gate sacrificial structures. The removal of the gate sacrificial material results in the formation of replacement gate cavities 2302a-2302b between the sidewall spacers 302. A first gate metal 2304 is formed within the replacement gate cavities 2302a-2302b. In various examples, the first gate metal 2304 can comprise a p-type gate metal, such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, or the like. In various examples, the first gate metal 2304 can be formed by a vapor deposition technique (for example, PVD, CVD, PE-CVD, ALD, etc.).

[0093] As in a cross-sectional view 2400 of the Fig. As shown in Figure 24, a dielectric sacrificial material 2402 is formed over the first gate metal 2304 to fill the replacement gate cavities 2302a-2302b. In some examples, the dielectric sacrificial material 2402 may comprise a spin-on glass (SOG).

[0094] As in a cross-sectional view 2500 of the Fig. As shown in Figure 25, a masking layer comprises a photosensitive material 2502 formed over the dielectric sacrificial material 2402. The photosensitive material 2502 is structured to define openings 2504 within it. The first gate metal 2304 is selectively exposed to the photosensitive material 2502 with an etchant to remove portions of the first gate metal 2304 located beneath the openings 2504 within the photosensitive material 2502. The dielectric sacrificial material 2402 remains above the divots 108 within the first region 1902a, while the dielectric sacrificial material 2402 is removed above the divots 108 within the second region 1902b. After etching the first gate metal 2304, a residue of the photosensitive material 2502 and the dielectric sacrificial material 2402 are removed.

[0095] As in a cross-sectional view 2600 of the Fig. As shown in Figure 26, a second gate metal 2602 is formed within the replacement gate cavities 2302a-2302b above the first gate metal 2304. The second gate metal 2602 has a work function that differs from that of the first gate metal 2304. The second gate metal 2602 defines a first gate electrode region 114, which has a first work function, and a second gate electrode region 116, which has a second work function that differs from (for example, is higher than) the first work function. In the first region 1902a, the first gate electrode region 114 is arranged above one or more divots 108, while in the second region 1902b, the second gate electrode region 116 is arranged above one or more divots 108.In some examples, the second gate metal 2602 can be an n-type metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum silicon nitride, chromium, tungsten, copper, titanium-aluminum, or the like. In several examples, the second gate metal 2602 can be formed using a vapor deposition technique (for example, PVD, CVD, PE-CVD, ALD, etc.).

[0096] As in a cross-sectional view 2700 of the Fig. As shown in Figure 27, a planarization process (along a line 2702) is carried out on the second gate metal 2602 to remove excess of the second gate metal 2602 above the first dielectric layer 1002.

[0097] As in a cross-sectional view 2800 of the Fig. As shown in Figure 28, a second dielectric layer 1702 (for example, a second ILD layer) is formed over the first dielectric layer 1002 and the gate structure 110. A conductive contact 120 is formed within the second dielectric layer 1702.

[0098] Fig. 29 illustrates a flowchart of some alternative examples of a method 2900 for forming an integrated chip having a transistor component comprising a gate structure configured to improve component performance.

[0099] In 2902, an isolation structure is formed within a substrate. The isolation structure comprises sidewalls that define an opening exposing an upper surface of the substrate, and surfaces that define one or more divots within an upper surface of the isolation structure. Fig. 19A-19B illustrate some examples corresponding to process 2902.

[0100] At 2904, a gate sacrificial structure, which has a gate sacrificial material, is formed above the opening. Fig. 20A-20B illustrate some examples corresponding to process 2904.

[0101] At 2906, source and drain regions are formed within the opening on opposite sides of the gate sacrificial structure. Fig. 21A-21B illustrate some examples corresponding to process 2906.

[0102] At 2908, a first dielectric layer is formed over the substrate and around the gate sacrificial structure. Fig. Figure 22 illustrates some examples that correspond to process 2908.

[0103] At 2910, the gate sacrificial material is removed from within the gate sacrificial structure to form a replacement gate cavity. Fig. 23 illustrates some examples that correspond to process 2910.

[0104] At 2912, a first gate metal is formed within the gate replacement cavity. Fig. 23 illustrates some examples that correspond to process 2912.

[0105] At 2914, a gate sacrificial material is formed within the gate replacement cavity above the first gate metal. Fig. 24 illustrates some examples that correspond to process 2914.

[0106] In 2916, the dielectric gate material and the first gate metal are structured according to a masking layer. Fig. 25 illustrates some examples that correspond to process 2916.

[0107] At 2918, the dielectric sacrificial material is removed from inside the replacement gate cavity. Fig. 26 illustrates some examples that correspond to process 2918.

[0108] At 2920, a second gate metal is formed within the gate replacement cavity above the first gate metal. Fig. 26 illustrates some examples that correspond to process 2920.

[0109] At 2922, a planarization process is performed to remove the second gate metal above the first dielectric layer. Fig. 27 illustrates some examples that correspond to process 2922.

[0110] At 2924, a conductive contact is formed within a second dielectric layer above the first dielectric layer. Fig. 28 illustrates some examples that correspond to process 2924.

[0111] In some examples, the present disclosure relates to a transistor device having a gate structure comprising multiple gate electrode regions having different work functions configured to reduce the transistor device's susceptibility to the kink effect, and an associated formation method.

[0112] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Integrated chip comprising the following: an insulation structure (104) set up within a substrate (102) and having internal surfaces defining one or more divots (108) recessed below a top surface of the insulation structure, and side walls defining an opening (106) that exposes the substrate (102); a source area (124) located within the opening (106); a drain area (126) arranged within the opening (106) and separated from the source area (124) by a channel area (125) along a first direction (128); and a gate structure (110) extending over the channel region (125), the gate structure comprising a first gate electrode region (114) having a first composition of one or more materials, and a second gate electrode region (116) arranged over the one or more divots (108) having a second composition of one or more materials that is different from the first composition of one or more materials; wherein the second gate electrode region (116) comprises a first segment, a second segment, a third segment and a fourth segment, wherein the first segment and the third segment of the second gate electrode region (116) are arranged over a first edge of the channel region (125); wherein the second segment and the fourth segment of the second gate electrode region (116) are arranged over a second edge of the channel region (125) opposite the first edge of the channel region; wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) each have a rectangular shape in a top view; wherein the first segment and the second segment of the second gate electrode region (116) are arranged along a first side (110a) of the gate structure (110) near the drain region (126), such that side surfaces of the first segment and the second segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the drain region; wherein the third segment and the fourth segment of the second gate electrode region (116) are arranged along an opposite second side (110b) of the gate structure near the source region (124), such that side surfaces of the third segment and the fourth segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the source region; wherein the first segment is separated from the third segment and the second segment from the fourth segment along the first direction (128) by the first gate electrode region (114); wherein the first segment is separated from the second segment and the third segment from the fourth segment along a second direction (130) perpendicular to the first direction (128) by the first gate electrode region (114); and wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) extend beyond the channel region (125) in the second direction (130). [2] Integrated chip according to claim 1, wherein the first composition of one or more materials includes an n-type gate metal, and wherein the second composition of one or more materials includes a p-type gate metal. [3] Integrated chip according to claim 1 or 2, where the first composition of one or more materials has an initial work function, and where the second composition, consisting of one or more materials, has a second work function that is greater than the first work function. [4] Integrated chip according to one of the preceding claims, wherein the first gate electrode region (114) is laterally adjacent to the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) along the first direction (128) and along the second direction (130). [5] Integrated chip according to any of the preceding claims, wherein the gate structure (110) is configured to cause a lower threshold voltage in magnitude along the first and second edges of the channel region (125) to be matched to a higher threshold voltage in magnitude at the center of the channel region, and wherein the center of the channel area (125) lies between the first edge and the second edge of the channel area along the second direction (130). [6] Integrated chip according to any of the preceding claims, wherein the second composition of one or more materials extends perpendicularly to below a lowest surface of the first composition of one or more materials. [7] Integrated chip according to any of the preceding claims, wherein the second composition of one or more materials directly contacts the inner surfaces defining the one or more divots (108). [8] Integrated chip according to any of the preceding claims, wherein the gate structure (110) further comprises: a gate dielectric (112) that separates the first composition of one or more materials from the substrate (102), wherein the second composition of one or more materials extends from within the one or more divots (108) to over the top surface of the insulating structure (104) and over the gate dielectric (112). [9] Integrated chip comprising the following: an insulation structure (104) comprising one or more dielectric materials within a trench (103) in a substrate (102), wherein internal surfaces of the insulation structure define one or more divots (108) recessed below a top surface of the insulation structure; a source region (124) that is located within the substrate (102); a drain area (126) arranged within the substrate (102) and separated from the source area (124) along a first direction (128) by a channel area (125); and a gate structure (110) arranged above the substrate (102) and between the source region (124) and the drain region (126), wherein the gate structure (110) comprises the following: a first gate electrode region (114) which is separated from the substrate (102) by a gate dielectric (112) and has a first work function; and a second gate electrode region (116) extending from within the one or more divots (108) to beyond the top surface of the insulating structure (104) and beyond the gate dielectric (112), wherein the second gate electrode region (116) has a second work function that is different from the first work function; wherein the second gate electrode region (116) comprises a first segment, a second segment, a third segment and a fourth segment; wherein the first segment and the third segment of the second gate electrode region (116) are arranged over a first edge of the channel region (125); wherein the second segment and the fourth segment of the second gate electrode region (116) are arranged over a second edge of the channel region (125) opposite the first edge of the channel region; wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) each have a rectangular shape in a top view; wherein the first segment and the second segment of the second gate electrode region (116) are arranged along a first side (110a) of the gate structure (110) near the drain region (126), such that side surfaces of the first segment and the second segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the drain region; wherein the third segment and the fourth segment of the second gate electrode region (116) are arranged along an opposite second side (110b) of the gate structure near the source region (124), such that side surfaces of the third segment and the fourth segment of the second gate electrode region form outer surfaces of the gate structure (110) facing the source region; wherein the first segment is separated from the third segment and the second segment from the fourth segment along the first direction (128) by the first gate electrode region (114); wherein the first segment is separated from the second segment and the third segment from the fourth segment along a second direction (130) perpendicular to the first direction (128) by the first gate electrode region (114); and wherein the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) extend beyond the channel region (125) in the second direction (130). [10] Integrated chip according to claim 9, wherein the first gate electrode region (114) comprises an n-type gate metal; and wherein the second gate electrode region (116) comprises a p-type gate metal. [11] Integrated chip according to claim 9 or 10, wherein the first gate electrode region (114) laterally contacts the first segment, the second segment, the third segment and the fourth segment of the second gate electrode region (116) along the first direction (128) and along the second direction (130). [12] Method (1800) for forming an integrated chip comprising the following: Deposition of a gate sacrificial material (802) over isolation structures (104) within a substrate (102), wherein the isolation structures have internal surfaces defining one or more divots (108) recessed below a top surface of the isolation structures; Forming (1806) a source region (124) and a drain region (126) within the substrate (102) on opposite sides of the gate sacrificial material (802), wherein the drain region is separated from the source region along a first direction (128) by a channel region (125); Removing (1810) a first part of the gate sacrificial material (802) directly above the one or more divots (108) to form openings (1302) extending through the gate sacrificial material, wherein the openings comprise a first opening, a second opening, a third opening and a fourth opening; wherein the first opening and the third opening are arranged above a first edge of the channel area (125); wherein the second opening and the fourth opening are arranged above a second edge of the channel area (125) which is opposite the first edge of the channel area; wherein the first opening, the second opening, the third opening and the fourth opening each have a rectangular shape in a top view; wherein the first opening and the second opening are arranged along a first side (110a) of the gate sacrificial material (802) near the drain area (126), such that the first opening and the second opening form lateral recesses of the gate sacrificial material (802); wherein the third opening and the fourth opening are arranged along an opposite second side (110b) of the gate sacrificial material (802) near the source region (124), such that the third opening and the fourth opening form lateral recesses of the gate sacrificial material (802); wherein the first opening is separated from the third opening and the second opening from the fourth opening along the first direction by a second part of the gate sacrificial material (802); wherein the first opening is separated from the second opening and the third opening from the fourth opening along a second direction (130) perpendicular to the first direction (128) by the second part of the gate sacrificial material (802); and wherein the first opening, the second opening, the third opening and the fourth opening extend beyond the channel area (125) in the second direction (130); Separation (1812) of a first composition of one or more materials which has a first exit work, within the openings (1302); Removal (1814) of the second part of the gate sacrificial material (802) between side walls of the first composition of one or more materials; and Separation (1816) of a second composition of one or more materials between the side walls of the first composition of one or more materials, wherein the second composition of one or more materials has a second work function that is different from the first work function. [13] Method (1800) according to claim 12, wherein the first composition consists of one or more materials from a p-type gate metal; and wherein the second composition consists of one or more materials from an n-type gate metal. [14] Method (1800) according to claim 12 or 13, wherein the first composition of one or more materials and the second composition of one or more materials together form a gate structure (110).

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