INTEGRATED CIRCUIT AND METHOD FOR MAKING THE SAME

Abstract

Integrated circuit (400, 900B) comprising: a set of active regions (402) in a substrate, wherein the active regions of the set of active regions (402) extend in a first direction (X), are arranged in a first plane, and are separated from each other in a second direction (Y) that differs from the first direction (X); a first set of conductive structures (420) extending at least in the first direction (X) or the second direction (Y), are arranged in the first plane, and are arranged between the active regions of the set of active regions (402); a trench isolation region (490) extending at least in the first direction (X) or the second direction (Y), is arranged at least in the first plane, and is arranged between one of the active regions (402) and the first set of conductive structures (420);a set of gates (404) extending in the second direction (Y), overlapping at least the first set of conductive structures (420), and arranged in a second plane distinct from the first plane, each gate of the set of gates (404) being separated from an adjacent gate of the set of gates (404) in the first direction (X) by a first distance; and a set of contacts (410) extending in the second direction (Y), overlapping the first set of conductive structures (420), and arranged in the second plane, each contact of the set of contacts (410) being separated from an adjacent contact of the set of contacts (410) in the first direction (X).

Description

PRIOR ARTThe current trend toward integrated circuit (IC) miniaturization results in smaller devices that consume less current and yet provide more functionality at higher speeds. The miniaturization process also resulted in more stringent design and manufacturing constraints, as well as reliability challenges. Various electronic design automation (EDA) tools create, optimize, and review standard cell layout designs for integrated circuits while ensuring that the requirements for standard cell layout design and fabrication are met.DE 10 2016 115 006 A1 describes a semiconductor structure that comprises an active region, a first conductor track, a conductive via, a first conductive metal segment that is connected to the conductor track via the conductive via, a second conductive metal segment that is arranged over the active region, and a local conductive segment that is configured to connect the first conductive metal segment and the second conductive metal segment. Further prior art is known from US 2013 / 0 026 572 A1.The invention is defined in the claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description with reference to the accompanying figures. It should be noted that, in accordance with common practice in the industry, various elements or functions are not shown to scale. Rather, the dimensions of the various elements can be arbitrarily increased or reduced for clarity. FIG. 1 is a circuit diagram of an integrated circuit in accordance with some embodiments. FIG. 2 is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIG. 3 is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 4A, 4B, 4C, 4D, and 4E are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 5A is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 5B, 5C, and 5D are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 6A is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 6B, 6C, 6D, and 6E are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 7A is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 7B, 7C, and 7D are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 8A is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 8B, 8C, 8D, 8E, 8E, 8F, and 8G are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 9A is a diagram of a laauout design of an integrated circuit in accordance with some embodiments. FIGS. 9B, 9C, 9D, and 9E are cross-sectional views of an integrated circuit in accordance with some embodiments. FIG. 10 is a flow diagram of a method of manufacturing an IC, in accordance with some embodiments. FIG. 11 is a flow diagram of a method for creating an integrated circuit laauout design, in accordance with some embodiments. FIG. 12 is a block diagram of a system for designing an IC laauout design, in accordance with some embodiments.DETAILED DESCRIPTIONThe following description provides various embodiments or examples for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are illustrated below to simplify the present disclosure. Other components, materials, values, steps, arrangements, or the like are provided. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or arrangements discussed.Further, terms of spatial relationships, such as "below," "below," "lower / r," "above," "upper / r," and the like, may be used herein to more easily describe the relationship of an element or feature with (another) element(s) or feature(s) depicted in the figures. The terms spatial relationships are intended to encompass different alignments of the used or operated components in addition to the alignment shown in the figures. The device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the terms spatial relationships used herein may also be interpreted accordingly.In accordance with some embodiments, an integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a trench isolation (STI) region, a set of gates, and a first set of vias. In some embodiments, the first set of conductive structures is disposed below the set of gates and the metal o (Mo) layer of the integrated circuit. In some embodiments, the first set of conductive structures is referred to as a buried track ("a hidden path") because the conductive structures of the first set of conductive structures are hidden in the substrate and disposed below at least one of the Mo layer, the MD layer, and the POLY layer. In some embodiments, using the hidden path under the Mo layer, an Mo path is reduced, resulting in a standard cell with a lower height and area compared to other approaches. In some embodiments, the height of a standard cell of the present disclosure is reduced by up to 50% compared to other approaches.In some embodiments, the first set of conductive structures includes a single conductive structure extending in a first direction or a second direction. In some embodiments, the single conductive structure extends in only a single direction (e.g., the first or second direction) and is referred to as a device structure ( 1D). In some embodiments, the first set of conductive structures includes first and second conductive structures. In some embodiments, the first conductive structure extends in the first direction and the second conductive structure extends in the second direction, and the first and second structures are referred to as a bidirectional structure (2D).In some embodiments, the STI region is disposed between the set of active regions and the first set of conductive structures. In some embodiments, a surface of the set of conductive structures is disposed below a surface of the active region of the integrated circuit or a surface of a fin of the integrated circuit. In some embodiments, the integrated circuit includes a transfer gate.In some embodiments, by using the first set of conductive structures of the integrated circuit of the present disclosure, the gate density of a standard cell is increased by up to 30%, by offering more routing flexibility than other approaches. In some embodiments, the first set of conductive structures increases the routing resources for standard cells compared to other approaches. In some embodiments, current resistance (IR) and electromigration (EM) of the present disclosure are improved compared to other approaches.FIG. 1 is a circuit diagram of an integrated circuit 100, in accordance with some embodiments. In some embodiments, integrated circuit 100 corresponds to a transfer gate.The integrated circuit 100 includes two P-type metal oxide semiconductor (PMOS) transistors P 1 and P 2 and two N-type metal oxide semiconductor (NMOS) transistors N 1 and N 2.PMOS transistor P 1 includes a gate terminal A 1, a terminal T 1, and a terminal T 3.NMOS transistor N1 includes a gate terminal B2, a terminal T2 and a terminal T4.Terminal T1 of the PMOS transistor P1 is electrically connected to terminal T2 of the NMOS transistor N1. Terminal T 3 of the PMOS transistor P 1 is electrically connected to terminal T 4 of the NMOS transistor N 1. NMOS transistor N1 and PMOS transistor P1 are interconnected to form a first transistor pair.PMOS transistor P 2 includes a gate terminal B 1, a terminal T 5, and a terminal T 7.NMOS transistor N2 includes a gate terminal A2, a terminal T6 and a terminal T8. Terminal T7 of the PMOS transistor P2 is electrically connected to terminal T8 of the NMOS transistor N2. Terminal T5 of the PMOS transistor P2 is electrically connected to terminal T6 of the NMOS transistor N2. NMOS transistor N2 and PMOS transistor P2 are interconnected to form a second transistor pair.The gate terminal A1 of the PMOS transistor P1 is electrically connected to the gate terminal A2 of the NMOS transistor N2. The gate terminal B1 of the PMOS transistor P2 is electrically connected to the gate terminal B2 of the NMOS transistor N1. Terminal T 3 of the PMOS transistor P 1 and terminal T 4 of the NMOS transistor N 1 are electrically connected to the terminal T 5 of the NMOS transistor N 2 and the terminal T 6 of the PMOS transistor P 2.In some embodiments, at least one terminal of terminals T 1, T 2, T 3, T 4, T 5, T 6, T 7, or T 8 corresponds to a source terminal. In some embodiments, at least one terminal of terminals T 1, T 2, T 3, T 4, T 5, T 6, T 7, or T 8 corresponds to a drain terminal. Other arrangements of the terminals in the integrated circuit 100 are possible.In some embodiments, at least one of integrated circuit 100, integrated circuit 400 (FIGS. 4A-4E ), layout design 200, layout design 300 (FIG. 3 ), layout design 500A (FIG. 5 ), layout design 600A (FIG. 6 ), layout design 700A (FIG. 7 ), layout design (FIG. 8 ), or layout design 800A (FIG. 9 ) corresponds to one or more standard cells. In some embodiments, the standard cell is a transfer gate. In some embodiments, a standard cell is a logic gate cell. In some embodiments, a logic gate cell includes AND, OR, NAND, NOR, XOR, INV, AND-OR invert (AOI), OR-AND invert (OAI), MUX, flip-flop, BUFF, latch, delay, clock cells, or the like. In some embodiments, a standard cell is a memory cell. In some embodiments, a memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magneto-resistive RAM (MRAM), a read only memory (ROM), or the like. In some embodiments, a standard cell includes one or more active or passive elements. Examples of active elements include, but are not limited to, transistors, diodes, or the like. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), FinFETs, planar raised / m source / drain MOS transistors, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or the like. In some embodiments, IC 100 includes other features / elements that are not shown for ease of illustration.FIG. 2 is a diagram of a laauout design 200 of an integrated circuit in accordance with some embodiments.Layout design 200 is usable for manufacturing integrated circuit 100 of FIG. 1, integrated circuit 400 of FIGS. 4A-4E, integrated circuit 500B of FIGS. 5B-5D, integrated circuit 600B of FIGS. 6B-6E, integrated circuit 700B of FIGS. 7B-7D, integrated circuit 800B of FIGS. 8B-8G, or integrated circuit 900B of FIGS. 9B-9E. Components that are the same as or similar to those in each of FIGS. 2-3 or 5A-9E are denoted by the same reference numerals, and a detailed description thereof is thus omitted.Layout design 200 includes active area layout patterns 202 a, 202 b(collectively referred to as a "set of active area layout patterns 202") extending in a first direction X. The active area layout patterns 202 a, 202 bof the set of active area layout patterns 202 are separated from each other in a second direction Y different from the first direction X. The set of active region layout patterns 202 is usable to fabricate a corresponding set of active regions 402 (FIGS. 4A-4E ) of the integrated circuit 400. In some embodiments, the set of active area layout patterns 202 are arranged in a first layout level.Layout design 200 further includes gate layout patterns 205 a, 205 b, 205 c, 205 d(collectively referred to as a "set of gate layout patterns 205") and gate layout patterns 206 a, 206 b, 206 c, 206 d(collectively referred to as a "set of gate layout patterns 206") each extending in the second direction Y. Each of the layout patterns of the set of gate layout patterns 205 is separated from an adjacent layout pattern of the set of gate layout patterns 205 in the first direction X by a first pitch (pitch). Each of the layout patterns of the set of gate layout patterns 206 is separated from an adjacent layout pattern of the set of gate layout patterns 206 in the first direction X by a first pitch (pitch). The sets of gate layout patterns 205 and 206 are separated from each other in the second direction Y. In some embodiments, the sets of gate layout patterns 205 and 206 are not separated from each other in the second direction Y and form a single set of gate layout patterns 204 (as shown in FIGS. 3 and 5A-9E ). The set of gate layout patterns 204, 205, or 206 is usable to fabricate a corresponding set of gates 404 (FIGS. 4A-4E) of integrated circuit 400. The set of gate layout patterns 204, 205, and 206 are arranged in a second layout level (POLY) different from the first layout level. The set of active area layout patterns 202 is arranged below the set of gate layout patterns 204, 205 or 206.The gate layout pattern 206 bis usable for manufacturing the gate terminal A 1 of the PMOS transistor P 1 of FIG. 1 ; the gate layout pattern 206 cis usable for manufacturing the gate terminal B 1 of the PMOS transistor P 2 of FIG. 1 ; the gate layout pattern 205 bis usable for manufacturing the gate terminal B 2 of the NMOS transistor N 1 of FIG. 1 ; the gate layout pattern 205 cis usable for manufacturing the gate terminal A 2 of the NMOS transistor N 2 of FIG. 1.Layout design 200 further includes metal-over-diffusion layout patterns 210 a, 210 b, 210 c(collectively referred to as a "set of metal-over-diffusion layout patterns 210") extending in second direction Y. Each of the layout patterns of the set of metal-over-diffusion layout patterns 210 is separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns 210 in the first direction X. The set of metal over diffusion layout patterns is arranged in the second layout level. The set of metal over diffusion layout patterns 210 is usable to make a corresponding set of contacts 410 (FIGS. 4A-4E ) of the integrated circuit 400.In some embodiments, the metal over diffusion layout pattern 210 ais usable for forming the terminal T 1 of the PMOS transistor P 1 of FIG. 1 and the terminal T 2 of the NMOS transistor N 1 of FIG. 1. In some embodiments, the metal over diffusion layout pattern 210 ais usable for forming the terminal T 7 of the PMOS transistor P 2 of FIG. 1 and the terminal T 8 of the NMOS transistor N 2 of FIG. 1. In some embodiments, the metal over diffusion layout pattern 210 bis usable for forming the terminal T 3 of the PMOS transistor P 1 of FIG. 1, the terminal T4 of the NMOS transistor N1 of FIG. 1, In some embodiments, the metal over diffusion layout pattern 210 cis usable for forming the terminal T 7 of the PMOS transistor P 2 of FIG. 1 and the terminal T 8 of the NMOS transistor N 2 of FIG. 1. In some embodiments, the metal over diffusion layout pattern 210 cis usable for forming the terminal T 7 of the PMOS transistor P 2 of FIG. 1 and the terminal T 8 of the NMOS transistor N 2 of FIG. 1.Layout design 200 further includes conductive element layout patterns 212 a, 212 b(collectively referred to as a "set of conductive element layout patterns 212") extending in at least one of first direction X and second direction Y. In some embodiments, the set of conductive element layout patterns 212 is arranged at least in the first layout level, the second layout level, or a third layout level. In some embodiments, the third layout level is different from the first layout level and the second layout level. The set of conductive element layout patterns 212 is usable to fabricate corresponding conductive structures (e.g., set of conductive structures 420 or set of conductive structures 430 (FIGS. 4A-4E )) of the integrated circuit 400. In some embodiments, the set of conductive element layout patterns 212 is usable to fabricate a corresponding set of conductive structures 420' of the integrated circuit 500B, a corresponding set of conductive structures 620' of the integrated circuit 600B, a corresponding set of conductive structures 720' of the integrated circuit 700B, a corresponding set of conductive structures 820' of the integrated circuit 800B, or a corresponding set of conductive structures 920' of the integrated circuit 900B. The conductive element layout pattern 212 acorresponds to fabricating a conductive pattern (e.g., the conductive pattern 420 or the conductive patterns 430 a, 430 b, 430 c) used to electrically connect the gate terminal A 1 of the PMOS transistor P 1 to the gate terminal A 2 of the NMOS transistor N 1 of FIG. 1. The conductive element layout pattern 212 bcorresponds to fabricating a conductive pattern (e.g., the conductive pattern 420 or the conductive patterns 430 a, 430 b, 430 c) used to electrically connect the gate terminal B 1 of the PMOS transistor P 2 to the gate terminal B 2 of the NMOS transistor N 2 of FIG. 1. In some embodiments, the set of conductive element layout patterns 212 is not included in layout design 200.FIG. 3 is a diagram of a laauout design 300 of an integrated circuit in accordance with some embodiments. Layout design 300 is usable for manufacturing integrated circuit 100 (FIG. 1 ) or integrated circuit 400 (FIGS. 4A-4E ).Layout design 300 is a variation of layout design 200 (FIG. 2 ). Layout design 300 is usable for manufacturing an integrated circuit similar to integrated circuit 100 (FIG. 1 ) or integrated circuit 400 (FIGS. 4A-4E ).In comparison to layout design 200 of FIG. 2, layout design 300 further includes one or more cut element layout patterns 304 aand 304 b, fin layout patterns 316 aand 316 b, conductive element layout patterns 320, 330 a, 330 b, 330 c, and 340, and via layout patterns 322 a, 322 b, 332 a, 332 b, 342 a, and 342 b.In comparison to layout design 200 of FIG. 2, set of gate layout patterns 204 of layout design 300 replaces set of gate layout patterns 205 and 206. The set of gate layout patterns 204 corresponds to the set of gate layout patterns 205 and 206 that are not separated from each other in the second direction Y, thereby forming a single set of gate layout patterns (e.g., the set of gate layout patterns 204). The set of gate layout patterns 204 is similar to the set of gate layout patterns 205 and 206, and therefore a similar detailed description is omitted.Cut element layout patterns 304 a, 304 b(collectively referred to as a "set of cut element layout patterns 304") extend in the first direction X. The set of cut element layout patterns 304 overlaps at least a first gate layout pattern of the set of gate layout patterns 204. The cut element layout patterns 304 a, 304 bapply the corresponding gate layout patterns 204 b, 204 cof the set of gate layout patterns 204. Each of the layout patterns of the set of cut element layout patterns 304 has a pattern width in the second direction Y and a pattern length in the first direction X.In some embodiments, the cut element layout pattern 304 ais usable to determine a position of the gates 404 b 1 and 404 b 2 (FIGS. 4A-4E ) of the integrated circuit 400 removed during operation 1006 of the method 1000 (FIG. 10 ). In some embodiments, the cut element layout pattern 304 bis usable to determine a position of the gates 404 c 1 and 404 c 2 (FIGS. 4A-4E ) of the integrated circuit 400 removed during operation 1006 of the method 1000 (FIG. 10 ). The removed gate portion of the gates 404 b 1 and 404 b 2 and the gates 404 c 1 and 404 c 2 is also referred to as a cut portion. In some embodiments, the set of gate layout patterns 204 and the cut element layout pattern 304 are arranged in the second layout level. In some embodiments, the second layout level corresponds to a poly layout level (POLY). Other arrangements or sets of structures in the set of slice layout structures 304 are possible.The fin layout patterns 316 a, 316 b(collectively referred to as "set of fin layout patterns 316") each extend in the first direction X. The fin layout patterns 316 a, 316 bare disposed over the corresponding active region layout pattern 202 a, 202 b. The set of fin layout patterns 316 is disposed below the set of gate layout patterns 204. Each of the layout patterns of the set of fin layout patterns 316 is separated from an adjacent layout pattern of the set of fin layout patterns 316 in the second direction Y by a fin pitch (fin pitch). The set of fin layout patterns 316 is usable to fabricate a corresponding set of fins of the integrated circuit 400. Other arrangements or sets of fins in the set of fin layout patterns 316 are possible.The conductive element layout design 320 a(hereinafter referred to as a "set of conductive element layout patterns 320) extends in at least one of the first direction X and the second direction Y. In some embodiments, the set of conductive element layout patterns 320 extends in a single direction (e.g., the first direction X or the second direction Y). In some embodiments, the set of conductive element layout patterns 320 extend in two directions (e.g., the first direction X and the second direction Y (FIG. 5 )). The set of conductive element layout patterns 320 includes one or more conductive element layout patterns. The set of conductive element layout patterns 320 is arranged in the first layout level. In some embodiments, the first layout level of layout design 300 is the active region. In some embodiments, the first layout level of layout design 300 is divided into a metal sub-portion (MU) and a via sub-portion (VU). In some embodiments, the MU portion is disposed below the VU portion. In some embodiments, the set of conductive element layout patterns 320 are disposed on the MU portion of the first layout level. In some embodiments, the MU portion is disposed below at least one of the Mo level, the POLY level, and the MD level of layout design 300.The set of conductive element layout patterns 320 is arranged between the set of active area layout patterns 202. The conductive element layout pattern 320 ais disposed between the active area layout pattern 202 aand the active area layout pattern 202 b. The set of conductive element layout patterns 320 is usable to fabricate a corresponding set of conductive structures 420 (FIGS. 4A-4E ) of the integrated circuit 400. The set of conductive element layout patterns 320 is disposed below the set of gate layout patterns 204 and the set of metal over diffusion layout patterns 210. In some embodiments, the set of metal over diffusion layout patterns 210 overlaps the set of conductive element layout patterns 320. The set of gate layout patterns 204 at least overlaps the set of conductive element layout patterns 320. Other arrangements or sets of structures in the set of conductive element layout structures 320 are possible.Via layout patterns 322 a, 322 b(collectively referred to as a "set of via layout patterns 322") are disposed between the set of conductive element layout patterns 320 and the set of gate layout patterns 204. The via layout patterns 322 a, 322 bof the set of via layout patterns 322 are arranged between the corresponding gate layout pattern 204 c, 204 bof the set of gate layout patterns 204 and the set of conductive element layout patterns 320. Via layout patterns 322 a, 322 bare disposed at the VU portion of the first layout level of layout design 300. In some embodiments, the VU portion is disposed over the MU portion. In some embodiments, the VU portion is located below at least one of the Vo level, the VG level, and the VD level of layout design 300.The set of via layout patterns 322 is usable to make a corresponding set of vias 422 (FIGS. 4A-4E). The set of vias 422 connect the set of conductive structures 420 to the set of gates 404.In some embodiments, a via layout pattern 322 a, 322 bof the set of via layout patterns 322 is disposed where a corresponding gate layout pattern 204 c, 204 bof the set of gate layout patterns 204 overlaps a corresponding layout pattern of the set of conductive element layout patterns 320. In some embodiments, a center of the via layout pattern 322 a, 322 bof the set of via layout patterns 322 is located below a center of a corresponding gate layout pattern 204 c, 204 bof the set of gate layout patterns 204. In some embodiments, a center of the via layout pattern 322 a, 322 bof the set of via layout patterns 322 ais aligned with a center of a corresponding gate layout pattern 204 c, 204 bof the set of gate layout patterns 204 at least in the first direction X or the second direction X. Other arrangements of via layout patterns 322 a, 322 bof the set of via layout patterns 322 are possible.The conductive element layout patterns 330 a, 330 b, 330 c(collectively referred to as a "set of conductive element layout patterns 330") extend in the first direction X. The set of conductive element layout patterns 330 is disposed between the set of active area layout patterns 202. Each of the conductive element layout patterns 330 a, 330 b, 330 cis arranged between the active area layout pattern 202 aand the active area layout pattern 202 b. In some embodiments, each of the layout patterns 330 a, 330 b, 330 cof the set of conductive layout patterns 330 is separated from an adjacent layout pattern of the set of conductive layout patterns 330 in the second direction Y. The set of conductive element layout patterns 320 is usable to fabricate a corresponding set of conductive structures 430 (FIGS. 4A-4E ) of the integrated circuit 400.The set of conductive element layout patterns 330 is disposed at a third layout level different from the first layout level and the second layout level. In some embodiments, the third layout level corresponds to the metal zero (Mo) layout level. In some embodiments, the third layout level corresponds to a top metal level that includes the metal one (M1) layout level, the metal two (M2) layout level, the metal three (M3) layout level, or the like. The set of conductive element layout patterns 330 overlaps at least one of the set of gate layout patterns 204 and the set of metal over diffusion layout patterns 210. The set of conductive element layout patterns 330 is disposed over the set of conductive element layout patterns 320 and the set of active area layout patterns 202.Via layout patterns 332 a, 332 b(collectively referred to as a "set of via layout patterns 332") are disposed between set of conductive element layout patterns 330 and set of gate layout patterns 204. Via layout patterns 332 a, 332 bare disposed in the via-over-gate (VG) level of layout design 300. The via layout patterns 332 a, 332 bof the set of via layout patterns 332 are arranged between a corresponding conductive element layout pattern 330 c, 330 aof the set of conductive element layout patterns 330 and a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204. The set of via layout patterns 332 is usable to form a corresponding set of vias 432 (FIGS. 4A-4E ). The set of vias 432 connect the set of conductive structures 430 to the set of gates 404.In some embodiments, a via layout pattern 332 a, 332 bof the set of via layout patterns 332 is disposed where a corresponding layout pattern 330 c, 330 aof the set of conductive element layout patterns 330 overlaps a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204. In some embodiments, a center of the via layout pattern 332 a, 332 bof the set of via layout patterns 332 is disposed over a center of a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204. In some embodiments, a center of the via layout pattern 332 a, 332 bof the set of via layout patterns 332 is located below a center of a corresponding conductive element layout pattern 330 c, 330 aof the set of conductive element layout patterns 330. In some embodiments, a center of the via layout pattern 332 a, 332 bof the set of via layout patterns 332 is aligned with a center of a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204 at least in the first direction X or the second direction Y. In some embodiments, a center of the via layout pattern 332 a, 332 bof the set of via layout patterns 332 is aligned with a center of a corresponding conductive element layout pattern 330 c, 330 aof the set of conductive element layout patterns 330 at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 332 a, 332 bof the set of via layout patterns 332 are possible.The conductive element layout design 340 a(hereinafter referred to as a "set of conductive element layout patterns 340) extends in the second direction Y. The set of conductive element layout patterns 340 includes one or more conductive element layout patterns. The set of conductive element layout patterns 340 is disposed between the set of gate layout patterns 204. In some embodiments, conductive element layout pattern 340 ais disposed between gate layout pattern 204C and gate layout pattern 204D. In some embodiments, each of the layout patterns of the set of conductive layout patterns 340 is separated from an adjacent layout pattern of the set of conductive layout patterns 340 in the first direction X. The set of conductive element layout patterns 340 is usable to fabricate a corresponding set of conductive patterns 440 (FIGS. 4A-4E ) of the integrated circuit 400.The set of conductive element layout patterns 340 overlaps at least one of the set of conductive element layout patterns 320, the set of conductive element layout patterns 330, the set of metal over diffusion layout patterns 210, or the set of active area layout patterns 202. The set of conductive element layout patterns 340 is disposed at a fourth layout level different from the first layout level, the second layout level, and the third layout level. In some embodiments, the fourth layout level corresponds to a metal one (M1) layout level 300. Other arrangements or sets of structures in the set of conductive element layout structures 340 are possible.Via layout patterns 342 a, 342 b(collectively referred to as a "set of via layout patterns 342") are disposed between set of conductive element layout patterns 330 and set of conductive element layout patterns 340. The via layout patterns 342 a, 342 bof the set of via layout patterns 342 are arranged between the corresponding conductive element layout pattern 330 a, 330 cof the set of conductive element layout patterns 330 and the set of conductive element layout patterns 340. Via layout patterns 342 a, 342 bare located in a via zero (Vo) level of layout design 300. The set of via layout patterns 342 is usable to form a corresponding set of vias 442 (FIGS. 4A-4E ). The set of vias 442 connect the set of conductive structures 430 to the set of conductive structures 440.In some embodiments, a via layout pattern 342 a, 342 bof the set of via layout patterns 342 is disposed where a corresponding conductive element layout pattern 330 a, 330 cof the set of conductive element layout patterns 330 overlaps a corresponding layout pattern of the set of conductive element layout patterns 340. In some embodiments, a center of the via layout pattern 342 a, 342 bof the set of via layout patterns 342 is disposed over a center of a corresponding conductive element layout pattern 330 a, 330 cof the set of conductive element layout patterns 330. In some embodiments, a center of the via layout pattern 342 a, 342 bof the set of via layout patterns 342 is aligned with a center of a corresponding conductive element layout pattern 330 a, 330 cof the set of conductive element layout patterns 330 at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 342 a, 342 bof the set of via layout patterns 342 are possible.In some embodiments, gate terminal A 1, 404 b 1 (FIG. 4C ) (fabricated by gate layout pattern 204 b) of layout design 300 is electrically connected to gate terminal A 2, 404 c 2 (FIG. 4B ) (fabricated by gate layout pattern 204 c). For example, in some embodiments, gate terminal A 1, 404 b 1 (fabricated by gate layout pattern 204 b) is electrically connected via 422 b(FIG. 4C ) (fabricated by via layout pattern 322 b) to conductive pattern 420 a(fabricated by conductive element layout pattern 320 a), and conductive pattern 420 ais electrically connected via 422 a(FIG. 4B ) (fabricated by via layout pattern 322 a) to gate terminal A 2, 404 c 2 (fabricated by gate layout pattern 204 c).In some embodiments, gate terminal B 1, 404 c 1 (formed by gate layout pattern 204 c) of layout design 300 is electrically connected to gate terminal B 2, 404 b 2 (formed by gate layout pattern 204 b). For example, in some embodiments, gate terminal B 1, 404 c 1 (FIG. 4B ) (fabricated by gate layout pattern 204 c) is electrically connected to conductive pattern 430 a(fabricated by conductive element layout pattern 330 a) via via 432 b(fabricated by via layout pattern 332 b). In some embodiments, conductive pattern 430a is electrically connected to conductive pattern 440a, M1 (formed by conductive element layout pattern 340a) via via 442a, V0 (formed by via layout pattern 342a). In some embodiments, conductive structure 440a is electrically connected to conductive structure 430c (formed by conductive element layout structure 330c) via via 442b, V0 (formed by via layout structure 342b). In some embodiments, conductive pattern 430 cis electrically connected to gate terminal B 2, 404 b 2 (formed by gate layout pattern 204 b) via via 432 a(formed by via layout pattern 332 a).In some embodiments, the set of conductive element layout patterns 320 is disposed below at least one of the set of gate layout patterns 304, the metal o (Mo) level, or the MD level of layout design 300. In some embodiments, as compared to other approaches, by using the set of conductive element layout patterns 320, at least an upper metal layer path in the set of conductive element layout patterns 330 is reduced. In some embodiments, an upper metal layer path comprises either Mo, and / or M1and / or M2and / or the like. In some embodiments, the set of conductive element layout patterns 330 includes an upper metal layer path pattern disposed in the M1 level, the M2 level, or the like. In some embodiments, by using an upper metal layer path, less in the set of conductive element layout patterns 330, a standard cell having a lower height and area results compared to other approaches. In some embodiments, the width of one or more layout patterns in the set of conductive element layout patterns 330 is increased because an upper metal layer path in the set of conductive layout patterns 330 is reduced, resulting in a standard cell with better current resistance (IR) and better electromigration (EM) compared to other approaches. In some embodiments, compared to other approaches, by using the set of conductive element layout patterns 320 of the present disclosure, the gate density of the set of gate layout patterns of a standard cell is increased by up to 30%. In some embodiments, layout design 200 provides more routing flexibility and increases routing resources compared to other approaches by using the set of conductive element layout structures 320 of the present disclosure.FIGS. 4A, 4B, 4C, 4D, and 4E are cross-sectional views of an integrated circuit 400, in accordance with some embodiments. FIG. 4A is a cross-sectional view of an integrated circuit 400 corresponding to layout design 300 cut by plane A-A', FIG. 4B is a cross-sectional view of an integrated circuit 400 corresponding to layout design 300 cut by plane B-B', FIG. 4C is a cross-sectional view of an integrated circuit 400 corresponding to layout design 300 cut by plane C-C', FIG. 4D is a cross-sectional view of an integrated circuit 400 corresponding to layout design 300 cut by plane D-D', and FIG. 4E is a cross-sectional view of an integrated circuit 400 corresponding to layout design 300 cut by plane E-E' in accordance with some of integrated circuits 400 are manufactured by layout design 300.Integrated circuit 400 is fabricated by layout design 300. Structural relationships including alignment, lengths, and widths, as well as arrangements of the integrated circuit 400 are similar to the structural relationships and arrangements of the layout design 200 of FIG. 2 and the layout design 300 of FIG. 3, and are not described in FIGS. 4A-4E for brevity.Integrated circuit 400 includes active regions 402 a, 402 b(collectively referred to as a "set of active regions 402") in a substrate 480. The set of active regions 402 extends in the first direction X and is disposed in a first plane of the integrated circuit 400. Each of the active regions of the set of active regions 402 is separated from each other in the second direction Y. In some embodiments, the set of active regions 402 of the integrated circuit 400 is referred to as an oxide definition (OD) region that defines the source or drain diffusion regions of the integrated circuit 400. In some embodiments, the first level of integrated circuit 400 is referred to as the active / fin level. In some embodiments, the active region 402 a, 402 bincludes a set of fins (not shown) extending in the first direction and disposed below the set of gates 404. In some embodiments, each of the fins (not shown) is separated from an adjacent fin of the set of fins (not shown) in the second direction Y by a fin pitch (not shown). Other sets or arrangements of the set of active regions 402 are possible.The integrated circuit 400 further includes a conductive structure 420 a(collectively referred to as a "set of conductive structures 420) extending at least in the first direction X or the second direction Y. The set of conductive structures 420 is disposed in the first level of the integrated circuit 400. The set of conductive structures 420 is disposed between the set of active regions 402. In some embodiments, the conductive structure 420 ais disposed between the active regions 402 a, 402 b. In some embodiments, a surface of conductive structure 420 aof set of conductive structures 420 is disposed below a surface of active region 402 a, 402 bof set of active regions 402 or a surface of a fin (not shown) of set of fins (not shown).In some embodiments, the first level of integrated circuit 400 is the active region of integrated circuit 400. In some embodiments, the first level of integrated circuit 400 is divided into a metal under (MU) region and a via under (VU) region. In some embodiments, the MU region is disposed below the VU region. In some embodiments, the set of conductive structures 420 is disposed in the first level MU region of the integrated circuit 400. In some embodiments, the conductive structure of the set of conductive structures 420 is hidden within the substrate 480 and disposed below at least the Mo layer, the POLY layer, the MD layer of the integrated circuit 400. In some embodiments, each conductive structure 420 ain the set of conductive structures 420 has a width (not shown) in the second direction Y of about 1-50 nm. In some embodiments, the conductive structure 420 ain the set of conductive structures 420 has a length (not shown) in the first direction X of about 1-10 μm. Other sets or arrangements of the set of conductive structures 404 are possible.The integrated circuit 400 further includes a trench isolation (STI) region 490 extending in at least one of the first direction X and the second direction Y. The STI region 490 is disposed at least in the first level of the integrated circuit 400. In some embodiments, STI region 490 is disposed between active region set 402 and conductive structure set 420. In some embodiments, the conductive structure 420 ais separated from each of the active regions 402 a, 402 bby the STI region 490. Other sets or arrangements of the STI region 490 are possible.The integrated circuit 400 further includes gates 404 b 1, 404 b 2, 404 c 1, 404 c 2 (collectively referred to as "set of gates 404") extending in the second direction Y, overlapping at least the set of conductive structures 420, and disposed in a second plane of the integrated circuit 400. In some embodiments, the second level of integrated circuit 400 is different than the first level. Each of the gates of the set of gates 404 is separated from an adjacent gate of the set of gates 404 by a first pitch in the first direction X. In some embodiments, the second level of integrated circuit 400 is referred to as the poly level. Other sets or arrangements of the set of gates 404 are possible.The integrated circuit 400 further includes contacts 410 a, 410 b, 410 c(collectively referred to as a "set of contacts 410") extending in the second direction Y, overlapping the set of conductive structures 420, and disposed in the second plane of the integrated circuit 400. Each of the contacts 410, 410 b, 410 cof the set of contacts 410 is separated from an adjacent contact of the set of contacts 410 in the first direction X. In some embodiments, the set of contacts 410 are disposed in the MD plane of the integrated circuit 400. In some embodiments, at least one contact of the set of contacts 410 is electrically connected to at least one of a source and a drain of the active regions 402 a, 402 b. Other sets or arrangements of the set of contacts 410 are possible.Integrated circuit 400 further includes vias 422 a, 422 b(collectively referred to as a "set of vias 422") that connect set of conductive structures 420 to set of gates 404. The set of vias 422 is disposed between the set of conductive structures 420 and the set of gates 404. Via 422a is located where gates 422c1, 404c2 overlap conductive pattern 420a. Via 422a is located where gates 422c1, 404c2 overlap conductive pattern 420a. In some embodiments, the set of vias 422 are disposed in the VU plane of integrated circuit 400. The VU plane of integrated circuit 400 is disposed between the first and second planes. Other sets or arrangements of the set of vias 422 are possible.The integrated circuit 400 further includes conductive structures 430 a, 430 b, 430 c(collectively referred to as a "set of conductive structures 430") extending in the first direction X between the set of active regions 402, overlapping at least the set of gates 404, and disposed in a third plane of the integrated circuit 400. In some embodiments, the third level of integrated circuit 400 is different from the first and second levels. In some embodiments, the third level of integrated circuit 400 is referred to as the Mo level. Each of the conductive structures 430 a, 430 b, 430 cof the set of conductive structures 430 is separated from an adjacent conductive structure of the set of conductive structures 430 in the second direction Y. Other sets or arrangements of the set of conductive structures 430 are possible.Integrated circuit 400 further includes vias 432 a, 432 b(collectively referred to as a "set of vias 432") that connect set of conductive structures 430 to set of gates 404. The set of vias 432 connect the set of conductive structures 430 and the set of gates 404. Via 432a is located where conductive pattern 430c overlaps gates 422c1, 404c2. Via 432 bis located where conductive pattern 430 a overlaps gates 422 c 1, 404 c 2. In some embodiments, the set of vias 432 are disposed in the VG plane of the integrated circuit 400. The VG plane of integrated circuit 400 is disposed between the second and third planes. Other sets or arrangements of the set of vias 432 are possible.The integrated circuit 400 further includes the conductive structure 440 a(collectively referred to as a "set of conductive structures 440") extending in the second direction Y, disposed between the set of gates 404, at least overlapping the set of conductive structures 420, and disposed in a fourth level of integrated circuit 400. In some embodiments, the fourth level of integrated circuit 400 is different from the first, second, and third levels. In some embodiments, the fourth level of integrated circuit 400 is referred to as the M1 level. In some embodiments, each of the structures of the set of conductive structures 440 is separated from an adjacent structure of the set of conductive structures 440 in the first direction X. Other sets or arrangements of the set of conductive structures 440 are possible.Integrated circuit 400 further includes vias 442 a, 442 b(collectively referred to as a "set of vias 442") that connect set of conductive structures 440 to set of conductive structures 430. The set of vias 442 are disposed between the set of conductive structures 440 and the set of conductive structures 430. Via 442a is located where conductive structure 440a overlaps conductive structure 430a. Via 442 bis located where conductive structure 440 aapped onto conductive structure 430 c. In some embodiments, the set of vias 442 are disposed in the VG plane of the integrated circuit 400. The Vo plane of the integrated circuit 400 is located between the third and fourth planes. Other sets or arrangements of the set of vias 442 are possible.In some embodiments, one or more conductive structures of the set of conductive structures 420, 430, or 440 comprises / comprise a metal, metal compound, or doped semiconductor. In some embodiments, one or more vias of the set of vias 422, 432, 442 comprise / comprise a metal, metal compound, or doped semiconductor. In some embodiments, a metal includes at least Cu (copper), Co, W, Ru, Al, or the like. In some embodiments, a metal compound includes at least AlCu, W-TiN, TiSi, NiSi, TiN, TaN, or the like. In some embodiments, a doped semiconductor includes at least doped silicon or the like.In some embodiments, the gate terminal A 1, 404 b 1 is electrically connected to the gate terminal A 2, 404 c 2. For example, gate terminal A 1, 404 b 1 is electrically connected to conductive pattern 420 avia via 422 b, and conductive pattern 420 ais electrically connected to gate terminal A 2, 404 c 2 via via 422 a.In some embodiments, the gate terminal B 1, 404 c 1 is electrically connected to the gate terminal B 2, 404 b 2. For example, in some embodiments, gate terminal B 1, 404 c 1 is electrically connected to conductive pattern 430 avia via 432 b. In some embodiments, conductive structure 430a is electrically connected to conductive structure 440a, M1 via via 442a, Vo. In some embodiments, conductive structure 440a is electrically connected to conductive structure 430c via via 442b, V0. In some embodiments, the conductive pattern 430 cis electrically connected to the gate terminal B 2, 404 b 2 via the via 432 a.In some embodiments, the set of conductive structures 420 is disposed below at least one of the set of gates 404, the metal o (Mo) layer, or the MD layer of the integrated circuit 400. In some embodiments, the set of conductive structures 420 is referred to as a hidden metal path (BMT) because the conductive structures of the set of conductive structures 420 are hidden within the substrate 480 and are disposed below at least the Mo layer, the POLY layer, the MD layer of the integrated circuit 400.In some embodiments, by using the set of conductive structures 420, an upper metal layer path (e.g., MD path, Mo path, M1 path, or the like) in the set of conductive structures 430 is reduced, and results in a standard cell having a lower height and area compared to other approaches. In some embodiments, an upper metal layer path (e.g., MD path, Mo path, M1 path, or the like) is reduced by using the set of conductive structures 420 in the set of conductive structures 430, and the space occupied by the removed upper metal path may be used by increasing a width of at least one conductive structure in the set of conductive structures 430, resulting in a standard cell with better current resistance (IR) and EM compared to other approaches.In some embodiments, the cell height may be reduced by reducing an upper metal layer path of the present disclosure, resulting in an increase in the gate density of a standard cell by up to 30% compared to other approaches. In some embodiments, by reducing an upper metal layer path of the present disclosure, integrated circuit 400 provides more routing flexibility and increases routing resources compared to other approaches.FIG. 5A is a diagram of a laauout design 500A of an integrated circuit in accordance with some embodiments.FIGS. 5B, 5C, and 5D are cross-sectional views of an integrated circuit 500B, in accordance with some embodiments.Layout design 500A is a variation of layout design 300 (FIG. 3 ). For example, layout design 500A illustrates an example in which the MU layer (e.g., set of conductive element layout patterns 520) extends in two directions.Layout design 500A is usable for manufacturing an integrated circuit similar to integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E), or 500B.500ACompared to layout design 300 of FIG. 3, conductive element layout patterns 520 a, 520 b, and 520 cof layout design 500A replace conductive element layout pattern 320 a.The conductive element layout patterns 520 a, 520 b, 520 c(collectively referred to as a "set of conductive element layout patterns 520") are arranged in the first layout level. The set of conductive element layout patterns 520 is usable to fabricate a corresponding set of two-dimensional (2D) conductive structures 420' of the integrated circuit 100, 400, or 500B.In some embodiments, the set of conductive element layout patterns 520 is disposed on the MU portion of the first layout level. The set of conductive element layout patterns 520 extend in two directions (e.g., the first direction X and the second direction Y). The conductive element layout patterns 520 aand 520 cextend in the first direction X, respectively. the conductive element layout pattern 520 bextends in the second direction Y.The set of conductive element layout patterns 520 is arranged between the set of active area layout patterns 202. The conductive element layout pattern 520 ais disposed between the conductive element layout pattern 330 aand the conductive element layout patterns 330 b. The conductive element layout pattern 520 cis disposed between the conductive element layout pattern 330 band the conductive element layout pattern 330 c.The conductive element layout pattern 520 bis disposed between the gate layout patterns 204 band 204 c. In some embodiments, conductive element layout pattern 520 bis disposed between conductive element layout pattern 330 aand conductive element layout pattern 330 c. In some embodiments, the metal over diffusion layout pattern 210 a, 210 b, 210 c overlaps a corresponding conductive element layout pattern 520 a, 520 b, 520 c.The set of gate layout patterns 204 overlaps the set of conductive element layout patterns 520. In some embodiments, gate layout pattern 204 a, 204 b overlaps conductive element layout pattern 520 a. In some embodiments, gate layout patterns 204 c, 204 dapply conductive element layout pattern 520 c. Other arrangements or sets of structures in the set of conductive element layout structures 520 are possible.As compared to layout design 300 of FIG. 3, via layout patterns 522 a, 522 bof layout design 500A replace corresponding via layout patterns 322 a, 322 b. The set of via layout patterns 522 is similar to the set of via layout patterns 322, and therefore a similar detailed description is omitted. In some embodiments, the set of via layout patterns 522 is usable to form a corresponding set of vias 422 (FIGS. 4A-4E) connected between the set of gates 204 and the set of conductive patterns 420' formed by the set of conductive element layout patterns 520.FIG. 5B is a cross-sectional view of an integrated circuit 500B corresponding to layout design 500A cut by plane F-F', FIG. 5C is a cross-sectional view of an integrated circuit 500B corresponding to layout design 500A cut by plane G-G', and FIG. 5D is a cross-sectional view of an integrated circuit 500B corresponding to layout design 500A cut by plane H-H', in accordance with some embodiments. Structural relationships including alignment, lengths, and widths, and arrangements of integrated circuit 500B are similar to the structural relationships and arrangements of layout design 500A of FIG. 5A, and are not described in FIGS. 5B-5D for brevity.Integrated circuit 500B is fabricated by layout design 500A. In some embodiments, integrated circuit 500B is similar to integrated circuit 400, and therefore, for brevity, a similar detailed description is omitted.Compared to integrated circuit 400 of FIGS. 4A-4E, set of conductive structures 420' of integrated circuit 500B replaced set of conductive structures 420, and set of vias 422' of integrated circuit 500B replaced set of vias 422.In some embodiments, the set of conductive structures 420' includes one or more conductive structures 420a', 420b', and 420c'. In some embodiments, the set of vias 422' includes one or more vias 422a' and 422b'.The conductive structures 420a' and 420c' extend in the first direction X and are separated from each other in the second direction Y. The conductive pattern 420b' extends in the second direction Y. The conductive pattern 420b' is in direct contact with the conductive patterns 420a' and 420c'. In some embodiments, conductive structures 420a', 420b', and 420c' form part of a same continuous conductive structure. In some embodiments, the set of conductive structures 420' is referred to as a 2D conductive structure.In some embodiments, gate terminal A 1 or gate 404 b 1 (fabricated by gate layout pattern 204 b) of integrated circuit 500B is electrically connected to gate terminal A 2 or gate 404 c 2 (fabricated by gate layout pattern 204 c). For example, in some embodiments, gate terminal A1 or gate 404b1 (fabricated by gate layout pattern 204b) is electrically connected to two-dimensional (2D) conductive pattern 420a', 420b', and 420c' (fabricated by conductive element layout patterns 520a, 520b, 520c) via via 422b' (fabricated by via layout pattern 522b'), and 2-D conductive pattern 420a', 420b', and 420c' is electrically connected to gate terminal A2 or gate 404c2 (fabricated by gate layout pattern 204c) via via 422a' (fabricated by via layout pattern 522a).In some embodiments, gate terminal B 1 or gate 404 c 1 (fabricated by gate layout pattern 204 c) of integrated circuit 500B are electrically connected to gate terminal B 2 or gate 404 b 2 (fabricated by gate layout pattern 204 b), similar to integrated circuit 400 (FIGS. 4A-4E ), and therefore, a similar detailed description is omitted.FIG. 6A is a diagram of a laauout design 600A of an integrated circuit 600B, in accordance with some embodiments.FIGS. 6B, 6C, 6D, and 6E are cross-sectional views of an integrated circuit 600B, in accordance with some embodiments.Layout design 600A is a variation of layout design 300 (FIG. 3 ). For example, layout design 600A illustrates an example in which the gate layout pattern (e.g., gate layout patterns 204 b, 204 c) is continuous, and the MU layer (e.g., a set of conductive element layout patterns 620) extends in a single direction.Layout design 600A is usable to fabricate an integrated circuit similar to integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E), or 600B (FIGS. 6B-6E).As compared to layout design 300 of FIG. 3, layout design 600A does not include the set of cut element layout patterns 304. By not including the set of cut element layout patterns 304, layout design 600A is usable to fabricate integrated circuit 500B having gate terminal A 1 directly connected to gate terminal A 2 and gate terminal B 1 directly connected to gate terminal B 2. For ease of illustration, layout design 600A of FIG. 6A, layout design 700A of FIG. 7A, layout design 800A of FIG. 8A, and layout design 900A of FIG. 9A do not show the set of fin layout patterns 316 of FIG. 3A.In comparison to layout design 300 of FIG. 3, a set of metal over diffusion layout patterns 610 of layout design 600A replaces the set of metal over diffusion layout patterns 210, and therefore a similar detailed description is omitted. The set of metal over diffusion layout patterns 610 is usable to make a corresponding set of contacts 610' (FIGS. 6B-6E) of integrated circuit 600B.The set of metal over diffusion layout patterns 610 includes one or more metal over diffusion layout patterns 610 a, 610 b, 610 c, 612 a, or 612 c. Metal over diffusion layout patterns 610a, 610b, 610c, 612a, and 612c are usable to make corresponding contacts 610a', 610b', 610c', 612a', and 612c' (FIGS. 6B-6E) of integrated circuit 600B.In comparison to layout design 300 of FIG. 3, metal over diffusion layout patterns 610 a, 612 aof layout design 600A replace metal over diffusion layout patterns 210 a, metal over diffusion layout pattern 610 b substitutes metal over diffusion layout pattern 210 b, and metal over diffusion layout patterns 610 c, 612 c substitutes metal over diffusion layout pattern 210 c, and therefore a similar detailed description is omitted.The metal over diffusion layout patterns 610 a, 612 aare similar to the metal over diffusion layout patterns 210 a. The metal over diffusion layout pattern 610 ais separated or interrupted from the metal over diffusion layout pattern 612 a. In some embodiments, the metal over diffusion layout patterns 610 aextend in the second direction Y from an edge of the active area layout pattern 202 bto an edge of the conductive element layout pattern 330 a. In some embodiments, the metal over diffusion layout pattern 612 aextends in the second direction Y from an edge of the active area layout pattern 202 ato an edge of the conductive element layout pattern 630 b.The metal over diffusion layout pattern 610 bis similar to the metal over diffusion layout pattern 310 bwith a reference numeral increased by 300, and thus a similar detailed description is omitted.Metal over diffusion layout patterns 610 c, 612 care similar to metal over diffusion layout patterns 210 c. The metal over diffusion layout pattern 610 cis separated or interrupted from the metal over diffusion layout pattern 612 c. In some embodiments, the metal over diffusion layout pattern 610c extends in the second direction Y from an edge of the active area layout pattern 202b to an edge of the conductive element layout pattern 630b'. In some embodiments, metal over diffusion layout pattern 612 cextends in second direction Y from an edge of active area layout pattern 202 ato an edge of conductive element layout pattern 330 cor 630 b'.As compared to layout design 300 of FIG. 3, a set of via layout patterns 622, 632, or 642 of layout design 600A replaces the corresponding set of via layout patterns 322, 332, or 342, and therefore a similar detailed description is omitted. The set of via layout patterns 622, 632, or 642 is usable to make a corresponding set of vias 622', 632', or 642' (FIGS. 6B-6E) of integrated circuit 600B.The set of via layout patterns 622 includes one or more via layout patterns 622 aor 622 b. The set of via layout patterns 632 includes one or more via layout patterns 632 aor 632 b. The set of via layout patterns 642 includes one or more via layout patterns 642 aor 642 b.Via layout patterns 622a, 622b, 632a, 632b, 642a, and 642b are usable to form corresponding vias 622a', 622b', 632a', 632b', 642a', and 642b' (FIGS. 6B-6E) of integrated circuit 600B.As compared to layout design 300 of FIG. 3, via layout patterns 622 a, 622 bof layout design 600A replace corresponding via layout patterns 322 a, 322 b, via layout patterns 632 a, 632 bcomprise corresponding via layout patterns 332 a, 332 b, and via layout patterns 642 a, 642 bcomprise corresponding via layout patterns 342 a, 342 b, and thus a similar detailed description is omitted.Via layout patterns 622 a, 622 bare similar to corresponding via layout patterns 322 a, 322 b. Via layout patterns 622 a, 622 b(collectively referred to as a "set of via layout patterns 622") are disposed between conductive element layout pattern 620 aand corresponding metal over diffusion layout patterns 612 a, 610 c. The set of via layout patterns 622 is usable to make a corresponding set of vias 622' (VU) that connect the set of conductive patterns 620' to the set of contacts 610'.In some embodiments, a via layout pattern 622 a, 622 bof the set of via layout patterns 622 is disposed where a corresponding layout pattern 612 a, 610 cof the set of metal over diffusion layout patterns 610 overlaps the conductive element layout pattern 620 aof the set of conductive element layout patterns 620. In some embodiments, a center of the via layout patterns 622 a, 622 bof the set of via layout patterns 622 is located below a center of a corresponding metal over diffusion layout pattern 612 a, 610 cof the set of metal over diffusion layout patterns 610. In some embodiments, a center of the via layout patterns 622 a, 622 bof the set of via layout patterns 622 is aligned with a center of a corresponding metal-over-diffusion layout pattern 612 a, 610 cof the set of metal-over-diffusion layout patterns 610 at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 622 a, 622 bof the set of via layout patterns 622 are possible.Via layout patterns 632 a, 632 b(collectively referred to as a "set of via layout patterns 632") are similar to corresponding via layout patterns 332 a, 332 b. The set of via layout patterns 632 is disposed between the set of conductive element layout patterns 630 and the set of gate layout patterns 204. The via layout pattern 632a, 632b of the set of via layout patterns 632 is arranged between a corresponding conductive element layout pattern 630b, 630b' and a corresponding gate layout pattern 204b, 204c of the set of gate layout patterns 204. The set of via layout patterns 632 is usable to make a corresponding set of vias 632' (FIGS. 6B-6E). As shown in FIGS. 6B-6E, vias 632a', 632b' connect corresponding conductive structures 660b1', 660b2' to corresponding gates 604b, 604c.In some embodiments, a via layout pattern 632a, 632b of the set of via layout patterns 632 is located where a corresponding layout pattern 630b, 630b' overlaps a corresponding gate layout pattern 204b, 204c of the set of gate layout patterns 204. In some embodiments, a center of the via layout pattern 632 a, 632 bof the set of via layout patterns 632 is disposed over a center of a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204. In some embodiments, a center of the via layout pattern 332a, 332b of the set of via layout patterns 632 is located below a center of a corresponding conductive element layout pattern 630b, 630b'. In some embodiments, a center of the via layout pattern 632 a, 632 bof the set of via layout patterns 632 is aligned with a center of a corresponding gate layout pattern 204 b, 204 cof the set of gate layout patterns 204 at least in the first direction X or the second direction Y. In some embodiments, a center of the via layout pattern 632 a, 632 bof the set of via layout patterns 632 is aligned with a center of a corresponding conductive element layout pattern 630 b, 630 b' at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 632 a, 632 bof the set of via layout patterns 632 are possible.Via layout patterns 642a, 642b are similar to corresponding via layout patterns 342a, 342b. Via layout pattern 642 a, 642 b(collectively referred to as "set of via layout patterns 642") is disposed between conductive element layout pattern 640 aand corresponding conductive element layout patterns 330 a, 330 b. Via layout patterns 642a, 642b are usable for forming corresponding vias 642a', 642b'. As shown in FIGS. 6B-6E, vias 642a', 642b' connect conductive pattern 640a' to corresponding conductive patterns 430a, 430b.In some embodiments, a via layout pattern 642 a, 642 bof the set of via layout patterns 642 is located where layout pattern 640 aof the set of conductive element layout patterns 640 overlaps a corresponding conductive element layout pattern 330 a, 330 c. In some embodiments, a center of the via layout patterns 642 a, 642 bof the set of via layout patterns 642 is located below a center of the conductive element layout pattern 640 a. In some embodiments, a center of the via layout patterns 642 a, 642 bof the set of via layout patterns 642 is arranged over a center of a corresponding conductive element layout pattern 330 a, 330 c. In some embodiments, a center of the via layout patterns 642 a, 642 bof the set of via layout patterns 642 is aligned with a center of a corresponding conductive element layout pattern 330 a, 330 cin at least one of the first direction X and the second direction Y. Other arrangements of via layout patterns 642a, 642b of the set of via layout patterns 642 are possible.In comparison to layout design 300 of FIG. 3, layout design 600A further includes via layout patterns 636 a, 636 b(collectively referred to as a "set of via layout patterns 636").Via layout patterns 636 a, 636 b(collectively referred to as a "set of via layout patterns 636") are disposed between the set of conductive element layout patterns 630 and the set of metal-over-diffusion layout patterns 610. Via layout pattern 636 a, 636 bof set of via layout patterns 636 is disposed between a corresponding conductive element layout pattern 330 a, 330 cand a corresponding metal over diffusion layout pattern 610 a, 612 c. The set of via layout patterns 636 is usable to form a corresponding set of vias 636' (e.g., VD). As shown in FIGS. 6B-6E, vias 636a', 636b' connect corresponding conductive structures 430a, 430c to corresponding contacts 610a', 612c'.In some embodiments, a via layout pattern 636 a, 636 bof the set of via layout patterns 636 is disposed where a corresponding layout pattern 330 a, 330 c overlaps a corresponding metal over diffusion layout pattern 610 a, 612 c. In some embodiments, a center of the via layout pattern 636 a, 636 bof the set of via layout patterns 636 is disposed over a center of a corresponding metal over diffusion layout pattern 610 a, 612 c. In some embodiments, a center of the via layout pattern 636 a, 636 bof the set of via layout patterns 636 is located below a center of a corresponding conductive element layout pattern 330 a, 330 c. In some embodiments, a center of the via layout pattern 636 a, 636 bof the set of via layout patterns 636 is aligned with a center of a corresponding metal over diffusion layout pattern 610 a, 612 cin at least one of the first direction X and the second direction Y. In some embodiments, a center of the via layout pattern 636 a, 636 bof the set of via layout patterns 636 is aligned with a center of a corresponding conductive element layout pattern 330 a, 330 cin at least one of the first direction X and the second direction Y. Other arrangements of via layout patterns 636 a, 636 bof the set of via layout patterns 636 are possible.As compared to layout design 300 of FIG. 3, conductive element layout pattern 620 aof layout design 600A replaces conductive element layout pattern 320 a, conductive element layout patterns 630 b, 630 b' replace conductive element layout pattern 330 b, and conductive element layout pattern 640 a substitutes conductive element layout pattern 340 a, and therefore similar detailed descriptions are omitted.Conductive element layout pattern 620a is increased by 300 like conductive element layout pattern 320a. Conductive element layout pattern 620a is usable for fabricating a corresponding conductive pattern 620a' (Figs. 6B-6E). Other arrangements of the conductive element layout pattern 620 aof the set of conductive element layout patterns 620 are possible.The conductive element layout patterns 630b, 630b' are increased by 300 similarly to the conductive element layout pattern 330b with the reference numerals. Conductive element layout patterns 630b, 630b' are usable to fabricate corresponding conductive pattern 660b1', 660b2' (Figs. 6B - 6E). Conductive element layout pattern 630b is separated or interrupted from conductive element layout pattern 630b'. In some embodiments, the conductive element layout pattern 630 bextends in the first direction X from an edge of the metal over diffusion layout pattern 610 b. In some embodiments, conductive element layout pattern 630b' extends in first direction X to another edge of metal over diffusion layout pattern 610b. Other arrangements of the conductive element layout patterns 630b, 630b' of the set of conductive element layout patterns 630 are possible.The conductive element layout pattern 640 ais increased by 300 by reference numerals, similar to the conductive element layout pattern 340 a. The conductive element layout pattern 640a is usable for fabricating a corresponding conductive pattern 440a (FIGS. 6B-6E). The conductive element layout pattern 640 bis disposed between the gate layout pattern 204 band the gate layout pattern 204 c. Other arrangements of the conductive element layout pattern 640 aof the set of conductive element layout patterns 640 are possible.FIG. 6B is a cross-sectional view of an integrated circuit 600B corresponding to layout design 600A cut by plane I-I', FIG. 6C is a cross-sectional view of an integrated circuit 600B corresponding to layout design 600A cut by plane J-J', FIG. 6D is a cross-sectional view of an integrated circuit 600B corresponding to layout design 600A cut by plane K-K', and FIG. 6E is a cross-sectional view of an integrated circuit 600B corresponding to layout design 600A cut by plane L-L', in accordance with some embodiments, The layout design 600A of FIG. 6A and arrangements of the integrated circuit 600B are similar to the structural relationships and arrangements of the layout design 600A and are not described in FIGS. 6B-6D for brevity.Integrated circuit 600B is fabricated by layout design 600A. In some embodiments, integrated circuit 600B is similar to integrated circuit 400, and therefore, for brevity, a similar detailed description is omitted.In comparison to integrated circuit 400 of FIGS. 4A-4E, a set of contacts 610' of integrated circuit 500B replaces the set of contacts 410, a set of vias 622', 632', 642' of integrated circuit 500B replaces the corresponding set of vias 422, 432, 442, a conductive structure 620a' of integrated circuit 500B replaces conductive structure 420a, conductive structure 640a' of integrated circuit 500B replaces conductive structure 440a, conductive structures 660b1', 660b2' of integrated circuit 500B replaces conductive structure 430b, gate 604b of integrated circuit 500B replaces gates 404b1 and 404b2, and gate 604c of integrated circuit 500B replaces gates 404c1 and 404c2, respectively, Therefore, a similar detailed description will be omitted for brevity.In some embodiments, the set of contacts 610' includes one or more contacts 610a', 610b', 610c', 612a' and 612c'. In some embodiments, the set of vias 622' includes one or more vias 622a' and 622b'. In some embodiments, the set of vias 632' includes one or more vias 632a' and 632b'. In some embodiments, the set of vias 642' includes one or more vias 642a' and 642b'.Compared to contact 410a of integrated circuit 400 of FIGS. 4A-4E, contacts 610a' and 612a' are not a single continuous structure. The contacts 610a' and 612a' are separated from each other in the second direction Y.Compared to contact 410c of integrated circuit 400 of FIGS. 4A-4E, contacts 610c' and 612c' are not a single continuous structure. The contacts 610c' and 612c' are separated from each other in the second direction Y.Compared to the conductive structure 430b of the integrated circuit 400 of FIGS. 4A-4E, the conductive structures 660b1', 660b2' are not a single continuous structure. With other features, the conductive structures 660b1' and 660b2' are separated from each other in the first direction X.In comparison to integrated circuit 400 of FIGS. 4A-4E, integrated circuit 600B further includes a set of vias 636'. In some embodiments, the set of vias 636' includes one or more vias 636a' or 636b'.The set of vias 636' is similar to the set of vias 432, except that the set of vias 636' is disposed between the set of contacts 610' and one or more conductive structures 430a, 430c, 660b1' or 600b2' and therefore, for brevity, a similar detailed description is omitted. In other words, the set of vias 636' (e.g., VD plane) is disposed over the set of contacts 610c' (e.g., MD plane) and configured to connect the set of contacts 610c' to top metal layers (e.g., Mo plane). For example, vias 636a', 636b' connect corresponding conductive structures 430a, 430c to corresponding contacts 610a', 612c'. Other arrangements of the set of vias 636' are possible.Compared to the gates 404 b 1 and 404 b 2 of the integrated circuit 400 of FIGS. 4A-4E, the gate 604 bis a continuous structure. In some embodiments, gate terminal A 1 (fabricated by gate layout pattern 204 b) of integrated circuit 600B is directly connected to gate terminal A 2 (fabricated by gate layout pattern 204 b) via gate 604 b.Compared to the gates 404 c 1 and 404 c 2 of the integrated circuit 400 of FIGS. 4A-4E, the gate 604 cis a continuous structure. In some embodiments, gate terminal B 1 (fabricated by gate layout pattern 204 c) of integrated circuit 600B is directly connected to gate terminal B 2 (fabricated by gate layout pattern 204 c) via gate 604 c.In some embodiments, terminal A 1D corresponds to contact 610 a', and terminal B 2D corresponds to contact 612 c'. In these embodiments, terminal A 1D or contact 610 a' (fabricated by (metal over diffusion layout pattern 610 a) of integrated circuit 600B is electrically connected to terminal B 2D or contact 612 c' (fabricated by metal over diffusion layout pattern 612 c). For example, in some embodiments, contact 610 a' (formed by metal over diffusion layout pattern 610 a) is electrically connected to conductive pattern 430 a(formed by conductive element layout pattern 330 a) via via 636 a' (formed by via layout pattern 636 a). In some embodiments, conductive pattern 430a is electrically connected to conductive pattern 640a' (formed by conductive element layout pattern 640a) via via 642a' (formed by via layout pattern 642a). In some embodiments, conductive pattern 640a' is electrically connected to conductive pattern 430c (formed by conductive element layout pattern 330c) via via 642b' (formed by via layout pattern 642b). In some embodiments, conductive pattern 430c is electrically connected to contact 612c' (formed by metal over diffusion layout pattern 612c) via via 636b' (formed by via layout pattern 636b). Thus, terminal A1D or contact 610a' is electrically connected to terminal B2D or contact 612c'.In some embodiments, terminal B 1D corresponds to contact 610 c', and terminal A 2D corresponds to contact 612 a'. In these embodiments, terminal B 1D or contact 610 c' (fabricated by (metal over diffusion layout pattern 610 c) of integrated circuit 600B is electrically connected to terminal A 2D or contact 612 a' (fabricated by metal over diffusion layout pattern 612 a). For example, in some embodiments, contact 610c' (formed by metal over diffusion layout pattern 610c) is electrically connected to conductive pattern 620a' (formed by conductive element layout pattern 620a) via via 622b' (formed by via layout pattern 622b). In some embodiments, conductive pattern 620a' is electrically connected to contact 612a' (formed by metal over diffusion layout pattern 612a) via via 622a' (formed by via layout pattern 622a). Thus, terminal B1D or contact 610c' of integrated circuit 600B is electrically connected to terminal A2D or contact 612a'.Other arrangements of the terminals A1D, A2D, B1D, B2D are possible. For example, in some embodiments, terminal A 1D corresponds to contact 610 c', and terminal B 2D corresponds to contact 612 a'. For example, in some embodiments, terminal A 2D corresponds to contact 610 a', and terminal B 1D corresponds to contact 612 c'.FIG. 7A is a diagram of a laauout design 700A of an integrated circuit in accordance with some embodiments.FIGS. 7B, 7C, or 7D are cross-sectional views of an integrated circuit 700B, in accordance with some embodiments.Layout design 700A is a variation of layout design 600A (FIG. 6A ). For example, layout design 700A depicts an example in which the MU layer (e.g., a set of conductive element layout patterns 720) extends in two directions.Layout design 700A is usable to fabricate an integrated circuit similar to integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E), or 700B (FIGS. 7B-7D ).Compared to layout design 600A of FIG. 6A, conductive element layout patterns 720 a, 720 band 720 cof layout design 700A replace conductive element layout pattern 620 a, and therefore a similar detailed description is omitted.Conductive element layout pattern 720 a, 720 b, 720 c(hereinafter referred to as a "set of conductive element layout patterns 720") is similar to corresponding conductive element layout patterns 520 a, 520 b, 520 cof FIG. 5A.The set of conductive element layout patterns 720 is usable to fabricate a corresponding set of two-dimensional (2D) conductive patterns 720' of the integrated circuit 100 or 700B (FIGS. 7B-7D ).In some embodiments, the set of conductive element layout patterns 720 is disposed on the MU portion of the first layout level. The set of conductive element layout patterns 720 extend in two directions (e.g., the first direction X and the second direction Y). The conductive element layout patterns 720 aand 720 cextend in the first direction X. The conductive element layout pattern 720 bextends in the second direction Y.The set of conductive element layout patterns 720 is arranged between the set of active area layout patterns 202. Conductive element layout pattern 720 ais disposed between conductive element layout pattern 330 cand conductive element layout pattern 630 b. Conductive element layout pattern 720c is disposed between conductive element layout pattern 330a and conductive element layout pattern 630b'.Conductive element layout pattern 720 bis disposed between gate layout pattern 204 band 204 c. In some embodiments, conductive element layout pattern 720 bis disposed between conductive element layout pattern 330 aand conductive element layout pattern 330 c. In some embodiments, metal over diffusion layout pattern 612 a, 610 b, 610 c overlaps a corresponding conductive element layout pattern 720 a, 720 b, 720 c.The set of gate layout patterns 204 overlaps the set of conductive element layout patterns 720. In some embodiments, gate layout patterns 204 a, 204 boverlainly overlap conductive element layout pattern 720 a. In some embodiments, gate layout patterns 204 c, 204 dapply conductive element layout pattern 720 c. Other arrangements or sets of structures in the set of conductive element layout structures 720 are possible.FIG. 7B is a cross-sectional view of integrated circuit 700B corresponding to layout design 700A cut by plane M-M', FIG. 7C is a cross-sectional view of integrated circuit 700B corresponding to layout design 700A cut by plane N-N', and FIG. 7D is a cross-sectional view of integrated circuit 700B corresponding to layout design 700A cut by plane O-O', in accordance with some embodiments. Structural relationships including alignment, lengths, and widths, and arrangements of integrated circuit 700B are similar to the structural relationships and arrangements of layout design 700A of FIG. 7A, and are not described in FIGS. 7B-7D for brevity.Integrated circuit 700B is fabricated by layout design 700A. In some embodiments, integrated circuit 700B is similar to integrated circuit 400 or 600A, and therefore, for brevity, a similar detailed description is omitted.In comparison to integrated circuit 600B of FIGS. 6B-6E, set of conductive structures 720' of integrated circuit 700B replaces set of conductive structures 620'.In some embodiments, the set of conductive structures 720' includes one or more conductive structures 720a', 720b', and 720c'.The conductive structures 720a' and 720c' extend in the first direction X and are separated from each other in the second direction Y. The conductive pattern 720b' extends in the second direction Y. The conductive pattern 720b' is in direct contact with the conductive patterns 720a' and 720c'. In some embodiments, conductive structures 720a', 720b', and 72oc' form part of a same continuous conductive structure. In some embodiments, the set of conductive structures 720' is referred to as a 2D conductive structure.In some embodiments, gate terminal A 1 (fabricated by gate layout pattern 204 b) of integrated circuit 700B is directly connected to gate terminal A 2 (fabricated by gate layout pattern 204 b) by gate 604 b(fabricated by gate layout pattern 204 b), similar to integrated circuit 600B of FIGS. 6B-6E, and therefore a detailed description is omitted.In some embodiments, gate terminal B 1 (fabricated by gate layout pattern 204 c) of integrated circuit 700B is directly connected to gate terminal B 2 (fabricated by gate layout pattern 204 c) by gate 604 b(fabricated by gate layout pattern 204 c), similar to integrated circuit 600B of FIGS. 6B-6E, and therefore a detailed description is omitted.In some embodiments, terminal A 1D (fabricated by metal over diffusion layout pattern 610 a) of integrated circuit 700B is electrically connected to terminal B 2D (fabricated by metal over diffusion layout pattern 612 c) similar to integrated circuit 600B of FIGS. 6B-6E, and therefore a detailed description is omitted.In some embodiments, terminal B 1D corresponds to contact 610 c', and terminal A 2D corresponds to contact 612 a'. In these embodiments, terminal B 1D or contact 610 c' (fabricated by (metal over diffusion layout pattern 610 c) of integrated circuit 700B is electrically connected to terminal A 2D or contact 612 a' (fabricated by metal over diffusion layout pattern 612 a). For example, in some embodiments, contact 610c' (formed by metal over diffusion layout pattern 610c) is electrically connected to conductive pattern 720c' (formed by conductive element layout pattern 720c) via via 622b' (formed by via layout pattern 622b). In some embodiments, conductive pattern 720c' (fabricated by conductive element layout pattern 720c) is electrically connected to conductive pattern 720a' (fabricated by conductive element layout pattern 720b) through conductive pattern 720b' (fabricated by conductive element layout pattern 720a). In some embodiments, conductive pattern 720a' (fabricated by conductive element layout pattern 720) is electrically connected to contact 612a (fabricated by metal over diffusion layout pattern 612a) via via 622a' (fabricated by via layout pattern 622a). Thus, terminal B1D or contact 610c' of integrated circuit 700B is electrically connected to terminal A2D or contact 612a'.FIG. 8A is a diagram of a laauout design 800A of an integrated circuit 800B, in accordance with some embodiments.FIGS. 8B, 8C, 8D, 8E, 8F, and 8G are cross-sectional views of an integrated circuit 800B, in accordance with some embodiments.Layout design 800A is a variation of layout design 300 (FIG. 3 ) and layout design 700A (FIG. 7A ). For example, layout design 800A represents an example layout design having a 4-poly pitch width in the first direction X, and the MU layer (e.g., a set of conductive element layout patterns 820) extends in a single direction, but has two portions (e.g., conductive element layout patterns 820 aand 820 b).Layout design 800A is usable for manufacturing an integrated circuit similar to integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E ), or integrated circuit 800B (FIGS. 8B-8G ).As compared to layout design 300 of FIG. 3, layout design 800A does not include the set of cut element layout patterns 304. By not including the set of cut element layout patterns 304, layout design 800A is usable to fabricate an integrated circuit having a gate terminal A 1 directly connected to gate terminal A 2.Compared to layout design 200, 300, 500A, 600A, or 700A, layout design 800A further includes an additional gate layout pattern 804 eextending in the second direction Y, resulting in a wider layout design (e.g., layout design 800A). For example, layout design 800A includes a 4-poly pitch width in first direction X. Layout design 800A includes elements of layout design 300 and 600A. For example, layout design includes at least metal diffusion layout patterns 610 a, 610 c, 612 aand 612 cof layout design 600A. Similarly, layout design 800A includes at least metal diffusion layout patterns 210 aand 210 cof layout design 300.Layout design 800A includes a set of active area layout patterns 202, gate layout patterns 204 a, 204 b, 204 c, 204 d, 804 e(collectively referred to as a "set of gate layout patterns 804"), metal over diffusion layout patterns 210 a, 210 c, 610 a, 610 c, 612 a, 612 c(collectively referred to as a "set of metal over diffusion layout patterns 810"), a set of conductive element layout patterns 330, a conductive element layout pattern 820 a, 820 b(collectively referred to as a "set of conductive element layout patterns 820"), via layout patterns 822 a, 822 b, 822 c, 822 d(collectively referred to as a "set of via layout patterns 822"), Via layout patterns 832a, 832b, 832c (collectively referred to as a "set of via layout patterns 832") and via layout patterns 836a, 836b (collectively referred to as a "set of via layout patterns 836").Compared to layout design 200, 300, 500A, 600A, or 700A, set of active area layout patterns 202 and set of conductive element layout patterns 330 extend over at least gate layout patterns 204 aand 804 e.The gate layout pattern 804 eis similar to one or more of the gate layout patterns 204 a, 204 b, 204 c, 204 dof the set of gate layout patterns 204, and thus a detailed description is omitted. Gate layout pattern 804 eis separated in first direction X by a poly pitch from gate layout pattern 204 d. The set of gate layout patterns 804 is usable to fabricate a corresponding set of gates 804' (FIGS. 8B-8G) of integrated circuit 800B. Gate layout pattern 804e is usable to form a corresponding gate 804e' (FIGS. 8B-8G) of integrated circuit 800B.The set of metal over diffusion layout patterns 810 is similar to the set of metal over diffusion layout patterns 210 of FIG. 2 and the set of metal over diffusion layout patterns 610 of FIGS. 6-7, and therefore a detailed description is omitted. The set of metal over diffusion layout patterns 810 is usable to make a corresponding set of contacts 810' (FIGS. 8B-8G) of integrated circuit 800B. Metal over diffusion layout patterns 210a, 210c, 610a, 610c, 612a, and 612c are usable to make corresponding contacts 410a, 410c, 610a', 610c', 612a', and 612c' (FIGS. 8B-8G) of integrated circuit 800B.The metal over diffusion layout pattern 210 ais disposed between the gate layout patterns 204 aand 204 b. The metal over diffusion layout pattern 210 cis disposed between the gate layout patterns 204 dand 804 e. Each of the metal over diffusion layout patterns 610 aand 612 ais disposed between the gate layout patterns 204 band 204 c. Each of the metal over diffusion layout patterns 610 cand 612 cis disposed between the gate layout patterns 204 cand 204 d.The set of conductive element layout patterns 820 is similar to the set of conductive element layout patterns 320, 420, 520, 620, 720, and therefore, a detailed description is omitted. The set of conductive element layout patterns 820 is usable to fabricate a corresponding set of conductive patterns 820' (FIGS. 8B-8G) of the integrated circuit 800B. The conductive element layout patterns 820 aand 820 bare similar to the corresponding conductive element layout patterns 720 aand 720 c, and therefore, a detailed description is omitted. Conductive element layout patterns 820a and 820b are usable to fabricate corresponding conductive patterns 820a' and 820b' (FIGS. 8B-8G) of integrated circuit 800B.The conductive element layout pattern 820 aextends in the first direction X and is disposed between the conductive element layout pattern 330 band the conductive element layout pattern 330 c. The conductive element layout pattern 820a is arranged between the gate layout pattern 204a and the gate layout pattern 204c. The conductive element layout pattern 820 ais disposed at least below the metal over diffusion layout pattern 210 a, 610 a, or 612 a. In some embodiments, metal over diffusion layout pattern 210 aor metal over diffusion layout patterns 612 aapped with conductive element layout pattern 820 a.The conductive element layout pattern 820 aextends in the first direction X and is disposed between the conductive element layout pattern 330 aand the conductive element layout pattern 330 b. The conductive element layout pattern 820 bis disposed between the gate layout pattern 204 cand the gate layout pattern 804 e. Conductive element layout pattern 820 bis disposed at least below metal over diffusion layout pattern 210 c, 610 c, or 612 c. In some embodiments, metal over diffusion layout pattern 210 cor metal over diffusion layout pattern 610 c overlaps conductive element layout pattern 820 b.The set of via layout patterns 822 is similar to the set of via layout patterns 322, 522, 622, 722, and thus detailed description is omitted. The set of via layout patterns 822 is usable to fabricate a corresponding set of vias 822' (FIGS. 8B-8G) of integrated circuit 800B.Via layout patterns 822a, 822b, 822c, and 822d are usable to form corresponding vias 822a', 822b', 822c', and 822d' (FIGS. 8B-8G) of integrated circuit 800B. Via layout patterns 822 a, 822 care similar to via layout pattern 622 a, and thus a detailed description is omitted. Via layout pattern 822 c, 822 ais disposed between conductive element layout pattern 820 aand corresponding metal over diffusion layout patterns 210 a, 612 a. In some embodiments, via layout pattern 822 c, 822 aof set of via layout patterns 822 is located where a corresponding layout pattern 210 a, 612 aof set of metal over diffusion layout patterns 810 overlaps conductive element layout pattern 820 aof set of conductive element layout patterns 820. In some embodiments, a center of the via layout patterns 822 c, 822 aof the set of via layout patterns 822 is located below a center of a corresponding metal over diffusion layout pattern 210 a, 612 aof the set of metal over diffusion layout patterns 810. In some embodiments, a center of the via layout patterns 822 c, 822 aof the set of via layout patterns 822 is aligned with a center of a corresponding metal-over-diffusion layout pattern 210 a, 612 aof the set of metal-over-diffusion layout patterns 810 at least in the first direction X or the second direction Y.Via layout patterns 822 b, 822 dare similar to via layout pattern 622 b, and thus a detailed description is omitted. Via layout pattern 822 b, 822 dis disposed between conductive element layout pattern 820 band corresponding metal over diffusion layout patterns 610 c, 210 c. In some embodiments, a via layout pattern 822 b, 822 dof the set of via layout patterns 822 is disposed where a corresponding layout pattern 610 c, 210 cof the set of metal over diffusion layout patterns 810 overlaps the conductive element layout pattern 820 bof the set of conductive element layout patterns 820. In some embodiments, a center of the via layout patterns 822 b, 822 dof the set of via layout patterns 822 is located below a center of a corresponding metal over diffusion layout pattern 610 c, 210 cof the set of metal over diffusion layout patterns 810. In some embodiments, a center of the via layout patterns 822 b, 822 dof the set of via layout patterns 822 is aligned with a center of a corresponding metal over diffusion layout pattern 610 c, 210 cof the set of metal over diffusion layout patterns 810 at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 822 a, 822 b, 822 c, 822 dof the set of via layout patterns 822 are possible.The set of via layout patterns 832 is similar to the set of via layout patterns 332, 632, and thus a detailed description is omitted. The set of via layout patterns 832 is usable to form a corresponding set of vias 832 (FIGS. 8B-8G ) of integrated circuit 800B. The set of conductive element layout patterns 832 is disposed between the set of conductive element layout patterns 330 and the set of gate layout patterns 804. Via layout patterns 832a, 832b, and 832c are usable to form corresponding vias 832a', 832b', and 832c' (FIGS. 8B-8G) of integrated circuit 800B. The via layout patterns 832 a, 832 bof the set of via layout patterns 832 are arranged between the corresponding gate layout pattern 330 c, 204 bof the set of gate layout patterns 204 dand the set of conductive element layout patterns 204. The via layout pattern 832 bof the set of via layout patterns 832 is arranged between the conductive element layout pattern 330 aand the gate layout pattern 204 cof the set of gate layout patterns 204.In some embodiments, a via layout pattern 832 a, 832 cof the set of via layout patterns 832 is disposed where a layout pattern 330 c overlaps a corresponding gate layout pattern 204 b, 204 dof the set of gate layout patterns 804. In some embodiments, a via layout pattern 832 bof the set of via layout patterns 832 is disposed where layout pattern 330 aadvocates gate layout pattern 204 cof the set of gate layout patterns 804. In some embodiments, a center of the via layout pattern 832 a, 832 cof the set of via layout patterns 832 is disposed over a center of a corresponding gate layout pattern 204 b, 204 dof the set of gate layout patterns 804. In some embodiments, a center of the via layout pattern 832 bof the set of via layout patterns 832 is disposed over a center of the gate layout pattern 204 cof the set of gate layout patterns 804. In some embodiments, a center of the via layout pattern 832 a, 832 bof the set of via layout patterns 832 is located below a center of the conductive element layout pattern 330 c. In some embodiments, a center of the via layout pattern 832 aof the set of via layout patterns 832 is located below a center of the conductive element layout pattern 330 a. Other arrangements of the via layout patterns 832 a, 832 b, 832 cof the set of via layout patterns 832 are possible.The set of via layout patterns 836 is similar to the set of via layout patterns 636, and therefore a detailed description is omitted. The set of via layout patterns 836 is usable to make a corresponding set of vias 836' (FIGS. 8B-8G) of integrated circuit 800B. The set of via layout patterns 836 is disposed between the set of conductive element layout patterns 330 and the set of metal over diffusion layout patterns 810. Via layout patterns 836a and 836b are usable to form corresponding vias 836a' and 836b' (FIGS. 8B-8G) of integrated circuit 800B. Via layout patterns 836 a, 836 bof set of via layout patterns 836 are disposed between conductive element layout pattern 330 band a corresponding metal over diffusion layout pattern 610 a, 612 c.In some embodiments, a via layout pattern 836 a, 836 bof the set of via layout patterns 836 is disposed where layout pattern 330 bsatisfies a corresponding metal over diffusion layout pattern 610 a, 612 c. Via layout pattern 836 a, 836 bof set of via layout patterns 836 is disposed over a corresponding metal over diffusion layout pattern 610 a, 612 c. In some embodiments, a center of the via layout pattern 836 a, 836 bof the set of via layout patterns 836 is disposed over a center of a corresponding metal over diffusion layout pattern 610 a, 612 c. In some embodiments, a center of the via layout pattern 836 a, 836 bof the set of via layout patterns 836 is located below a center of the conductive element layout pattern 330 b. In some embodiments, a center of the via layout pattern 836 a, 836 bof the set of via layout patterns 836 is aligned with a center of a corresponding metal over diffusion layout pattern 610 a, 612 cin at least one of the first direction X and the second direction Y. In some embodiments, a center of the via layout pattern 836 a, 836 bof the set of via layout patterns 836 is aligned with a center of a corresponding conductive element layout pattern 330 bin at least one of the first direction X and the second direction Y. Other arrangements of via layout patterns 836 a, 836 bof the set of via layout patterns 836 are possible.FIG. 8B is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane P-P', FIG. 8C is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane Q-Q', FIG. 8D is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane R-R', FIG. 8E is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane S-S', FIG. 8F is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane T-T', FIG. 8G is a cross-sectional view of integrated circuit 800B corresponding to layout design 800A cut by plane U-U', in accordance with some embodiments. Structural relationships including alignment, lengths, and widths, as well as arrangements of integrated circuit 800B are similar to the structural relationships and arrangements of layout design 800A of FIG. 8A and are not described in FIGS. 8B-8D for brevity.Integrated circuit 800B is fabricated by layout design 800A. In some embodiments, integrated circuit 800B is similar to integrated circuit 400, 600B, or 700B, and therefore, for brevity, a similar detailed description is omitted.The integrated circuit 800B has a 4-poly pitch width in the first direction X. Integrated circuit 800B includes elements of integrated circuit 400 and 600B. For example, integrated circuit 800B includes at least contacts 610a', 610c', 612a', and 612c' of integrated circuit 600B. Similarly, integrated circuit 800B includes at least contacts 210a' and 210c' of integrated circuit 400.Integrated circuit 800B includes set of active regions 402, gates 404a, 404d, 604b, 604c, and 804e' (collectively referred to as a set of gates 804'), contacts 410a, 410c, 610a', 610c', 612a', 612c' (collectively referred to as contacts 810'), set of conductive structures 430, conductive structures 820a', 820b' (collectively referred to as a set of conductive structures 820'), vias 822a', 822b', 822c', 822d' (collectively referred to as a set of vias 822'), vias 832a', 832b', 832c' (collectively referred to as a set of vias 832'), and vias 836a', 836b' (collectively referred to as a set of vias 836').In comparison to integrated circuit 600 (FIGS. 6B-6E) or 700 (FIGS. 7B-7D), conductive structures 820a', 820b' replace conductive structures 720a', 720c' of integrated circuit 700B, vias 822a', 822b', 822c', 822d' replace vias 622a', 622b' of integrated circuit 700B, vias 832a', 832b', 832c' replace vias 632a', 632b' of integrated circuit 600B, vias 836a', 836b' replace vias 636a', 636b' of integrated circuit 600B, and therefore, for brevity, a similar detailed description is omitted.In comparison to integrated circuit 600 (FIGS. 6B-6E) or 700 (FIGS. 7B-7D), gate 804e' is similar to gate 404a, 404d, 604b, or 604c, and therefore, for brevity, a similar detailed description is omitted.Compared to the conductive structures 720a' and 720c' of the integrated circuit 700B of FIGS. 7B-7E, the conductive structures 820a' and 820b' are not interconnected. In other words, conductive structures 820a' and 820b' are not interconnected by another conductive structure (e.g., conductive structure 720b').The set of vias 822' electrically connect the set of conductive structures 820' to the set of contacts 810'. The set of vias 832' electrically connect the set of conductive structures 430 to the set of gates 804'. The set of vias 836' electrically connect the set of conductive structures 430 to the set of contacts 810'.In some embodiments, terminal A 1 or A 2 corresponds to gate 604 c. The gate 604 cis a continuous structure. In some embodiments, gate terminal A 1 is directly connected to gate terminal A 2 via gate 604 c(formed by gate layout pattern 204 cof layout design 800A).In some embodiments, terminal B 1 corresponds to gate 404 d, and terminal B 2 corresponds to gate 604 b. In these embodiments, gate 404 d(fabricated by gate layout pattern 204 dof layout design 800A) of integrated circuit 800B is electrically connected to gate 604 b(fabricated by gate layout pattern 204 bof layout design 800A). For example, in some embodiments, gate 404d (formed by gate layout pattern 204d of layout design 800A) is electrically connected to conductive pattern 430c (formed by via layout pattern 832c) via via 832c' (formed by via layout pattern 832c), and conductive pattern 430c is electrically connected to gate 604b (formed by gate layout pattern 204b of layout design 800A) via via 832a' (formed by via layout pattern 832a).In some embodiments, terminal B 2D corresponds to contact 410a, and terminal B 2D' corresponds to contact 612a'. In these embodiments, terminal B 2D or contact 410 a(made by metal over diffusion layout pattern 210 a) of integrated circuit 800B is electrically connected to terminal B 2D' or contact 612 a' (made by metal over diffusion layout pattern 612 a). For example, in some embodiments, contact 410a (formed by metal over diffusion layout pattern 210a) is electrically connected to conductive pattern 820a' (formed by conductive element layout pattern 820a) via via via 822c' (formed by via layout pattern 822c). In some embodiments, conductive structure 820a' is electrically connected to contact 612a' (formed by metal-over-diffusion layout structure 612a) via via 822a' (formed by via layout structure 822a). Thus, terminal B2D or contact 410a is electrically connected to terminal B2D' or contact 612a'.In some embodiments, terminal B 1D corresponds to contact 410c, and terminal B 1D' corresponds to contact 610c'. In these embodiments, terminal B 1D or contact 410 c(made by metal over diffusion layout pattern 210 c) of integrated circuit 800B is electrically connected to terminal B 1D' or contact 610 c' (made by metal over diffusion layout pattern 610 c). For example, in some embodiments, contact 410c (formed by metal over diffusion layout pattern 210c) is electrically connected to conductive pattern 820b' (formed by conductive element layout pattern 820b) via via via 822d' (formed by via layout pattern 822d). In some embodiments, conductive structure 820b is electrically connected to contact 610c' (formed by metal-over-diffusion layout structure 610c) via via 822b' (formed by via layout structure 822b). Thus, terminal B1D or contact 410c is electrically connected to terminal B1D' or contact 610c'.FIG. 9A is a diagram of a laauout design 900A of an integrated circuit 900B, in accordance with some embodiments.FIGS. 9B, 9C, 9D, and 9E are cross-sectional views of an integrated circuit 900B, in accordance with some embodiments.Layout design 900A is a variation of layout design 800A (FIG. 8A ). For example, layout design 900A illustrates an example in which the gate (e.g., gate 904 b1' and 94 b2') formed by gate layout patterns 204 bis not continuous, and the MU layer (e.g., a set of conductive element layout patterns 920) extends in a single direction but includes two portions (e.g., conductive element layout patterns 920 aand 920 b).Layout design 900A is usable for manufacturing an integrated circuit similar to integrated circuit 100 (FIG. 1 ) or integrated circuit 400 (FIGS. 4A-4E ).As compared to layout design 800A of FIG. 8A, layout design 900A further includes a set of cut element layout patterns 904 and via layout patterns 932 a. By including the set of cut element layout patterns 904, layout design 900A is usable to fabricate integrated circuit 900B (FIGS. 9B-9E ) having gate terminal A 1 that is not connected to gate terminal B 2.The set of cut element layout patterns 904 is usable for cutting gate 604 bto form the gates 904 b1' and 904 b2' of the integrated circuit 900B (FIGS. 9B-9E ). The set of slice layout patterns 904 is similar to the set of interface layout patterns 304, and therefore detailed description is omitted.Via layout pattern 932 ais similar to one or more of the layout patterns of the set of via layout patterns 332, 632, and 832, and thus a detailed description is omitted. Via layout pattern 932a is usable to form via 932a' in set of vias 932' (Figs. 9B-9E).Via layout pattern 932 aof layout design 900A is similar to via layout pattern 832 a, and thus a detailed description is omitted. Via layout pattern 932 ais disposed between conductive element layout pattern set 330 and gate layout pattern set 804. Via layout pattern 932 ais disposed between conductive element layout pattern 330 aand gate layout pattern 204 bof set of gate layout patterns 804. In some embodiments, via layout pattern 932 ais disposed where layout pattern 330 aabides gate layout pattern 204 bof set of gate layout patterns 804. In some embodiments, a center of the via layout pattern 932 ais disposed over a center of the gate layout pattern 204 bof the set of gate layout patterns 804. In some embodiments, a center of the via layout pattern 932 ais located below a center of the conductive element layout pattern 330 a. Other arrangements of the via layout pattern 932 aare possible.Layout design 900A is a variation of layout design 800A (FIG. 8 ). As compared to layout design 800A of FIG. 8A, layout design 900A does not include via layout pattern 836 b. In comparison to layout design 800A of FIG. 8A, set of metal-over-diffusion layout patterns 910 of layout design 900A replaces set of metal-over-diffusion layout patterns 810, conductive element layout patterns 920 a, 920 b(collectively referred to as "set of conductive element layout patterns 920") replace corresponding conductive element layout pattern 820 a, 820 b, and via layout patterns 922 a, 922 c, 922 d(collectively referred to as "set of via layout patterns 922") replace corresponding via layout pattern 822 a, 822 c, 822 d, and therefore a similar detailed description is omitted.The set of metal over diffusion layout patterns 910 is usable to make a corresponding set of contacts 910' (FIGS. 9B-9E) of integrated circuit 900B. The set of metal over diffusion layout patterns 910 includes one or more metal over diffusion layout patterns 210 a, 910 b, 610 c, 612 c, 910 c, and 912 c. Metal over diffusion layout patterns 210a, 910b, 610c, 612c, 910c, and 912c are usable to make corresponding contacts 410a, 910b', 610c', 612c', 910c', and 912c' (FIGS. 9B-9e) of integrated circuit 900B. The metal over diffusion layout pattern 910 b substitutes the metal over diffusion layout pattern 610 aand the metal over diffusion layout pattern 612 aof the layout design 800A, and therefore a similar detailed description is omitted. Metal over diffusion layout patterns 910 cand 912 csubstitute metal over diffusion layout pattern 210 cof layout design 800A, and therefore a similar detailed description is omitted.In some embodiments, the metal over diffusion layout pattern 910 bextends in the second direction Y from an edge of the active area layout pattern 202 bto an edge of the active area layout pattern 202 a. In some embodiments, metal over diffusion layout pattern 910 cextends in second direction Y from an edge of active area layout pattern 202 bto an edge of conductive element layout pattern 330 b. In some embodiments, the metal over diffusion layout pattern 912 cextends in the second direction Y from one edge of the active area layout pattern 202 ato another edge of the conductive element layout pattern 330 b. Other arrangements of the metal over diffusion layout patterns 210 a, 910 b, 610 c, 612 c, 910 c, and 912 cof the set of metal over diffusion layout patterns 910 are possible.The set of conductive element layout patterns 920 is similar to the set of conductive element layout patterns 320, 420, 520, 620, 720, and 820, and thus a detailed description is omitted. The set of conductive element layout patterns 920 is usable to fabricate a corresponding set of conductive patterns 920' (FIGS. 9B-9E) of the integrated circuit 900B. The conductive element layout patterns 920 aand 920 bare similar to the corresponding conductive element layout patterns 820 aand 820 c, and thus a detailed description is omitted. Conductive element layout patterns 920a and 920b are usable for fabricating corresponding conductive patterns 920a' and 920b' (FIGS. 9B-9E) of integrated circuit 900B.The conductive element layout pattern 920 aextends in the first direction X and is disposed between the conductive element layout pattern 330 band the conductive element layout pattern 330 c. The conductive element layout pattern 920 ais disposed between the gate layout pattern 204 cand the gate layout pattern 804 e. Conductive element layout pattern 920 ais disposed at least below metal over diffusion layout pattern 612 cor 912 c. In some embodiments, metal over diffusion layout pattern 612 cor metal over diffusion layout pattern 912 c overlaps conductive element layout pattern 920 a.The conductive element layout pattern 920 bextends in the first direction X and is disposed between the conductive element layout pattern 330 aand the conductive element layout pattern 330 b. The conductive element layout pattern 920 bis disposed between the gate layout pattern 204 band the gate layout pattern 204 d. Conductive element layout pattern 920 bis disposed at least below metal over diffusion layout pattern 910 bor 610 c. In some embodiments, metal over diffusion layout pattern 910 bor metal over diffusion layout pattern 610 c overlaps conductive element layout pattern 920 b. Other arrangements of the conductive element layout patterns 920 a, 920 bof the set of conductive element layout patterns 920 are possible.The set of via layout patterns 922 includes via layout patterns 922 a, 822 b, 922 c, 922 d. The set of via layout patterns 922 is similar to the set of via layout patterns 322, 522, 622, 722, and 822, and thus a detailed description is omitted. The set of via layout patterns 922 is usable to make a corresponding set of vias 922' (FIGS. 9B-9E) of integrated circuit 900B that connect the set of conductive patterns 420 to the set of contacts 410.Via layout patterns 922a, 822b, 922c, and 922d are usable to form corresponding vias 922a', 822b', 922c', and 922d' (FIGS. 9B-9E) of integrated circuit 900B. Via layout patterns 922 a, 922 care similar to corresponding via layout patterns 822 a, 822 c, and thus a detailed description is omitted. Via layout pattern 922 c, 922 ais disposed between conductive element layout pattern 920 aand corresponding metal over diffusion layout patterns 612 c, 912 c. In some embodiments, via layout patterns 922 c, 922 aof set of via layout patterns 922 are located where a corresponding layout pattern 612 c, 912 cof set of metal over diffusion layout patterns 910 overlaps conductive element layout pattern 920 aof set of conductive element layout patterns 920. In some embodiments, a center of the via layout patterns 922 c, 922 aof the set of via layout patterns 922 is located below a center of a corresponding metal over diffusion layout pattern 612 c, 912 cof the set of metal over diffusion layout patterns 910. In some embodiments, a center of the via layout patterns 922 c, 922 aof the set of via layout patterns 922 is aligned with a center of a corresponding metal-over-diffusion layout pattern 612 c, 912 cof the set of metal-over-diffusion layout patterns 910 at least in the first direction X or the second direction Y.Via layout pattern 922 dis similar to via layout pattern 622 bor 822 d, and thus a detailed description is omitted. Via layout pattern 922 dis disposed between conductive element layout pattern 920 band metal over diffusion layout pattern 910 b. In some embodiments, via layout pattern 922 dof set of via layout patterns 922 is located where layout pattern 910 bof set of metal over diffusion layout patterns 910 overlaps conductive element layout pattern 920 bof set of conductive element layout patterns 920. In some embodiments, a center of the via layout pattern 922 dof the set of via layout patterns 922 is located below a center of the metal over diffusion layout pattern 910 bof the set of metal over diffusion layout patterns 910. In some embodiments, a center of the via layout pattern 922 dof the set of via layout patterns 922 is aligned with a center of the metal-over-diffusion layout pattern 910 bof the set of metal-over-diffusion layout patterns 910 at least in the first direction X or the second direction Y. Other arrangements of via layout patterns 922 a, 922 c, 922 dof the set of via layout patterns 922 are possible.FIG. 9B is a cross-sectional view of an integrated circuit 900B corresponding to layout design 900A cut by plane V-V', FIG. 9C is a cross-sectional view of an integrated circuit 900B corresponding to layout design 900A cut by plane W-W', FIG. 9D is a cross-sectional view of an integrated circuit 900B corresponding to layout design 900A cut by plane X-X', and FIG. 9E is a cross-sectional view of an integrated circuit 900B corresponding to layout design 900A cut by plane Y-Y', in accordance with some embodiments. Structural relationships including alignment, lengths, and widths, as well as arrangements of integrated circuit 900B are similar to the structural relationships and arrangements of layout design 900A of FIG. 9A and are not described in FIGS. 9B-9E for brevity.Integrated circuit 900B is fabricated by layout design 900A. In some embodiments, integrated circuit 900B is similar to integrated circuit 400, 600B, 700B, or 800B, and therefore, for brevity, a similar detailed description is omitted.The integrated circuit 900B has a 4-poly pitch width in the first direction X.Integrated circuit 900B includes set of active regions 402, gates 404a, 404d, 904b1', 904b2', 604c, and 804e' (collectively referred to as a set of gates 904'), contacts 410a, 910b', 610c', 612c', 910c', and 912c' (collectively referred to as contacts 910'), set of conductive structures 430, conductive structures 920a', 920b' (collectively referred to as a set of conductive structures 920'), vias 922a', 822b', 922c', 922d' (collectively referred to as a set of vias 922'), vias 832a', 832b', 832c', 932a' (collectively referred to as a set of vias 932'), and via 836b'.In comparison to integrated circuit 800B (FIGS. 8B-8G), gates 904b1' and 904b2' replace gate 604b, contacts 910b' replace contacts 610a' and 612a', contacts 910c' and 912c' replace contact 410c, conductive structures 920a' and 920b' replace corresponding conductive structures 820a' and 820b', vias 922a', 922c' and 922d' replace corresponding vias 822a', 822c' and 822d', and therefore, a similar detailed description is omitted for brevity.In comparison to integrated circuit 800B (FIGS. 8A-8G), integrated circuit 900B further includes via 932a'. Via 932a' is similar to via 832a, and therefore, a similar detailed description is omitted for brevity. Via 932a' electrically connects conductive structures 430a to gate 904b1'.Compared to integrated circuit 800B (FIGS. 8B-8G), integrated circuit 900B does not include via 836b'.The set of vias 932' electrically connect the set of conductive structures 430 to the set of gates 904'. The set of vias 922' electrically connect the set of conductive structures 920' to the set of contacts 910'.In some embodiments, terminal A1 corresponds to gate 904b1', terminal B2 corresponds to gate 904b2' and terminal A2 corresponds to gate 604c. In these embodiments, due to the cut element layout pattern 904 of layout design 900A, gate 904b1' (fabricated by gate layout pattern 204b of layout design 900A) is not directly connected to gate 904b2' (fabricated by gate layout pattern 204b of layout design 900A). In other words, in some embodiments, the cut element layout pattern 904 of layout design 900A is used to determine a removed portion of gate 604 b(not shown in FIGS. 8F-8G ), thereby forming discontinuous gates 904 b1' and 904 b2'.In some embodiments, terminal A1 corresponds to gate 904b1', and terminal A2 corresponds to gate 604c. In these embodiments, gate 904b1' (fabricated by gate layout pattern 204b of layout design 900A) of integrated circuit 900B is electrically connected to gate 604c (fabricated by gate layout pattern 204c of layout design 900A). For example, in some embodiments, gate 904b1' (fabricated by gate layout pattern 204b of layout design 900A) is electrically connected to conductive pattern 430a (fabricated by via layout pattern 932a) via via 932a' (fabricated by via layout pattern 932a), and conductive pattern 430a is electrically connected to gate 604c (fabricated by gate layout pattern 204c of layout design 900A) via via 832b' (fabricated by via layout pattern 832b).In some embodiments, terminal B1 corresponds to gate 404d and terminal B2 corresponds to gate 904b2'. In these embodiments, gate 404d (formed by gate layout pattern 204d of layout design 900A) is electrically connected to gate 904b2' (formed by gate layout pattern 204b of layout design 900A). For example, in some embodiments, gate 404d (formed by gate layout pattern 204d of layout design 900A) is electrically connected to conductive pattern 430c (formed by via layout pattern 832c) via via 832c' (formed by via layout pattern 832c), and conductive pattern 430c is electrically connected to gate 904b2' (formed by gate layout pattern 204b of layout design 900A) via via 832a' (formed by via layout pattern 832a).In some embodiments, terminal A 2D corresponds to contact 612c', and terminal A 2D' corresponds to contact 912c'. In these embodiments, terminal A 2D or contact 612 c' (fabricated by metal over diffusion layout pattern 612 cof layout design 900A) is electrically connected to terminal A 2D' or contact 912 c' (fabricated by metal over diffusion layout pattern 912 cof layout design 900A). For example, in some embodiments, contact 612c' (formed by metal over diffusion layout pattern 612c) is electrically connected to conductive pattern 920a' (formed by conductive element layout pattern 920a) via via 922c' (formed by via layout pattern 922c). In some embodiments, conductive pattern 920a' (formed by conductive element layout pattern 920a) is electrically connected to contact 912c' (formed by metal over diffusion layout pattern 912c of layout design 900A) via via 922a' (formed by via layout pattern 922a). Thus, terminal A2D or contact 612c' is electrically connected to terminal A2D' or contact 912c'.In some embodiments, terminal A 1D corresponds to contact 910b', and terminal A 1D' corresponds to contact 610c'. In these embodiments, terminal A 1D or contact 910 b' (fabricated by metal over diffusion layout pattern 910 bof layout design 900A) is electrically connected to terminal A 1D' or contact 610 c' (fabricated by metal over diffusion layout pattern 610 cof layout design 900A). For example, in some embodiments, contact 910b' (formed by metal over diffusion layout pattern 910b) is electrically connected to conductive pattern 920b' (formed by conductive element layout pattern 920b of layout design 900A) via via 922d' (formed by via layout pattern 922d). In some embodiments, conductive pattern 920b' is electrically connected to contact 610c' (formed by metal over diffusion layout pattern 610c) via via 822b' (formed by via layout pattern 822b). Thus, terminal A1D or contact 910b' is electrically connected to terminal A1D' or contact 610c'.In some embodiments, the set of conductive element layout patterns 320, 520, 620, 720, 820, and 920 is disposed below at least the set of gate layout patterns 304 and the metal o (Mo) level of layout design 300 & 500A- 900A.In some embodiments, by using the set of conductive element layout patterns 320, 520, 620, 720, 820, and 920, a Mo path in the set of conductive element layout patterns 330 of FIGS. 3 & 5A-9A is reduced, resulting in a standard cell having a lower height and area compared to other approaches. In some embodiments, by using the set of conductive element layout patterns 320, 520, 620, 720, 820, and 920, the width of one or more layout patterns in the set of conductive element layout patterns 330 of FIGS. 3 & 5A-9A is increased because an Mo path is reduced, resulting in a standard cell with better current resistance (IR) and better electromigration (EM) compared to other approaches.In some embodiments, by using the set of conductive element layout patterns 320, 520, 620, 720, 820, and 920 of the present disclosure, the gate density of the set of gate layout patterns of a standard cell is increased by up to 30% compared to other approaches. In some embodiments, layout design 200- 300 and 500A- 900 A and integrated circuits 400 and 500B- 900B of FIGS. 2 - 3 & 5A- 9E provide more routing flexibility and increase routing resources compared to other approaches by using the set of conductive element layout patterns 320, 520, 620, 720, 820, and 920 of the present disclosure.FIG. 10 is a flow diagram of a method 1000 of forming an integrated circuit, in accordance with some embodiments. It is contemplated that additional operations may be performed before, during, and / or after the method 1000 illustrated in FIG. 10, and that some other methods may be described only briefly herein. In some embodiments, the method 1000 is usable to form integrated circuits, such as integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E ), integrated circuit 500B, integrated circuit 600B, integrated circuit 700B, integrated circuit 800B, or dir integrated circuit 900B.In operation 1002 of method 1000, a layout design 300 (FIG. 3 ) of an integrated circuit (e.g., integrated circuit 100 (FIG. 1 ) or integrated circuit 400 (FIGS. 4A-4E )) is generated. Operation 1002 is performed by a processing device (e.g., processor 1202 (FIG. 12 )) configured to execute instructions to generate a layout design (e.g., layout design 200 or 300). In some embodiments, layout design 200 or 300 is a graphical database system (GDSII) file format. In some embodiments, operation 1002 of method 1000 is used to generate one or more of layout designs 200 (FIG. 2 ), 300 (FIG. 3 ), 500A (FIG. 5 ) 600A (FIG. 6 ) 700A (FIG. 7 ) 800A (FIG. 8 ) or 900 a(FIG. 9 ).The method 1000 continues with operation 1004 where the integrated circuit (e.g., the integrated circuit 100 (FIG. 1 ) or the integrated circuit 400 (FIGS. 4A-4E )) is fabricated based on the layout design 300 (FIG. 3 ). In some embodiments, operation 1004 includes fabricating integrated circuit 500B, 600B, 700B, 800B, or 900B based on corresponding layout design 500A, 600A, 700A, 800A, or 900A. In some embodiments, integrated circuit 100 (FIG. 1 ) or integrated circuit 400 (FIGS. 4A-4E) includes gates 404 b 1, 404 b 2, 404 c 1, or 404 c 2. In some embodiments, operation 1004 includes forming at least one mask based on one or more of layout designs 200 (FIG. 2 ), 300 (FIG. 3 ), 500A (FIG. 5A ), 600A (FIG. 6A ), 700A (FIG. 7A ), 800A (FIG. 8A ) or 900A (FIG. 9A ), and forming integrated circuit (e.g., integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E ), or integrated circuit 500B, 600B, 700B, 800B, or 900B ) based on the at least one mask. In some embodiments, operation 1004 of method 1000 is used to fabricate an integrated circuit (e.g., integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E ), or integrated circuit 500B, 600B, 700B, 800B, or 900B ) based on one or more of layout designs 200 (FIG. 2 ), 300 (FIG. 3 ), 500A (FIG. 5A ), 600A (FIG. 6A ), 700A (FIG. 7A ), 800A (FIG. 8A ), or 900A (FIG. 9A ).The method 1000 continues with operation 1006, where a portion of a gate (e.g., gate A 1, A 2, B 1, or B 2) is removed, thereby forming a first gate structure (e.g., gate 404 b 1 or 404 c 1) and a second gate structure (e.g., gate 404 b 2 or 404 c 2) of the integrated circuit 100, 400, 500B, 600B, 700B, 800B, or 900B. In some embodiments, the portion of the gate (e.g., gate A 1, A 2, B 1, or B 2) removed in operation 1006 in layout designs 300, 500A, and 900A is determined by cut element layout pattern 304 aor 304 b(FIGS. 3 and 5A ) or cut element layout pattern 904 (FIG. 9A ). In some embodiments, operation 1006 of method 1000 is referred to as a poly cut process (CPO). In some embodiments, operation 1006 results in the formation of integrated circuit 100 (FIG. 1 ), 400 (FIGS. 4A-4E ), 500B, 600B, 700B, 800B, or 900B. In some embodiments, the removed gate portion of the gates 404 b 1 and 404 b 2 and the gates 404 c 1 and 404 c 2 is referred to as a cut portion.In some embodiments, operation 1006 is performed by a removal operation. In some embodiments, the removal process includes one or more etch processes suitable for removing a portion of the gate (e.g., gate A 1, A 2, B 1, or B 2). In some embodiments, the etching process of operation 1006 includes determining a portion of the gate (e.g., gate A 1, A 2, B 1, or B 2) to be removed and etching the portion of the gate (e.g., gate A 1, A 2, B 1, or B 2) to be removed. In some embodiments, a mask is used to define portions of the gate (e.g., gate A 1, A 2, B 1, or B 2) to be cut or removed. In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, the etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable methods, any combination thereof, or the like.In some embodiments, method 1000 is used with layout designs other than layout design 200 or 300. In some embodiments, layout design 200 (FIG. 2 ) or 300 (FIG. 3 ) of operation 1004 or 1006 is replaced with, for example, one or more of layout designs 500A (FIG. 5A), 600A (FIG. 6A), 700A (FIG. 7A), 800A (FIG. 8A), or 900A (FIG. 9A).In some embodiments, operation 1006 is not performed. For example, in some embodiments, operation 1006 is not performed to fabricate integrated circuit 100 or 400. In some embodiments, the method 1000 is performed to fabricate an integrated circuit 600B, 700B, or 800B based on one or more of the layout designs 600A, 700A, or 800A, and the operation 1006 is not performed on the fabricated integrated circuit.FIGS. 11A-11B is a flow diagram of a method 1100 of generating an integrated circuit laauout design, in accordance with some embodiments. It is contemplated that additional operations may be performed before, during, and / or after the method 1100 illustrated in FIGS. 11A-11B, and that some other methods may be described only briefly herein. In some embodiments, method 1100 is usable to generate one or more layout designs, such as layout design 200 (FIG. 2 ), layout design 300 (FIG. 3 ), layout design 500A (FIG. 5A ), layout design 600A (FIG. 6A ), layout design 700A (FIG. 7A ), layout design 800A (FIG. 8A ), or layout design 9004 (FIG. 9A ) of an integrated circuit, such as integrated circuit 100 (FIG. 1 ), integrated circuit 400 (FIGS. 4A-4E ), or integrated circuit 500B, 600B, 700B, 800B, or 900B. In some embodiments, the method 1100 is usable to form integrated circuits having similar structural relationships as one or more of layout designs 200- 300 or 500A- 900A (FIGS. 2- 3 or 5A- 9A ). In some embodiments, the method 1100 is performed by a processing device (e.g., processor 1202 (FIG. 12 )) configured to generate instructions for generating layout design 200 (FIG. 2 ), layout design 300 (FIG. 3 ), layout design 500A (FIG. 5A ), layout design 600A (FIG. 6A ), layout design 700A (FIG. 7A ), layout design 800A (FIG. 8A ), or layout design 9004 (FIG. 9A ).In operation 1102 of method 1100, a set of active area layout patterns is generated. In some embodiments, the set of active area layout patterns of method 1100 includes one or more structures of the set of active area layout patterns 202 of FIGS. 2-3 and 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1104 of method 1100, the set of active area layout patterns is placed in the first layout level of layout design 200, 300 or 500A- 900A. In some embodiments, the first layout level corresponds to the OD layout level.In operation 1106 of method 1100, a set of fin layout patterns is generated. In some embodiments, the set of fin layout patterns of method 1100 includes one or more structures of the set of fin layout patterns 316 of FIG. 3, and therefore a detailed description of these layout patterns is omitted.In operation 1108 of method 1100, the set of fin layout patterns is placed in a second layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the second layout level corresponds to the FIN layout level. In some embodiments, the second layout level is the same as the first layout level. In some embodiments, the second layout level is different from the first layout level. In some embodiments, the second layout level is disposed over the first layout level. In some embodiments, the second layout level is disposed below the first layout level.In operation 1110 of method 1100, a set of conductive element layout patterns is generated. In some embodiments, the set of conductive element layout patterns of method 1100 includes one or more structures of the set of conductive element layout patterns 320, 520, 620, 720, 820, or 920 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1112 of method 1100, the first set of conductive element layout patterns is placed in a first portion of the first layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the first portion of the first layout level corresponds to the MU layout level.In operation 1114 of method 1100, a set of gate layout patterns is generated. In some embodiments, the set of gate layout patterns of method 1100 includes one or more of the set of gate layout patterns 205 of FIG. 2, the set of gate layout patterns 206 of FIG. 2, the set of gate layout patterns 204 of FIGS. 3 & 5A- 7A, and the set of gate layout patterns 804 of FIGS. 8A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1116 of method 1100, the set of gate layout patterns is placed in a third layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the third layout level corresponds to the poly or MD layout level. In some embodiments, the third layout level is different from the first layout level and the second layout level. In some embodiments, the third layout level is disposed over one or more of the first or second layout level. In some embodiments, the third layout level is disposed below one or more of the first or second layout level.In operation 1118 of method 1100, a set of via layout patterns is generated. In some embodiments, the first set of via layout patterns of method 1100 includes one or more patterns of the set of via layout patterns 322, 522, 622, 822, 922 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1120 of method 1100, the first set of via layout patterns is placed between the first layout level and the third layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the first set of via layout patterns is placed in the VU layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the first set of via layout patterns is placed between the set of gate layout patterns and the first set of conductive element layout patterns.In operation 1122 of method 1100, a set of metal over diffusion layout patterns is generated. In some embodiments, the set of metal over diffusion layout patterns of method 1100 includes one or more layout patterns of the set of metal over diffusion layout patterns 210, 610, 612, 810, or 910 of FIGS. 2-3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1124 of method 1100, the set of metal over diffusion layout patterns is placed in the third layout level of layout design 200, 300 or 500A- 900A. In some embodiments, the third layout level corresponds to the MD layout level.In operation 1126 of method 1100, a second set of via layout patterns is generated. In some embodiments, the second set of via layout patterns of method 1100 includes one or more patterns of the set of via layout patterns 322, 522, 622, 822, 922 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1128 of method 1100, the second set of via layout patterns is placed in the third layout level and the first layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the second set of via layout patterns is placed in the VU layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the second set of via layout patterns is placed between the set of metal over diffusion layout patterns and the first set of conductive element layout patterns.In operation 1130 of method 1100, a second set of conductive element layout patterns is generated. In some embodiments, the second set of conductive element layout patterns of method 1100 includes one or more structures of the set of conductive element layout patterns 330 of FIGS. 3 & 5A- 9A, or conductive element layout patterns 630 b, 630 b' of FIGS. 3 & 5A- 9A, and therefore a detailed description of these layout patterns is omitted.In operation 1132 of method 1100, the second set of conductive element layout patterns is placed in a fourth layout level of layout design 200, 300 or 500A- 900A. In some embodiments, the fourth layout level is different from the first layout level, the second layout level, and the third layout level. In some embodiments, the fourth layout level is disposed over one or more of the first, second, or third layout level. In some embodiments, the fourth layout level is disposed below one or more of the first, second, or third layout level. In some embodiments, the fourth layout level corresponds to the Mo layout level.In operation 1134 of method 1100, a third set of via layout patterns is generated. In some embodiments, the third set of via layout patterns of method 1100 includes one or more patterns of the set of via layout patterns 332, 632, 832, 932 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1136 of method 1100, the third set of via layout patterns is placed between the third layout level and the fourth layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the third set of via layout patterns is placed in the VG layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the third set of via layout patterns is placed between the set of gate layout patterns and the second set of conductive element layout patterns.In operation 1138 of method 1100, a fourth set of via layout patterns is generated. In some embodiments, the fourth set of via layout patterns of method 1100 includes one or more patterns of the set of via layout patterns 636, 836 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1140 of method 1100, the fourth set of via layout patterns is placed between the third layout level and the fourth layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the fourth set of via layout patterns is placed in the VD layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the fourth set of via layout patterns is placed between the set of metal over diffusion layout patterns and the second set of conductive element layout patterns.In operation 1142 of method 1100, a third set of conductive element layout patterns is generated. In some embodiments, the third set of conductive element layout patterns of method 1100 includes one or more structures of the set of conductive element layout patterns 340, 640 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1144 of method 1100, the third set of conductive element layout patterns is placed in a fifth layout level of layout design 200, 300 or 500A- 900A. In some embodiments, the fifth layout level is different from the first layout level, the second layout level, the third layout level, and the fourth layout level. In some embodiments, the fifth layout level is disposed over one or more of the first, second, third, or fourth layout levels. In some embodiments, the fifth layout level is disposed below one or more of the first, second, third, or fourth layout levels. In some embodiments, the fifth layout level corresponds to the M1 layout level.In operation 1146 of method 1100, a fifth set of via layout patterns is generated. In some embodiments, the fifth set of via layout patterns of method 1100 includes one or more patterns of the set of via layout patterns 342, 642 of FIGS. 3 & 5A-9A, and therefore a detailed description of these layout patterns is omitted.In operation 1148 of method 1100, the fifth set of via layout patterns is placed between the fourth layout level and the fifth layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the fifth set of via layout patterns is placed in the V0 layout level of layout design 200, 300 or 500A- 9004. In some embodiments, the fifth set of via layout patterns is placed between the first set of conductive layout patterns and the second set of conductive element layout patterns.In operation 1150 of method 1100, a cut element layout pattern is generated. In some embodiments, the cut element layout pattern of method 1100 includes cut element layout pattern 304 aor 304 b(FIGS. 3 and 5A ), or cut element layout pattern 904 (FIG. 9A ), and therefore a detailed description of these layout patterns is omitted.In operation 1152 of method 1100, the cut element layout pattern is placed in one or more of the third, fourth, or fifth layout level of layout design 200, 300, or 500A- 900A.In some embodiments, one or more of the operations of method 1100 is / are not performed. One or more of the operations of methods 1000- 1100 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit, such as integrated circuit 100, 400, 500B, 600B, 700B, 800B, or 900B. In some embodiments, one or more of the operations of methods 1000- 1100 are performed using the same processing apparatus used in one or more other operations of methods 1000- 1100. In some embodiments, a processing device other than that used to perform one or more operations of methods 1000- 1100 is used to perform one or more operations of methods 1000- 1100.FIG. 12 is a schematic view of a system 1200 for designing an IC laauout design, in accordance with some embodiments. In some embodiments, system 1200 generates or places one or more of the IC layout designs described herein. The system 1200 includes a hardware processor 1202 and a non-transitory computer readable storage medium 1204 in which the computer program code 1206, i.e., a set of executable instructions, is encoded, i.e., stored. The computer readable storage medium 1204 is configured to interface with manufacturing machines for producing the integrated circuit. The processor 1202 is electrically connected to the computer readable storage medium 1204 via a bus 1208. Processor 1202 is also electrically connected to an input / output interface by bus 1208. A network interface 1212 is also connected to processor 1202 via bus 1208. The network interface 1212 is connected to a network 1214 such that the processor 1202 and the computer readable storage medium 1204 are capable of connecting external elements via the network 1214. The processor 1202 is operable to execute the computer program code 1206 encoded on the computer readable storage medium 1204 to cause the system 1200 to be usable to perform a portion or all of the operations as described in methods 1000 or 1100.In some embodiments, the processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.In some embodiments, the computer readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus). For example, the computer readable storage medium 1204 includes a semiconductor or solid state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In some embodiments using optical disks, the computer readable storage medium 1204 includes a compact disk read only memory (CD-ROM), a compact disk for read / write (CD-R / W), and / or a digital video disk (DVD).In some embodiments, storage medium 1204 stores computer program code 1206, which is configured to cause system 1200 to perform method 1000 or 1100. In some embodiments, storage medium 1204 also stores information necessary to perform methods 1000 or 1100, as well as information generated during execution of methods 1000 or 1100, such as layout design 1216 and operator interface 1218, and / or a set of executable instructions for executing the operations of methods 1000 or 1100. In some embodiments, layout design 1216 includes one or more of layout designs 200- 300 or 500A- 900A. In some embodiments, layout design 1216 includes one or more layout structures of layout designs 200- 300 or 500A- 900A.In some embodiments, storage medium 1204 stores instructions (e.g., computer program code 1206) for interfacing with manufacturing machines. The instructions (e.g., computer program code 1206) enable the processor 1202 to generate manufacturing instructions readable by the manufacturing machines to effectively implement the method 1000 or 1000 during a manufacturing operation.The system 1200 includes an input / output interface 1210. The input / output interface 1210 is connected to an external circuit. In some embodiments, input / output interface 1210 includes a keyboard, keypad, mouse, trackball, keypad, and / or cursor direction keys for communicating information and commands to processor 1202.Further, the system 1200 includes a network interface 1212 connected to the processor 1202. Network interface 1212 enables system 1200 to communicate with network 1214 to which one or more other computer systems are connected. The network interface 1212 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1394. In some embodiments, method 1000 or 1100 is implemented in two or more systems 1200, and information such as layout design, as well as the operator interface, is exchanged between different systems 1200 through network 1214.The system 1200 is configured to receive information related to layout design through the input / output interface 1210 or the network interface 1212. The information is transmitted through bus 1208 to processor 1202 to determine a layout design for producing an integrated circuit, for example, integrated circuit 100, 400, 500B, 600B, 700B, 800B, or 900B. The layout design is then stored in the computer readable medium 1204 as layout design 1216. The system 1200 is configured to receive information associated with an operator interface via the input / output interface 1210 or the network interface 1212. The information is stored in the computer readable medium 1204 as the operator interface 1218.In some embodiments, method 1000 or 1100 is implemented as a stand-alone software application for execution by a processor. In some embodiments, method 1000 or 1100 is implemented as a software application that forms part of an additional software application. In some embodiments, method 1000 or 1100 is implemented as a plug-in (plug-in) of a software application. In some embodiments, method 1000 or 1100 is implemented as a software application that represents a portion of an EDA (Electronic Design Automation) tool. In some embodiments, method 1000 or 1100 is implemented as a software application used by an EDA (Electronic Design Automation) tool. In some embodiments, the EDA tool is used to generate a design of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is created using a tool such as the VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool. In some embodiments, the layout is created based on a netlist created based on the schematic structure. In some embodiments, method 1000 or 1100 is implemented by a manufacturing apparatus for manufacturing an integrated circuit (e.g., integrated circuit 100, 400, 500B, 600B, 700B, 800B, or 900B) using a set of masks generated by system 1200 based on one or more layout designs (e.g., layout design 200- 300 or 500A- 900A). The system 1200 of FIG. 12 creates layout designs (e.g., layout design 200- 300 or 500A- 900A) of an integrated circuit (e.g., integrated circuit 100, 400, 500B, 600B, 700B, 800B, or 900B) that are smaller than other approaches.One aspect of this specification relates to an integrated circuit comprising a set of active regions in a substrate, a first set of conductive structures, a trench isolation (STI) region, a set of gates, and a first set of vias. The set of active regions extending in a first direction is arranged in a first plane and separated from each other in a second direction different from the first direction. The first set of conductive structures extending at least in the first direction or the second direction is disposed in the first plane and between the set of active regions. The ST region extending at least in the first direction or the second direction is disposed at least in the first plane and between the set of active regions and the first set of conductive structures. The set of gates extends in the second direction, overlaps at least the first set of conductive structures, and is disposed in a second plane different from the first plane, wherein each of the gates of the set of gates is separated from an adjacent gate of the set of gates in the first direction by a first pitch. The first set of vias connects the first set of conductive structures to the set of gates, wherein the first set of vias is disposed between the first set of conductive structures and the set of gates, and a via of the first set of vias is disposed where a gate of the set of gates overlaps a conductive structure of the first set of conductive structures. In some embodiments, a set of contacts extends in the second direction, overlaps the first set of conductive structures, and is disposed in the second plane, each of the contacts of the set of contacts being separated from an adjacent contact of the set of contacts in the first direction; and a second set of vias connect the first set of conductive structures to the set of contacts, the second set of vias being disposed between the first set of conductive structures and the set of contacts, and a via of the second set of vias being disposed where a contact of the set of contacts overlaps the conductive structure of the first set of conductive structures. In some embodiments, a second set of conductive structures extends in the first direction, is disposed between the set of active regions, overlaps at least the set of gates, and is disposed in a third plane different from the first plane and the second plane, and each of the conductive structures of the second set of conductive structures is separated from an adjacent conductive structure of the second set of conductive structures in the second direction; and a third set of vias connect the second set of conductive structures to the set of contacts, wherein the third set of vias is disposed between the second set of conductive structures and the set of contacts, and a via of the third set of vias is disposed where a conductive structure of the second set of conductive structures overlaps another contact of the set of contacts. In some embodiments, a second set of conductive structures extends in the first direction, is disposed between the set of active regions, overlaps at least the set of gates, and is disposed in a third plane different from the first plane and the second plane, and each of the conductive structures of the second set of conductive structures is separated from an adjacent conductive structure of the second set of conductive structures in the second direction; and a third set of vias connect the second set of conductive structures to the set of gates, wherein the third set of vias is disposed between the second set of conductive structures and the set of gates, and a via of the third set of vias is disposed where a conductive structure of the second set of conductive structures overlaps another gate of the set of gates. In some embodiments, a third set of conductive structures extends in the second direction, is disposed between the set of gates, overlaps at least the first set of conductive structures, and is disposed in a fourth plane different from the first plane, the second plane, and the third plane, and each of the structures of the fourth set of conductive structures is separated from an adjacent structure of the fourth set of conductive structures in the first direction; and a fourth set of vias connect the third set of conductive structures to the second set of conductive structures, the fourth set of vias is disposed between the third set of conductive structures and the second set of conductive structures, and a via of the fourth set of vias is disposed where a structure of the third set of conductive structures overlaps another structure of the second set of conductive structures. In some embodiments, a set of fins extends in the first direction and below the set of gates, each of the fins being separated from an adjacent fin of the set of fins in the second direction by a fin pitch. In some embodiments, a surface of the conductive structure of the first set of conductive structures is disposed below a surface of an active region of the set of active regions or a surface of a fin of the set of fins. In some embodiments, the integrated circuit includes a transfer gate.Another aspect of this specification relates to a method of manufacturing an integrated circuit. The method includes creating, by a processor, a layout design of the integrated circuit, and fabricating the integrated circuit based on the layout design. In some embodiments, creating the layout design includes creating a set of active area layout patterns, creating a first set of conductive element layout patterns, creating a set of gate layout patterns, and creating a first set of via layout patterns. In some embodiments, the set of active region layout patterns extends in a first direction, is arranged in a first layout level, and is separated from each other in a second direction different from the first direction, wherein the set of active region layout patterns corresponds to fabricating a set of active regions of the integrated circuit. In some embodiments, the first set of conductive element layout patterns extends at least in the first direction or the second direction, is disposed in the first layout level, and is disposed between the set of active area layout patterns, wherein the first set of conductive element layout patterns corresponds to fabricating a first set of conductive structures of the integrated circuit. In some embodiments, the set of gate layout patterns extends in the second direction, overlaps at least the first set of conductive element layout patterns, and is disposed in a second layout level different from the first layout level, wherein each of the layout patterns of the set of gate layout patterns is separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, the set of gate layout patterns corresponding to fabricating a set of gates of the integrated circuit. In some embodiments, the first set of via layout patterns corresponds to fabricating a first set of vias, the first set of vias connect the first set of conductive patterns of the set of gates, the first set of via layout patterns is disposed between the first set of conductive element layout patterns and the set of gate layout patterns, and a layout pattern of the first set of via layout patterns is disposed where a layout pattern of the set of gate layout patterns overlaps a layout pattern of the first set of conductive element layout patterns. In some embodiments, creating the layout design further includes creating a second set of conductive element layout patterns corresponding to fabricating a second set of conductive structures of the integrated circuit, wherein the second set of conductive element layout patterns extends in the first direction, is disposed between the set of active area layout patterns, overlaps at least the set of gate layout patterns, and is disposed in a third layout level different from the first layout level and the second layout level, and wherein each of the layout patterns of the second set of conductive layout patterns is separated from an adjacent layout pattern of the second set of conductive layout patterns in the second direction. In some embodiments, creating the layout design further includes creating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias connecting the second set of conductive patterns to the set of gates, the second set of via layout patterns being disposed between the second set of conductive element layout patterns and the set of gate layout patterns, and a layout pattern of the second set of via layout patterns being disposed where a layout pattern of the second set of conductive element layout patterns overlaps another layout pattern of the set of gate layout patterns. In some embodiments, creating the layout design further includes creating a third set of conductive element layout patterns corresponding to fabricating a third set of conductive structures of the integrated circuit, wherein the third set of conductive element layout patterns extends in the second direction, is disposed between the set of gate layout patterns, overlaps at least the first set of conductive element layout patterns, and is disposed in a fourth layout level different from the first layout level, the second layout level, and the third layout level, and each of the layout patterns of the fourth set of conductive layout patterns is separated from an adjacent layout pattern of the fourth set of conductive layout patterns in the first direction; generating a fourth set of via layout patterns according to fabricating a fourth set of vias, wherein the fourth set of vias connect the third set of conductive patterns to the second set of conductive patterns, the fourth set of via layout patterns is disposed between the third set of conductive element layout patterns and the second set of conductive element layout patterns, and a layout pattern of the fourth set of via layout patterns is disposed where a layout pattern of the third set of conductive element layout patterns overlaps another layout pattern of the second set of conductive element layout patterns. In some embodiments, creating the layout design further includes creating a set of metal-over-diffusion layout patterns corresponding to fabricating a set of contacts of the integrated circuit, the set of metal-over-diffusion layout patterns extending in the second direction, overlapping the first set of conductive patterns, and disposed in the second layout level, each of the layout patterns of the set of metal-over-diffusion patterns being separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns in the first direction; generating a second set of via layout patterns according to fabricating a second set of vias, wherein the second set of vias connects the first set of conductive patterns to the set of contacts, the second set of via layout patterns is disposed between the first set of conductive element layout patterns and the set of metal-over-diffusion layout patterns, and a layout pattern of the second set of via layout patterns is disposed where a layout pattern of the set of metal-over-diffusion layout patterns overlaps the layout pattern of the first set of conductive element layout patterns. In some embodiments, creating the layout design further includes generating a set of fin layout patterns corresponding to fabricating a set of fins of the integrated circuit structure, wherein the set of fin layout patterns extends in the first direction and below the set of gate layout patterns, and each of the layout patterns of the set of fin layout patterns is separated from an adjacent layout pattern of the set of fin layout patterns in the second direction by a fin pitch. In some embodiments, creating the layout design further includes creating a cut element layout pattern corresponding to a cut region of a first gate of the set of gates of the integrated circuit, the cut element layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns. In some embodiments, the method further comprises removing a portion of the first gate of the set of gate structures to form a first gate structure and a second gate structure, and determining a position of the removed portion of the first gate of the set of gate structures through the cut element layout structure.Yet another aspect of this specification relates to a method of manufacturing an integrated circuit. The method includes creating, by a processor, a layout design of the integrated circuit, and fabricating the integrated circuit based on the layout design. In some embodiments, the integrated circuit includes a transfer gate. In some embodiments, creating the layout design includes placing a set of active area layout patterns in a first layout level, placing a first set of conductive element layout patterns in the first layout level, placing a set of metal over diffusion layout patterns in a second layout level different from the first layout level, and placing a first set of via layout patterns between the first set of conductive element layout patterns and the set of metal over diffusion layout patterns. In some embodiments, the set of active region layout patterns extends in a first direction and is separated from each other in a second direction different from the first direction, the set of active region layout patterns corresponding to fabricating a set of active regions of the integrated circuit. In some embodiments, the first set of conductive element layout patterns extends at least in the first direction or the second direction, and is disposed between the set of active area layout patterns, wherein the first set of conductive element layout patterns corresponds to fabricating a first set of conductive structures of the integrated circuit. In some embodiments, the set of metal-over-diffusion layout patterns corresponds to fabricating a set of contacts of the integrated circuit, the set of metal-over-diffusion layout patterns extends in the second direction and overlaps the first set of conductive element layout patterns, each of the layout patterns of the set of metal-over-diffusion structures being separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns in the first direction. In some embodiments, the first set of via layout patterns corresponds to fabricating a first set of vias, the first set of vias connect the first set of conductive patterns to the set of contacts, and a layout pattern of the first set of via layout patterns is disposed where a layout pattern of the set of metal over diffusion layout patterns overlaps the layout pattern of the first set of conductive element layout patterns. In some embodiments, creating the layout design further includes placing a second set of conductive element layout patterns in a third layout level different from the first layout level and the second layout level, the second set of conductive element layout patterns corresponds to fabricating a second set of conductive structures of the integrated circuit, the second set of conductive element layout patterns extends in the first direction, is disposed between the set of active area layout patterns, and overlaps at least the first set of conductive element layout patterns, each of the layout patterns of the second set of conductive layout patterns being separated from an adjacent layout pattern of the second set of conductive layout patterns in the second direction; Placing a second set of via layout patterns between the first set of conductive element layout patterns and the set of metal over diffusion layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias, wherein the second set of vias connect the second set of conductive patterns to the set of contacts, and a layout pattern of the second set of via layout patterns is disposed where a layout pattern of the second set of conductive element layout patterns overlaps another layout pattern of the set of metal over diffusion layout patterns. In some embodiments, creating the layout design further includes placing a set of gate layout patterns in the second layout level, the set of gate layout patterns extending in the second direction and overlapping at least the first set of conductive element layout patterns, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in the first direction by a first pitch, and the set of gate layout patterns corresponds to fabricating a set of gates of the integrated circuit. In some embodiments, creating the layout design further includes placing a second set of via layout patterns between the first set of conductive element layout patterns and the set of gate layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias, the second set of vias connecting the first set of conductive patterns to the set of gates, and a layout pattern of the second set of via layout patterns is located where a layout pattern of the second set of gate layout patterns overlaps a layout pattern of the first set of conductive element layout patterns.

Claims

An integrated circuit (400, 900B) comprising: a set of active regions (402) in a substrate, wherein the active regions of the set of active regions (402) extend in a first direction (X), are arranged in a first plane, and are separated from each other in a second direction (Y) different from the first direction (X); a first set of conductive structures (420) extending at least in the first direction (X) or the second direction (Y), are arranged in the first plane, and are arranged between the active regions of the set of active regions (402); a trench isolation region (490) extending at least in the first direction (X) or the second direction (Y), arranged at least in the first plane, and arranged between one of the active regions (402) and the first set of conductive structures (420); a set of gates (404) extending in the second direction (Y), overlapping at least the first set of conductive structures (420), and arranged in a second plane different from the first plane, each of the gates of the set of gates (404) being separated from an adjacent gate of the set of gates (404) by a first distance in the first direction (X); and a set of contacts (410) extending in the second direction (Y), overlapping the first set of conductive structures (420) and arranged in the second plane, each of the contacts of the set of contacts (410) being separated from an adjacent contact of the set of contacts (410) in the first direction (X).The integrated circuit (400, 900B) of claim 1, further comprising: a first set of vias (422) connecting the first set of conductive structures (420) to the set of gates (404), wherein the vias of the first set of vias (422) are disposed between the conductive structures (420) and the gates (404), and wherein a via of the first set of vias (422) is disposed where a gate of the set of gates (404) overlaps a conductive structure of the first set of conductive structures (420); a second set of vias (822) connecting the first set of conductive structures (420, 820') to the set of contacts (410), wherein the vias (822) of the second set of vias (822) are arranged between the conductive structures of the first set of conductive structures (420, 820') and the contacts (410, 810), and wherein a via of the second set of vias (822) is arranged where a contact of the set of contacts (410, 810) overlaps a conductive structure of the first set of conductive structures (420, 820').The integrated circuit (400, 900B) of claim 2, further comprising: a second set of conductive structures extending in the first direction (X), arranged between the active regions, overlapping at least the set of gates (404), and arranged in a third plane different from the first plane and the second plane, and wherein each of the conductive structures of the second set of conductive structures is separated from an adjacent conductive structure of the second set of conductive structures in the second direction (Y); and a third set of vias connecting the second set of conductive structures to the set of contacts (410, 810), wherein the vias of the third set of vias are disposed between the conductive structures of the second set of conductive structures and the contacts (410, 810), and wherein a via of the third set of vias is disposed where a conductive structure of the second set of conductive structures overlaps a contact of the set of contacts.The integrated circuit (400, 900B) of claim 2, further comprising: a second set of conductive structures (430) extending in the first direction, disposed between the active regions, at least overlapping the set of gates (404), and disposed in a third plane different from the first plane and the second plane, and wherein each of the conductive structures of the second set of conductive structures (430) is separated from an adjacent conductive structure of the second set of conductive structures (430) in the second direction (Y); and a third set of vias (432) connecting the second set of conductive structures (430) to the set of gates (404), wherein the vias of the third set of vias (432) are arranged between the conductive structures of the second set of conductive structures (430) and the gates (404), and wherein a via of the third set of vias (432) is arranged where a conductive structure of the second set of conductive structures (430) overlaps a gate of the set of gates (404).The integrated circuit (400, 900B) of claim 4, further comprising: a third set of conductive structures (440) extending in the second direction (Y), disposed between the gates (404), overlapping at least the first set of conductive structures (420), and disposed in a fourth plane different from the first plane, the second plane, and the third plane, and wherein each of the structures of the third set of conductive structures (440) is separated from an adjacent structure of the third set of conductive structures (440) in the first direction (X); and a fourth set of vias (442) connecting the third set of conductive structures (440) to the second set of conductive structures (430), wherein the vias of the fourth set of vias (442) are arranged between the third set of conductive structures (440) and the second set of conductive structures (430), and wherein a via of the fourth set of vias (442) is arranged where a structure of the third set of conductive structures (440) overlaps a structure of the second set of conductive structures (430).The integrated circuit (400, 900B) of claim 5, further comprising: a set of fins extending in the first direction and below the set of gates (404), each of the fins being separated from an adjacent fin of the set of fins by a fin pitch in the second direction.The integrated circuit (400, 900B) of claim 6, wherein a surface of the conductive structures of the first set of conductive structures is disposed below a surface of an active region of the set of active regions or a surface of a fin of the set of fins.The integrated circuit (400, 900B) of any preceding claim, wherein the integrated circuit comprises a transfer gate.A method of forming an integrated circuit (400, 900B), the method comprising: creating, by a processor (1202), a layout design (300, 900A) of the integrated circuit (400, 900B), wherein creating the layout design (300, 900A) comprises: creating a set of active area layout patterns (202) extending in a first direction (X), arranged in a first layout plane, and separated from each other in a second direction (Y) different from the first direction (X), the set of active area layout patterns (202) corresponding to fabricating a set of active areas (402) within a substrate (480) of the integrated circuit (400, 900B); generating a first set of conductive element layout patterns (320, 920) extending at least in the first direction (X) or the second direction (Y), arranged in the first layout plane, and arranged between active area layout patterns (202), the first set of conductive element layout patterns (320, 920) corresponding to fabricating a first set of conductive patterns (420, 920') of the integrated circuit (400, 900B) within the substrate (480); generating a set of gate layout patterns (204, 804) extending in the second direction (Y), overlapping at least the first set of conductive element layout patterns (320, 920), and arranged in a second layout level different from the first layout level, wherein each of the layout patterns of the set of gate layout patterns (204, 804) is separated from an adjacent layout pattern of the set of gate layout patterns (204, 804) by a first distance in the first direction (X), the set of gate layout patterns (204, 804) corresponding to fabricating a set of gates (404) of the integrated circuit (400, 900B); generating a set of metal-over-diffusion layout patterns (210, 910) according to fabricating a set of contacts (410, 910') of the integrated circuit (400, 900B), the metal-over-diffusion layout patterns (210, 910) extending in the second direction (Y), overlapping the first set of conductive element layout patterns (320, 920), and being arranged in the second layout plane, each of the layout patterns of the set of metal-over-diffusion layout patterns (210, 910) being separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns (210, 910) in the first direction (X); and generating a first set of via layout patterns (322, 910), 922) corresponding to fabricating a first set of vias (422, 922'), wherein the first set of vias (922') connect the first set of conductive structures (420) to the set of contacts (410), the first set of via layout structures (322, 922) is disposed between the first set of conductive element layout structures (320, 920) and the set of metal-over-diffusion layout structures (210, 910), and a layout structure (922d) of the first set of via layout structures (322, 922) is disposed where a layout structure (910b) of the set of metal-over-diffusion layout structures (910) overlaps the layout structure (920b) of the first set of conductive element layout structures (320, 920); and fabricating the integrated circuit ( 400, 900B) based on the layout design ( 300, 900A).The method of claim 9, wherein creating the layout design (300, 900A) further comprises: creating a second set of conductive element layout patterns (330) corresponding to fabricating a second set of conductive structures (430) of the integrated circuit (400), wherein the conductive element layout patterns of the second set (330) extend in the first direction (X), are arranged between the set of active area layout patterns (202, 402), overlap at least the set of gate layout patterns (204, 804, 904'), and are arranged in a third layout level different from the first layout level and the second layout level, and wherein each of the layout patterns of the second set of conductive element layout patterns (330) is separated from an adjacent layout pattern of the second set of conductive element layout patterns (330) in the second direction (Y).The method of claim 10, wherein creating the layout design (300, 900A) further comprises: creating a second set of via layout patterns (332, 932) corresponding to fabricating a second set of vias (432, 932'), wherein the vias of the second set (432, 932') connect the second set of conductive patterns (430) to the set of gates (404, 904'), the via layout patterns of the second set (332, 932) are disposed between the second set of conductive element layout patterns (330, 430) and the set of gate layout patterns (204, 904'), and a layout pattern (932a') of the second set of via layout patterns (332, 932) is disposed there, where a layout pattern ( 430 a) of the second set of conductive element layout patterns ( 330, 430) overlaps a layout pattern ( 904 b1') of the set of gate layout patterns ( 204, 904').The method of claim 11, wherein creating the layout design (300, 900A) further comprises: creating a third set of conductive element layout patterns (340) corresponding to fabricating a third set of conductive structures (440) of the integrated circuit (400), wherein the conductive element layout patterns of the third set (340) extend in the second direction (Y), are arranged between the set of gate layout patterns (204), overlap at least the first set of conductive element layout patterns (320), and are arranged in a fourth layout level different from the first layout level, the second layout level, and the third layout level, and wherein each of the layout patterns of the third set of conductive element layout patterns (340) is separated from an adjacent layout pattern of the third set of conductive element layout patterns (340) in the first direction (X); generating a third set of via layout patterns (342) according to fabricating a third set of vias (442), wherein the vias of the third set (442) connect the third set of conductive patterns (440) to the second set of conductive patterns (430), the third set of via layout patterns (342) is disposed between the third set of conductive element layout patterns (340) and the second set of conductive element layout patterns (330), and a layout pattern of the third set of via layout patterns (340) is disposed where a layout pattern of the third set of conductive element layout patterns (340) overlaps a layout pattern of the second set of conductive element layout patterns (330).The method of claim 9, wherein creating the layout design (300, 900A) further comprises: creating a second set of via layout patterns corresponding to fabricating a second set of vias, wherein the second set of vias connect the first set of conductive patterns (320, 920) to the set of gates (404), the second set of via layout patterns is disposed between the first set of conductive element layout patterns and the set of gate layout patterns (404), and a layout pattern of the second set of via layout patterns is disposed where a layout pattern of the set of gate layout patterns overlaps a layout pattern of the first set of conductive element layout patterns.The method of any of claims 9 to 13, wherein creating the layout design (300, 900A) further comprises: creating a set of fin layout patterns (316) corresponding to fabricating a set of fins of the integrated circuit structure, wherein the set of fin layout patterns extends in the first direction and is disposed below the set of gate layout patterns, and each of the layout patterns of the set of fin layout patterns is separated from an adjacent layout pattern of the set of fin layout patterns in the second direction by a fin pitch.The method of any of claims 9 to 14, wherein creating the layout design (300, 900A) further comprises: creating a cut element layout pattern (304, 904) corresponding to a cut region of a first gate (604b) of the set of gates (404, 904') of the integrated circuit (400, 900B), wherein the cut element layout pattern (304, 904) extends in the first direction (X) and overlaps at least one first gate layout pattern of the set of gate layout patterns (204, 904).The method of claim 15, further comprising: removing a portion of the first gate (604b) of the set of gate structures (404, 904') to form a first gate structure (904b1') and a second gate structure (904b2'), and determining a position of the removed portion of the first gate (604b) of the set of gate structures (404, 904') by the cut element layout structure (304, 904).A method of forming an integrated circuit (400), the method comprising: creating, by a processor (1202), a layout design (300) of the integrated circuit (400), wherein creating the layout design (300) comprises: placing a set of active area layout patterns (202) in a first layout level, the active area layout patterns extending in a first direction (X) and separated from each other in a second direction (Y) different from the first direction (X), the set of active area layout patterns (202) corresponding to fabricating a set of active areas (402) within a substrate (480) of the integrated circuit (400); placing a first set of conductive element layout patterns (320) in the first layout level, wherein the conductive element layout patterns of the first set (320) extend at least in the first direction (X) or the second direction (Y) and are arranged between active area layout patterns, the first set of conductive element layout patterns (320) corresponding to fabricating a first set of conductive structures (420) within the integrated circuit substrate (480); placing a set of metal-over-diffusion layout patterns (210) in a second layout level different from the first layout level, the set of metal-over-diffusion layout patterns corresponding to fabricating a set of contacts (410) of the integrated circuit, wherein the set of metal contacts (410) are electrically connected to the active regions (402) of the integrated circuit, the metal-over-diffusion layout patterns (210) extend in the second direction (Y) and overlap the first set of conductive element layout patterns (320), wherein each of the layout patterns of the set of metal-over-diffusion structures (210) is separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns (210) in the first direction (X); Placing a first set of via layout patterns (322, 922) between the first set of conductive element layout patterns (320, 920) and the set of metal over diffusion layout patterns (210, 910), the first set of via layout patterns (322, 922) corresponding to fabricating a first set of vias (422, 922'), wherein the first set of vias (422, 922') connect the first set of conductive patterns (420, 920) to the set of contacts (410, 910'), and a layout pattern of the first set of via layout patterns (322, 922) is located where a layout pattern of the set of metal over diffusion layout patterns (210, 910) overlaps the layout pattern of the first set of conductive element layout patterns (320, 920); and fabricating the integrated circuit (400, 900B) based on the layout design (300, 900A), the integrated circuit (400, 900B) including a transfer gate.The method of claim 17, wherein creating the layout design (300, 900A) further comprises: placing a second set of conductive element layout patterns (330) in a third layout level different from the first layout level and the second layout level, the second set of conductive element layout patterns (330) overlapping at least the first set of conductive element layout patterns (320), according to fabricating a second set of conductive patterns (430) of the integrated circuit (400, 900B), wherein the conductive element layout patterns of the second set (330) extend in the first direction (X), are disposed between the active area layout patterns (202, 402), and wherein each of the layout patterns of the second set of conductive layout patterns (330) is separated from an adjacent layout pattern of the second set of conductive layout patterns (330) in the second direction (Y); Placing a second set of via layout patterns (922) between the first set of conductive element layout patterns (320) and the set of metal over diffusion layout patterns (210, 910), the second set of via layout patterns (922) corresponding to fabricating a second set of vias (922'), wherein the second set of vias (922') connect the second set of conductive patterns to the set of contacts, and a layout pattern of the second set of via layout patterns is located where a layout pattern of the second set of conductive element layout patterns overlaps the layout pattern of the set of metal over diffusion layout patterns.The method of claim 17 or 18, wherein creating the layout design (300, 900A) further comprises: placing a set of gate layout patterns (204, 804) in the second layout level, the gate layout patterns (204, 804) extending in the second direction (Y) and overlapping at least the first set of conductive element layout patterns (320, 920), each of the layout patterns of the set of gate layout patterns (204, 804) being separated from an adjacent layout pattern of the set of gate layout patterns (204, 804) in the first direction (X) by a first distance, and the set of gate layout patterns (204, 804) corresponding to fabricating a set of gates (404) of the integrated circuit (400, 900B).The method of claim 19, wherein creating the layout design (300, 900A) further comprises: placing a second set of via layout patterns (332, 932) between the first set of conductive element layout patterns (320, 920) and the set of gate layout patterns (204, 904), the second set of via layout patterns (332, 932) corresponding to fabricating a second set of vias (432, 932'), the second set of vias (422) connecting the first set of conductive patterns (420) to the set of gates (404, 904'), and a layout pattern of the second set of via layout patterns (332, 932) is located where a layout pattern of the set of gate layout patterns (204, 932) is located, 804) overlaps a layout pattern of the first set of conductive element layout patterns ( 320, 920).

Images