METHOD AND DEVICE FOR OPERATING A MEMORY ARRANGEMENT

Abstract

A method (100) for operating a memory device (210), the method (100) comprising: Receiving (102) a physical address (A1), wherein the physical address (A1) is associated with a first memory segment (S1) of a memory array (210); Modifying (104) the physical address (A1) to a modified physical address (A2), wherein the modified physical address (A2) is associated with a second memory segment (S2) of the memory array (210); Selecting (106) the second memory segment (S2); and Providing a modification value (M), where the physical address (A1) and the modification value (M) are each a binary number with N digits, where the modified physical address (A2) is obtained: - is obtained from an exclusive-OR operation of the physical address (A) and the modification value (M), and / or - from a shift and rotation of bit values ​​of the physical address (A1) by K positions towards a first or a last position of the physical address (A1), where N is a positive integer, and K is a positive integer greater than zero and not equal to N.

Description

BACKGROUND OF THE INVENTION

[0001] The present disclosure relates to a method and apparatus for operating a memory array.

[0002] Some computing systems include a memory array for storing and providing data for real-time program execution. The memory array may include an array of memory segments, each capable of storing and providing a unit of information. Each of the memory segments may be assigned a respective physical address to enable unique assignment.

[0003] The lifetime of a memory array can be influenced by the total number of write and read operations performed. In particular, the lifetime of a memory array can be shortened due to aging effects. Often, the memory segments of a memory array cannot be repaired or replaced in isolation, so the occurrence of a defect in one of the memory segments can lead to the failure of the entire memory array.

[0004] Uneven utilization of certain memory segments, for example due to an above-average frequency of repeated writing and reading, can therefore lead to a shortening of the lifetime of a memory array.

[0005] The prior art relevant to the present invention is provided by DE 199 22 155 A1, EP 0 176 939 A1, and DE 11 2008 003 878 T5. A memory arrangement is known from the prior art, comprising a memory with a plurality of memory cells and a selection device. The selection device selects a memory cell for physical access based on a logical address supplied via an address bus. The selection device includes a scrambling device that assigns a memory cell in the memory arrangement to a logical address transmitted to the selection devices by scrambling, to which the physical access then takes place. SUMMARY OF THE INVENTION

[0006] Against this background, it is an object of the present invention to provide a method and / or a device for operating a memory device in order to positively influence the lifetime of the memory device.

[0007] The problem is solved by the subject matter of claim 1 and the independent claims. Advantageous examples are recited by the subject matter of the dependent claims.

[0008] Disclosed herein is a method for operating a memory array. According to the method, a physical address is received. The physical address is assigned to a first memory segment of a memory array. The physical address is modified to a modified physical address. The modified physical address is assigned to a second memory segment of the memory array. Subsequently, the memory segment corresponding to the modified physical address can be selected. Thus, the second memory segment can be selected, for example, to store a memory value or to retrieve a memory value stored there.

[0009] The memory arrangement can be configured to store data and provide stored data for reading. In particular, the memory arrangement can be configured to store and provide data for executing a program in real time. For example, the memory arrangement can (temporarily) store memory values ​​that are generated, retrieved, and / or processed during the execution of a program.

[0010] The memory arrangement may comprise memory cells of a volatile memory. For example, the memory arrangement is configured to retain stored information or stored values ​​as long as it is in operation and / or is supplied with an operating current. In the event of an interruption in the power supply, the volatile memory may, for example, retain the stored information for a fraction of a second or for a longer period. In some examples, the memory arrangement comprises cells of an SRAM and / or cells of a DRAM. In some examples, the memory arrangement is part of a processor register and / or coupled to machine code operands of a processor. For example, the memory arrangement is coupled to a processor unit as data memory and / or program memory.

[0011] In other examples, the memory array may include memory cells of a non-volatile memory. The non-volatile memory may include, for example, a ROM, PROM, EPROM, EEPROM, Flash EEPROM, FRAM, MRAM, or Phase-Change RAM.

[0012] The memory arrangement may comprise an array of memory segments. A memory segment may comprise a memory cell comprising a circuit of active and passive semiconductor components. Each memory cell may be configured to store a unit of information, for example, a binary value, or a bit for short, and make it available for reading. For example, a memory cell comprises an SRAM cell with four, six, eight, or more transistors. In further examples, a memory cell comprises a DRAM cell with two transistors. The transistors may comprise field-effect transistors (FETs).

[0013] Additionally or alternatively, a memory segment may comprise multiple memory cells. A quantity of data, or a memory value, that can be stored in multiple memory cells of a memory segment may be referred to as a word. Accordingly, the number of memory cells of a memory segment may correspond to a (maximum) word length. For example, the number of memory cells in a memory segment is 2, 4, 8, 16, 32, 64, or 2 to the power of n, where n is greater than 6. In further examples, the number of memory cells of a memory segment may correspond to half the length of a word (halfword). For example, the memory arrangement may have a word length of eight bits, and the memory segments may each be four bits long.

[0014] Each memory segment can be assigned a respective physical address to enable unique allocation and thus unique selection of the respective memory segment for a read or write operation. The memory segments of the memory array can be organized into rows and columns. Furthermore, the memory array can be divided into banks, wherein each bank can comprise a predetermined number of rows and / or a predetermined number of columns. Consequently, a specific memory segment can be uniquely selected using a combination of the associated row, the associated column, and, if applicable, the associated bank. For example, the physical address can include details of the row, the column, and, if applicable, the bank.

[0015] The memory arrangement can be provided as a separate, stand-alone unit and / or integrated into an overall system. For example, the memory arrangement can be part of a main memory, a secondary memory, and / or other memory of a computer system. The computer system can be a general-purpose computer system, which can include, for example, a multi-purpose computer, a PC, a mobile computing device, or a workstation.

[0016] According to one example, the memory arrangement may be part of an embedded system that is configured and adapted to perform specific operations. In some examples, the embedded system comprises a computer system. The embedded system may, for example, be configured to perform a monitoring function, a control function, and / or a regulation function. The embedded system may be configured to process data or signals, e.g., to encrypt, decrypt, code, decode, or filter them. The embedded system may be implemented in application-specific hardware, for example, in a motor vehicle, an aircraft, a medical device, a household appliance, a consumer electronics device, or a mobile device. Furthermore, the embedded system may communicate with other embedded systems and / or form a larger overall system with them, e.g.,for controlling parts of a motor vehicle or an aircraft. Multiple embedded systems can be coupled, for example, via a bus. In some examples, the memory arrangement is configured to communicate with a microprocessor.

[0017] The memory segments of the memory device can each be suitable for storing a memory value and for making a stored memory value available for retrieval. The term memory value can refer to the content of the information to be stored. The memory value can in particular comprise information that is (temporarily) stored for further processing. For example, the memory value comprises an input value for an operation. The input value can, for example, have been entered by a user or generated by a program. Furthermore, the memory value can comprise an output value that is to be output as the result of an operation. Alternatively or additionally, the memory value comprises an intermediate result of a processor, a simple or complex operation of a switching unit, a calculating unit and / or an arithmetic-logic unit.Consequently, the storage value may include an input value, an intermediate result, and / or a result of an arithmetic and / or logic operation. The storage value may have a length of one or more bits. For example, the length of the storage value is 2, 4, 8, 16, 32, or 64 bits. In examples where the memory array is configured to store words of length 2 to the nth power, the length of the storage value may be the length of one word of the memory array.

[0018] The physical address can uniquely identify an associated memory segment of the memory array. The physical address can be a binary number, i.e., a sequence of multiple bits. Alternatively or additionally, the physical address can be in a language that is interpretable by machines. For example, the physical address can be a hexadecimal number that can be translated into a corresponding binary number. The physical address can be assigned by a processor unit to a respective memory value to be stored in the memory array. Furthermore, the processor unit can use the physical address to retrieve a memory value stored in the respective memory segment of the memory array.Alternatively or additionally, a memory management unit (MMU) may use the physical address, wherein the memory management unit may be configured to provide a processor unit or an executed program with a virtual memory that at least partially maps the memory arrangement.

[0019] The physical address can be delivered together with the memory value in a data packet. For example, it can be specified which (bit) positions of the data packet designate the physical address and which others designate the memory value. Alternatively or additionally, the physical address and the memory packet can be received via separate paths. For example, the memory value is transmitted via a data bus, while the physical address is transmitted via an address bus.

[0020] According to the method described herein, the physical address is modified to a modified physical address. In particular, the modified physical address may be from the same address space as the physical address before the modification. The modified physical address is assigned to a different memory segment of the memory array than the physical address before the modification. Accordingly, the physical address may be assigned to a first memory segment of the memory array, and the modified physical address may be assigned to a second memory segment of the memory array.

[0021] The modified physical address can be translated into corresponding control signals to select the corresponding memory segment. This process can also be referred to as decoding. For this purpose, a control unit can be provided which is configured to receive the modified physical address and generate corresponding control signals to select the memory segment to which the modified physical address is assigned. The control unit can comprise one or more of the decoding units. If the memory segments of the memory array are organized into rows and columns as mentioned above, a specific memory segment can be selected by controlling the associated row and column with a respective control signal. In examples in which the memory array is organized into banks, the associated bank can also be controlled to select the corresponding memory segment.

[0022] In some examples, the individual memory segments of the memory array are connected to a respective word line and a respective bit line. Depending on the design and structure of the memory array, the memory segments may each be connected to more than one word line and / or more than one bit line. An individual memory segment can be selected by applying respective predefined voltages to the word lines and bit lines.

[0023] The method described herein enables the second memory segment to be selected instead of the first memory segment by modifying the physical address to the modified physical address. In particular, the modified physical address can be from the same address space as the physical address. This can facilitate the translation of the physical address into the modified physical address. For example, the physical address can be modified to the modified physical address using suitable circuitry. Consequently, the modification of the physical address to the modified physical address can be performed purely on hardware. This can reduce the processing time for modifying the physical address to the modified physical address, for example, compared to a software-based solution.For example, the hardware-based modification of the physical address to the modified physical address can occur within a fraction of a clock cycle, while a comparable software-based modification can require several clock cycles. The time specified in clock cycles can refer to the clock cycle of a processor unit and / or a data transmission unit. This can create an opportunity to enable balanced use of the memory array by regularly changing the storage destinations for the data to be stored. This allows the utilization of the memory segments to be better distributed. In this way, the service life of the memory array can be positively influenced.

[0024] Further disclosed is a device comprising a memory array having a plurality of memory segments and a modification unit. The modification unit is configured to receive a physical address and to modify the physical address into a modified physical address. The physical address is assigned to a first memory segment of the memory array. The modified physical address is assigned to a second memory segment of the memory array. The device can be configured to perform the method described above.

[0025] The device described herein may further be part of an embedded system. Additionally or alternatively, the device may be part of a general-purpose computer system. The device, embedded system, or computer system described herein may be capable of performing the method described herein.

[0026] The memory arrangement of the device described herein may correspond to the memory arrangement described above with reference to the method. Accordingly, the memory segments may each be configured to store and provide a memory value. As described above, a respective physical address may be assigned to each memory segment.

[0027] According to one example, the physical address can be modified to the modified physical address before the corresponding memory segments are selected. This can, in particular, eliminate the process of accessing the corresponding memory segments. Furthermore, the modification of the physical address to the modified physical address can be performed independently of a memory management unit, if present.

[0028] According to one example, the physical address comprises a group of address segments, a subset of which can be modified to obtain the modified physical address. Accordingly, the physical address can be divided into the address segments. The address segments can comprise a row, a column, and, if present, a bank, which can define a single memory segment. For example, the group of address segments comprises a first address segment that identifies the row of the memory segment, a second address segment that identifies the column of the memory segment, and a third segment that identifies the bank of the memory segment. The physical address can comprise one or more further address segments. The order of the address segments within the physical address can depend on a particular embodiment.When modifying the physical address, one or more address segments from the group of address segments can be modified. The subgroup of address segments can refer to the address segments modified in this process.

[0029] One or more address segments of the physical address can be extracted from the physical address and processed separately. This process can be referred to as segmentation or parsing. For example, the physical address can be segmented into three address segments, each for the row, column, and bank of the corresponding memory segment. For example, the address segments can be individually fed to a respective decoder to access the corresponding memory segment.

[0030] The physical address can first be segmented into multiple address segments, and then one or more of the address segments can be modified individually. For example, the physical address is segmented into three address segments for the row, column, and bank of the corresponding memory segment, and then one, two, or all of these three address segments are modified.

[0031] In further examples, the physical address may first be modified to the modified physical address and then segmented into individual address segments. For example, the physical address includes three address segments for the row, column, and bank of the associated memory segment, and the physical address may be modified by modifying one, two, or all of the three address segments before being segmented into individual address segments.

[0032] According to one example, a modifier value may be provided. The physical address and the modifier value may each be a binary number with N digits, where N is a positive integer. The modified physical address is obtained from an exclusive-OR operation of the physical address and the modifier value. For example, the exclusive-OR operation, which may also be called an XOR operation for short, receives two binary values ​​or two logical values ​​as input values. The exclusive-OR operation may be configured to output a zero or a logical false if the input values ​​are equivalent. Furthermore, the exclusive-OR operation may be configured to output a one or a logical true if the input values ​​are different.

[0033] Accordingly, the device described herein may comprise an XOR gate configured to receive the physical address and the modification value and to output the modified physical address as a result of an XOR operation of the physical address and the modification value. In particular, an XOR gate may be provided for each individual bit to be modified. Thus, the device may comprise multiple XOR gates configured to modify the bits of the physical address.

[0034] According to another example, the modified physical address can be obtained from an XNOR operation of the physical address and the modification value. In other examples, one or more of the N locations of the physical address and the modification value can be XORed, while the remaining N locations can be XNORed. Furthermore, one or more of the N locations of the physical address and the modification value can be connected to an inverter. In particular, an XNOR gate can be provided for each individual bit to be modified. Thus, the device can comprise a plurality of XNOR gates configured to modify the bits of the physical address. Furthermore, the device can comprise one or more XOR gates in combination with one or more XNOR gates.

[0035] According to one example, the modification value is generated using a random number generator. The random number generator can be configured to generate a random number or a sequence of random numbers. The random number generator can comprise a deterministic mechanism, a non-deterministic mechanism, or a combination thereof. For example, a random number or a sequence of random numbers can be generated according to a deterministic mechanism based on software. Additionally or alternatively, a random number or a sequence of random numbers can be generated according to a non-deterministic mechanism based on a physical process. In particular, the random number generator can help ensure that the generated modification value runs through all permutations for an N-digit binary number as evenly as possible.

[0036] According to one example, the modification value is determined using an integer counter. The integer counter increments or decrements at predefined operating points, for example, upon re-sorting, starting, or restarting the memory array or the memory segments. In particular, the integer counter can store and provide a count value, i.e., a counter reading. Furthermore, the integer counter can increment or decrement by one or more upon re-sorting, starting, or restarting the memory array. For example, the counter reading of the integer counter is an N-digit binary number that is incremented or decremented by a value, for example, one, upon an event that triggers re-sorting, starting, or restarting. In particular, with an incrementing integer counter, the integer counter can be reset to a minimum value after a maximum value is reached.The minimum value can be 0. The maximum value of the counter reading can be, for example, the number of possible physical addresses or the number of bit positions of the physical address. In other examples, the maximum value of the counter reading can be smaller than the number of possible physical addresses or smaller than the number of bit positions of the physical address. With a decrementing integer counter, the integer counter can be reset to a maximum value after a minimum value is reached.

[0037] The terms integer counter and counter are used interchangeably herein unless a difference is explicitly noted. The modification value may be identical to the counter reading of the counter. In some examples, the counter reading of the counter may be modified according to the design of the method or device in order to obtain the modification value. For example, the maximum value for the counter reading may exceed both the number of possible physical addresses and the number of bit positions of the physical address. In such a case, a circuit may be provided which converts the counter reading into a value that is compatible with the addresses from the address space of the physical address. This converted value may correspond to the modification value.In further examples, the maximum value of the counter reading may be less than the number of possible physical addresses or less than the number of bit positions of the physical address.

[0038] When the memory array or memory segments are re-sorted, stored data can be moved to other memory locations. For example, the memory array can be re-sorted if the memory array has been inactive for longer than a defined period, such as 10 minutes, 30 minutes, one hour, or several hours. The memory array can be re-sorted using hardware and / or software for direct memory access (DMA). When the memory array or memory segments are put into operation, restarted, or operated again, the stored data can be deleted or can be deleted. When such an event is detected, the counter reading and the modification value can be changed.Consequently, upon reordering, starting, or restarting the memory array or memory segments, the manner in which the physical address is modified can be changed to the modified physical address. This allows balanced utilization of the memory array and memory segments to be achieved over an extended period of time.

[0039] Accordingly, the device described herein may comprise a counter for providing the modification value. Furthermore, such a counter may be configured to increment or decrement the modification value upon re-sorting, starting, or restarting the memory segments. The counter may detect an event that triggers re-sorting, starting, or restarting of the memory segments and, in response, change the modification value. The counter may comprise a volatile or non-volatile memory to store the counter reading. The counter may further comprise or be connected to its own power supply in order to maintain the counter reading even after the memory arrangement is switched off.

[0040] In some examples, the value of the integer counter is identical to the modifier value. In other examples, the modifier value can be uniquely determined from the counter value of the integer counter, for example, by overlaying it with another value. Additionally or alternatively, the modifier value can be obtained from a bitwise inversion at one, some, or all of the N digits of the counter value of the integer counter. The use of an integer counter can help ensure that the modifier value cycles through all permutations for an N-digit binary number as evenly as possible.

[0041] According to one example, the modified physical address is obtained from a shift and rotation of bit values ​​of the N-digit physical address by K positions toward a first or a last position, i.e., an Nth position, of the physical address. The number K can be greater than zero and not equal to N. Thus, the modified physical address can correspond to a periodic and bitwise shift of the physical address. This allows the modified physical address to traverse all possible permutations for the N-digit binary number in the address space of the physical address. Thus, the addresses in the address space of the physical address can be used as evenly as possible.

[0042] Such a shift of the bit values ​​of the physical address can be performed, for example, using a barrel shifter. Accordingly, the device described herein can comprise a barrel shifter. The barrel shifter can be configured to output the modified physical address from a shift and rotation of bit values ​​of the physical address by K positions toward a first or an Nth position of the physical address.

[0043] A barrel shifter can comprise a circuit which is configured to receive a bit sequence, i.e. a sequence of several bit values, at its input and to shift this by a definable number of bit positions and, if necessary, also to rotate it. The shift distance, i.e. the number of bit positions by which the bit sequence is to be shifted, can be predetermined by a control circuit. The control circuit can in particular comprise a counter. The circuit of the barrel shifter can in particular be designed such that the bit positions are cyclically connected to one another so that, depending on the direction of shift, the least significant bit position changes into the most significant bit position or vice versa. The barrel shifter can thus be configured to output a bit sequence shifted from the input bit sequence by one or more bit positions.

[0044] The barrel shifter may comprise a circuit with multiple multiplexers. For example, the barrel shifter may comprise N N-to-1 multiplexers. Alternatively or additionally, the barrel shifter may be decomposed into multiple steps. For example, the barrel shifter may comprise N 2 √ N-to-1 multiplexers, where N is a square number. In further examples, the barrel shifter may comprise N E d-to-1 multiplexers, where N = d E In other examples, the barrel shifter may comprise N E d-to-1 multiplexers and N G f-to-1 multiplexers, where N = d E · f G is.

[0045] Furthermore, the barrel shifter may include a decoder that converts the displacement distance into a corresponding electrical signal. For example, the barrel shifter may include a 1-of-N decoder that includes N outputs and activates one of these outputs according to the displacement distance. In further examples, the barrel shifter may include multiple decoders arranged in a cascade.

[0046] The design, operation, structure, and embodiments of the barrel shifter are known to those skilled in the art and are not explicitly described in detail herein. For example, "Implementing Barrel Shifters Using Multipliers" by Paul Gigliotti, from Xilinx Application Note, Aug. 17, 2004, XAPP195 (v1.1), on page 1 with reference to Fig. 1 shows several embodiments of an 8-bit barrel shifter using an 8-out-of-1 multiplexer. On page 3 and in Fig. 3 of the aforementioned document describes examples of a 32-bit barrel shifter with thirty-two 32-to-1 multiplexers.

[0047] In "Design Alternatives for Barrel Shifters" by Michael J. Schulte et al., from Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, Dec. 6, 2002, doi: 10.1117 / 12.452034, the authors describe some concrete examples for the implementation of a barrel shifter. In sections 2 and 3.1, with reference to Fig. 1 and Fig. 2, this document describes two 8-bit barrel shifters that receive eight input bits and shift them in three steps to the right ( Fig. 1) or to the left ( Fig. 2) postpone. Furthermore, with reference to Fig. 3 and Fig. 4 describes two further examples of an 8-bit barrel shifter, which are designed as right shifters and are also able to shift the input bits to the left, see section 3.1. In section 3.2 and with reference to Fig. 5 and Fig. 6 describes another example that is capable of shifting or rotating the input bits logically or arithmetically, to the left or to the right.

[0048] According to one example, the number K is determined using an integer counter that increments or decrements upon re-sorting of the memory array. The integer counter may be configured as described above. The device described herein may comprise a corresponding counter, for example, as described above.

[0049] According to one example, it is determined whether the binary number of the physical address contains N zeros or N ones. If it is determined that the binary number of the physical address contains N zeros or N ones, it is determined whether the number N is even or odd. If N is an even number, the binary number of the physical address is inverted at N / 2 positions. If N is an odd number, the binary number of the physical address is inverted at (N-1) / 2 positions. Thus, modification instructions can be provided for situations in which a shift of the incoming physical address would be unsuccessful because it consists of only zeros or only ones. This can prevent a possible reduction in the effectiveness of the method or device described herein.

[0050] According to another example, it is determined whether the count of the integer counter is even or odd. If it is determined that the binary number of the physical address N contains zero or N one, and the count of the integer counter is odd, the binary number of the physical address is inverted. Alternatively, the binary number of the physical address can be inverted if the count of the integer counter is even. Thus, exception conditions can be provided for situations in which a shift of the physical address would be unsuccessful. This can prevent a possible reduction in the effectiveness of the method or device described herein.

[0051] According to one example, the second memory segment is selected by decoding the modified physical address. After one of the memory segments is selected according to the method and apparatus described herein, a memory value may further be stored in the selected memory segment. Furthermore, a stored memory value may be read analogously to the above description. Accordingly, an operation for reading the memory value may be linked to the physical address, which is converted into the modified physical address prior to reading, thereby enabling access to the memory value.

[0052] According to one example, the device described herein further comprises a processor unit and a data transmission unit. The processor unit can be configured to transmit a memory value to the memory device or to retrieve a stored memory value from the memory device. The physical address can be associated with the memory value. The data transmission unit can connect the processor unit to the memory device and be configured to transmit the physical address between the processor unit and the memory device. The data transmission unit can comprise a bus. The bus can comprise a data bus for transmitting a memory value and an address bus for transmitting the physical address. The data bus and the address bus can be provided as separate buses.

[0053] Hereinafter, some examples of the present disclosure will be explained in detail with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic flow diagram of a method according to an example. Fig. 2A to 2C are schematic diagrams of an apparatus according to an example. Fig. 3 is a schematic diagram of a modification unit according to an example. Fig. 4 is a schematic diagram of an apparatus according to an example. Fig. 5 is a schematic diagram of an apparatus according to an example. Fig. 6A and Fig. 6B are schematic diagrams of a modification unit and a physical address table and the associated modified physical addresses according to an example. Fig. 7A and Fig. 7B are schematic diagrams of a modification unit and a shift and rotation of a physical address to modified physical addresses according to an example. Fig. 8 is a schematic diagram of an apparatus according to an example. DETAILED DESCRIPTION OF THE DRAWINGS

[0054] Fig. 1 shows a schematic flow diagram of a method 100 for operating a memory device. The method 100 may be applicable to one of the examples of a memory device described herein. In particular, the method 100 may be applicable to the device 200 described below.

[0055] At 102, a physical address associated with a first memory segment of a memory array is received. At 104, the physical address is modified to a modified physical address associated with a second memory segment of the memory array. At 106, the second memory segment may be selected.

[0056] Fig. 2A to 2C show a device 200 for operating a memory array 210. The device 200 may be part of a general-purpose computer system, part of an embedded system, or a combination thereof. In particular, the device 200 may be configured to receive a memory value for storage or buffering in the memory array 210.

[0057] The memory array 210 may be configured as described above. In particular, the memory array 210 may comprise an array of multiple SRAMs, DRAMs, or other RAMs or flash memories. The memory array 210 comprises multiple memory segments, including the first memory segment S1 and the second memory segment S2. Fig. In Figures 2A to 2C, the memory segments S1 and S2 are provided with reference symbols. Other memory segments are not provided with reference symbols to increase clarity.

[0058] The memory segments S1, S2 can have a uniform storage capacity, for example 8 bits, 16 bits, 32 bits, 64 bits or 2 n Bits, where n is a natural number greater than 6. The memory segments of the memory array can be organized in rows and columns as well as in banks.

[0059] Fig. 2A shows a schematic partial view of the device 200 and illustrates the assignment of a first physical address A1 and a second physical address A2 to a first memory segment S1 and a second memory segment S2, respectively, of the memory array 210. Accordingly, the first physical address A1 uniquely identifies the associated first memory segment S1. Likewise, the second physical address A2 uniquely identifies the associated second memory segment S2.

[0060] As in Fig. 2B and Fig. As shown in Figure 2C, the memory array 210 includes a modification unit 220 configured to receive the first physical address A1 and modify it to the second physical address A2. The second physical address A2 corresponds to the modified physical address as described above.

[0061] In Fig. 2C further shows a control unit 230 configured to receive the modified physical address A2 and to generate control signals corresponding to the modified physical address A2 in order to select the associated second memory segment S2. The control unit 230 may comprise one or more of the decoding units (not explicitly shown in Fig. 2A to 2C).

[0062] Consequently, a memory segment is selected that differs from the memory segment identified initially. A rule according to which the received physical address A1 is modified can vary over time. In this way, the local utilization of the memory segments of the memory array 210 can be distributed as evenly as possible across the entire memory array 210. This can positively influence the service life of the memory array 210.

[0063] Fig. 3 schematically shows the physical address A1 being modified by the modification unit 220 to the modified physical address A2. The physical address A1 comprises four address segments A11 to A14. For example, the address segments A11 to A13 each designate a row, a column, and a bank of the first memory segment S1. The address segment A14 can be empty, contain further information for determining the associated memory segment, and / or contain other information. Each of the address segments A11 to A14 can be one bit or multiple bits long. The address segments A11 to A14 can have different lengths.

[0064] The modification unit 220 may modify one, part, or all four of the four address segments A11 to A14 into a respective address segment A21 to A24. In particular, the address segments A21 to A24 of the modified physical address A2 each have the same length as the address segments A11 to A14 of the incoming physical address A1. In some examples, the physical address A1 is segmented into the address segments A11 to A14, which are individually modified by the modification unit 220. Accordingly, the modification unit 220 may include multiple modification units for a respective address segment. In further examples, the modification unit 220 receives the physical address A1 contiguously and modifies it. For example, the modification unit 220 may selectively modify the address segments A11 to A14 from the contiguous physical address A1 without segmenting it.

[0065] Fig. 4 schematically shows examples of the memory arrangement 210, the modification unit 220 and the control unit 230. The memory arrangement 210 comprises a plurality of memory segments 214, which comprises the first memory segment S1 and the second memory segment S2 which are shown in Fig. 4 are not explicitly shown. The memory segments 214 are organized into banks 212, rows, and columns. The memory segments 214 each comprise one or more SRAM cells. The memory segments 214 are associated with a respective physical address. In Fig. 4, not all memory segments are provided with a corresponding reference numeral 214 in order to increase clarity.

[0066] The control unit 230 includes a row decoder 232, a column decoder 234, a bank decoder 236. In examples in which the memory array 210 includes multiple memory banks 212, as in Fig. 4, the decoding unit 230 may include a plurality of column decoders 234 and a plurality of read / write circuits 238, the number of which corresponds to the number of memory banks 212. Furthermore, the control unit 230 may include a read / write circuit 238 for reading or writing a memory value.

[0067] Decoders 232 to 236 are configured to select a single memory segment 214. For example, row decoder 232 can select a single row by applying a predetermined voltage to that row. Similarly, column decoder 234 and bank decoder 236 can select a single column and a single bank by varying a voltage applied thereto. Concurrently, read / write circuit 238 can be operated to write a memory value to or read a memory value from the selected memory segment.

[0068] The physical address A1 comprises address segments A11 to A13, which determine the row, column, and bank of the first memory segment S1. In the example of Fig. 4, the modification unit 220 can be configured to receive the physical address A1 contiguously, i.e., without the physical address A1 being segmented into the address segments A11 to A13. After modifying the physical address A1 to the modified physical address A2, the modified physical address A2 is segmented into its address segments A21 to A23 and fed to the respective decoder 232 to 236. The address segments A21 to A23 of the modified physical address determine the row, column, and bank of the associated memory segment S2 in the memory array 210. The decoders 232 to 236 receive the respective address segment A21 to A23 and select the associated second memory segment S2.

[0069] Fig. Figure 5 schematically shows another example of the modification unit 220. In the example of Fig. 5, the modification unit 220 comprises a row modification unit 222, a column modification unit 224, and a bank modification unit 226. The row modification unit 222 is configured to receive the first address segment A11 of the physical address A1 and modify it into a modified first address segment A21. Accordingly, the column modification unit 224 and the bank modification unit 226 are configured to receive the respective address segments A12 and A13 and modify them into a respective modified address segment A22 and A23.

[0070] Following the example of Fig. 5, the modification unit 220 includes three modification units 222-226 for the row, column, and bank. In further examples, the modification unit 220 may include only one or two of the modification units 222-226 to selectively modify the row, column, and / or bank of the physical address A1.

[0071] Fig. 6A and Fig. 6B schematically show an example of a modification unit 220. The modification unit according to the example of Fig. 6A and Fig. 6B includes a counter 240 and a plurality of XOR gates 242. The number of XOR gates 242 may correspond to the number of bit positions of the incoming physical address A1 to be modified. Alternatively or additionally, the number of XOR gates 242 may correspond to the number of bit positions of an address segment of the incoming physical address A1 to be modified. Fig. 6A and Fig. 6B, the incoming physical address A1 is exemplified as a four-digit binary number, and the modification unit 220 includes four XOR gates 242.

[0072] Counter 240 includes circuitry for storing and incrementing a counter value as an N-digit binary number. In another example, counter 240 may include circuitry for storing and decrementing a counter value as an N-digit binary number. The length N of the binary number of the counter value corresponds to the number of bit positions of the incoming physical address A1. The counter value of counter 240 increments or decrements upon re-sorting, starting, or restarting of memory array 210. Furthermore, counter 240 may be configured as described above.

[0073] Each XOR gate 242 is configured to modify a respective bit of the physical address A1. The XOR gates 242 receive at their input a respective bit of the physical address A1, as illustrated by lines 228, and a respective bit of the counter reading of the counter 240. In the example of Fig. 6A, the counter reading of counter 232 corresponds to a modification value M, see Fig. 6B. In another example not explicitly shown, the counter value may be modified to a modification value M and supplied to the XOR gates 242. In an example not shown, one or more of the XOR gates 242 may each be replaced by an XNOR gate.

[0074] Fig. Figure 6B shows a tabular representation of modified physical addresses A2 resulting from an exclusive-OR operation of a four-digit binary physical address A1 with a four-digit binary counter value as modification value M. In the example of Fig. 6A and Fig. 6B is the physical address A1 from a linear address space in which a total of sixteen addresses are linearly numbered from 0 to 15, which are represented as four-digit binary numbers (0000 to 1111) in the first column of the table. In this example, the modifier value M can take a value between 0 and 15, which are represented as four-digit binary numbers (0000 to 1111) in the top row of the table of Fig. 6B. The values ​​from the second row and from the second column of the table represent the modified physical address A2 as the result of an exclusive-OR operation of the incoming physical address A1 with the respective modification value M.

[0075] In the second column of the table of Fig. 6B shows the values ​​from an exclusive-OR operation of the physical address A1 with a modification value M of (0000). Consequently, the modified physical address A2 in this case is identical to the incoming physical address A1. The last column of the table shows the values ​​from an exclusive-OR operation of the physical address A1 with a modification value M of (1111), which corresponds to an inversion of the physical address A1. By exclusively ORing the counter reading of counter 240 with the physical address A1, the physical address A1 is uniquely modified into a modified physical address A2.

[0076] As described above, the modification value M, together with the count of counter 240, may be changed upon a re-sort, start, or restart of the memory array 210 or device 200. The maximum value for the count of counter 240 may correspond to the number of possible physical addresses. For example, the modification value M is incremented by one starting from 0000 upon a re-sort, start, or restart of the memory array 210. If the modification value M has the maximum value 1111 (or 15 in decimal notation), the modification value M may be reset to 0000 (or 0 in decimal notation) upon a re-sort, start, or restart of the memory array 210. In further examples, the modification value M may be incremented by more than one. The value shift of the modification value M may be varied over time or as desired.In further examples, the modification value M may be decremented by one or more upon re-sorting, starting, or restarting the memory array 210 and reset to 1111 if the modification value M is 0000 and is to be further decremented.

[0077] In addition to or as an alternative to the counter 240, a random number generator configured to generate a four-digit random binary number may be provided. Accordingly, the modification value M may correspond to the four-digit random binary number from the random number generator. In further examples, the modification value M may be obtained by combining the counter reading of the counter 240 with the four-digit random binary number from the random number generator.

[0078] Fig. 7A shows another example of a modification unit 220. The modification unit 220 includes a counter 240 and a barrel shifter 244. The counter 240 and / or the barrel shifter 244 may be configured as described above. The barrel shifter 244 may receive the physical address A1 bit-by-bit, as illustrated by lines 228. In Fig. 7A and Fig. 7B, the physical address A1 and the modified physical address A2 are each shown as four-digit binary numbers. Alternatively or additionally, the barrel shifter 244 may modify a portion or an address segment of the incoming physical address A1.

[0079] Barrel shifter 236 may further receive the counter reading of counter 240. Barrel shifter 244 may determine from the counter reading of counter 240 a number of bit positions by which the bits of physical address A1 are to be shifted. The result of the shift may correspond to the modified physical address A2.

[0080] Additionally or alternatively, a random number generator can be provided that generates a four-digit random binary number. Accordingly, the counter reading can be replaced by or overlaid with the four-digit random binary number of the random number generator. The random number generator can be configured as described above.

[0081] The modification unit 220 may further comprise a multiplexer 246 and a detection circuit 248. The detection circuit 248 may be configured to detect whether the binary number of the physical address A1 consists of only ones or only zeros. In the example of Fig. 7A, the detection circuit 248 includes an AND gate and a NOR gate, each receiving the bits of the physical address A, an OR gate that combines the output values ​​of these gates, and another AND gate that combines the output value of the OR gate with the count of the counter 240 and feeds an output value to the multiplexer 246. Accordingly, the multiplexer 246 inverts the bits of the physical address A1 if all bits of the physical address are zeros or ones and if the count of the counter 240 is an odd number. In further examples, the binary number of the physical address A1 may be inverted in two of the four bit positions.

[0082] Fig. Figure 7B shows the incoming physical address A1 and two examples of modified addresses A2 and A2*, which are created using the modification unit 220 of the Fig. 7A can be obtained. The modified addresses A2 and A2* are obtained by shifting the four-digit binary number of the physical address A1 in a respective direction M1, M2.

[0083] The binary number of the physical address A1 comprises four bit positions with the bit values ​​a1 to a4, where a1 is the least significant bit and a4 is the most significant bit of the physical address A1. In the example in Fig. 7B, the incoming physical address A1 is a four-digit binary number 1000, which corresponds to a value of 8 in decimal notation.

[0084] In one example, the binary number of physical address A1 is shifted one bit position to the right, as illustrated by arrow M1. This can correspond to shifting the bit values ​​a1 through a4 of physical address A1 by one bit position toward the least significant bit position, as represented by the corresponding modified physical address A2. In doing so, bit a1 is rotated left from the least significant bit position of physical address A1 and placed in the most significant bit position. The remaining bit values ​​a2 through a4 are shifted one bit to the right, resulting in a value of 0100 (4 in decimal notation).

[0085] In another example, the binary number of physical address A1 is shifted one bit position to the left, as illustrated by arrow M2. This can correspond to a shift of the bit values ​​a1 to a4 of physical address A1 by one bit position towards the most significant bit position, as represented by the corresponding modified physical address A2*. In this process, bit a4 is rotated right from the most significant bit position of physical address A1 and placed in the least significant bit position. The remaining bit values ​​a1 to a3 are shifted one bit to the left, resulting in a value of 0001 (1 in decimal notation).

[0086] The examples of Fig. 7B show a shift and rotation of the bit values ​​of the physical address A1 by one bit position each. In further examples, which are shown in Fig. 7B are not shown, the modification unit 220 may be configured to shift the bit values ​​of the physical address by more than one bit position to the left or to the right.

[0087] Fig.8 shows a device 200 according to a further example. Accordingly, the device 200 may comprise a processor unit 250 and a data transmission unit 252. The processor unit 250 may, in particular, be configured to transmit a memory value to the memory device 210 or to retrieve a memory value from the memory device 210. The data transmission unit 252 may connect the processor unit 210 to the memory device 210 and be configured to transmit the physical address A1 between the processor unit 250 and the memory device 210. The data transmission unit 252 may comprise a data bus for transmitting the memory value and an address bus for transmitting the physical address between the processor unit 250 and the memory arrangement 210. LIST OF REFERENCE SYMBOLS 100 procedures 102 - 106 Process steps 200 device 210 Memory arrangement 212 memory bank 214 memory cells 220 Modification Unit 222 Line modification unit 224 Column modification unit 226 bench modification unit 228 data line 230 decoding unit 232 line decoders 234 column decoders 236 bank decoders 238 Read / write circuit 240 counters 242 XOR gates 244 Barrel Shifter 246 multiplexers 248 detection circuit 250 processor unit 252 Data transmission unit A1 physical address A11 - A14 address segment A2, A2* modified physical address A21 - A24 address segment a1 - a4 bit value M modification value S1, S2 memory segment

Claims

[1] A method (100) for operating a memory device (210), the method (100) comprising: Receiving (102) a physical address (A1), wherein the physical address (A1) is associated with a first memory segment (S1) of a memory array (210); Modifying (104) the physical address (A1) to a modified physical address (A2), wherein the modified physical address (A2) is associated with a second memory segment (S2) of the memory array (210); Selecting (106) the second memory segment (S2); and Providing a modification value (M), where the physical address (A1) and the modification value (M) are each a binary number with N digits, where the modified physical address (A2) is obtained: - is obtained from an exclusive-OR operation of the physical address (A) and the modification value (M), and / or - from a shift and rotation of bit values ​​of the physical address (A1) by K positions towards a first or a last position of the physical address (A1), where N is a positive integer, and K is a positive integer greater than zero and not equal to N. [2] Method according to claim 1, wherein the physical address (A1) comprises a group of address segments (A11, A12, A13, A14), wherein the modified physical address (A2) is obtained from a modification of a subset of the address segments (A11, A12, A13, A14). [3] The method of claim 1, further comprising: Determining the modification value (M) by means of an integer counter (221) which increments or decrements upon re-sorting, starting and / or restarting of the memory arrangement (210); and / or Determining the modification value (M) using a random number generator. [4] The method of claim 1, further comprising: Determining K by means of an integer counter (221) which increments or decrements upon re-sorting, starting and / or restarting of the memory array (210); and / or Determine K using a random number generator. [5] The method of claim 1 or 4, further comprising: Determine whether the binary number of the physical address (A1) contains N zeros or N ones; if the binary number of the physical address (A1) contains N zeros or N ones, inverting the binary number of the physical address (A1) if the integer counter (221) is an odd number. [6] A method according to any one of the preceding claims, further comprising: Decoding the modified physical address (A2) to select (106) the second memory segment (S2). [7] Device (200) comprising: a memory arrangement (210) having a first memory segment (S1) and a second memory segment (S2); a modification unit (220) for receiving a physical address (A1), wherein the physical address (A1) is assigned to the first memory segment (S1), wherein the modification unit (220) is configured to modify the physical address (A1) to a modified physical address (A2), wherein the modified physical address (A2) is assigned to the second memory segment (S2), wherein the physical address (A1) is a binary number with N digits, wherein the device further comprises: - a counter (221) for providing a modification value (M), wherein the modification value (M) is a binary number with N digits; and - an XOR gate (234) for receiving the physical address (A1) and the modification value (M) and for outputting the modified physical address (A2) as a result of an XOR operation of the physical address (A1) and the modification value (M); and / or wherein the device (200) further comprises a barrel shifter (225) configured to output the modified physical address (A2) from a shift and rotation of bit values ​​of the physical address (A1) by K positions toward a first or a last position of the physical address (A1), where K is a positive integer greater than zero and not equal to N. [8] Device according to claim 7, wherein the physical address (A1) comprises a group of address segments (A11, A12, A13, A14), wherein the modification unit (220) is configured to modify a subset of the address segments (A11, A12, A13, A14) to obtain the modified physical address (A2). [9] Apparatus according to claim 7, wherein the counter (221) is arranged to increment or decrement the modification value (M) upon re-sorting, starting and / or restarting of the memory arrangement (210). [10] Apparatus according to any one of claims 7 to 9, further comprising: a control unit (230) for controlling the memory segments (S1, S2) [11] Apparatus according to any one of claims 7 to 10, further comprising: a processor unit (250) configured to transmit a memory value to the memory device (210) or to retrieve the memory value from the memory device (210), wherein the physical address (A1) is associated with the memory value; and a data transmission unit (252) connecting the processor unit (250) to the memory device (210) and configured to transmit the physical address (A1) between the processor unit (250) and the memory device (210).

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