Method for manufacturing a superjunction transistor device

Abstract

A process that exhibits: Creating active regions of several transistor cells (10) in an interior region (110) of a semiconductor body (100), wherein each transistor cell contains a drift region (11) of a first doping type and a compensation region (12) of a second doping type; and Creating a field stop region (30) of the first doping type or of the second doping type in an edge region (120) of the semiconductor body, the creation of the drift and compensation areas (11, 12) exhibits: Manufacturing multiple semiconductor layers (1401-140 n ) one on top of the other; in each of the multiple semiconductor layers (1401-140 n ) before the production of each of the next of the several semiconductor layers (1401-140 n): Creating several first trenches (150) and implanting dopant atoms of the first doping type and / or dopant atoms of the second doping type into sidewalls (151, 152) of the several first trenches (150), and where the establishment of the field stop area (30) exhibits: in each semiconductor layer of a selection of the several semiconductor layers (1401-140 n ) before the production of each of the next of the several semiconductor layers (1401-140 n ): Creating at least one second trench (160) and implanting dopant atoms of one of the first and second doping types into at least one surface (161-163) of the at least one second trench (160), where the selection of two or more of the several semiconductor layers (1401-140 n ), but less than all of the multiple semiconductor layers (1401-140 n ) includes.

Description

[0001] This disclosure generally relates to a method of manufacturing a superjunction transistor device, in particular a vertical superjunction transistor device.

[0002] A vertical superjunction transistor component contains a plurality of transistor cells. Each of the transistor cells contains a source region, a body region, a drift region, a compensation region, and a drain region in an interior region of the semiconductor body. The source region and the drain region of each cell are spaced apart from one another in a vertical direction of the semiconductor body, wherein the drain regions of the plurality of transistor cells can be formed by a contiguous semiconductor layer. A vertical superjunction transistor component can further contain a field stop region, which is arranged in an edge region of the semiconductor body and can form a closed loop around the interior region. The field stop region is of the same doping type as the drift regions, but is more highly doped.

[0003] Forming the drift and compensation regions of the plurality of transistor cells may include forming multiple semiconductor layers on top of each other, forming multiple trenches in each of these semiconductor layers, implanting dopant atoms into sidewalls of these trenches, and a thermal process that diffuses and activates the implanted dopant atoms.

[0004] DE 10 2016 115 759 A1 describes a method for manufacturing a superjunction transistor component. In this method, trenches are formed in an inner region and an edge region of a semiconductor body, which are filled with a semiconductor material that can be undoped or lightly doped. The semiconductor body also comprises p- and n-dopants with different diffusion characteristics, so that after filling the trenches, a diffusion process creates n-doped and p-doped semiconductor regions that form the drift regions and compensation regions of the component.

[0005] DE 10 2007 026 745 A1 describes a method for producing a superjunction transistor component. In this method, several semiconductor layers of a first doping type are formed one above the other. A trench is formed in each of these semiconductor layers before the formation of a subsequent semiconductor layer, into the sidewalls of which trenches dopant atoms of a second doping type are implanted. The trenches in a semiconductor layer are filled by the subsequently formed semiconductor layer.

[0006] The object underlying the invention is to produce a field stop region of a transistor component efficiently and at acceptable additional costs. This object is achieved by a method according to claim 1.

[0007] One example relates to a method for manufacturing a transistor device. The method includes: forming active regions of a plurality of transistor cells in an interior region of a semiconductor body, each transistor cell including a drift region of a first doping type and a compensation region of a second doping type; and forming a field stop region of one of the first doping type and the second doping type in an edge region of the semiconductor body. Forming the drift and compensation regions includes: forming a plurality of semiconductor layers one above the other; forming a plurality of first trenches and implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into sidewalls of the plurality of first trenches in each of the plurality of semiconductor layers prior to forming a respective next one of the plurality of semiconductor layers.Furthermore, forming the field stop region includes forming at least one second trench and implanting dopant atoms of one of the first and second doping types at least into a surface of the at least one second trench in each semiconductor layer of a selection of the plurality of semiconductor layers.

[0008] Examples are explained below with reference to the drawings. The drawings are intended to illustrate certain principles, so only those aspects necessary for understanding those principles are shown. The drawings are not to scale. Throughout the drawings, the same reference numerals indicate the same features. Fig. 1 schematically shows a vertical cross-sectional view of a vertical superjunction transistor device; Fig. Figure 2 shows schematically a horizontal cross-sectional view of a transistor device of the Fig. 1 type shown; Fig. 3 shows a vertical cross-sectional view of a plurality of semiconductor layers after forming first trenches in each of the semiconductor layers and implanting dopant atoms into the sidewalls of the first trenches, and after forming second trenches in a selection of the semiconductor layers and implanting dopant atoms into the sidewalls of the second trenches; The Fig. 4A to 4C show an example of a method for forming first trenches and implanting dopant atoms into sidewalls of the first trenches; The Fig. 5A to 5D show an example of a method for forming a second trench and implanting dopant atoms into surfaces of the second trench; The Fig. 6A and Fig. 6B show a plan view of a Fig. 5D shows a semiconductor layer during an implantation process; The Fig. 7A and Fig. 7B show a modification of the Fig. 5A to 5D; Fig. 8 shows the formation of a further semiconductor layer on a topmost one of the plurality of semiconductor layers; The Fig. 9 and Fig. 10 show optional implantation processes; The Fig. 11 and Fig. 12 show the arrangement of the Fig. 8 after a thermal process; Fig. 13 shows a modification of the Fig. 1 transistor component shown; Fig. 14 shows an example of a trench transistor cell; Fig. 15 shows a plan view of a second trench containing several trench sections; and The Fig. 16A and Fig. 16B show plan views of various corner sections of a second trench.

[0009] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for the purpose of illustration, show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with one another unless expressly stated otherwise.

[0010] Fig. 1 schematically shows a vertical cross-sectional view of an example of a superjunction transistor device. The transistor device includes a semiconductor body 100 having a first surface 101, a second surface 102 opposite the first surface 101, and an edge surface 103 extending from the first surface 101 to the second surface 102. The second surface 102 is spaced apart from the first surface 101 in a vertical direction z of the semiconductor body 100. The "vertical direction z" is a direction perpendicular to the first and second surfaces 101, 102. According to one example, the semiconductor body 100 includes a monocrystalline semiconductor material. Examples of the monocrystalline semiconductor material include, but are not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like.

[0011] The semiconductor body 100 includes an inner region 110 and an edge region 120. The edge region 120 is arranged between the edge surface 103 and the inner region 110 and encloses the inner region 110 in a horizontal plane. The "horizontal plane" is a plane parallel to the first and second surfaces 101, 102.

[0012] Referring to Fig. 1, the transistor component contains a plurality of transistor cells 10, wherein each of these transistor cells 10 contains active component regions in the interior region 110 of the semiconductor body 100. The active component regions of each transistor cell 10 contain a drift region 11 of the first doping type and a compensation region 12 of a second doping type complementary to the first doping type. Furthermore, the active component regions of each transistor cell 10 contain a body region 13 of the second doping type and a source region 14 of the first doping type, wherein the body region 13 is arranged between the source region 14 and the drift region 11 such that the source region 14 is separated from the drift region 11 by the body region 13. According to one example, the compensation region 12 borders the body region 13. Furthermore, the active device regions of each transistor cell 10 contain a drain region 17.The drain region 17 may be adjacent to either the drift region 11 or the compensation region 12. Optionally, as shown in . Fig. 1 by dashed lines, a buffer region of the first doping type may be arranged between the drain region 17 and each of the drift region 11 and the compensation region 12.

[0013] According to one example, the semiconductor body 100 comprises monocrystalline silicon and the individual active device regions are implemented such that a respective doping concentration lies in a range as set out below: Drift region 11: between 1E15 cm -3 and 1E17 cm -3 ; Compensation area 12: between 1E15 cm -3 and 1E17 cm -3 ; Body area 13: between 1E17 cm -3 and 1E18 cm -3 ; Source area 14: between 1E18 cm -3 and 1E21 cm -3 ; Drain area 17: between 1E18 cm -3 and 1E21 cm -3; optional buffer area 18: between 1E15 cm -3 and 1E17 cm -3 .

[0014] Referring to Fig. 1, the drain regions 17 of each of the plurality of transistor cells 10 can be formed by a contiguous semiconductor region, which is referred to below as the drain region of the transistor device. Furthermore, the drift regions 11 of two adjacent transistor cells 10 can be formed by a contiguous semiconductor region of the first doping type, and the compensation regions 12 of two (other) transistor cells 10 can be formed by a contiguous semiconductor region of the second doping type.

[0015] Referring to Fig. 1, each transistor cell further includes a gate electrode 15, which is arranged adjacent to the body region 13 and which is dielectrically insulated from the body region 13 by a gate dielectric 16. The gate electrode 15 serves to control a conductive channel in the body region 13 between the source region 14 and the drift region 11. The gate electrodes 15 of the individual transistor cells are connected to a gate node G. The gate node G as well as the connections between the gate electrodes 15 and the gate node G are shown in Fig. 1 is shown only schematically. Furthermore, the source and body regions 14, 15 of the individual transistor cells 10 are connected to a source electrode 21, which is electrically insulated from the gate electrodes 15 by an insulation layer 22. The source electrode 21 is connected to a source node S or forms a source node S of the transistor component. Furthermore, the drain region 17 is connected to a drain node D of the transistor component.

[0016] The transistor component can be an n-type transistor component or a p-type transistor component. In an n-type transistor component, the source regions 14 and the drift regions 11 are n-type semiconductor regions, and the body regions 13 and the compensation regions 12 are p-type semiconductor regions. In a p-type transistor component, the doping types of the individual active component regions are complementary to the doping type of the corresponding component regions in an n-type transistor component. Furthermore, the transistor component can be implemented as a MOSFET (metal oxide semiconductor field-effect transistor). In this case, the drain region 17 has the same doping type as the source region 14. According to another example, the transistor component is implemented as an IGBT (Insulated Gate Bipolar Transistor).In this case, the drain region 17 has a doping type complementary to the doping type of the source region 14.

[0017] The transistor component can be operated in an on or off state. In the on state, the gate electrodes 15 are controlled by applying a suitable voltage (gate-source voltage) between the gate node G and the source node S such that a conductive channel is present in the body region 13 between the source region 14 and the drift region 11, so that a current can flow between the drain node D and the source node S when a voltage (drain-source voltage) greater than zero is applied between these circuit nodes D, S. In the off state, the gate electrodes 15 are controlled such that the conductive channel in the body regions 13 between the source regions 14 and the drift regions 11 is interrupted.In the off state, when a voltage is applied between the drain node D and the source node S, which reverse-biases the pn junctions between the drift regions 11 on the one hand and the body regions 13 and compensation regions 12 on the other hand, space charge regions (depletion regions) propagate in the semiconductor body 100. In this operating state, current flow through the transistor device is prevented.

[0018] Referring to Fig. 1, the transistor device further includes a field stop region 30 in the edge region 120. According to one example, the field stop region 30 is of the first doping type and extends from the first surface 101 to the drain region 17 or the optional buffer region 18. The drain region 17, the optional buffer region 18, and the field stop region 30 form a well of the first doping type around the other active device regions (the drift regions 11, the compensation region 12, the body regions 13, the source regions 14) located in the interior region 110 of the semiconductor body 100. The electrical potential of this well substantially corresponds to a drain potential, which is the electrical potential of the drain node D.

[0019] According to another example, the field stop region 30 of the second doping type is complementary to the first doping type. For illustrative purposes only, it is assumed below that the field stop region 30 is of the first doping type, so that dopant atoms of the first doping type are introduced into the semiconductor body 100 to form the field stop region. However, in each of these examples, dopant atoms introduced into the semiconductor body 100 to form a field stop region 30 of the first doping type can be replaced by dopant atoms of the second doping type to form a field stop region 30 of the second doping type. A field stop region of the second doping type can be implemented, for example, in a source-down transistor in which the drain electrode and the gate electrode are arranged on the same side of the semiconductor body.

[0020] Fig. 1 shows a section of the transistor device in a vertical sectional plane defined by the vertical direction z of the semiconductor body 100 and a first lateral (horizontal) direction x. Fig. 2 schematically shows a horizontal cross-sectional view of the semiconductor body 100 in a horizontal sectional plane AA, which is defined by the first lateral direction x and the second lateral direction y. Referring to Fig. 2, the field stop region 30 may form a closed loop (a ring) around the active component regions in the interior region 110 in the horizontal plane, wherein in Fig. 2 the drift and compensation areas 11, 12 are shown schematically.

[0021] With reference to the Fig. 2, the drift and compensation regions 11, 12 can be elongated in the second horizontal direction y, which is perpendicular to the first horizontal direction x. According to one example, "elongated" means that a length of these drift and compensation regions is significantly greater than a width. According to one example, a ratio l1 / w1 between the length l1 and the width w1 is at least 10, at least 100, or at least 1000. In the case of the Fig. In the example shown in Figure 2, the length l1 of the drift and compensation regions 11, 12 is the dimension in the second horizontal direction y and the width w1 is the dimension in the first horizontal direction x.

[0022] Fig. Figure 3 shows an example of a method for producing the drift and compensation regions 11, 12 and the field stop region 30 after several process steps. More specifically, Fig. 1 the semiconductor body 100 after several process steps of producing the drift and compensation regions 11, 12. Referring to Fig. 3, the method includes producing a plurality of semiconductor layers 1401-140 n one above the other, forming a plurality of first trenches 150 in each of the plurality of semiconductor layers 1401-140 n , and implanting dopant atoms into opposite first and second sidewalls 151, 152 of each of the plurality of trenches 150. First implanted regions 41 are formed by implanting the dopant atoms into the first sidewalls 151, and second implanted regions 42 are formed by implanting the dopant atoms into the second sidewalls 152. According to one example, forming each of the plurality of semiconductor layers 1401-140 n an epitaxial growth process so that each of the semiconductor layers 1401-140 na monocrystalline epitaxial layer. Referring to Fig. 3, a first or lowermost 1401 of the plurality of semiconductor layers 1401-140 n grown on a carrier 130. According to one example, the carrier 130 is a monocrystalline semiconductor substrate that forms the drain region 17 of the finished semiconductor device. Optionally, an epitaxial layer forming the buffer region 18 is grown on the substrate 130 before the bottom semiconductor layer 1401 is grown.

[0023] The semiconductor body 100 with the substrate 130, the optional epitaxial layer forming the buffer region 18 grown on the substrate 130, and the plurality of semiconductor layers 1401-140 n represent a monocrystalline semiconductor layer. Therefore, there are no visible boundaries between the individual semiconductor layers 1401-140 in the semiconductor body 100 n However, in Fig. 3 For illustrative purposes, boundaries between the individual semiconductor layers 1401-140 n shown by dashed lines.

[0024] Furthermore, the production of the plurality of semiconductor layers 1401-140 n one above the other and on the substrate 130 at wafer level. This means that several semiconductor bodies 100 can be processed simultaneously by being part of a wafer on which several semiconductor layers are epitaxially grown, wherein the wafer is divided at a later stage of the manufacturing process to produce several semiconductor bodies 100. Edge surfaces 103 of the individual semiconductor bodies 100 are produced by dividing the wafer into the individual semiconductor bodies 100. Thus, in the Fig. 3, the edge surface 103 has not necessarily been formed yet. In this case, reference numeral 103 indicates where the edge surface of the semiconductor body 100 will be located after the plurality of semiconductor bodies 100 have been formed from a wafer.

[0025] In the Fig. In the example shown in Figure 3, the lowest semiconductor layer 1401 was formed on the substrate 130 and the other semiconductor layers 1402-140 n were each deposited on a different semiconductor layer 1401-140 n That is, a second semiconductor layer 1402 was formed on the first semiconductor layer 1401, a third semiconductor layer 1403 was formed on the second semiconductor layer 1402, and so on. Hereinafter, 140 denotes i any one of the plurality of semiconductor layers 1401-140 n . The production of a semiconductor layer 140 ion another semiconductor layer 140 i-1 includes the production of the semiconductor layer 140 i on a surface 141 i-1 the previous semiconductor layer and in the trenches of the previous semiconductor layer 140 i-1 .

[0026] Fig. 3 shows the semiconductor body 100 after forming each of the plurality of semiconductor layers 1401-140 n , so that the first trenches 150 in the semiconductor layers 1401-140 n-1 were filled, while the first trenches 150 in a top 140 n the semiconductor layers 1401-140 n are still open. For illustrative purposes only, the plurality of semiconductor layers 1401-140 n n = 4 semiconductor layers. However, this is only an example. According to one example, the number n of semiconductor layers is selected between 2 and 20, in particular between 3 and 15. According to one example, the semiconductor layers 1401-140n manufactured so that their respective thickness d 140 between 2 micrometers and 12 micrometers. The thickness d 140 a layer 140 i is the dimension of the semiconductor layer 140 i outside the trenches 150 and in the vertical direction z.

[0027] According to one example, the first trenches 150 are elongated trenches. That is, a length which is a dimension of these trenches 150 in a direction perpendicular to the Fig. 3 is much larger than a width, which is a dimension of these trenches 150 in the first horizontal direction x. According to one example, a ratio between the length and the width is at least 10, at least 100, or at least 1000. According to one example, as shown in Fig. 3, the first trenches 150 formed in the individual semiconductor layers 1401-140 nare formed, aligned in the vertical direction z. Furthermore, the first trenches 150 are formed at positions of the semiconductor layers 1401-140 n which form the interior region 110 of the finished semiconductor body 100. The first and second implanted regions 41, 42 form the basis for the drift and compensation regions 11, 12. This will be explained in more detail below.

[0028] In the Fig. 3, the first trenches 150 were formed such that each of these trenches 150 is formed within only one semiconductor layer. This means that each of the trenches 150 formed in a semiconductor layer 140 i manufactured trenches 150 does not extend into a semiconductor layer 140 i-1 which is directly in front of the semiconductor layer 140 i However, this is only an example. According to another example (not shown), the first trenches 150 formed in a semiconductor layer 140i are manufactured into the previously produced semiconductor layer 140 i-1 extend.

[0029] Referring to Fig. 3, the method further includes forming at least one second trench 160 in each of a selection of the plurality of semiconductor layers 1401-140 n and implanting dopant atoms of the first doping type into at least one surface of the second trench 160. In the Fig. In the example illustrated in Figure 3, dopant atoms of the first doping type were implanted into a first sidewall 161 of each second trench 160 to form first implanted regions 51, a second sidewall 162 to form second implanted regions 52, and a bottom 163 of each second trench 160 to form third implanted regions 53. However, this only represents an example. According to another example, only one or only two of these regions 51, 52, 53 are formed. According to one example, the selection of semiconductor layers includes every m-th of the plurality of semiconductor layers 1401-140 n, where m is an integer greater than one (m>1). According to one example, m is selected from 2 to 5. In this example, m-1 semiconductor layers are located between two selected semiconductor layers. However, it is also possible for the number of semiconductor layers to vary between two adjacent selected semiconductor layers. In general, the selection of semiconductor layers comprises two or more of the plurality of semiconductor layers 1401-140 n , but less than each of the plurality of semiconductor layers 1401-140 n .

[0030] For the purpose of illustration only, the Fig. 3, m = 2. That is, the selection of semiconductor layers contains every second semiconductor layer of the plurality of semiconductor layers 1401-140 n . In the Fig. 3, in which the plurality of semiconductor layers 1401-140 nn = 4 semiconductor layers, every second semiconductor layer contains the second semiconductor layer 1402 and the n-th semiconductor layer 140 n However, the selection of semiconductor layers does not necessarily include semiconductor layers formed in a regular sequence from the plurality of semiconductor layers 1401-140 n selected. That is, m can vary. For example, if m varies between 2 and 3, the selected semiconductor layers can include a second semiconductor layer 1402, a fifth semiconductor layer 1405, a seventh semiconductor layer 1407, and so on.

[0031] The Fig. 4A to 4C show an example of a method for forming the first trenches 150 and the first and second implanted regions 41, 42 in a semiconductor layer 140 i . Each of the Fig. 4A to 4C shows a vertical cross-sectional view of the semiconductor layer 140 iduring various process steps, whereby only the semiconductor layer 140 i shown in these figures and only the section in which the first trenches 150 are made is shown.

[0032] Referring to Fig. 4A, the method includes forming a patterned etch mask 210 on the surface 141 i the semiconductor layer 140 i . The etching mask 210 is structured to form openings at the positions of the surface 141 i where the trenches 150 are to be formed. The patterning of the etch mask 210 may include a lithography process. Referring to Fig. 4A, the method further includes etching the first trenches 150 using the etch mask 210. Etching the first trenches 150 includes, for example, an anisotropic etching process. According to one example, the first trenches 150 are formed such that an aspect ratio, which is a ratio between a depth d2 and a width w2 of the first trenches 150, is between 1:1 and 5:1, in particular between 1:1 and 3:1. The "depth d2" of the first trenches 150 is the dimension in the vertical direction z, and the "width w2" of the first trenches 150 is their dimension in the first lateral direction x. A distance w3 between adjacent trenches is between 0.8 times the width w2 and 1.2 times the width w2 of the first trenches 150. The distance between adjacent trenches can also be referred to as the width of mesa regions formed between the first trenches 150.

[0033] Referring to Fig. 4B, the method further includes forming the first implanted regions 41 along the first sidewalls 151 by implanting dopant atoms into the first sidewalls 151. The implantation process is an oblique implantation process in which an implantation direction is inclined relative to the vertical direction z, such that dopant atoms are implanted into the first sidewalls 151, but not into the bottoms 153 of the first trenches 150. According to one example, the implantation process includes forming a protective layer that prevents dopant atoms from implanting into the surface 141. i implanted on the surface 141 i . According to one example, the etching mask 210 is used as a protective layer. Optionally, the etching mask 210 is removed and deposited on the first surface 141 i a protective layer is created.

[0034] Referring to Fig. 4C, the method further includes a second implantation process in which dopant atoms are implanted into the second sidewalls 152 to form the second implanted regions 42. The second implantation process is also a slant implantation process, such that the dopant atoms are implanted into the sidewalls 152, but not into the bottoms 153 of the trenches 150. The first and second implanted regions 41, 42 form the basis for at least one of the drift regions 11 and the compensation regions 12. More specifically, in a thermal process, which will be explained further below, dopant atoms contained in the first and second implanted regions diffuse and are activated to form the drift regions 11 and / or the compensation regions 12.

[0035] The first and second implantation processes can be implemented in different ways, i.e. the first and second implanted regions 41, 42 can be produced in different ways: (a) The semiconductor layer 140 i can be manufactured such that it has a basic doping of one of the first and second doping types, and only dopant atoms of the other of the first and second doping types are implanted in the first and second implantation processes into each of the first and second sidewalls 151, 152. In this case, the implanted dopant atoms in the first and second implanted regions 41, 42 form - after the thermal process - the drift regions 11 or the compensation regions 12, and the respective other of the drift regions 11 and the compensation regions are formed by those portions of the semiconductor layer 140 i , in which the basic doping of the first doping type is retained. (b) The semiconductor layer 140 i can be manufactured to be intrinsic (i.e. a basic doping concentration of less than 1E14 cm -3in the first implantation process, dopants of only one of the first and second doping types are implanted into the first sidewalls 151, and in the second implantation process, dopant atoms of only the other of the first and second doping types are implanted into the second sidewalls 152, so that the first and second implanted regions 41, 42 each contain dopant atoms of only one of the first and second doping types. For example, if the first implanted regions 41 contain only dopants of the first doping type and the second implanted regions 42 contain only dopants of the second doping type, the first implanted regions 41 form the basis of the drift regions 11, and the second implanted regions 42 form the basis of the compensation regions 12. (c) According to another example, in each of the first and second implantation processes, both dopants of the first doping type and dopants of the second doping type are implanted into each of the first and second sidewalls 151, 152, such that each of the first and second implanted regions 41, 42 contains both dopants of the first doping type and dopants of the second doping type. In this case, each of the first and second implanted regions 41, 42 forms the basis for a drift region and a compensation region.Implanting dopant atoms of both the first doping type and the second doping type into respective ones of the first and second sidewalls 151, 152 may include two implantation sub-processes: a first implantation sub-process in which dopants of the first doping type are implanted, and a second implantation sub-process in which dopants of the second doping type are implanted. According to another example, implanting both dopants of the first doping type and dopants of the second doping type into the respective ones of the first and second sidewalls 151, 152 may include only one implantation process in which dopants of the first doping type and dopants of the second doping type are implanted simultaneously, for example, by implanting molecules containing both dopants of the first doping type and dopants of the second doping type.According to one example, when dopant atoms of both types are implanted into a sidewall, the dopant atoms can be chosen to have different diffusion coefficients. According to one example, the dopant atoms of the first type are arsenic (As) or antimony (Sb) atoms, and the atoms of the second type are boron (B) atoms. Boron, being a p-type dopant, diffuses faster than As or Sb, which are n-type dopants.

[0036] The Fig. 5A to 5D illustrate an example of a method for forming a second trench 160 in a selected semiconductor layer 140 j and for forming at least one implanted region along at least one sidewall of the second trench 160. Each of the Fig. 5A to 5D shows a vertical cross-sectional view of the selected semiconductor layer 140 j and a semiconductor layer 140 j-1, on the top side of which the selected semiconductor layer 140 j was manufactured. Fig. 5A shows the arrangement with the two semiconductor layers after the production of the selected semiconductor layer 140 j on top of the previous semiconductor layer 140 j-1 . The selected semiconductor layer 140 j is produced after the first and second implanted regions 41, 42 in the previous semiconductor layer 140 j-1 The production of these first and second implanted regions 41, 42 may include any of the Fig. 4A to 4C.

[0037] Referring to Fig. 5B, the method further includes forming the first trenches 150 and the second trench 160 in the selected semiconductor layer 140 jThe formation of the first trenches 150 and the second trench 160 may include an etching process using the same etching mask 210, wherein the etching mask 210 includes openings in the inner region 110 for forming the first trenches 150 and an opening in the edge region 120 for forming the second trench 160. The etching process is, for example, an anisotropic etching process. In this type of process, a depth of the trenches depends on a duration of the etching process and a width of the respective opening in the etching mask. In principle, the longer the etching process, the deeper the trench, and the wider the opening, the deeper the trench obtained for a given duration of the etching process.

[0038] According to one example, the duration of the etching process is selected such that the first trenches 150 reach the desired depth d2. The depth of the second trench 160 depends on a width w4 of the second trench 160 relative to the width of the first trenches 150. According to one example, the opening in the etching mask 210 for forming the second trench 160 is wider than the openings for forming the first trenches 150, such that a width w4 of the second trench 160 is greater than a width w2 of the first trenches 150 (w4>w2). In this case, as in Fig. 5B, the second trench 160 is deeper than the first trenches 150, that is, d4>d2, where d2 is the depth of the first trenches 150 and d4 is the depth of the second trench 160.

[0039] According to one example, the second trench 160 is formed such that it extends into the previous semiconductor layer 140 j-1 extends.

[0040] However, implementing the second trench 160 wider and thus deeper than the first trenches 150 is only an example. According to another example (not shown), the second trench 160 is manufactured such that its width w4 is substantially equal to the width w2 (w4=w2) of the first trenches 150 and its depth d4 is substantially equal to the depth d2 (d4=d2) of the first trenches 150.

[0041] Referring to Fig. 5C, the method further includes forming the first and second implanted regions 41, 42 by implanting dopant atoms into the sidewalls of the first trenches 150. These first and second implanted regions 41, 42 may be formed according to any method described with reference to the Fig. 4A to 4C. According to one example, the same method is used to form the first and second implanted regions 41, 42 in each of the semiconductor layers 1401-140 nThis means that in each of the semiconductor layers 1401-140 n each of the first and second implanted regions 41, 42 contains dopants of only one doping type or in each of the semiconductor layers 1401-140 n each of the first and second implanted regions 41, 42 contains both dopants of the first doping type and dopants of the second doping type.

[0042] According to one example, the second trench 160 is not covered during the implantation processes that create the first and second implanted regions 41, 42. In this case, corresponding implanted regions are formed along those first and second sidewalls 161, 162 of the second trench 160 that run parallel to the first and second sidewalls 151, 152 of the first trenches 150. Such implanted regions are Fig. 5C using dashed lines. According to another example, a protective layer 230 (in Fig. 5C by dashed lines), such as a resist layer, covers the second trench 160 during the implantation processes so that dopant atoms are not implanted into the sidewalls 161, 162 of the second trench 160.

[0043] Referring to Fig. 5D, the method further includes implanting dopant atoms of the first doping type into at least one of the surfaces of the second trench 160. The “surfaces” of the second trench 160 include the first sidewall 161, the second sidewall 162, and the bottom 163. Dopant atoms of the first doping type may be implanted into one of these surfaces 161-163, two of these surfaces 161-163, or, as in Fig. 5D, are implanted into each of these surfaces 161-163. The implantation of dopant atoms into a surface leads to the formation of an implanted region adjacent to the respective surface. Fig. 5D, a first implanted region 51 was formed along the first sidewall 161, a second implanted region 52 was formed along the second sidewall 162, and a third implanted region 53 was formed along the bottom 163 of the second trench 160.

[0044] The formation of the first implanted region 51 may include a first oblique implantation process. In this implantation process, the inclination angle may be selected such that dopant atoms are implanted only into the first sidewall 161. Alternatively, the inclination angle is selected such that dopant atoms are implanted into the first sidewall 161 and the bottom 163, so that the first implanted region 51 and the third implanted region 53 (at least portions thereof) are formed by the same implantation process. The formation of the second implanted region 52 may include a second oblique implantation process. In this implantation process, the inclination angle may be selected such that dopant atoms are implanted only into the second sidewall 162.Alternatively, the tilt angle is selected such that dopant atoms are implanted into the second sidewall 162 and the bottom 163, such that the second implanted region 52 and the third implanted region 53 (at least portions thereof) are formed by the same implantation process. Alternatively, or in addition to forming the third implanted region 53 by one of the tilt implantation processes, forming the third implanted region may include a non-tilted implantation process, i.e., an implantation process in which dopant atoms are implanted into the bottom 163 using an implantation angle of substantially 0°.

[0045] Therefore, the formation of the three implanted regions 51, 52, 53 may include two oblique implantation processes, a first implantation process in which the inclination angle is selected such that dopants are implanted into the first sidewall 1611 and the bottom 163, and a second implantation process in which the inclination angle is selected such that dopant atoms are implanted into the second sidewall 162 and the bottom 163. An example of the implantation vector in the first implantation process is shown in Fig. 5D labeled V1 and an example of the implantation vector in the second implantation process is shown in Fig. 5D denoted by V2. Another example of a process for producing the three implanted regions is described with reference to Fig. 6A and Fig. 6B explained below.

[0046] In the at least one implantation process for producing the at least one implanted region, on the surface 141 j A protective layer 220 is formed, so that the protective layer 220 prevents dopant atoms from being implanted into the first trenches 150. The protective layer 220 is, for example, a resist layer. The protective layer 220 can be formed after removal of the etching mask 210 (as shown) or with the etching mask 210 still present (not shown). In the first case, the protective layer 210 is formed such that it covers the first trenches 150 and portions of the surface 141. j the semiconductor layer 140 j between the first trenches 150. Furthermore, the protective layer covers a portion of the surface 141 j in the edge region 120 between the first trenches 150 and the second trench 160. The protective layer 210 can cover the surface 141 jcompletely cover and leave only the surfaces 161-163 of the second trench 160 uncovered. According to another example (as illustrated), surface portions adjacent to the sidewalls 161, 162 of the second trench 160 are not covered by the protective layer 210. A dimension of these surface portions in directions perpendicular to the trench sidewalls 161, 162 is between 10 nanometers (nm) and several micrometers (µm), in particular between 300 nanometers and 1 micrometer.

[0047] Referring to the above, the second trench 160 may be formed to form a closed loop around the inner region 110 in the horizontal plane. According to one example, forming the implanted regions 51, 52, 53 along the sidewalls 161, 162 and the bottom of this type of second trench 160 includes four oblique implantation processes. This is shown in Fig. 6 shown.

[0048] The Fig. 6A and Fig. 6B show a top view of the selected semiconductor layer 140 j during the implantation process. More specifically, Fig. 6A a top side of the selected semiconductor layer 140 j and Fig. 6B shows a top view of one of four corner sections of the selected semiconductor layer 140 j. The second trench 160, which forms a closed loop around the interior region 110, includes four trench sections, a first trench section 1601 substantially parallel to a first section 1031 of the edge surface 103, a second trench section 1602 substantially parallel to a second section 1032 of the edge surface 103 and substantially vertical to the first trench section 1601, a third trench section 1603 substantially parallel to a third section of the edge surface 103 and substantially parallel to the first trench section 1601, and a fourth trench section 1604 substantially parallel to a fourth section of the edge surface 103 and substantially parallel to the second trench section 1602.Each of the four trench sections 1601, 1602, 1603, 1604 has a first side wall 1611, 1612, 1613, 1614 and a second side wall 1621, 1622, 1621, 1622, wherein the first side walls 1611, 1612, 1613, 1614 are also referred to below as inner side walls and the second side walls 1621, 1622, 1621, 1622 are also referred to as outer side walls.

[0049] The implantation angles in the four oblique implantation processes can be selected such that, in each of these implantation processes, dopant atoms are implanted into an inner sidewall and an outer sidewall of a pair of parallel trench sections and into the bottoms of a second pair of trench sections that differ from the first pair. For example, (1) in a first implantation process, dopant atoms of the first doping type are implanted into the inner sidewall 1611 of the first trench section 1601, the outer sidewall of the third trench section 1603, and the bottoms of the second trench section 1602 and the fourth trench section 1604; (2) in a second implantation process, dopant atoms of the first doping type are implanted into the outer sidewall 1611 of the first trench section 1601, the inner sidewall of the third trench section 1603, and the bottoms of the second trench section 1602 and the fourth trench section 1604; (3) in a third implantation process, dopant atoms of the first doping type are implanted into the inner sidewall 1612 of the second trench section 1602, the outer sidewall of the fourth trench section 1604, and the bottoms of the first trench section 1601 and the third trench section 1603; and (4) In a fourth implantation process, dopant atoms of the first doping type are implanted into the outer sidewall 1612 of the second trench section 1602, the inner sidewall of the fourth trench section 1604 and the bottoms of the first trench section 1601 and the third trench section 1603.

[0050] Horizontal components V1 x , V2 x , V3 x , V4 x of the implantation vectors in these four oblique implantation processes are in Fig. 6B. An implantation process with four tilted implantation processes, in which the implantation angles are chosen so that dopant atoms are implanted into the inner and outer sidewalls of a loop-shaped trench, is sometimes referred to as a quad-mode implantation process.

[0051] Optionally, the tilt angle in the first implantation process is such that dopant atoms are also implanted into the bottoms of the first trench section 1601 and the third trench section 1603 and / or the tilt angle in the second implantation process is such that dopant atoms are also implanted into the bottoms of the first trench section 1601 and the third trench section 1603 and / or the tilt angle in the third implantation process is such that dopant atoms are also implanted into the bottoms of the second trench section 1602 and the fourth trench section 1604 and / or the tilt angle in the fourth implantation process is such that dopant atoms are also implanted into the bottoms of the second trench section 1602 and the fourth trench section 1604.

[0052] The implantation dose in the individual implantation processes depends on the tilt angle(s), the number of implantation processes in each selected semiconductor layer 140 jand the number of selected semiconductor layers in which a second trench 160 is formed. As explained in more detail below, the field stop region 30 is formed by diffusing the dopants contained in the implanted regions 51, 52, 53. In principle, the total number of dopant atoms introduced into the implanted regions 51, 52, 53 should be high enough to result in a field stop region with a desired effective horizontal dopant dose. The "effective horizontal dopant dose" in the field stop region 30 is the integral of the effective doping concentration in a horizontal direction. More specifically, the field stop region 30 has four sections, each of which runs substantially parallel to a sidewall section 1031-1034.The effective doping dose of a section of the field-stop region is the integral of the effective doping concentration in a horizontal direction perpendicular to the sidewall section running parallel to the respective section of the field-stop region. According to one example, the implantation doses are such that the effective horizontal doping dose is higher than 2E12 cm-2. -2 is.

[0053] In the Fig. In the example shown in Figures 5A to 5D, the first and second implanted regions 41, 42 in the selected semiconductor layer 140 j before the second trench 160 was made. However, this is only an example. According to another example, Fig. 7A and Fig. In the example illustrated in Figure 7B, the dopant atoms are implanted into the surfaces 161-163 of the second trench 160 along the sidewalls 151, 152 of the first trenches 150 prior to forming the first and second implanted regions 41, 42. In this example, the protective layer 210 may be formed on the etch mask 210, wherein the etch mask 210 acts as a protective layer during the process of forming the first and second implanted regions 41, 42 and prevents dopant atoms from penetrating the surface 141. j be implanted.

[0054] Fig. 8 shows the arrangement with the multiple semiconductor layers 1401-140 n after a further process step. This process step involves the production of a further semiconductor layer 170 on the uppermost semiconductor layer 140 n . This further semiconductor layer 170 fills the first trenches 150 and the second trench 160 in the uppermost semiconductor layer 140 n. The formation of this further semiconductor layer 170 may involve an epitaxial growth process.

[0055] Optionally, as in Fig. 9, an implantation mask 230 is formed on a surface 171 of the further semiconductor layer 170, and dopant atoms of the first doping type are implanted into the further semiconductor layer 170 using the implantation mask 230. During this implantation process, a further implanted region 54 containing dopant atoms of the first doping type is formed in the edge region 120.

[0056] In addition or alternatively to the Fig. 9, the process includes reference to Fig. 10 further comprises forming at least one third implanted region 43 above the first implanted regions 41 and at least one fourth implanted region 44 above the second implanted regions 42 in the further semiconductor layer 170 using at least one further implantation mask 240. The third implanted regions 43 are of the same type as the first implanted regions 41. That is, the third implanted regions 43 contain either dopants of only one of the first and second doping types or dopants of both doping types, and the fourth implanted regions 44 contain either dopants of only one of the first and second doping types or dopants of both doping types. According to one example, the first and second implanted regions 41, 42 each contain dopants of the first doping type and of the second doping type.In this example, the third and fourth implanted regions are formed such that each of the third and fourth implanted regions 43, 44 contains both dopant atoms of the first doping type and dopant atoms of the second doping type. Third and fourth implanted regions of this type may be formed using only one implantation mask 240 (illustrated in FIG. Fig. 10) having openings at positions above the first and second implanted regions 41, 42.

[0057] The method further includes a thermal process in which the dopants in the first and second implanted regions 41, 42, the dopant atoms in the optional third and fourth implanted regions 43, 44, the dopant atoms in the at least one implanted region 51-53 adjacent to each second trench 160, and the dopant atoms in the optional implanted region 54 are activated and diffused to produce the drift regions 11 and the compensation regions 12 in the inner region 110 and the field stop region 30 in the edge region 120. According to one example, a temperature in the thermal process is between 1000°C and 1200°C, and the duration of the thermal process is between 20 minutes and 10 hours. Optionally, the thermal process takes place in an oxidizing or wet oxidizing atmosphere. Fig. 11 shows a vertical cross-sectional view of the semiconductor body 100 after the thermal process.

[0058] Fig. 11 shows an example in which the first and second implanted regions 41, 42 contain dopant atoms of both the first doping type and the second doping type, and Fig. 12 includes an example in which the first implanted regions 41 contain dopant atoms of only one of the first and second doping types and the second implanted regions 42 contain dopants of only the other of the first and second doping types.

[0059] Referring to the above, the first trenches 150 may be formed such that they are aligned in the vertical direction, such that the first implanted regions 41 are formed substantially one above the other and the second implanted regions 42 are formed substantially one above the other. The resulting drift and compensation regions 11, 12 are elongated regions in the vertical direction z of the semiconductor body 100. The second trenches 160 in the selected semiconductor layers may, as shown in the Fig. 8 to 10, be aligned in the vertical direction or they can be aligned as shown in Fig. 3, be offset from one another in the lateral direction. In any case, the second trenches 160 are positioned relative to one another such that, during the thermal process, the dopant atoms in the at least one implanted region diffuse along the second trenches, thus forming a continuous field stop region 30. By forming a second trench 160 only in selected ones of the semiconductor layers, the field stop region 30 can be produced at an acceptable cost.

[0060] Referring to the above, at least one implanted region 51, 52, 53 is formed adjacent to at least one surface of each of the semiconductor layers 140 selected. j formed second trenches, so that after the plurality of semiconductor layers 1401-140 nmanufactured, two or more implanted regions spaced apart in the vertical direction z are present. An example of implanted regions 51-53 spaced apart in the vertical direction is shown in Fig. 3. According to one example, the duration of the thermal process is adapted to a vertical spacing of these implanted regions and a diffusion rate of the implanted dopant atoms, so that a continuous field stop region 30 is produced.

[0061] According to one example, dopant atoms implanted into the second trenches 160 to create at least one implanted region adjacent to each second trench 160 are selected to diffuse faster than dopant atoms of the same doping type implanted into the first trenches 150. According to one example, the first-type dopant atoms implanted into the first trenches 150 are arsenic (As) atoms, the field-stop region 30 is a first-doping-type region, and the dopant atoms implanted into the second trenches 160 are phosphorus (P) atoms. Each of As and P is an n-type dopant in silicon, with P diffusing faster than As.

[0062] According to another example, dopant atoms implanted into the second trenches 160 to create at least one implanted region adjacent to each second trench 160 and dopant atoms implanted into the first trenches 150 have similar diffusion rates. Therefore, arsenic may be implanted into the first trenches 150 to create the drift regions and into the second trenches 160 to create the field stop region. According to another example, boron is implanted into the first trenches 150 to create the compensation regions 12 and into the second trenches 160 to create the field stop region.

[0063] Based on a structure according to one of the Fig. 11 and Fig. 12, the transistor device is completed by forming the body regions 13 and the source regions 14 in the further semiconductor layer 170, by forming the gate electrode 15 and the gate dielectric 16, and by forming the source electrode 21. Methods for forming these device features are generally known, so no further explanation is required in this regard.

[0064] Fig. 13 shows a modification of the Fig. 1. In this example, a plurality of doped regions 61 of the first doping type and a plurality of doped regions 62 of the second doping type are included in the edge region 120 between the field stop region 30 and the inner region 110. The first regions 61 can be formed by the same process steps as the drift regions 11 in the inner region 110, and the second regions 62 can be formed by the same process steps as the compensation regions 12 in the inner region 110. However, the first and second regions 61, 62 located in the edge region 120 do not adjoin any body regions 13 of transistor cells.

[0065] In the Fig. 1 and Fig. 13, the transistor cells include a planar gate electrode 14 arranged on the surface 101 of the semiconductor body 100. However, this is only an example. According to another embodiment shown in Fig. 14, the transistor cells can equally well be realized with trench gate electrodes 15. It is pointed out that Fig. 14 shows only those portions of several transistor cells 10 that contain the gate electrodes 15.

[0066] In the examples explained above, the second trench 160 forms in each selected semiconductor layer 140 j a closed loop around the interior area 110. However, this is only an example. According to another, in Fig. 15, the second trench 160 contains a plurality of trench sections (trench segments) 164, which are formed by mesa regions 142 of the semiconductor layer 140 jare spaced apart from each other. The mesa regions 142 are regions of the semiconductor layer 140 j , which separate two trench sections and extend to the surface 141 j the semiconductor layer 140 j The trench sections 164 and the mesa regions 142 form a trench-mesa region structure that forms a closed loop around the interior region 110.

[0067] A distance d164 between two adjacent trench sections 164, that is, a width of the mesa regions 142, is such that in the thermal process, the dopant atoms implanted in surfaces of the trench sections 164 can diffuse in lateral directions, so that a continuous field stop region 30 forming a closed loop around the inner region 110 is produced.

[0068] Furthermore, in the examples explained above, the second trench 160 has a substantially right angle in each of the corners of the respective semiconductor layer 140 j However, this is only one example. According to other Fig. 16A and Fig. 16B, the second trench 160 includes two or more stepped portions in one or more of the corners.

[0069] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure.

[0070] Example 1. A method includes: forming active regions of a plurality of transistor cells in an interior region of a semiconductor body, each transistor cell containing a drift region of a first doping type and a compensation region of a second doping type; and forming a field stop region of one of the first doping type and the second doping type in an edge region of the semiconductor body, wherein forming the drift and compensation regions includes: forming a plurality of semiconductor layers one above the other;in each of the plurality of semiconductor layers, prior to forming a respective next one of the plurality of semiconductor layers: forming a plurality of first trenches and implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into sidewalls of the plurality of first trenches, and wherein forming the field stop region includes: in each semiconductor layer of a selection from the plurality of semiconductor layers: forming at least one second trench and implanting dopant atoms of one of the first and second doping types at least into a surface of the at least one second trench;

[0071] Example 2. The method of Example 1, wherein the dopant atoms implanted into at least one surface of the at least one second trench are selected to diffuse faster than the at least one of dopant atoms of the first doping type and dopant atoms of the second doping type implanted into at least one of the first and second sidewalls of the first trenches.

[0072] Example 3. The method of example 1 or 2, wherein implanting dopant atoms into at least a surface of the at least one second trench includes implanting dopant atoms into a bottom of the at least one second trench.

[0073] Example 4. The method according to any one of the preceding examples, wherein in each of the selections of the plurality of semiconductor layers, implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into sidewalls of the plurality of first trenches simultaneously includes implanting the at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into sidewalls of the at least one second trench, wherein implanting dopant atoms of one of the first and second doping types at least into a surface of the at least one second trench in addition to implanting the at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into sidewalls of the at least one second trench.

[0074] Example 5. The method according to any one of examples 1 to 4, wherein the field stop region is of the first doping type.

[0075] Example 6. The method according to any one of examples 1 to 4, wherein the field stop region is of the second doping type.

[0076] Example 7. The method of any preceding example, wherein the selection of the plurality of semiconductor layers includes every m-th of the plurality of semiconductor layers, where m is an integer greater than 1.

[0077] Example 8. The method according to any one of the preceding examples, wherein in at least one semiconductor layer of the selection, forming the plurality of first trenches includes forming the plurality of first trenches together with the at least one second trench.

[0078] Example 9. The method of example 8, the method further comprising: forming a protective layer over the first trenches prior to implanting the dopant atoms of the first doping type into at least one surface of the at least one second trench.

[0079] Example 10. The method according to any one of the preceding examples, wherein forming the plurality of semiconductor layers includes forming a lowermost one of the plurality of semiconductor layers on a carrier.

[0080] Example 11. The method of any preceding example, wherein forming the plurality of transistor cells further comprises: forming at least one further semiconductor layer on a topmost one of the plurality of semiconductor layers; and forming body regions and source regions of the transistor cells in the at least one further semiconductor layer.

[0081] Example 12. The method of any preceding example, wherein implanting dopant atoms into the at least one surface of the second trench includes implanting dopant atoms of the first doping type into opposite sidewalls of the second trench and into a bottom of the second trench.

[0082] Example 13. The method of Example 12, wherein the second trench forms a closed loop around the interior region.

[0083] Example 14. The method of example 12, wherein the second trench includes a plurality of trench sections separated by mesa regions, wherein an arrangement including the trench sections and the mesa regions forms a closed loop around the interior region.

[0084] Example 15. The method of example 13 or 14, wherein implanting the dopant atoms into at least one surface of the second trench includes four oblique implantation processes.

[0085] Example 16. The method of any one of Examples 1 to 15, wherein implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into the sidewalls of the plurality of first trenches includes: implanting dopant atoms of only the first doping type into first sidewalls; and implanting dopant atoms of only the second doping type into second sidewalls opposite the first sidewalls.

[0086] Example 17. The method of any one of Examples 1 to 15, wherein implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into the sidewalls of the plurality of first trenches includes: implanting dopant atoms of both the first doping type and the second doping type into each of the first sidewalls and second sidewalls opposite the first sidewalls.

[0087] Example 18. A process according to any one of the preceding examples, further comprising a thermal process at a temperature between 1000°C and 1200°C.

Claims

[1] Method comprising: Producing active regions of a plurality of transistor cells (10) in an inner region (110) of a semiconductor body (100), each transistor cell containing a drift region (11) of a first doping type and a compensation region (12) of a second doping type; and Producing a field stop region (30) of the first doping type or of the second doping type in an edge region (120) of the semiconductor body, wherein the production of the drift and compensation regions (11, 12) comprises: Manufacturing multiple semiconductor layers (1401-140 n ) on top of each other; in each of the several semiconductor layers (1401-140 n ) before producing each of the next semiconductor layers (1401-140 n): Producing a plurality of first trenches (150) and implanting dopant atoms of the first doping type and / or dopant atoms of the second doping type into sidewalls (151, 152) of the plurality of first trenches (150), and wherein the production of the field stop region (30) comprises: in each semiconductor layer of a selection of the plurality of semiconductor layers (1401-140 n ) before producing each of the next semiconductor layers (1401-140 n ): Producing at least one second trench (160) and implanting dopant atoms of one of the first and second doping types at least into a surface (161-163) of the at least one second trench (160), wherein the selection of two or more of the plurality of semiconductor layers (1401-140 n ), but less than all of the multiple semiconductor layers (1401-140 n ) includes. [2] The method of claim 1, wherein the dopant atoms implanted into the at least one surface (161-163) of the at least one second trench (160) are selected to diffuse faster than the dopant atoms of the first doping type and / or the dopant atoms of the second doping type implanted into at least one of the first and second sidewalls (151, 152) of the first trenches (150). [3] The method of claim 1 or 2, wherein implanting dopant atoms into at least a surface (161-163) of the at least one second trench (160) comprises implanting dopant atoms into a bottom (163) of the at least one second trench (160). [4] Method according to one of the preceding claims, wherein in each of the selection of the plurality of semiconductor layers (1401-140 n) the implantation of dopant atoms of the first doping type and / or dopant atoms of the second doping type into the side walls (151, 152) of the plurality of first trenches (150) simultaneously comprises the implantation of the dopant atoms of the first doping type and / or the dopant atoms of the second doping type into the side walls (161, 162) of the at least one second trench (160), wherein the implantation of dopant atoms of the first or second doping type takes place at least into a surface (161-163) of the at least one second trench (160) in addition to the implantation of the dopant atoms of the first doping type and / or the dopant atoms of the second doping type into sidewalls (161, 162) of the at least one second trench (160). [5] Method according to one of claims 1 to 4, wherein the field stop region (30) is of the first doping type. [6] Method according to one of claims 1 to 4, wherein the field stop region (30) is of the second doping type. [7] Method according to one of the preceding claims, wherein the selection from the plurality of semiconductor layers (1401-140 n ) every m-th of the plurality of semiconductor layers (1401-140 n ), where m is an integer greater than 1. [8] Method according to one of the preceding claims, wherein in at least one semiconductor layer (140 j ) the selection comprises producing the plurality of first trenches (150) producing the plurality of first trenches (150) together with the at least one second trench (160). [9] The method according to claim 8, wherein the method further comprises: Producing a protective layer (220) over the first trenches (150) before implanting the dopant atoms of the first doping type into at least one surface (161-163) of the at least one second trench (160). [10] Method according to one of the preceding claims, wherein the production of the plurality of semiconductor layers (1401-140 n ) producing a bottom layer (1401) of the plurality of semiconductor layers (1401-140 n ) on a carrier (130). [11] The method of any preceding claim, wherein fabricating the plurality of transistor cells further comprises: Producing at least one further semiconductor layer (170) on an uppermost (140 n ) of the multiple semiconductor layers (1401-140 n ); and Producing body regions (13) and source regions (14) of the transistor cells (10) in the at least one further semiconductor layer (170). [12] The method of any preceding claim, wherein implanting dopant atoms into the at least one surface of the second trench (160) comprises implanting dopant atoms of the first doping type into opposite sidewalls (161, 162) of the second trench (160) and into a bottom (163) of the second trench (160). [13] The method of claim 12, wherein the second trench (160) forms a closed loop around the interior region (110). [14] The method of claim 12, wherein the second trench (160) comprises a plurality of trench sections (164) separated by mesa regions (142), wherein an arrangement comprising the trench sections (164) and the mesa regions (142) forms a closed loop around the interior region (110). [15] The method of claim 13 or 14, wherein implanting the dopant atoms into the at least one surface of the second trench (160) comprises four oblique implantation processes. [16] The method according to any one of claims 1 to 15, wherein implanting dopant atoms of the first doping type and / or dopant atoms of the second doping type into the sidewalls (151, 152) of the plurality of first trenches (150) comprises: implanting dopant atoms of only the first doping type into first sidewalls (151); and Implanting dopant atoms of only the second doping type into second sidewalls (152) opposite the first sidewalls (151). [17] The method according to any one of claims 1 to 15, wherein implanting at least one of dopant atoms of the first doping type and dopant atoms of the second doping type into the sidewalls (151, 152) of the plurality of first trenches (150) comprises: Implanting dopant atoms of both the first doping type and the second doping type into the first sidewalls (151) and the second sidewalls (152) opposite the first sidewalls (151). [18] A method according to any one of the preceding claims, further comprising a thermal process at a temperature between 1000°C and 1200°C. [19] Method according to one of the preceding claims, in which the at least one second trench (160) is produced such that it extends through the respective semiconductor layer (1402, 140 n ) of the selection extends into the previously produced semiconductor layer (1401, 1403).

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