INTEGRATED CHIP AND MANUFACTURING PROCESS

Abstract

Integrated chip (100), comprising: a substrate (102); an insulating structure (104) in the substrate, comprising one or more dielectrics and having sidewalls that define an active region (106) in the substrate (102), wherein the active region (106) has a channel region (106b), a source region (106a) and a drain region (106c) separated from the source region (106a) by the channel region (106b) along a first direction (128), wherein the source region (106a) has a first width W SD_1 along a second direction (130) perpendicular to the first direction (128), the drain area (106c) has a second width W SD_2 along the second direction (130) and the canal area (106b) has a third width W CH along the second direction (130) and greater than the first latitude W SD_1 and the second width W SD_2 has; and a gate structure (110) extending over the channel region (106b), wherein the gate structure (110) comprises a first gate electrode region (114) with a first composition of one or more materials and a second gate electrode region (116) with a second composition of one or more materials that differs from the first composition of one or more materials, wherein the insulation structure (104) has surfaces defining one or more divots (108) recessed below a top surface of the insulation structure (104); where a difference between the first width W SD_1 and the third latitude W CH is greater than or equal to twice the width of one or more of the divots (108); and wherein the second gate electrode region (116) comprises two or more segments arranged in gaps in the first gate electrode region above the channel region (106b), separated by a middle section of the first gate electrode region and each set back along the second direction (130) from a boundary between the one or more divots (108) and the channel region (106b) by a non-zero distance (303), wherein the first gate electrode region (114) is located above the one or more divots (108) and wherein the second gate electrode region (116) is separated from the one or more divots (108) by the first gate electrode region (114) along the second direction (130).

Description

BACKGROUND

[0001] Modern integrated chips comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., a silicon substrate). To improve the functionality of integrated chips, the semiconductor industry has continuously miniaturized the dimensions of semiconductor devices to provide integrated chips with small, densely packed components. By forming integrated chips with small and densely packed components, the speed of the devices increases and energy consumption decreases.

[0002] From US patent 9,406,771 B1, a transistor device is known which has a channel area with a width increased compared to the source / drain areas and a polysilicon gate layer with two implantation areas with different doping.

[0003] Another transistor device with a wider channel area is known, for example, from US 2014 / 0 281 810 A1.

[0004] US 2010 / 0 044 801 A1 describes a transistor device with a gate structure having areas with different work functions.

[0005] From JP 2010-34468A, a transistor structure is known which has a gate structure with a work function control layer, wherein the work function control layer has a greater thickness over an active region of the transistor structure than over divot regions in an isolation structure adjacent to the active region.

[0006] B. El-Kareh, Silicon Devices and Process Integration, Springer (New York), 2009, and CY. Hu et al., J. Vac. Sci. Technol. B 28(2), Mar / Apr 2010, deal with the effects of divots in isolation regions on the threshold voltage of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention and other examples of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. Fig. Figure 1A shows a cross-sectional view of an integrated chip according to some embodiments of the present invention. Fig. Figure 1B shows a top view of the integrated chip in Fig. 1A. Fig. Figure 2 shows a diagram illustrating some embodiments of exemplary absolute threshold voltages that correspond to the transistor device of the Fig. 1A - 1B belong to this group. Fig. Figure 3A shows a top view of an integrated chip according to some embodiments of the present invention. The Fig. 3B - 3D show cross-sectional views of the integrated chip in Fig. 3A. The Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A and Fig. Figure 9A shows top views illustrating some alternative embodiments of integrated chips. The Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B and Fig. Figure 9B shows cross-sectional views illustrating some alternative embodiments of integrated chips. The Fig. 10A, Fig. 11A, Fig. 12A and Fig. Figure 13A shows a top view of an integrated chip at various stages of a method according to some embodiments of the present disclosure. The Fig. Figures 10B, 11B, 12B, 13B and 14-20 show a cross-sectional view of an integrated chip at various stages of a method according to some embodiments of the present disclosure. Fig. Figure 21 shows a flowchart of some embodiments of a method for forming an integrated chip. The Fig. 22A, Fig. 23A, Fig. 24A and Fig. Figure 25A shows a top view of an integrated chip at various stages of a method according to some embodiments of the present disclosure. The Fig. Figures 22B, 23B, 24B, 25B and 26-34 show a cross-sectional view of an integrated chip at various stages of a method according to some embodiments of the present disclosure. Fig. Figure 35 shows a flowchart of some embodiments of a method for forming an integrated chip. DETAILED DESCRIPTION

[0008] The present invention provides integrated chips or a method for forming an integrated chip according to the independent claims. Exemplary embodiments are given in the dependent claims.

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For instance, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0010] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly.

[0011] In integrated chips, active devices (e.g., MOSFETs (metal-oxide-semiconductor field-effect transistors), embedded memory devices, etc.) are generally arranged on a common semiconductor substrate (e.g., a silicon substrate). However, semiconductor materials can be electrically conductive, allowing leakage currents to flow between active devices located in close proximity on the semiconductor substrate. If such leakage currents are not adequately mitigated, crosstalk between adjacent devices can lead to the failure of the integrated chip.

[0012] To prevent leakage currents from flowing between adjacent devices, many modern integrated chips use shallow trench isolation (STI) structures. STI structures are formed by forming a pad oxide or spacer oxide over a substrate, structuring the pad oxide according to a nitride masking layer, etching trenches in the substrate according to the nitride masking layer, filling the trenches with one or more dielectrics (such as silicon dioxide or silicon nitride), and removing excess material of the dielectric(s) over the substrate. STI formation processes may further employ a wet etching process to remove the nitride masking layer and / or the pad oxide used during the formation of the STI structures.

[0013] However, it has been recognized that divots (depressions) can form in an upper surface of an STI structure during its formation (e.g., due to the wet etching process used to remove the nitride masking layer and / or pad oxide). Such divots can negatively affect the electrical behavior (e.g., both threshold and subthreshold voltages) of the devices, leading to unpredictable device performance. For example, during the fabrication of a transistor device, a conductive gate material can fill divots in an STI structure, giving the conductive gate material sharp edges that can amplify an electric field generated by the gate structure during transistor device operation.The increased electric field reduces the threshold voltage of the transistor device, leading to a problem known as the kink effect (defined, for example, by a double peak in the relationship between drain current and gate voltage). The kink effect has several negative consequences, such as being difficult to model (e.g., in SPICE curve fitting and / or parameter extraction).

[0014] The present disclosure relates, in some embodiments, to a transistor device with a gate structure comprising multiple gate electrode regions exhibiting different work functions and arranged in an active region with a shape configured to reduce the transistor device's susceptibility to performance degradation (e.g., kinking) caused by divots in an adjacent insulation structure, and to the associated forming method. The transistor device comprises a substrate with internal surfaces defining a trench in an upper surface of the substrate. One or more dielectrics are arranged in the trench. The one or more dielectrics define an active region in the substrate. The active region has a source region, a drain region, and a channel region between the source and drain regions.The source and drain regions have widths smaller than the channel region. A gate structure extends across the active region at a point between the source and drain regions. Because the source and drain regions have smaller widths than the channel region, a resulting effective channel region extending between the source and drain regions is separated from the edges of the isolation structure by a non-zero distance. This non-zero separation of the effective channel region from the edges of the isolation structure reduces the influence of divots in the isolation structure on the effective channel region.Furthermore, the gate structure comprises a first gate electrode region with a first composition of one or more materials and a second gate electrode region with a second composition of one or more materials that differs from the first composition. The different material compositions in the gate structure have different work functions, which can be used to set a threshold voltage of the transistor device in order to compensate for the undesirable influence of divots and / or dopant diffusion on the threshold voltage.

[0015] The Fig. Figures 1A-1B show some embodiments of an integrated chip, with a transistor device comprising a gate structure configured to improve device performance, wherein Fig. 1A a cross-sectional view 100 of the integrated chip along a cross-sectional line BB' of the Fig. Figure 1B shows. Furthermore, the transistor device is located in an active area with a shape configured to improve device performance.

[0016] As shown in the cross-sectional view 100 of Fig. As shown in Figure 1A, the integrated chip comprises a substrate 102 with internal surfaces defining a trench 103 extending in a top surface 102u of the substrate 102. An insulating structure 104 (e.g., a shallow trench insulating structure (STI structure)) with one or more dielectrics is arranged within the trench 103. The insulating structure 104 includes sidewalls defining an active region 106 in the substrate 102 (i.e., a region of the substrate 102 containing a transistor device). The insulating structure 104 further includes surfaces defining one or more divots 108 recessed beneath a top surface of the insulating structure 104. The one or more divots 108 may be arranged along edges of the insulating structure 104 located near the active region 106.

[0017] As shown in the top view 122 of Fig. As shown in Figure 1B, the insulation structure 104 extends continuously around the active region 106, and the one or more divots 108 in the insulation structure 104 surround the active region 106. A first doped region 124 and a second doped region 126 are arranged in the substrate 102 within the active region 106. The first doped region 124 and the second doped region 126 are highly doped regions arranged in the substrate 102. In some embodiments, the first and second doped regions 124 and 126 comprise n-type dopants such as phosphorus, arsenic, etc. In some embodiments, the first and second doped regions 124 and 126 comprise p-type dopants such as boron, gallium, etc. The first doped region 124 is separated from the second doped region 126 along the first direction 128 by an effective channel region 125.A gate structure 110 extends over the effective channel area 125 along a second direction 130, which is perpendicular to the first direction 128.

[0018] Referring again to cross-sectional view 100 of Fig. In 1A, the gate structure 110 is arranged above the substrate 102 and extends beyond opposite edges of the active region 106. The gate structure 110 comprises a gate dielectric 112 arranged above the substrate 102 and a gate electrode 113 separated from the substrate 102 by the gate dielectric 112. A conductive contact 120 is arranged in a dielectric structure 118 (e.g., an ILD layer) above the substrate 102. The conductive contact 120 extends vertically from a top surface of the gate structure 110 to a top surface of the dielectric structure 118.

[0019] The gate structure 110 comprises a first gate electrode region 114 and a second gate electrode region 116. The first gate electrode region 114 has a first work function, and the second gate electrode region 116 has a second work function that differs from the first work function. In some embodiments, the first gate electrode region 114 comprises a first composition of one or more materials with the first work function, and the second gate electrode region 116 comprises a second composition of one or more materials that differs from the first composition and has the second work function. In some embodiments, the first composition and the second composition do not comprise the same material.

[0020] In some embodiments, where the transistor device is an NMOS device, the first composition of one or more materials (in the first gate electrode region 114) comprises an n-gate metal with a first work function, while the second composition of one or more materials (in the second gate electrode region 116) comprises a p-gate metal with a second work function that is greater than the first work function (in order to increase an absolute value of a threshold voltage under the second gate electrode region 116).In further embodiments, in which the transistor device is a PMOS device, the first composition of one or more materials (in the first gate electrode region 114) comprises a p-gate metal with a first work function, while the second composition of one or more materials (in the second gate electrode region 116) comprises an n-gate metal with a second work function that is smaller than the first work function (in order to increase an absolute value of a threshold voltage under the second gate electrode region 116).

[0021] As shown in the top view 122 of Fig. As shown in Figure 1B, the first gate electrode region 114 and the second gate electrode region 116 are arranged directly above the effective channel region 125. In some embodiments, the effective channel region 125 extends continuously along the first direction 128 and along the second direction 130 from directly below the second gate electrode region 116 to beyond the outer edges of the second gate electrode region 116.

[0022] During operation, the gate structure 110 is configured to form a conducting channel in the effective channel region 125 in response to an applied gate voltage. The different work functions of the various gate electrode regions cause charge carriers in the effective channel region 125 to respond differently to the applied voltage. For example, the higher work function of the second gate electrode region 116 causes the gate electrode 113 to use a higher threshold voltage to form a conducting channel under the second gate electrode region 116 than under the first gate electrode region 114. The higher threshold voltage required to form a conducting channel under the second gate electrode region 116 compensates for a decrease in the threshold voltage caused by one or more divots 108 and / or by dopant diffusion (e.g., boron) from the substrate 102 into the insulating structure 104.By reducing the influence of one or more divots 108 and / or the dopant diffusion from the substrate 102 into the insulation structure 104, the performance of the transistor device is improved (e.g., the kink effect in the drain current is reduced).

[0023] Fig. Figure 2 shows some embodiments of diagrams 208 and 212, which provide examples of how different features of the integrated chip affect the absolute threshold voltage (shown along the y-axis) depending on a position in an active region (shown along the x-axis).

[0024] Diagram 208 shows an example of the influence of divots and / or dopant diffusion (e.g., of boron) on the absolute threshold voltage. As shown by line 210 of Diagram 208, due to one or more divots in the insulation structure and / or dopant diffusion into the insulation structure, the absolute threshold voltage under the second gate electrode region 116 is lower than under the first gate electrode region 114, leading to the kink effect.

[0025] Diagram 212 shows an example of the influence of the different work functions of the first gate electrode region 114 and the second gate electrode region 116 on the absolute threshold voltage. As shown by line 214 of diagram 212, due to the different work functions of the first gate electrode region 114 and the second gate electrode region 116, the gate structure has a higher absolute threshold voltage under the second gate electrode region 116 than under the first gate electrode region 114. In some embodiments, there is a difference between the absolute threshold voltage Δ|V TH | under the first gate electrode area 114 and under the second gate electrode area 116 in a range between approximately 0.5 V and approximately 1.5 V.

[0026] The higher absolute threshold voltage under the second gate electrode region 116 (shown in Diagram 212) compensates for the decrease in the absolute threshold voltage (shown in Diagram 208) caused by the one or more divots and / or dopant diffusion from the substrate into the insulation structure. By mitigating the influence of the one or more divots or dopant diffusion from the substrate into the insulation structure, the performance of the transistor device is improved (e.g., the kink effect in the drain current caused by the influence of the one or more divots on the electric field generated by the gate structure is reduced).

[0027] Referring again to cross-sectional view 122 of Fig. In 1B, the active region 106 has a source region 106a, which is separated from a drain region 106c along a first direction 128 by a channel region 106b. Along the second direction 130, the source region 106a has a first width W SD_1 , the drain area 106c a second width W SD_2 and the canal section 106b a third width W CH , which are greater than the first latitude W SD_1 and the second width W SD_2 is. In some embodiments, the first width W can be SD_1 and the second width W SD_2 They are essentially the same. In some embodiments, there is a difference between the first width W. SD_1 and the third latitude W CH greater than or equal to approximately twice the width of one or more of the divots 108.

[0028] A first doped region 124 is arranged in the source region 106a and a second doped region 126 is arranged in the drain region 106c. The first doped region 124 and the second doped region 126 are highly doped regions in an upper surface of the substrate 102. In some embodiments, the first doped region 124 has a width that is substantially equal to the first width W. SD_1 is, and the second doped area 126 has a width that is essentially equal to the second width W SD_2 In some embodiments, the channel region 106b extends beyond opposite sides of the first doped region 124 and the second doped region 126 along the second direction 130. The gate structure 110 extends beyond the active region 106 at a position between the first doped region 124 and the second doped region 126.

[0029] During operation, the gate structure 110 is configured to generate an electric field that forms a conducting channel in the effective channel region 125, which extends in the substrate 102 between the first doped region 124 and the second doped region 126. Since the width of the first doped region 124 and the second doped region 126 is smaller than the third width W CH of channel area 106b, the effective channel area 125 has an effective channel width W eff , which is separated from the one or more divots 108 in the isolation structure 104 along the second direction 130 by a non-zero distance ΔW. The separation of the effective channel width W effBy reducing the distance ΔW of the effective channel area 125 from the one or more divots 108 in the isolation structure 104, the influence of the one or more divots 108 on the electric field generated by the gate structure 110 along the edges of the effective channel area 125 is reduced. By reducing the influence of the one or more divots 108 on the effective channel area 125, the performance of the transistor device is improved (e.g., the kink effect in the drain current caused by the influence of the one or more divots 108 on the electric field generated by the gate structure 110 is reduced).

[0030] As shown in the top view 122 of Fig. As shown in Figure 1B, the second gate electrode region 116 extends along the first direction 128 by a non-zero distance 301 beyond opposite sides of the channel region 106b. The second gate electrode region 116 thus extends along the first direction to above the divot 108. According to the invention, the second gate electrode region 116 is set back (i.e., offset or separated) from a boundary between the divot 108 and the channel region 106b along the second direction 130 by a non-zero distance 303. In some embodiments, the second gate electrode region 116 extends along the second direction 130 by a non-zero distance beyond opposite sides of the source region 106a (or the drain region 106c). In some embodiments, the first gate electrode region 114 can have a first length L1 along the first direction 128 that is greater than a second length L2 of the second gate electrode region 116.In some embodiments, the first gate electrode region 114 and the second gate electrode region 116 can be substantially symmetrical along a first line extending in the first direction 128 and / or along a second line extending in the second direction 130.

[0031] The Fig. Figures 3A-3D show some additional embodiments of an integrated chip having a transistor device in an active area with a shape configured to improve device performance.

[0032] As shown in the top view 300 of Fig. As shown in Figure 3A, the integrated chip has an insulation structure 104 over a substrate (102 of Fig. 3B) with sidewalls defining an active region 106, which comprises a source region 106a and a drain region 106c, separated along a first direction 128 by a channel region 106b. A first doped region 124 lies within the source region 106a and has a width (along a second direction 130) that is substantially equal to the width of the source region 106a, and the second doped region 126 lies within the drain region 106c and has a width that is substantially equal to the width of the drain region 106c. In some embodiments, the active region 106 is substantially symmetrical about a line that bisects the first doped region 124 and the second doped region 126. In some alternative embodiments (not shown) the active region 106 need not be symmetrical about a line that bisects the first doped region 124 and the second doped region 126.For example, a central area of ​​the active area 106 may extend a greater distance beyond a first side of the source area 106a than beyond an opposite second side of the source area 106a.

[0033] A gate structure 110 is arranged between the first doped region 124 and the second doped region 126 along the first direction 128. The gate structure 110 extends along the second direction 130 beyond the active region 106. The gate structure 110 comprises a first gate electrode region 114 and a second gate electrode region 116. In some embodiments, the first gate electrode region 114 comprises a continuous segment, while the second gate electrode region 116 may comprise two or more separate and distinct segments. In some embodiments where the transistor device is an NMOS transistor (n-metal oxide semiconductor transistor), the first gate electrode region 114 may comprise an n-metal (e.g., a metal with a work function of about 4.2 eV or less), while the second gate electrode region 116 may comprise a p-metal (e.g., a metal with a work function of about 5.0 eV or more).For example, in some embodiments where the transistor device is an NMOS transistor, the first gate electrode region 114 may comprise an n-metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum silicon nitride, chromium, tungsten, copper, titanium-aluminum, or the like. In some embodiments, the second gate electrode region 116 may comprise a p-gate metal such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, or the like. In some embodiments where the transistor device is a PMOS transistor (p-metal oxide semiconductor transistor), the first gate electrode region 114 may comprise a p-metal, while the second gate electrode region 116 may comprise an n-metal.For example, in some embodiments where the transistor device is a PMOS transistor, the first gate electrode region 114 may comprise a p-gate metal such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, or the like. In some embodiments, the second gate electrode region 116 may comprise an n-metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum-silicon nitride, chromium, tungsten, copper, titanium-aluminum, or the like.

[0034] In some embodiments, the first gate electrode region 114 contacts the second gate electrode region 116 along the first direction 128 and along a second direction 130 that is perpendicular to the first direction 128. In some embodiments, the second gate electrode region 116 is arranged in gaps (i.e., openings) in the first gate electrode region 114. The segments of the second gate electrode region 116 may be separated by a central section of the first gate electrode region 114. In some embodiments, the first gate electrode region 114 extends around a circumference of the gate structure 110, such that the second gate electrode region 116 is completely surrounded by a peripheral section of the first gate electrode region 114.

[0035] In some embodiments, sidewall spacers 302 can be arranged along outer sidewalls of the gate structure 110. The sidewall spacers 302 comprise one or more dielectrics. In some embodiments, the sidewall spacers 302 can, for example, comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide), or the like. In some embodiments, the gate structure 110 and / or the sidewall spacers 302 can extend along the first direction 128 over the first doped region 124 and / or the second doped region 126.

[0036] The Fig. 3B and Fig. 3C shows cross-sectional views 322 and 344 of the integrated chip from Fig. 3A along the cross-sectional lines AA' and B-B'. As shown in cross-sectional view 322 along the cross-sectional line AA' of Fig. As shown in Figure 3B, a side section of the active area 106 has a first width W eff ', which is essentially equal to an effective channel width W eff of an effective channel area 125 between the first doped area 124 and the second doped area 126 is (see Fig. 3A). As shown in cross-sectional view 308 along the cross-sectional line BB' of Fig. As shown in 3C, a central region of the active area 106 has a second width of W eff + 2ΔW, which is greater than the first width by a non-zero value of twice the distance ΔW (i.e., 2ΔW).

[0037] In some embodiments, the size of the distance ΔW can be non-zero in a range between approximately 2% and approximately 10% of the size of the effective width W. eff For example, in some embodiments the distance ΔW can be non-zero and have a size between approximately 10 nm and approximately 1,000 nm, while the effective width Weff a size between approximately 100 nm and approximately 50,000 nm. A non-zero distance ΔW of more than approximately 2% of the effective channel width W eff This ensures a sufficiently large distance between the divot and the effective channel area, thus reducing the influence of changes in the electric field on the effective channel area caused by one or more divots. A non-zero distance of less than 10% of the effective width W is required. eff keeps the transistor's footprint small enough to be cost-effective.

[0038] In some embodiments, a well region 312 can be arranged in the substrate 102 below the active region 106. The well region 312 has a doping type that differs from that of the substrate 102. For example, in some embodiments where the transistor device is an NMOS transistor device, the substrate 102 can have n-type doping, the well region 312 can have p-type doping, and the first doped region 124 and the second doped region 126 can have n-type doping. In other embodiments where the transistor device is a PMOS transistor device, the substrate 102 can have n-type doping, the well region 312 can have n-type doping, and the first doped region 124 and the second doped region 126 can have p-type doping.

[0039] A dielectric structure 118 (e.g., an integrated dielectric layer (ILD)) is arranged over the substrate 102. In some embodiments, the dielectric structure 118 may comprise borosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), or the like. A conductive contact 120 extends vertically through the dielectric structure 118 to the gate structure 110. The conductive contact 120 touches the first gate electrode region 114.

[0040] Fig. 3D shows a cross-sectional view 366 of the integrated chip along a cross-sectional line CC' of Fig. 3A. As shown in the cross-sectional view 366, the first doped area 124 and the second doped area 126 are arranged in the trough area 312 on opposite sides of the gate structure 110.

[0041] The effective channel region 125 has a length along the first direction 128 that is approximately equal to the first length L1 of the first gate electrode region 114 (see Fig. 3A). In further embodiments, the length of the effective channel region 125 is shorter than the first length L1 of the first gate electrode region 114. In some embodiments, a source and a drain extension region 318 can project outwards from the first doped region 124 and the second doped region 126 to below the sidewall spacers 302 and / or the gate structure 110. In such embodiments, the effective channel region 125 extends between the source and drain extension regions 318. In some embodiments, a silicide layer (not shown) can be arranged on the first doped region 124 and the second doped region 126. In some embodiments, the silicide layer can comprise a nickel silicide, cobalt silicide, titanium silicide, or the like.

[0042] The Fig. Figures 4A-4B show a top view 400 and a cross-sectional view 422, respectively, illustrating some alternative embodiments of integrated chips with a transistor device having a gate structure configured to improve device performance. Fig. 4A - 4B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116a. As shown in the top view 400 of Fig. As shown in Figure 4A, the second gate electrode region 116a does not extend beyond opposite sides of the channel region 106b. Instead, the second gate electrode region 116a is set back from a boundary between the divot 108 and the channel region 106b along the first direction 128 by a non-zero distance 401.

[0043] The Fig. Figures 5A-5B show a top view 500 and a cross-sectional view 522, which show some non-inventive alternative embodiments of integrated chips with a transistor device having a gate structure configured to improve device performance. Fig. 5A - 5B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116b. As shown in the top view 500 of Fig. As shown in Figure 5A, the second gate electrode region 116b extends along the second direction 130 across opposite sides of the divot 108. In other words, the second gate electrode region 116b extends along the second direction 130 through the divot 108.

[0044] The Fig. Figures 6A-6B show a top view 600 and a cross-sectional view 622, which show some non-inventive alternative embodiments of integrated chips with a transistor device having a gate structure configured to improve device performance. Fig. 6A - 6B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116c. As shown in the top view 600 of Fig. As shown in Figure 6A, the second gate electrode region 116c is set back from a boundary between the divot 108 and the channel region 106b along the first direction 128 by a non-zero distance of 601. Furthermore, the second gate electrode region 116c extends beyond the boundary between the divot 108 and the channel region 106b along the second direction 130, but is set back from an outer edge of the divot 108 along the second direction 130 by a non-zero distance of 602.

[0045] The Fig. Figures 7A-7B show a top view 700 and a cross-sectional view 722, which show some non-inventive alternative embodiments of integrated chips with a transistor device comprising a gate structure configured to improve device performance. Fig. 7A - 7B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116d. As shown in the top view 700 of Fig. As shown in Figure 7A, the second gate electrode region 116d extends along the first direction 128 by a non-zero distance 701 beyond opposite sides of the channel region 106b. Furthermore, the second gate electrode region 116d extends along the second direction 130 by a non-zero distance 702 beyond an outer edge of the divot 108.

[0046] The Fig. Figures 8A-8B show a top view 800 and a cross-sectional view 822, which show some non-inventive alternative embodiments of integrated chips with a transistor device having a gate structure configured to improve device performance. Fig. 8A - 8B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116e. As shown in the top view 800 of Fig. As shown in Figure 8A, the second gate electrode region 116e extends along the first direction 128 by a non-zero distance 801 across opposite sides of the channel region 106b. Furthermore, the second gate electrode region 116e extends along the second direction 130 across the boundary between the divot 108 and the channel region 106b, but is set back from an outer edge of the divot 108 along the second direction 130 by a non-zero distance 802.

[0047] The Fig. Figures 9A-9B show a top view 900 and a cross-sectional view 922, which show some non-inventive alternative embodiments of integrated chips with a transistor device having a gate structure configured to improve device performance. Fig. 9A - 9B essentially show the same transistor device as the Fig. 1A - 1B, with the exception of the second gate electrode area 116f. As shown in the top view 900 of Fig. As shown in Figure 9A, the second gate electrode region 116f extends along the first direction 128 by a non-zero distance 901 beyond an outer edge of the divot 108. Furthermore, the second gate electrode region 116f extends along the second direction 130 by a non-zero distance 902 beyond an outer edge of the divot 108.

[0048] The Fig. Figures 10A-20 show cross-sectional and top views according to some alternative embodiments of a method for forming an integrated chip with a transistor device having a gate structure configured to improve device performance. Furthermore, the transistor device is located in an active region with a shape configured to improve device performance. Although the Fig. 10A - 20 are described with reference to a procedure; it is understood that the [documents] in the Fig. The structures shown in 10A - 20 are not limited to the procedure, but can stand alone separately from the procedure.

[0049] As seen in the top view, 1000 of Fig. 10A and the cross-sectional view 1022 of Fig. As shown in Figure 10B, an isolation structure 104 is formed in a trench 103 in a substrate 102. The isolation structure 104 defines a first active region 1062 in a first region 1002a, corresponding to a first transistor type (e.g., an NMOS transistor), and a second active region 1064 in a second region 1002b, corresponding to a second transistor type (e.g., a PMOS transistor). In some embodiments, the first region 1002a is equivalently referred to as the NMOS region and the second region 1002b is equivalently referred to as the PMOS region. The first active region 1062 and the second active region 1064 expose top surfaces 102u of the substrate 102. As shown in the top view 1000 of Figure 10B, the isolation structure 104 defines a first active region 1062 in a first region 1002a, corresponding to a first transistor type (e.g., an NMOS transistor), and a second active region 1064 in a second region 1002b, corresponding to a second transistor type (e.g., a PMOS transistor). Fig. As shown in Figure 10A, the first active region 1062 has a source region 1062a, a drain region 1062c, and a channel region 1062b. The channel region 1062b is located between the source region 1062a and the drain region 1062c along a first direction 128. The source region 1062a and the drain region 1062c have a smaller width than the channel region 1062b along a second direction 130, which is perpendicular to the first direction 128. The second active region 1064 has a source region 1064a, a drain region 1064c, and a channel region 1064b. The channel region 1064b is located between the source region 1064a and the drain region 1064c along the first direction 128. The source area 1064a and the drain area 1064c have a smaller width along the second direction than the channel area 1064b. The insulation structure 104 is arranged in a trench 103, which is defined by the inner surfaces of the substrate 102.During the formation of the isolation structures 104, one or more divots 108 may form within the isolation structure 104, recessed beneath a top surface of the isolation structure 104. The one or more divots 108 may be located along edges of the isolation structure 104 that are near the active regions 1062 and 1064.

[0050] In some embodiments, the insulating structure 104 can be formed by selectively etching the substrate 102 to create the groove 103. Subsequently, one or more dielectrics are formed within the groove 103. In various embodiments, the substrate 102 can be selectively etched by a wet etching agent (e.g., hydrofluoric acid, potassium hydroxide, or the like) or a dry etching agent (e.g., an etching chemistry comprising fluorine, chlorine, or the like). In various embodiments, the substrate 102 can consist of any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) as well as any other type of semiconductor, epitaxial, dielectric, or metal layers associated with it. In various embodiments, the one or more dielectrics can comprise an oxide, a nitride, a carbide, or the like.

[0051] In some additional embodiments, the insulating structure 104 can be formed by using a thermal process to form a pad oxide over the substrate 102, followed by the formation of a nitride film over the pad oxide. The nitride film is then patterned (e.g., using a photosensitive material such as a photoresist), and the pad oxide and the substrate 102 are patterned according to the nitride film to form the trench 103 in the substrate 102. The trench 103 is then filled with one or more dielectrics, followed by a planarization process (e.g., a chemical-mechanical planarization (CMP) process) to expose a top surface of the nitride film, and an etching process to remove the nitride film.

[0052] As shown in the top view 1100 of Fig. 11A and the cross-sectional view 1122 of Fig. As shown in Figure 11B, a gate dielectric 112 is formed over the substrate 102 and in the first active region 1062 and the second active region 1064. In some embodiments, the gate dielectric 112 can comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon oxynitride), a high-k gate dielectric layer (with a dielectric constant k of more than about 3.9), one or more other suitable dielectrics, the like, or combinations thereof. In some embodiments, the gate dielectric 112 can be formed by a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In other embodiments, the gate dielectric 112 can be formed by a thermal growth process. In some embodiments, an implantation process can be carried out prior to the formation of the gate dielectric 112 in order to form a trough region (not shown) in the substrate 102.In some of these embodiments, a dielectric sacrificial layer (not shown) can be formed over the substrate 102 prior to the implantation process to control the depth of the trough region. The dielectric sacrificial layer is subsequently removed prior to the formation of the gate dielectric.

[0053] In some embodiments, the gate dielectric 112 can be formed as part of a multi-gate dielectric process in which different gate dielectric layers are formed in different regions of the substrate 102. For example, in some embodiments, the multi-gate dielectric process can form a high-voltage gate dielectric layer (e.g., by a thermal process) over a high-voltage well in the substrate 102. The high-voltage gate dielectric layer can then be removed from one or more regions of a chip (e.g., in an embedded memory region), and a dual gate dielectric layer can be formed over a logic well in the substrate 102 (e.g., by one or more deposition processes).It was recognized that the formation of multiple gate dielectric layers can increase the size of one or more divots 108 in the insulation structures 104 due to the additional etching processes carried out to remove the gate dielectric layers from different areas of the substrate, thereby exacerbating the kink effect in the associated transistor devices.

[0054] As shown in the top view 1200 of Fig. 12A and the cross-sectional view 1222 of Fig. As shown in Figure 12B, a sacrificial gate material 115 is formed above the gate dielectric 112 and in the divots 108 of the insulation structure 104. The sacrificial gate material 115 can be formed by a deposition process (e.g., CVD, PE-CVD, PVD, or ALD). In some embodiments, the sacrificial gate material 115 can comprise doped polysilicon or undoped polysilicon. In some embodiments (not shown), the sacrificial gate material 115 can comprise a material that is subsequently replaced by a metal gate material such as aluminum, cobalt, ruthenium, or the like. The gate dielectric 112 and the sacrificial gate material 115 are structured to define sacrificial gate structures 111 that extend over the first active region 1062 and the second active region 1064 and over the insulation structure 104. The sacrificial gate structures 111 can fill one or more divots 108 in the upper surface of the isolation structure 104.In some embodiments, side wall spacers 302 can be formed along sides of the sacrificial gate structures 111.

[0055] The gate dielectric 112 and the sacrificial gate material 115 can be selectively structured according to a masking layer (not shown) formed over the sacrificial gate material 115. In some embodiments, the masking layer can comprise a photosensitive material (e.g., a photoresist) formed by a rotational coating process. In such embodiments, the layer of photosensitive material is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies the solubility of exposed areas in the photosensitive material to define soluble regions. The photosensitive material is then developed to define openings in the photosensitive material by removing the soluble regions. In further embodiments, the masking layer can be a hard mask layer (e.g.,a silicon nitride layer, a silicon carbide layer, or the like).

[0056] In some embodiments, the one or more sidewall spacers 302 are formed on opposite sides of the sacrificial gate structures 111. In some embodiments, the one or more sidewall spacers 302 can be formed by depositing a spacer material (e.g., a nitride, an oxide, or a combination thereof) on horizontal and vertical surfaces of the sacrificial gate structures 111 and subsequently etching the spacer material to remove it from the horizontal surfaces to form the one or more sidewall spacers 302.

[0057] As shown in the top view 1300 of Fig. 13A and the cross-sectional view 1322 of Fig. As shown in Figure 13B, a first doped region 124a and a second doped region 126a are formed in the substrate 102 on opposite sides of the sacrificial gate material 115 in the first active region 1062. A first doped region 124b and a second doped region 126b are formed in the substrate 102 on opposite sides of the sacrificial gate material 115 in the second active region 1064. In some embodiments, the first doped region 124a and the second doped region 126a can be formed by a first implantation process, while the first doped region 124b and the second doped region 126b can be formed by a second implantation process. For example, the first implantation process can be carried out by selectively implanting a first dopant species (e.g., with an n-dopant such as phosphorus, arsenic, etc.).) into substrate 102 according to a first mask covering the second region 1002b. Similarly, the second implantation process can be carried out by selectively implanting a second dopant species (e.g., with a p-doper such as boron, gallium, etc.) into substrate 102 according to a second mask covering the first region 1002a.

[0058] In some embodiments, the first doped region 124a is set back from a boundary between the source region 1062a and the channel region 1062b by a non-zero distance 306a, and the second doped region 126a is set back from a boundary between the drain region 1062c and the channel region 1062b by a non-zero distance 308a. By setting back the first doped region 124a and the second doped region 126a from the channel region 1062b (along the first direction 128), the first doped region 124a and the second doped region 126a have widths that are smaller than the width of the channel region 1062b.The smaller widths of the first doped region 124a and the second doped region 126a cause the first doped region 124a and the second doped region 126a to also be set back by a non-zero distance ΔWa along the second direction 130, which is essentially perpendicular to the first direction 128, from side walls of the insulation structure 104 that define the channel region 1062b. Resetting the first doped region 124a and the second doped region 126a from side walls of the isolation structure 104 separates an effective channel region (between the first doped region 124a and the second doped region 126a) from the one or more divots 108 in the isolation structure 104 and thereby reduces the influence that the one or more divots 108 have on an electric field generated by a gate structure in the effective channel region.

[0059] Similarly, the first doped region 124b is set back from a boundary between the source region 1064a and the channel region 1064b by a non-zero distance of 306b, and the second doped region 126b is set back from a boundary between the drain region 1064c and the channel region 1064b by a non-zero distance of 308b. By setting back the first doped region 124b and the second doped region 126b from the channel region 1064b (along the first direction 128), the first doped region 124b and the second doped region 126b have widths that are less than the width of the channel region 1064b.The smaller widths of the first doped region 124b and the second doped region 126b cause the first doped region 124b and the second doped region 126b to also be set back by a non-zero distance ΔWb along the second direction 130, which is essentially perpendicular to the first direction 128, from side walls of the insulation structure 104 that define the channel region 1064b. Resetting the first doped region 124b and the second doped region 126b from side walls of the isolation structure 104 separates an effective channel region (between the first doped region 124b and the second doped region 126b) from the one or more divots 108 in the isolation structure 104 and thereby reduces the influence that the one or more divots 108 have on an electric field generated by a gate structure in the effective channel region.

[0060] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, a first dielectric layer 1402 (e.g., a first dielectric intermediate layer (ILD layer)) is formed over the substrate 102. The first dielectric layer 1402 covers the sacrificial gate material 115 and the sidewall spacers 302. A planarization process is performed to remove the first dielectric layer 1402 over the sacrificial gate material 115 and the sidewall spacers 302. In various embodiments, the first dielectric layer 1402 can comprise an oxide, PSG, a low-k dielectric, or another dielectric and can be formed by a vapor deposition process (e.g., CVD, PVD, or ALD).

[0061] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, a photosensitive material 1502 is formed over the sacrificial gate material 115. In some embodiments, the photosensitive material 1502 may comprise a positive resist or a negative resist formed over the substrate 102 by a rotational coating process. The photosensitive material 1502 is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies the solubility of exposed regions in the photosensitive material 1502 to define soluble regions. The photosensitive material 1502 is then developed to define first and second openings 1506a and 1506b in the photosensitive material 1502 by removing the soluble regions, wherein the first openings 1506a are located in the first region 1002a and the second openings 1506b are located in the second region 1002b.Subsequently, sections of the sacrificial gate material 115 located beneath the openings 1506a and 1506b in the structured photosensitive material 1506 are selectively removed. These sections of the sacrificial gate material 115 can be removed by selectively exposing the sacrificial gate material 115 to an etching agent corresponding to the photosensitive material 1502. The removal of these sections of the sacrificial gate material 115 results in one or more first and second openings 1508a and 1508b extending through the sacrificial gate material 115 to the gate dielectric 112 and the insulating structure 104, with the first openings 1508a located in the first region 1002a and the second openings 1508b located in the second region 1002b. The one or more second openings 1508b are located above the one or more divots 108.In various embodiments, the etchant used for etching the sacrificial gate material 115 may comprise a dry etchant with an etching chemistry comprising a fluorine species (e.g. CF4, CHF3, C4F8 etc.) or a wet etchant comprising hydrofluoric acid (HF).

[0062] As shown in the cross-sectional view 1600 of Fig. As shown in Figure 16, a second composition of one or more materials (e.g., a second metal stack 1602 comprising a p-gate metal) is formed in one or more openings 1508a and 1508b to form a second gate electrode region 116a in the NMOS region 1002a and a first gate electrode region 114b in the PMOS region 1002b. The second metal stack 1602 laterally contacts the sacrificial gate material 115. In some embodiments, the second metal stack 1602 can completely fill one or more of the openings 1508a and 1508b. In various embodiments, the second metal stack 1602 comprises a p-gate metal such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, or the like. The p-gate metal 1602 can be formed in various embodiments using a gas phase deposition technique (e.g. PVD, CVD, PE-CVD, ALD, etc.).

[0063] As shown in the cross-sectional view 1700 of Fig. As shown in Figure 17, a planarization process is carried out on the second metal stack 1602 until the sacrificial gate material 115 is reached. In this way, the remaining sacrificial gate material 115 can be exposed. In some embodiments, the planarization process is a chemical-mechanical planarization process (CMP process).

[0064] As shown in the cross-sectional view 1800 of Fig. As shown in Figure 18, the remaining sacrificial gate material 115 is removed by selective etching. The removal of the sections of the sacrificial gate material 115 results in one or more first openings 1808a in the NMOS region 1002a and one or more second openings 1808b in the PMOS region 1002b. The second gate electrode regions 116a in the NMOS region 1002a are separated by the first openings 1808a, and the first gate electrode regions 114b in the PMOS region 1002b are separated by the second openings 1808b. The one or more first openings 1808a are located above the one or more divots 108. In various embodiments, the etchant used for etching the sacrificial gate material 115 may comprise a dry etchant with an etching chemistry containing a fluorine species (e.g. CF4, CHF3, C4F8 etc.) or a wet etchant containing hydrofluoric acid (HF).

[0065] As shown in the cross-sectional view from 1900 Fig. As shown in Figure 19, a first composition of one or more materials (e.g., a first metal stack 1902 comprising an n-gate metal) is formed in openings 1808a and 1808b. A planarization process is performed on the n-gate metal 1902 to remove excess portions of the first metal stack 1902 outside openings 1808a and 1808b. Remaining portions of the first metal stack 1902 in openings 1808a serve as the first gate electrode regions 114a in the NMOS region 1002a, and remaining portions of the first metal stack 1902 in openings 1808b serve as the second gate electrode regions 116b in the PMOS region 1002b. In some embodiments, the first metal stack 1902 comprises an n-gate metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum silicon nitride, chromium, tungsten, copper, titanium-aluminum or the like.In various embodiments, the first metal stack 1902 can be formed using a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). The first and second gate electrode regions 114a and 116a are referred to together as the first gate structure 110a in the NMOS region 1002a, and the first and second gate electrode regions 114b and 116b are referred to together as the second gate structure 110b in the PMOS region 1002b. In the NMOS region 1002a, the first gate electrode region 114a has a first work function that differs from the second work function of the second gate electrode region 116a (e.g., is lower than it). In the PMOS region 1002b, the second gate electrode region 114b has a first work function that differs from a second work function of the second gate electrode region 116b (e.g., is larger than it).

[0066] As shown in the cross-sectional view 2000 from Fig. As shown in Figure 20, a second dielectric layer 2002 (e.g., a second ILD layer) is formed over the first dielectric layer 1402 and the first and second gate structures 110a and 110b. A conductive contact 120 is formed in the second dielectric layer 2002. The conductive contact 120 extends from an upper surface of the second dielectric layer 2002 to the gate structure 110a. In some embodiments, the conductive contact 120 can be formed by selectively etching the second dielectric layer 2002 to form an opening 2004. The opening 2004 is then filled with a conductive material to form the conductive contact 120. A planarization process (e.g. a chemical-mechanical polishing process) can be carried out after the conductive material to make the upper surfaces of the second dielectric layer 2002 and the conductive contact 120 coplanar.In various embodiments, the conductive material can include tungsten, copper, aluminum-copper, or another conductive material.

[0067] Fig. Figure 21 shows a flowchart of some embodiments of a method 2100 for forming an integrated chip with a transistor device having a gate structure configured to improve device performance.

[0068] While the disclosed methods (e.g., methods 2100 and 3500) are shown and described here as a sequence of operations or events, it is understood that the sequence of such operations or events shown is not to be understood in a restrictive sense. For example, some operations may occur in a different sequence and / or simultaneously with other operations or events than those shown and / or described here. Additionally, not all of the operations shown need be required to implement one or more aspects or embodiments of the present description. Furthermore, one or more of the operations shown here may be performed in one or more separate steps and / or phases.

[0069] In block 2102, an isolation structure is formed within a substrate. This isolation structure comprises sidewalls that define a first and a second active region within the substrate, and surfaces that define one or more divots in the upper faces of the isolation structure. The first and second active regions are located in an NMOS and a PMOS region, respectively. Fig. Figures 10A - 10B show some embodiments corresponding to Block 2102.

[0070] In block 2104, a sacrificial gate structure with a gate dielectric and a sacrificial gate material is formed above the first and second active areas. Fig. Figures 11A - 12B show some embodiments corresponding to Block 2104.

[0071] In Block 2106, the first endowed areas are trained in the first active area on opposite sides of the victim gate material, and the second endowed areas are trained in the second active area on opposite sides of the victim gate material. Fig. Figures 13A - 13B show some embodiments corresponding to Block 2106.

[0072] In block 2108, a first dielectric layer is formed above the substrate and around the sacrificial gate material. Fig. Figure 14 shows some embodiments corresponding to Block 2108.

[0073] At Block 2110, some of the sacrificial gate material is removed from the sacrificial gate structure to form first and second openings. Fig. Figure 15 shows some embodiments corresponding to Block 2110.

[0074] In block 2112, a second composition of one or more materials is formed in the first and second openings. This second composition defines one or more second gate electrode regions in the NMOS region and one or more first gate electrode regions in the PMOS region. Fig. Figure 16 shows some embodiments corresponding to Block 2112.

[0075] In block 2114, a planarization process is carried out on the second composition of one or more materials to remove an excess of the second composition of one or more materials above the first dielectric layer. Fig. Figure 17 shows some embodiments corresponding to Block 2114.

[0076] At block 2116, a residue of the sacrificial gate material is removed to form one or more first openings adjacent to the second gate electrode areas in the NMOS area, and one or more second openings adjacent to the first gate electrode areas in the PMOS area. Fig. Figure 18 shows some embodiments corresponding to Block 2116.

[0077] In block 2118, a first composition of one or more materials is formed in the first and second openings in place of the remaining sacrificial gate material. This first composition of one or more materials defines one or more first gate electrode regions in the NMOS region and one or more second gate electrode regions in the PMOS region. Fig. Figure 19 shows some embodiments corresponding to Block 2118.

[0078] In block 2120, a second dielectric layer is formed over the first dielectric layer, and a conductive contact is formed in the second dielectric layer. Fig. Figure 20 shows some embodiments corresponding to Block 2120.

[0079] The Fig. Figures 22A-34 show cross-sectional and top views belonging to some alternative embodiments of a method for forming an integrated chip with a transistor device having a gate structure configured to improve device performance. Although the Fig. 22A - 34 are described with reference to a procedure; it is understood that the provisions in the Fig. The structures shown in 22A - 34 are not limited to the procedure, but can stand separately from the procedure on their own.

[0080] As shown in the top view 2200 from Fig. 22A and the cross-sectional view 2222 of Fig. As shown in Figure 22B, an isolation structure 104 is formed in a trench 103 in a substrate 102. The isolation structure 104 defines a first active region 1062 in a first region 1002a, corresponding to a first transistor type (e.g., an NMOS transistor), and a second active region 1064 in a second region 1002b, corresponding to a second transistor type (e.g., a PMOS transistor). The first active region 1062 and the second active region 1064 expose the top surface 102u of the substrate 102. Details about the isolation structure 104 and the active regions 1062 and 1064 were previously described with reference to the Fig. 10A and Fig. They are described in section 10B and will therefore not be repeated for the sake of brevity.

[0081] As shown in the top view 2300 from Fig. 23A and the cross-sectional view 2322 of Fig. As shown in Figure 23B, a gate dielectric 112 is formed above the substrate 102 and in the first active region 1062 and the second active region 1064. Details about the gate dielectric 112 were previously described with reference to the Fig. 11A and Fig. 11B and are therefore not repeated for the sake of brevity.

[0082] As shown in the top view 2400 from Fig. 24A and the cross-sectional view 2442 of Fig. As shown in Figure 24B, a sacrificial gate material 115 is formed above the gate dielectric 112 and in divots in the insulation structure 104. The sacrificial gate material 115 and the underlying gate dielectric 112 are referred to together as sacrificial gate structures 111. In some embodiments, sidewall spacers 302 can be formed along sides of the sacrificial gate structures 111. Details of the sacrificial gate material 115 and the sidewall spacers 302 were previously described with reference to the Fig. 12A and Fig. Section 12B describes the points and will therefore not be repeated for the sake of brevity.

[0083] As shown in the top view 2500 of Fig. 25A and the cross-sectional views 2522 of Fig. As shown in Figure 25B, a first doped region 124a and a second doped region 126a are formed in the substrate 102 on opposite sides of the sacrificial gate material 115 in the first active region 1062. A first doped region 124b and a second doped region 126b are formed in the substrate 102 on opposite sides of the sacrificial gate material 115 in the second active region 1064. In some embodiments, the first doped region 124a and the second doped region 126a can be formed by a first implantation process, while the first doped region 124b and the second doped region 126b can be formed by a second implantation process. For example, the first implantation process can be carried out by selectively implanting a first dopant species (e.g., with an n-dopant such as phosphorus, arsenic, etc.).The implantation process can be carried out by selectively implanting a second dopant species (e.g., with a p-dopant such as boron, gallium, etc.) into substrate 102 according to a second mask covering the first region 1002a. Further details regarding the doped regions 124a, 126a, 124b, and 126b have been previously described with reference to the following. Fig. 13A and Fig. Section 13B describes the above and will therefore not be repeated for the sake of brevity.

[0084] As shown in the cross-sectional view 2600 of Fig. As shown in Figure 26, a first dielectric layer 1402 (e.g., a first dielectric intermediate layer (ILD layer)) is formed over the substrate 102. The first dielectric layer 1402 covers the sacrificial gate material 115 and the sidewall spacers 302. A planarization process is performed to remove the first dielectric layer 1402 over the sacrificial gate material 115 and the sidewall spacers 302. In various embodiments, the first dielectric layer 1402 can comprise an oxide, PSG, a low-k dielectric, or another dielectric and can be formed by a vapor deposition process (e.g., CVD, PVD, or ALD).

[0085] As shown in the cross-sectional view 2700 of Fig. As shown in Figure 27, the sacrificial gate material 115 is removed from the sacrificial gate structures 111. The removal of the sacrificial gate material 115 leads to the formation of replacement gate cavities 2702a and 2702b between the side wall spacers 302. Replacement gate cavity 2702a is located in the NMOS area 1002a and replacement gate cavity 2702b is located in the PMOS area 1002b.

[0086] As shown in the cross-sectional view 2800 of Fig. As shown in Figure 28, a barrier layer 2802, a first gate metal 2804, and a sacrificial dielectric 2806 are formed successively to fill the substitute gate cavities 2702a and 2702b. In some embodiments, the barrier layer 2802 is configured to prevent the diffusion of the subsequently formed metals (e.g., the first gate metal 2804) into the gate dielectric layer 112. The barrier layer 2802 can be made of metal carbonitride (such as titanium carbonitride or tantalum carbonitride) or metal nitride (such as titanium nitride or tantalum nitride). In various embodiments, the barrier layer 2802 can be formed by a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first gate metal 2804 may comprise a p-gate metal such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper or the like.In various embodiments, the first gate metal 2804 can be formed by a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the sacrificial dielectric 2806 can comprise a spin-on glass (SOG).

[0087] After forming the sacrificial dielectric 2806, a masking layer 2808, comprising a photosensitive material, is formed over the sacrificial dielectric 2806. The photosensitive material 2808 is structured to define first and second openings 2810a and 2810b in the photosensitive material 2808, wherein the first openings 2810a are located in the first region 1002a and the second openings 2810b are located in the second region 1002b.

[0088] As shown in the cross-sectional view 2900 of Fig. As shown in Figure 29, the sacrificial dielectric 2806 is selectively exposed to an etching agent according to the photosensitive material 2808 in order to remove sections of the sacrificial dielectric 2806 that lie beneath the first and second openings 2810a and 2810b in the photosensitive material 2808. The remaining sections of the sacrificial dielectric 2806 can be referred to as a structured mask 2902, which has one or more first openings 2904a in the first region 1002a and one or more second openings 2904b in the second region 1002b.

[0089] As shown in the cross-sectional view 3000 of Fig. As shown in Figure 30, the first gate metal 2804 is selectively exposed to an etching agent according to the structured mask 2902 to remove sections of the first gate metal 2804 that lie below the first and second openings 2904a and 2904b in the structured mask 2902. The structured mask 2902 remains over the divots 108 in the second region 1002b, while the structured mask 2902 over the divots 108 in the first region 1002a is removed. After etching the first gate metal 2804, a residue of the photosensitive material 2808 and the structured mask 2902 is removed. The resulting structure is shown in the cross-sectional view 3100 of Figure 30. Fig. 31 shown.

[0090] As shown in the cross-sectional view 3200 of Fig. As shown in Figure 32, a second gate metal 3202 and a filler metal 3204 are successively formed to fill the replacement gate cavities 2702a and 2702b above the first gate metal 2804. In some embodiments, the second gate metal 3202 can comprise an n-gate metal such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum-silicon nitride, chromium, tungsten, copper, titanium-aluminum, or the like. In various embodiments, the second gate metal 3202 can be formed by a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). The filler metal 3204 can comprise aluminum, tungsten, gold, platinum, cobalt, another suitable metal, an alloy thereof, or combinations thereof. The filler metal 3204 can be deposited using a PVD process, a CVD process, a plating process, an ALD process or the like, or combinations thereof.

[0091] As shown in the cross-sectional view 3300 of Fig. As shown in Figure 33, a planarization process is carried out on the filler metal 3204 until the first dielectric layer 1402 is reached. The planarization process leads to a first gate structure 110a in the NMOS region 1002a and a second gate structure 110b in the PMOS region 1002b. The first gate structure 110a comprises a first and a second gate electrode region 114a and 116a, respectively, with the first gate metal 2804 not present in the first gate electrode region 114a but present in the second gate electrode region 116a. Thus, the first and second gate electrode regions 114a and 116a have different work functions. For example, if the first gate metal 2804 is a p-gate metal which has a higher work function than the n-gate metal, then the second gate electrode region 116a has a higher work function than the first gate electrode region 114a.The second gate structure 110b in the PMOS region 1002b comprises a first and a second gate electrode region 114b and 116b, respectively, with the first gate metal 2804 being present in the first gate electrode region 114b but not in the second gate electrode region 116b. Thus, the first and second gate electrode regions 114b and 116b have different work functions. For example, if the first gate metal 2804 is a p-gate metal, which has a higher work function than an n-gate metal, then the first gate electrode region 114b will have a higher work function than the second gate electrode region 116b.

[0092] As shown in the cross-sectional view 3400 of Fig. As shown in Figure 34, a second dielectric layer 3402 (e.g., a second ILD layer) is formed over the first dielectric layer 1402 and the first and second gate structures 110a and 110b. A conductive contact 120 is formed in the second dielectric layer 3402. The conductive contact 120 extends from an upper surface of the second dielectric layer 3402 to the gate structure 110a. In some embodiments, the conductive contact 120 can be formed by selectively etching the second dielectric layer 3402 to form an opening 3404. The opening 3404 is then filled with a conductive material to form the conductive contact 120. A planarization process (e.g. a chemical-mechanical polishing process) can be carried out after the conductive material to make the upper surfaces of the second dielectric layer 3402 and the conductive contact 120 coplanar.In various embodiments, the conductive material can include tungsten, copper, aluminum-copper, or another conductive material.

[0093] Fig. Figure 35 shows a flowchart of some alternative embodiments of a method 3500 for forming an integrated chip with a transistor device having a gate structure configured to improve device performance.

[0094] In block 3502, an isolation structure is formed within a substrate. This isolation structure comprises sidewalls that define a first and a second active region within the substrate, and surfaces that define one or more divots in the upper faces of the isolation structure. The first and second active regions are located in an NMOS and a PMOS region, respectively. Fig. Figures 22A and 22B show some embodiments corresponding to block 3502.

[0095] In block 3504, a sacrificial gate structure with a gate dielectric and a sacrificial gate material is formed above the first and second active areas. Fig. Figures 23A - 24B show some embodiments corresponding to block 3504.

[0096] In Block 3506, first-level endowed areas are trained in the first active area on opposite sides of the victim gate material, and second-level endowed areas are trained in the second active area on opposite sides of the victim gate material. Fig. 25A - 25B show some embodiments corresponding to block 3506.

[0097] In block 3508, a first dielectric layer is formed above the substrate and around the sacrificial gate material. Fig. Figure 26 shows some embodiments corresponding to Block 3508.

[0098] At Block 3510, the sacrificial gate material is removed from the sacrificial gate structure to form replacement gate cavities. Fig. Figure 27 shows some embodiments corresponding to block 3510.

[0099] In block 3512, a barrier layer, a first gate metal and a sacrificial dielectric are formed successively to fill the replacement gate cavities. Fig. Figure 28 shows some embodiments corresponding to block 3512.

[0100] In block 3514, the sacrificial dielectric is structured to form a structured mask. Fig. Figure 29 shows some embodiments corresponding to block 3514.

[0101] In block 3516, the first gate metal is structured using the structured mask as an etching mask. Fig. Figure 30 shows some embodiments corresponding to block 3516.

[0102] In block 3518, the sacrificial dielectric is removed from the replacement gate cavities. Fig. Figure 31 shows some embodiments corresponding to block 3518.

[0103] In block 3520, a second gate metal and a filler metal are formed in the replacement gate cavities and above the first gate metal. Fig. Figure 32 shows some embodiments corresponding to block 3520.

[0104] Block 3522 undergoes a planarization process to remove the excess filler metal and second gate metal above the first dielectric layer. Fig. Figure 33 shows some embodiments corresponding to block 3522.

[0105] In block 3524, a second dielectric layer is formed over the first dielectric layer and a conductive contact is formed in the second dielectric layer. Fig. Figure 34 shows some embodiments corresponding to block 3524.

[0106] Based on the above descriptions, it is evident that the present disclosure offers advantages. However, it is understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage required for all embodiments. One advantage is that the kink effect is reduced because the source and drain regions have smaller widths than the channel region and because different gate electrode regions have different outlet works. Another advantage is that the saturation drain current (I) DSATThe efficiency can be improved (e.g., by more than 10%) because the source and drain regions have smaller widths than the channel region and because different gate electrode regions have different work functions. Another advantage is that the influence of narrow widths can be reduced because the source and drain regions have smaller widths than the channel region and because different gate electrode regions have different work functions.

Claims

[1] Integrated chip (100), comprising: a substrate (102); an insulating structure (104) in the substrate comprising one or more dielectrics and having sidewalls defining an active region (106) in the substrate (102), wherein the active region (106) has a channel region (106b), a source region (106a) and a drain region (106c) separated from the source region (106a) by the channel region (106b) along a first direction (128), wherein the source region (106a) has a first width W SD_1 along a second direction (130) perpendicular to the first direction (128), the drain area (106c) has a second width W SD_2 along the second direction (130) and the canal area (106b) has a third width W CH along the second direction (130) and greater than the first latitude W SD_1 and the second width W SD_2 has; and a gate structure (110) extending over the channel region (106b), wherein the gate structure (110) comprises a first gate electrode region (114) with a first composition of one or more materials and a second gate electrode region (116) with a second composition of one or more materials that differs from the first composition of one or more materials, wherein the insulation structure (104) has surfaces defining one or more divots (108) recessed below a top surface of the insulation structure (104); where a difference between the first width W SD_1 and the third latitude W CH is greater than or equal to twice the width of one or more of the divots (108); and wherein the second gate electrode region (116) comprises two or more segments arranged in gaps in the first gate electrode region above the channel region (106b), separated by a middle section of the first gate electrode region and each set back along the second direction (130) from a boundary between the one or more divots (108) and the channel region (106b) by a non-zero distance (303), wherein the first gate electrode region (114) is located above the one or more divots (108) and wherein the second gate electrode region (116) is separated from the one or more divots (108) by the first gate electrode region (114) along the second direction (130). [2] Integrated chip (100) according to one of the preceding claims, wherein the second gate electrode region (116) extends beyond opposite sides of the channel region (106b) along the first direction (128). [3] Integrated chip (100) according to one of the preceding claims, wherein the length of the first gate electrode region (114) along the first direction (128) is greater than the length of the channel region (106b) along the first direction (128). [4] Integrated chip (100) according to one of the preceding claims, wherein the length of the second gate electrode region (116) along the first direction (128) is smaller than the length of the first gate electrode region (114) along the first direction. [5] Integrated chip (100) according to one of the preceding claims, wherein the length of the second gate electrode region (116) along the first direction (128) is greater than the length of the channel region (106b) along the first direction (128). [6] Integrated chip (100) according to one of the preceding claims, wherein the active area (106) is located at a position directly below the second gate electrode area (116) between the first width WSD_1 to the third latitude W CH changes. [7] Integrated chip (100) according to any one of the preceding claims, wherein the first composition of one or more materials comprises an n-gate metal and the second composition of one or more materials comprises a p-gate metal. [8] Integrated chip (100) according to any one of claims 1 to 6, wherein the first composition of one or more materials has a work function that differs from a work function of the second composition of one or more materials. [9] Integrated chip (100) according to one of the preceding claims, wherein the first gate electrode region (114) is laterally adjacent to the second gate electrode region (116) along the first direction (128) and along the second direction (130). [10] Integrated chip (400), comprising: an isolation structure (104) arranged in a substrate (102) and defining an active area (106) in the substrate; a first doped area (106a) which is arranged in the active area (106); a second doped region (106c) arranged within the active region (106) and separated from the first doped region (106a) along a first direction (128) by a middle region (106b) of the active region (106), the middle region (106b) of the active region (106) extending along a second direction (130) perpendicular to the first direction (128) beyond opposite sides of the first doped region (106a); and a gate structure (110) extending over the active region (106) and beyond its edges along the second direction (130), wherein the gate structure (110) comprises a first gate electrode region (114) with a first work function and a plurality of second gate electrode regions (116a, 116b) with second work functions that differ from the first work function, wherein the second gate electrode regions (116a, 116b) are arranged in gaps in the first gate electrode region above the central region (106b) of the active region (106) and are separated by a central section of the first gate electrode region (114), wherein the insulation structure (104) has surfaces defining one or more divots (108) recessed below a top surface of the insulation structure (104); wherein a difference between a width of the middle region (106b) of the active region (106) along the second direction (130) and a width of the first doped region (106a) along the second direction (130) is greater than or equal to twice the width of one or more of the divots (108); and wherein the second gate electrode regions (116a, 116b) are each offset along the second direction (130) from a boundary between the one or more divots (108) and the central region (106b) of the active region (106) by a distance (303) not equal to zero. [11] Integrated chip (400) according to claim 10, wherein the second gate electrode regions (116a, 116b) are arranged along the second direction (130). [12] Integrated chip (400) according to claim 10 or 11, wherein the first gate electrode region (114) comprises a peripheral section that completely surrounds the second gate electrode regions (116a, 116b). [13] Integrated chip (400) according to one of claims 10 to 12, wherein the first gate electrode region (114) comprises an n-gate metal and the second gate electrode regions (116a, 116b) comprise a p-gate metal. [14] Method (2100) for forming an integrated chip (100), comprising: Forming an isolation structure (104) in a trench (103) in a substrate (102), wherein the isolation structure (104) defines a source region (106a), a drain region (106c), and a channel region (106b) arranged along a first direction (128) between the source region (106a) and the drain region (106c), and extending along a second direction (130) perpendicular to the first direction (128) beyond the source region (106a) and the drain region (106c), wherein the isolation structure (104) has surfaces defining one or more divots (108) recessed below a top surface of the isolation structure (104), and wherein a difference between a width of the channel region (106b) along the second direction (130) and a width of the source region (106a) along the second direction (130) is greater than or equal to twice the width of one or more of the divots (108); Separating and structuring a sacrificial gate material (115) so that it extends beyond the channel area (106b) and its edges in the second direction; and Replacing the sacrificial gate material (115) with a gate structure (110), wherein the gate structure (110) comprises a first gate electrode region (114) with a first composition of one or more materials and a second gate electrode region (116) with a second composition of one or more materials that differs from the first composition of one or more materials, wherein the second gate electrode region (116) comprises two or more segments arranged in gaps in the first gate electrode region above the channel region and separated by a middle section of the first gate electrode region and each set back along the second direction (130) from a boundary between the one or more divots (108) and the channel region (106b) by a non-zero distance (303). [15] Method (2100) according to claim 14, comprising replacing the sacrificial gate material (115) with the gate structure (110): Removing an initial section of the sacrificial gate material (115) to form an opening (1508a) extending through the sacrificial gate material (115); Separation of the second composition from one or more materials into the opening (1508a); Removing a second section of the sacrificial gate material (115) between side walls of the second composition of one or more materials; and Separation of the first composition of one or more materials between the side walls of the second composition of one or more materials. [16] Method (2100) according to claim 14, wherein replacing the sacrificial gate material (115) with the gate structure comprises: Removing the sacrificial gate material (115) to form a replacement gate cavity (2702a) between side wall spacers (302); Separation of the second composition from one or more materials in the replacement gate cavity (2702a); Structuring the second composition from one or more materials; and Deposition of the first composition of one or more materials over the structured second composition of one or more materials.

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