Semiconductor device

Abstract

Semiconductor device (10) comprising: a substrate (14) comprising an insulating plate (11) with a front surface and a plurality of circuit structures (12a-12h) formed on the front surface of the insulating plate; a plurality of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) formed on at least facing side sections of the plurality of circuit structures (12a-12h), such that bond regions (15a1-16g1) are exposed on front surfaces of the plurality of circuit structures (12a-12h); and a plurality of components (15a-15c, 16a-16g, 17a-17e) bonded via solder (18a-18i) to the bond regions (15a1-16g1) of the plurality of circuit structures (12a - 12h), wherein: the majority of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) are formed on at least the facing side sections and on edge sections of the front surfaces of the majority of circuit structures (12a-12h) along the side sections; and the majority of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) are made of metal.

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

[0001] The embodiments discussed herein relate to a semiconductor device. 2. Background of the related prior art

[0002] Semiconductor devices include semiconductor elements such as IGBTs (insulated bipolar gate transistors) and power MOSFETs (metal oxide semiconductor field-effect transistors). These semiconductor devices are used, for example, as power conversion devices.

[0003] A semiconductor device comprises a substrate with an insulating plate and a plurality of circuit structures formed on a front surface of the insulating plate. Semiconductor elements and external terminals are arranged on the circuit structures, and signals applied by the external terminals are fed into the semiconductor elements via the circuit structures.

[0004] Cylindrical contact elements are used to attach the external terminals to the circuit structures. The external terminals are pressed into contact elements that are bonded to the circuit structures using solder, thus electrically connecting the external terminals to the circuit structures via the contact elements. See, for example, US Patent Application No. US 2009 / 0194884A1.

[0005] In the semiconductor device described above, a plating process using nickel or the like is performed on the surfaces of the circuit structures. This suppresses corrosion of the circuit structures, thereby preventing substances produced by corrosion (hereinafter referred to as "corrosion products") from causing short circuits between the circuit structures.

[0006] Circuit structures that have undergone a plating process are less wettable with respect to the solder, making it difficult to avoid the formation of voids within the solder. This means that when components such as cylindrical contact elements and semiconductor elements are bonded to clad circuit structures via solder, it is not possible to achieve sufficient bond strength for the components on the circuit structures.

[0007] WO 2017 / 006 661 A1 discloses a device in which a ceramic-metal printed circuit board and a metal plate are connected via a bonding layer on both surfaces of the ceramic substrate. A metal film is provided on the surface of the metal plate located on one surface of the ceramic substrate, and the ceramic-metal printed circuit board is located on the surface of a metal plate located on the other surface. There is also a section where no metal coating is provided.

[0008] US 2017 / 0 025 344 A1 discloses a semiconductor module comprising an insulated printed circuit board (PCB) containing an insulating substrate, a first conductive plate located on a first major surface of the insulating substrate and within the outer edges of the insulating substrate, and a second conductive plate located within the outer edges of the insulating substrate on a second major surface of the insulating substrate, opposite the first major surface. Furthermore, the interfaces between the first major surface of the insulating substrate and the side faces of the first conductive plate are covered with an ionic gel containing an ionic liquid.

[0009] US 2007 / 0 246 833 A1 shows a semiconductor module with different solder compositions. BRIEF SUMMARY OF THE INVENTION

[0010] The present embodiments were developed in light of the problem described above and aim to provide a semiconductor device capable of preventing a decrease in the bond strength of components on circuit structures. To this end, a semiconductor device comprising the features of the independent claim is provided. The dependent claims relate to exemplary embodiments. The following aspects serve to better understand the invention.

[0011] In one aspect of the embodiments, a semiconductor device is provided comprising: a substrate comprising an insulating plate and a plurality of circuit structures formed on a front surface of the insulating plate; a plurality of protective films formed on at least facing side sections of the plurality of circuit structures to expose bond regions on front surfaces of the plurality of circuit structures; and a plurality of components bonded to the bond regions of the plurality of circuit structures using solder. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a semiconductor device according to a first embodiment; Fig. Figure 2 is a cross-sectional view of the semiconductor device according to the first embodiment; Fig. 3 is a top view of the semiconductor device according to the first embodiment, with components omitted; Fig. Figure 4 shows circuit structures on a substrate of a semiconductor device, which is a modification of the first embodiment; Fig. 5 is a top view of a main part of a semiconductor device according to a second embodiment; Fig. Figure 6 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment; Fig. 7 is a top view of a main part of a semiconductor device according to a third embodiment; Fig. Figure 8 is a first cross-sectional view of a main part of the semiconductor device according to the third embodiment; and Fig. Figure 9 is a second cross-sectional view of a main part of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Several embodiments are described below with reference to the accompanying drawings, whereby identical reference numerals always refer to identical elements. First embodiment

[0013] A semiconductor device according to a first embodiment is now described with reference to the Fig. 1 to 3 described. The first embodiment illustrates a non-inventive example.

[0014] Fig. Figure 1 is a top view of a semiconductor device according to the first embodiment. Fig. Figure 2 is a cross-sectional view of the semiconductor device according to the first embodiment. Fig. Figure 3 is a top view of the semiconductor device according to the first embodiment, with components omitted.

[0015] Note that in Fig. 1 and Fig. 3 a cover section 21a of a housing 21 and a metal substrate 20 have been omitted from the drawings. Fig. Figure 2 is a cross-sectional view along a dash-dot line XX in Fig. 1. Also note that the in Fig. 1 components shown, i.e. semiconductor elements 15a, 15b and 15d, an electronic component 15c, contact elements 16a to 16g and bond wires 17a to 17e, in Fig. 3 were omitted.

[0016] As in the Fig. 1 and Fig. As shown in Figure 2, a semiconductor device 10 comprises a ceramic circuit substrate 14 (or simply “substrate”), the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g bonded to a front surface of the ceramic circuit substrate 14, and external terminals 19a to 19g, each attached to the contact elements 16a to 16g. Note that the number and bond positions of the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g bonded to the ceramic circuit substrate 14 (i.e., to circuit structures 12a to 12h, as described later) are merely examples. As long as the semiconductor elements 15a, 15b and 15d, the electronic component 15c and the contact elements 16a to 16g are located on the ceramic circuit substrate 14 (i.e. on the circuit structures 12a to 12h), configurations in addition to those shown in the Fig. 1 and Fig. The two shown can be used.

[0017] Furthermore, the semiconductor device 10 comprises the metal substrate 20 on which the ceramic circuit substrate 14 is arranged, and the housing 21, which is provided on the metal substrate 20, which covers the ceramic circuit substrate 14 and from which the external terminals 19a to 19g extend.

[0018] The ceramic circuit substrate 14 has an insulating plate 11, the circuit structures 12a to 12h formed on the front surface of the insulating plate 11, and a metal plate 13 formed on a rear surface of the insulating plate 11.

[0019] The circuit structures 12a to 12h are formed from a material with excellent electrical conductivity and excellent wettability with respect to the solder. Examples of this type of material are silver, copper, and alloys containing at least one of these metals. As in Fig. As shown in Figure 1, these circuit structures 12a to 12h are each formed in predefined shapes. Note that the number, shapes, and positions formed on the insulating plate 11 of the circuit structures 12a to 12h are merely examples and differ from the example in the Fig. 1 and Fig. 2. They can distinguish between them.

[0020] First protective films 12a1, 12a2, 12b1 to 12b3, 12c1 to 12c3, 12d1, 12d2, 12e1 to 12e4, 12f1, 12f2, 12g1 to 12g3, 12h1 and 12h2 are formed on facing side surfaces of the circuit structures 12a to 12h.

[0021] In more detail, the first protective films 12a1 and 12a2 are formed on the side faces of the circuit structure 12a that face the circuit structures 12b and 12e. The first protective films 12b1 to 12b3 are formed on the side faces of the circuit structure 12b that face the circuit structures 12c, 12e, and 12a. The first protective films 12c1 to 12c3 are formed on the side faces of the circuit structure 12c that face the circuit structures 12d, 12e, and 12b. The first protective films 12d1 and 12d2 are formed on the side faces of the circuit structure 12d that face the circuit structures 12c and 12e.

[0022] The first protective films 12e1 to 12e3 are formed on side faces of the circuit structure 12e that face the circuit structures 12d, 12c, 12b and 12a. Furthermore, the first protective film 12e4 is formed on a side face of the circuit structure 12e that faces the circuit structures 12f to 12h.

[0023] The first protective films 12f1 and 12f2 are formed on side faces of the circuit structure 12f that face the circuit structures 12e and 12g. The first protective films 12g1 to 12g3 are formed on side faces of the circuit structure 12g that face the circuit structures 12f, 12e, and 12h. The first protective films 12h1 and 12h2 are formed on side faces of the circuit structure 12h that face the circuit structures 12g and 12e.

[0024] Note that if no specific distinction is made between the first protective films, the reference numbers 12a1, 12a2, 12b1 to 12b3, 12c1 to 12c3, 12d1, 12d2, 12e1 to 12e4, 12f1, 12f2, 12g1 to 12g3, 12h1 and 12h2 can be omitted in the following description.

[0025] The first protective films are made from a material with excellent corrosion resistance. Examples of suitable materials include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, platinum, palladium, and alloys containing at least one of these metals.

[0026] It is possible to form the first protective films described above on the side surfaces of the circuit structures 12a to 12h, for example, by electroless plating. It is also possible to form the first protective films only on the desired side surfaces of the circuit structures 12a to 12h by first applying a mask (photoresist) to regions of the circuit structures 12a to 12h where the first protective films should not form, and then removing the photoresist after electroless plating.

[0027] Accordingly, the first protective films described above are formed only on facing side surfaces of the circuit structures 12a to 12h, and no plating process is carried out in regions other than the side surfaces on which the first protective films are formed (i.e., no plating films are formed).

[0028] For example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate can be used as the ceramic circuit substrate 14 with the configuration described above. The ceramic circuit substrate 14 is able to conduct heat produced by the semiconductor elements 15a, 15b and 15d and the electronic component 15c via the circuit structures 12e to 12h, the insulating plate 11 and the metal plate 13 to the side of the metal substrate 20.

[0029] The metal plate 13 is made of a metal material with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy comprising at least one of these metals.

[0030] The insulating plate 11 is made of a ceramic material with high thermal conductivity, such as aluminum oxide, aluminum nitride, and silicon nitride. Note that the insulating plate 11 can be rectangular when viewed from above. The metal plate 13 is also rectangular, but with a smaller area than the insulating plate 11 when viewed from above.

[0031] For example, semiconductor elements 15a, 15b, and 15d include switching elements such as IGBTs or power MOSFETs. In an exemplary configuration, semiconductor elements 15a, 15b, and 15d are each equipped with drain electrodes (or "collector electrodes") as main electrodes on their back faces and with gate electrodes and source electrodes (or "emitter electrodes") as main electrodes on their front faces.

[0032] The semiconductor elements 15a, 15b, and 15d include, as applicable, diodes such as SBDs (Schottky barrier diodes) and FWDs (freewheeling diodes). In this case, the semiconductor elements 15a, 15b, and 15d are each equipped with cathode electrodes as the main electrodes on their back faces and with anode electrodes as the main electrodes on their front faces. The back faces of the semiconductor elements 15a, 15b, and 15d described above are bonded to predefined circuit structures 12e to 12h.

[0033] It is possible to use silicon semiconductor elements and wide bandgap semiconductor elements such as silicon carbide as semiconductor elements 15a, 15b and 15d.

[0034] Note that semiconductor elements 15a and 15b are bonded to bond regions 15a1 and 15b1 of circuit structure 12e via solder 18h and 18i. Additionally, semiconductor element 15d is bonded to bond region 15d1 of circuit structure 12h via solder 18l.

[0035] For example, electronic component 15c is a resistor, a thermistor, a capacitor, or a surge arrester. Electronic component 15c extends between circuit structures 12f and 12g and is bonded to bond regions 15c1 and 15c2 of circuit structures 12f and 12g via solder 18j and 18k.

[0036] As previously described and in the Fig. 1 and Fig. As shown in Figure 3, with the exception of the side surfaces where the first protective films are formed, no plating process or the like is carried out on the circuit structures 12a to 12h. This means that the solder 18h to 18l is applied directly to the bonding regions of the circuit structures 12e to 12h for the semiconductor elements 15a, 15b, and 15d and the electronic component 15c, thus preventing a reduction in the wettability of the circuit structures 12e to 12h with respect to the solder 18h to 18l. Accordingly, a decrease in the bond strength of the semiconductor elements 15a, 15b, and 15d and the electronic component 15c on the circuit structures 12e to 12h is avoided.

[0037] In a configuration where the plating process is performed on the bond regions 15a1, 15b1, and 15d1 of the circuit structures 12e and 12h for the semiconductor elements 15a, 15b, and 15d, the wettability of the circuit structures 12e and 12h with respect to the solder 18h, 18i, and 18l decreases. This results in voids remaining in the bonds between the semiconductor elements 15a, 15b, and 15d and the circuit structures 12e and 12h, causing a decrease in the bond strength of the semiconductor elements 15a, 15b, and 15d. Furthermore, the thermal resistance between the semiconductor elements 15a, 15b, and 15d and the metal substrate 20 increases, thereby reducing heat dissipation.

[0038] In a configuration where a plating process is performed on the bond regions 15c1 and 15c2 of the circuit structures 12f and 12g for the electronic component 15c, the wettability of the circuit structures 12f and 12g with respect to the solder 18j and 18k decreases. This causes the solder 18j and 18k to migrate up an electrode surface of the electronic component 15c. Consequently, the amount of solder 18j and 18k formed between the circuit structures 12f and 12g and the electronic component 15c decreases, resulting in a reduction in the bond strength of the electronic component 15c.

[0039] The contact elements 16a to 16g have cylindrical shapes with internal cavities between their open ends. One open end of each contact element 16a to 16g is bonded via solder 18a to 18g to bond regions 16a1 to 16g1 of the circuit structures 12a to 12d and 12f to 12h. The external terminals 19a to 19g are each pressed into the other open ends of the contact elements 16a to 16g. In this way, the contact elements 16a to 16g are bonded to the circuit structures 12a to 12d and 12f to 12h using solder 18a to 18g. Note that Fig. Figure 2 shows contact elements 16a to 16g bonded to circuit structures 12b and 12h. Contact elements 16a to 16g are made of metals with excellent electrical conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. To increase corrosion resistance, a plating film can be applied to the surface of contact elements 16a to 16g using a plating process with a metal such as nickel or gold. Besides nickel and gold, specific materials for a plating film include nickel-phosphorus alloys and nickel-boron alloys.

[0040] The external terminals 19a to 19g are made of metal with excellent electrical conductivity, such as aluminum, iron, silver, copper, or an alloy comprising at least one of these metals. The external terminals 19a to 19g are rod-shaped and have, for example, a square cross-section. The external terminals 19a to 19g are each pressed into the internal cavities of the contact elements 16a to 16g, so that the external terminals 19a to 19g are electrically connected to the circuit structures 12a to 12d and 12f to 12h via the contact elements 16a to 16g.

[0041] As in the Fig. 1 and Fig. As shown in Figure 3 and described above, no plating process or similar is carried out on parts of the circuit structures 12a to 12h, except for the side surfaces where the first protective films are formed. This means that the solder 18a to 18g is applied directly to the bonding regions for the contact elements 16a to 16g on the circuit structures 12a to 12d and 12f to 12h, thus preventing a reduction in the wettability of the circuit structures 12a to 12d and 12f to 12h with respect to the solder 18a to 18g. Consequently, a decrease in the bond strength of the contact elements 16a to 16g on the circuit structures 12a to 12d and 12f to 12h is avoided, and it is possible to reliably and stably press the external terminals 19a to 19g into the contact elements 16a to 16g.

[0042] In a configuration where a plating process is performed on the bond regions for the contact elements 16a to 16g on the circuit structures 12a to 12d and 12f to 12h, the wettability of the circuit structures 12a to 12d and 12f to 12h with respect to the solder 18a to 18g is reduced. When the contact elements 16a to 16g are bonded to the circuit structures 12a to 12d and 12f to 12h via the solder 18a to 18g, the solder 18a to 18g migrates upwards inside the contact elements 16a to 16g. This results in a reduction of the amount of solder 18a to 18g formed between the circuit structures 12a to 12d and 12f to 12h and the contact elements 16a to 16g, leading to a decrease in the bond strength of the contact elements 16a to 16g. It also becomes difficult to press the external terminals 19a to 19g into the contact elements 16a to 16g.Alternatively, there is a risk that the contact elements 16a to 16g will be bent when the external terminal blocks 19a to 19g are pressed into the contact elements 16a to 16g.

[0043] Since no plating process or similar is carried out on the bond regions for the semiconductor elements 15a, 15b and 15d, the electronic component 15c and the contact elements 16a to 16g on the circuit structures 12a to 12h, a reduction in the wettability of the circuit structures 12a to 12h with respect to the solder 18a to 18g is avoided. Accordingly, a decrease in the bond strength for the semiconductor elements 15a, 15b and 15d, the electronic component 15c and the contact elements 16a to 16g on the circuit structures 12a to 12h is avoided.

[0044] Solder 18a to 18l is made from a lead-free solder that has at least one alloy of a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, or a tin-silver-indium-bismuth alloy as its main component. In addition to this main component, solder 18a to 18l may contain additives such as nickel, germanium, cobalt, or silicon.

[0045] Note that the circuit structures 12a to 12h on the ceramic circuit substrate 14 can be connected accordingly by bond wires 17a to 17e. More details are given in the Fig. 1 and Fig. Figure 3 shows that a bond region 12b4 of circuit structure 12b and a bond region 12e5 of circuit structure 12e are electrically connected by the bond wire 17a. A bond region 12c4 of circuit structure 12c and the semiconductor element 15a (its source electrode) are electrically connected by the bond wire 17b, and a bond region 12d4 of circuit structure 12d and the semiconductor element 15a (its gate electrode) are electrically connected by the bond wire 17c. Furthermore, the semiconductor elements 15a and 15b are electrically connected by the bond wire 17d, and a bond region 12a4 of circuit structure 12a and a bond region 12h4 of circuit structure 12h are electrically connected by the bond wire 17e.

[0046] Note that the bonding of the bond wires 17a to 17e to the bond regions 12a4, 12b4, 12c4, 12d4, 12e5 and 12h4 on the circuit structures 12a to 12e and 12h is carried out, for example, by ultrasonic bonding. The bond wires 17a to 17e are made of metal with excellent electrical conductivity, such as aluminum, copper, gold, or an alloy comprising at least one of these metals.

[0047] As in the Fig. 1 and Fig. As shown in Figure 3 and described above, no plating process or similar is carried out on parts of the circuit structures 12a to 12h other than the desired side surfaces. Accordingly, it is possible to reliably bond the bond wires 17a to 17e to the bond regions 12a4, 12b4, 12c4, 12d4, 12e5 and 12h4 of the circuit structures 12a to 12e and 12h without any loss of bond strength.

[0048] In this semiconductor device 10, the circuit structures 12a to 12h and the semiconductor elements 15a, 15b and 15d are connected accordingly by the bond wires 17a to 17e. Furthermore, a predefined circuit is formed by electrically connecting the external terminals 19a to 19g to the circuit structures 12a to 12d and 12f to 12h, which includes the semiconductor elements 15a, 15b and 15d and the electronic component 15c.

[0049] The metal substrate 20 is made of a metal with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy comprising at least one of these metals. To improve corrosion resistance, a plating process or similar can be performed to apply a material such as nickel to the surface of the metal substrate 20. As a specific example, a nickel-phosphorus alloy or a nickel-boron alloy can be used instead of nickel.

[0050] Note that it is also possible to improve heat dissipation by providing a cooler (not illustrated) on a rear surface of the metal substrate 20 by bonding it with solder, silver solder, or the like, or by mechanical attachment with thermal paste or the like in between. The cooler mentioned here is formed from a metal with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy comprising at least one of these metals. It is possible to use a fin, a heat sink with multiple fins, a water-cooled cooling device, or the like as the cooler. It is also possible to use a configuration in which the metal substrate 20 is integral with the cooler. This configuration is made from a metal with excellent thermal conductivity, such as...Aluminum, iron, silver, copper, or an alloy comprising at least one of these metals. To improve corrosion resistance, it is also possible to perform a plating process or the like to provide a material such as nickel on the surface of the metal substrate 20 integrated into the cooler. As a specific example, instead of nickel, a nickel-phosphorus alloy or a nickel-boron alloy can be used.

[0051] The housing 21 is box-shaped and has a cover section 21a that covers the ceramic circuit substrate 14 from above, and a side wall section 21b that is provided on the outer circumference of the ceramic circuit substrate 14 and covers side sections of the ceramic circuit substrate 14. The housing 21 is formed from a thermoplastic resin. It is possible to use polyphenylene sulfide (PPS), polybutylene terephthalate resin (PBT resin), polybutylene succinate resin (PBS resin), polyamide resin (PA resin), acrylonitrile butadiene styrene resin (ABS resin), or the like as the resin.

[0052] The side wall section 21b of the housing 21 is bonded to the metal substrate 20 by means of an adhesive (not illustrated). Note that the adhesive can be applied to a base section of the side wall section 21b of the housing 21 or to a region of the metal substrate 20 where the housing 21 is attached. It is possible to use any method known in the field as a method for applying the adhesive, such as screen printing using a mask or a dispensing method using a syringe.

[0053] It is also possible to seal the interior of the housing 21 using a sealant (not illustrated). For example, the sealant is formed from a thermosetting resin such as maleimide-modified epoxy resin, maleimide-modified phenolic resin, or maleimide resin. The sealant can also be formed from a gel. The sealant is injected into the housing 21 from a predefined injection hole formed in the housing 21. The sealant injected into the housing 21 seals the ceramic circuit substrate 14, the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, the contact elements 16a to 16g, the bond wires 17a to 17e, and parts of the external terminals 19a to 19g on the metal substrate 20.

[0054] As previously described, no plating process or the like is carried out on parts of the circuit structures 12a to 12h, except for the side surfaces on which the first protective film is formed. This improves the adhesive strength of the sealant on the circuit structures 12a to 12h. Accordingly, it is possible to seal the ceramic circuit substrate 14, the semiconductor elements 15a, 15b and 15d, the electronic component 15c and the like inside the housing 21 with the sealant.

[0055] This completes the description of the configuration of semiconductor device 10.

[0056] In semiconductor device 10, input signals are applied externally to the external terminals 19a to 19g, and output signals are sent out. In a configuration where the first protective films are not formed on the side faces of the circuit structures 12a to 12h, short circuits between the circuit structures can occur due to corrosion products. More specifically, the copper of the circuit structures 12a to 12h is ionized by electric fields and the like, which are produced between the facing side faces of the circuit structures 12a to 12h, so that products of copper corrosion are produced between the circuit structures 12a to 12h (a phenomenon known as "ion migration"). When corrosion products are produced between adjacent circuit structures, short circuits occur between these adjacent circuit structures.

[0057] In the semiconductor device 10, however, the first protective films are formed on the facing side surfaces of the circuit structures 12a to 12h. This prevents corrosion products from being produced by ion migration on the facing side surfaces of adjacent circuit structures 12a to 12h. This makes it possible to avoid short circuits between adjacent circuit structures.

[0058] The semiconductor device 10 described above comprises the ceramic circuit substrate 14, which includes the insulating plate 11 and the plurality of circuit structures 12a to 12h formed on the front surface of the insulating plate 11. The semiconductor device 10 includes the semiconductor elements 15a, 15b and 15d, the electronic component 15c, the contact elements 16a to 16g, which are arranged by the solder 18a to 18i on the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 on the front surfaces of the plurality of circuit structures 12a to 12h, and also the bond wires 17a to 17e. Furthermore, the semiconductor device 10 comprises a plurality of first protective films formed on facing side surfaces of the plurality of circuit structures 12a to 12h.

[0059] In the semiconductor device 10, the majority of first protective films are formed on the facing side surfaces of the majority of circuit structures 12a to 12h, and no plating process or the like is carried out on parts other than the side surfaces.

[0060] This means that if the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g are bonded directly to the bond regions 15a1, 15b1, 15d1, 15c1, 15c2, and 16a1 to 16g1 of the majority of circuit structures 12a to 12h by the solder 18a to 18i, a reduction in the wettability of the circuit structures 12a to 12h with respect to the solder 18a to 18i is avoided. Accordingly, a decrease in bond strength for the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g on the majority of circuit structures 12a to 12h is avoided.

[0061] Since the first protective films are formed on the facing surfaces of the majority of circuit structures 12a to 12h, the production of corrosion products through ion migration on the facing surfaces of adjacent circuit structures is prevented. This makes it possible to avoid short circuits between adjacent circuit structures.

[0062] Accordingly, malfunctions of the semiconductor device 10 are reduced, thereby improving reliability.

[0063] Note that the semiconductor elements 15a, 15b and 15d, the electronic component 15c, the contact elements 16a to 16g and the bond wires 17a to 17e are included as components of the semiconductor device 10 in the above description. However, the term “components” is not limited to these and it is also possible to integrate any components that are bonded to the circuit structures 12a to 12h by solder, such as a printed circuit board.

[0064] For example, the circuit structures 12a to 12h of the ceramic circuit substrate 14 of the semiconductor device 10 are obtained by forming a copper foil on the insulating plate 11 and etching the copper foil into predefined patterns. In the first embodiment described above, the side faces of the circuit structures 12a to 12h are formed by etching so that they are perpendicular to the front face of the insulating plate 11. However, depending on the state of the etching and the copper foil or the like on the insulating plate 11, there may be cases in which the side faces of the circuit structures 12a to 12h are not perpendicular to the front face of the insulating plate 11 as described above. As examples of this situation, the circuit structures 12e and 12h are shown below with reference to Fig. 4 described.

[0065] Fig. Figure 4 shows circuit structures on a substrate of a semiconductor device, which is a modification of the first embodiment.

[0066] Note that the in Fig. The area shown in section 4 is an enlargement of a main part of the image. Fig. The cross-section shown in Figure 2 is shown. The semiconductor elements 15a, 15b and 15d, the electronic component 15c and the contact elements 16a to 16g on the ceramic circuit substrate 14 and the bond wires 17a to 17e are in Fig. 4 omitted.

[0067] As in Fig. As shown in Figure 4, the side surfaces 12es and 12hs of the circuit structures 12e and 12h are formed by etching, so that they are inclined and therefore not normal to the front surface of the insulating plate 11.

[0068] Even when the side surfaces 12es and 12hs of the circuit structures 12e and 12h are inclined towards the front surface of the insulating plate 11 in the manner described above, the first protective films 12e4 and 12h2 are formed on the side surfaces 12es and 12hs. Likewise, first protective films are formed in the same way on the side surfaces of the other circuit structures 12a to 12d, 12f and 12g, which have been omitted from the drawings, even when the side surfaces are inclined towards the front surface of the insulating plate 11.

[0069] Even if the first protective films are formed in this way on inclined side surfaces, the same effects are obtained as with the semiconductor device 10 described above. Second embodiment

[0070] In this second embodiment, a configuration is described in which, in addition to the first protective films of the first embodiment, second protective films are formed.

[0071] A semiconductor device 10a according to the second embodiment is now described with reference to the Fig. 5 and Fig. 6 described.

[0072] Fig. Figure 5 is a top view of a main part of the semiconductor device according to the second embodiment. Fig. Figure 6 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment.

[0073] Note that in the Fig. 5 and Fig. 6 Semiconductor device 10a shown, parts with the same reference numerals as in the semiconductor device 10 according to the first embodiment (in the Fig. (1 to 3 shown) index the same configurations.

[0074] Fig. Figure 5 corresponds to a top view of the circumference of the circuit structure 12e in Fig. 1 of the first embodiment. Fig. Figure 6 is a cross-sectional view along the dash-dot line XX in Fig. 5.

[0075] Similar to semiconductor device 10, the first protective film of semiconductor device 10a is formed on the facing side surfaces of the majority of circuit structures 12a to 12h. Furthermore, the second protective films of semiconductor device 10a are formed on edge sections of the front surfaces of circuit structures 12a to 12h along the first protective films formed on the side surfaces of circuit structures 12a to 12h.

[0076] For example, as in the Fig. 5 and Fig. As shown in Figure 6, the circuit structure 12e has a first protective film 12e1 formed on the side surface facing the circuit structures 12b to 12d (see Figure 6). Fig. 1) and has a second protective film 12e6 formed on a boundary section of the front surface of the circuit structure 12e along the first protective film 12e1. The circuit structure 12e has first protective films 12e2 and 12e3 formed on side surfaces facing the circuit structure 12a (see Fig. 1) and has second protective films 12e7 and 12e8 formed on edge sections of the front surface of the circuit structure 12e along the first protective films 12e2 and 12e3. Furthermore, the circuit structure 12e has a first protective film 12e4 formed on a side surface facing the circuit structures 12f to 12h (see Fig. 1) and has the second protective film 12e9 formed on a boundary section of the front surface of the circuit structure 12e along the first protective film 12e4.

[0077] As in Fig. As shown in Figure 5, the circuit structure 12a has first protective films 12a1 and 12a2 formed on the side surfaces facing the circuit structures 12b and 12e (see Figure 5). Fig. 1) and has the second protective films 12a5 and 12a6, which are formed on edge sections of the front surface of the circuit structure 12a along the first protective films 12a1 and 12a2. Note that if no specific distinction is made between the second protective films, the reference numerals 12a6, 12a7 and 12e6 to 12e9 can be omitted.

[0078] Although not shown in the drawings, first protective films are formed on facing side surfaces of the circuit structures 12b to 12d and 12f to 12h in the same way as the circuit structures 12a and 12e, and second protective films (also not illustrated) are formed on edge sections of the front surfaces of the circuit structures 12b to 12d and 12f to 12h along the first protective films.

[0079] As with the first protective films, the second protective films use a material with excellent corrosion resistance. Examples of such materials include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, platinum, palladium, and alloys containing at least one of these metals.

[0080] As with the first protective films of the first embodiment, it is possible to form the second protective films by electroless plating. It is possible to form the first and second protective films on the circuit structures 12a to 12h by first forming a mask (photoresist) in parts of the circuit structures 12a to 12h where the first and second protective films are not to be formed, and then removing the photoresist after electroless plating.

[0081] As described above in the first embodiment, the first protective films formed on the facing side surfaces of the circuit structures 12a to 12h make it possible to prevent the production of corrosion products on the side surfaces.

[0082] However, the first protective films alone are insufficient to prevent the formation of corrosion products on the edge sections along the front surfaces of adjacent circuit structures. In particular, when the distance between adjacent circuit structures is small and large electric fields are applied between them, corrosion products are formed on the edge sections of the front surfaces of adjacent circuit structures. This can create a risk of electrically connecting adjacent circuit structures.

[0083] For this reason, in the second embodiment, in addition to the first protective films formed on the side sections of the circuit structures, second protective films are formed on the edge sections of the front surfaces of the circuit structures along the first protective films. This suppresses the production of corrosion products by ion migration on facing side surfaces and the edge sections of the front surfaces of adjacent circuit structures 12a to 12h. This means that it is possible to reliably prevent short circuits between adjacent circuit structures.

[0084] In the semiconductor device 10a, the majority of first protective films of the majority of circuit structures 12a to 12h are formed in this way on side surfaces facing adjacent circuit structures, and the second protective films are formed along the first protective films on edge sections of the front surfaces of the circuit structures 12a to 12h. Parts of the majority of circuit structures 12a to 12h, other than the side surfaces and edge sections as mentioned above, are not subjected to any plating process or the like.

[0085] Therefore, when the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g are bonded directly to the bond regions 15a1, 15b1, 15d1, 15c1, 15c2, and 16a1 to 16g1 of the majority of circuit structures 12a to 12h by the solder 18a to 18i, a reduction in the wettability of the majority of circuit structures 12a to 12h with respect to the solder 18a to 18i is avoided. Accordingly, a decrease in bond strength for the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g on the majority of circuit structures 12a to 12h is avoided.

[0086] Since the majority of the first protective films (reference symbols omitted) of the majority of circuit structures 12a to 12h are formed on the side faces of adjacent circuit structures, and the second protective films are formed along the first protective films on the edge sections of the front faces of the circuit structures, the production of corrosion products by ion migration on the opposite side faces of adjacent circuit structures is also prevented. This makes it possible to reliably prevent short circuits between the adjacent circuit structures.

[0087] Accordingly, malfunctions of the semiconductor device 10a are reduced, thereby improving reliability. Third embodiment

[0088] In the semiconductor device 10a according to the second embodiment, the first protective films and the second protective films are formed in such a way that the production of corrosion products by ion migration on facing side surfaces and edge sections of front surfaces along these side surfaces of adjacent circuit structures of the circuit structures 12a to 12h is suppressed.

[0089] A semiconductor device 10b, capable of more reliably suppressing the production of corrosion products between the circuit structures 12a to 12h by ion migration, is now described with reference to the Fig. Described in sections 7 to 9.

[0090] Fig. Figure 7 is a top view of a main part of a semiconductor device according to a third embodiment. Fig. 8 and Fig. Figure 9 shows cross-sectional views of main parts of the semiconductor device according to the third embodiment.

[0091] Note that in the Fig. 7 and Fig. 9 Semiconductor device 10b parts with the same reference numerals as in the semiconductor device 10 according to the first embodiment (in the Fig. (1 to 3 shown) index the same configurations.

[0092] As with the second embodiment, Fig. 7 a top view of the circumference of the circuit structure 12e of the first embodiment, which is in Fig. 1 is shown. Fig. 8 is a cross-sectional view along a dash-dot line X1-X1 in Fig. 7 and Fig. 9 is a cross-sectional view along a dash-dot line X2-X2 in Fig. 7.

[0093] As with semiconductor device 10, first protective films of semiconductor device 10b are formed on the facing side surfaces of the majority of circuit structures 12a to 12h. Furthermore, in semiconductor device 10b, the first protective films are formed on side surfaces other than the facing side surfaces of the majority of circuit structures 12a to 12h. Second protective films of semiconductor device 10b are formed on edge sections of the front surfaces of the circuit structures 12a to 12h along the first protective films formed on the side surfaces of the circuit structures 12a to 12h. Second protective films of semiconductor device 10b are also formed on edge sections of the front surfaces of the circuit structures 12a to 12h along the first protective films formed on side surfaces other than the facing side surfaces of the majority of circuit structures 12a to 12h.In the semiconductor device 10b, third protective films are formed on the front surfaces of the circuit structures 12a to 12h to expose the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 of the circuit structures 12a to 12h.

[0094] In other words, the first protective films, the second protective films and the third protective films cover all of the majority of circuit structures 12a to 12h of the semiconductor device 10b, while simultaneously exposing the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 on the front surfaces of the circuit structures 12a to 12h.

[0095] For example, as in the Fig. As shown in Figures 7 to 9, the circuit structure 12e has, as in the second embodiment, first protective films 12e1 to 12e4, which are formed on the side surfaces facing the circuit structures 12a to 12d and 12f to 12h (see Figures 7 to 9). Fig. 1) Furthermore, first protective films 12e11 and 12e12 are formed on the remaining side surfaces of the circuit structure 12a. Second protective films 12e6 to 12e9 are formed on edge sections of the front surface of the circuit structure 12e along the first protective films 12e1 to 12e4. In addition, the circuit structure 12e has second protective films 12e13 and 12e14, which are formed on edge sections of the front surface of the circuit structure 12e along the first protective films 12e11 and 12e12.

[0096] Furthermore, the third protective film 12e10 is formed on the front surface of the circuit structure 12e, so that the bond regions 15a1 and 15b1 are exposed.

[0097] As in Fig. As shown in Figure 7, the first protective films 12a1 and 12a2 of the circuit structure 12a are formed on the side surfaces facing the circuit structures 12b and 12e (see Figure 7). Fig. 1) and the second protective films 12a5 and 12a6 are formed on edge sections of the front surface of the circuit structure 12a along the first protective films 12a1 and 12a2.

[0098] The circuit structure 12a also has a first protective film 12a7 formed on the remaining side surface and a second protective film 12a8 formed on the edge section of the front surface of the circuit structure 12a along the first protective film 12a7. However, on the circuit structure 12a of the semiconductor device 10b, the first protective film 12a2 and the second protective film 12a6 are formed such that they extend along the edge of the circuit structure 12a, unlike in the semiconductor device 10a.

[0099] Furthermore, the circuit structure 12a has a third protective film 12a10 formed on the front surface of the circuit structure 12a to expose the bond region 16a1 (see Fig. 1, in Fig.7 (however, omitted). Note that if no specific distinction is made between the third protective films, references 12a10 and 12e10 may be omitted.

[0100] Although not shown in the drawings, the first and second protective films of the circuit structures 12b to 12d and 12f to 12h are formed on all of the side faces around the perimeter and the edge sections of the front faces along these side faces, just as with the circuit structures 12a and 12e, and third protective films (not illustrated) are also formed on the front faces of the circuit structures 12b to 12d and 12f to 12h to expose the bond regions 12b1, 12c1, 12d1, 12f1, 12g1, 12h1 and 16a1 to 16g1.

[0101] Note that, as with the first and second protective films, the third protective films use a material with excellent corrosion resistance. As with the first protective films, exemplary materials include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, platinum, palladium, and alloys containing at least one of these metals.

[0102] As with the first and second protective films of the first and second embodiments, it is possible to form the third protective films by electroless plating. Specifically, the first, second, and third protective films can be formed on the circuit structures 12a to 12h by first forming a mask (photoresist) in bond regions 15a1, 15b1, 15d1, 15c1, 15c1, and 16a1 to 16g1 of the circuit structures 12a to 12h and then removing the photoresist after electroless plating. Accordingly, the first, second, and third protective films are integrally formed. In other words, it is sufficient to mask (i.e., apply a photoresist to) the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 to form the first protective films, the second protective films and the third protective films on the majority of circuit structures 12a to 12h of the semiconductor device 10b.This means that the formation of the first protective films, the second protective films, and the third protective films is simple compared to the first and second embodiments.

[0103] In the semiconductor device 10b described above, the majority of first protective films are formed on the side surfaces around the perimeters of the majority of circuit structures 12a to 12h, and second protective films are formed along the edge regions of the front surfaces of the circuit structures 12a to 12h. Furthermore, third protective films are formed on the front surfaces of the majority of circuit structures 12a to 12h to expose the bond regions 15a1, 15b1, 15d1, 15c1, 15c2, and 16a1 to 16g1.

[0104] This means that if the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g are bonded directly to the bond regions 15a1, 15b1, 15d1, 15c1, 15c2, and 16a1 to 16g1 of the majority of circuit structures 12a to 12h by the solder 18aa to 18i, a reduction in the wettability of the majority of circuit structures 12a to 12h with respect to the solder 18a to 18i is avoided. Accordingly, a decrease in bond strength for the semiconductor elements 15a, 15b, and 15d, the electronic component 15c, and the contact elements 16a to 16g on the majority of circuit structures 12e to 12h is avoided.

[0105] Furthermore, a majority of first protective films are formed on the side surfaces around the perimeters of most circuit structures 12a to 12h, second protective films are formed along the first protective films on edge sections of the front surfaces of the circuit structures, and third protective films are formed in such a way that bond regions on the front surfaces of the circuit structures are exposed. This means that the production of corrosion products between the circuit structures through ion migration is reliably suppressed. This makes it possible to reliably prevent short circuits between the circuit structures.

[0106] Accordingly, malfunctions of the semiconductor device 10b are reduced, thereby improving reliability.

[0107] Note that when deciding how to form the first protective films, the second protective films and the third protective films in the semiconductor device 10b according to the third embodiment, it is sufficient to form a plurality of first protective films on at least facing side surfaces of adjacent circuit structures of the plurality of circuit structures 12a to 12h, as long as the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 of the plurality of circuit structures 12a to 12h in the semiconductor device 10 are exposed.

[0108] Likewise, it is sufficient to form the majority of first protective films on facing side surfaces of the circuit structures and to form the second protective films along the first protective films on edge sections of the front surfaces of the circuit structures 12a to 12h, as long as the bond regions 15a1, 15b1, 15d1, 15c1, 15c2 and 16a1 to 16g1 of the majority of circuit structures 12a to 12h are exposed at the semiconductor device 10b.

[0109] According to the present embodiments, it is possible to avoid a decrease in the bond strength of components on circuit structures and to avoid a reduction in the reliability of a semiconductor device.

Claims

Semiconductor device (10) comprising: a substrate (14) comprising an insulating plate (11) with a front surface and a plurality of circuit structures (12a-12h) formed on the front surface of the insulating plate; a plurality of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) formed on at least facing side sections of the plurality of circuit structures (12a-12h) such that bond regions (15a1-16g1) are exposed on front surfaces of the plurality of circuit structures (12a-12h);and a plurality of components (15a-15c, 16a-16g, 17a-17e) bonded via solder (18a-18i) to the bond regions (15a1-16g1) of the plurality of circuit structures (12a-12h), wherein: the plurality of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) are formed on at least the facing side sections and on edge sections of the front surfaces of the plurality of circuit structures (12a-12h) along the side sections; and the majority of protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) are made of metal.; Semiconductor device (10) according to claim 1, wherein at least one of the plurality of components (15a-15c, 16a-16g, 17a-17e) is bonded such that it extends between adjacent circuit structures of the plurality of circuit structures (12a-12h). Semiconductor device (10) according to claim 1, wherein the plurality of components (15a-15c, 16a-16g, 17a-17e) is at least one from the group: semiconductor elements (15a, 15b, 15d) and contact elements (16a-16g). Semiconductor device (10) according to claim 2, wherein the plurality of components (15a-15c, 16a-16g, 17a-17e) are electronic components (15c). Semiconductor device (10) according to claim 1, wherein the majority of circuit structures (12a-12h) are formed from copper or copper alloy. Semiconductor device (10) according to claim 1, wherein the plurality of first protective films (12a1, 12a2, 12b1-12b3, 12c1-12c3, 12d1, 12d2, 12e1-12e14) are formed of nickel or nickel alloy. Semiconductor device (10) according to claim 1, wherein the solder (18a-18i) is a lead-free solder comprising at least one alloy selected from a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy and a tin-silver-indium-bismuth alloy as the main component. Semiconductor device (10) according to claim 7, wherein nickel, germanium, cobalt or silicon is added to the solder (18a-18i).

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