Short circuit detector and device

Abstract

Short circuit detector, comprising: a voltage detection circuit (30) for detecting a gate voltage input from a gate drive circuit (2) to a semiconductor element (11, 12); and a short-circuit detection circuit (32) for detecting a short-circuit condition of the semiconductor element (11, 12), only when the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a first reference voltage during a first detection period, wherein the first detection period is at least part of a transition period, which is a period from the time at which a turn-on signal is input to the gate drive circuit until the time at which a mirror period of the semiconductor element begins, or when, during a second detection period, the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a second reference voltage, wherein the second detection period differs from the first detection period and does not overlap with the first detection period, wherein: the first reference voltage is lower than a mirror voltage, and the short-circuit condition is not detected if the gate voltage of the semiconductor element (11, 12) is higher than the first reference voltage and lower than the second reference voltage during the second detection period.

Description

BACKGROUND TECHNICAL AREA

[0001] The present invention relates to a short circuit detector and a device. GENERAL STATE OF THE ART

[0002] Conventionally, for a device for driving each gate of two semiconductor elements connected in series between power supply lines, various techniques have been proposed to detect a short circuit between the power supply lines (see, for example, Patent Documents 1 to 5). Patent Document 1: Japanese Patent Laid-Open No. JP 2015-53749 A. Patent specification 2: US 6,680,837 B1. Patent specification 3: US 2014 / 140 102 A1. Patent specification 4: US 5,864,211 A. Patent specification 5: JP 3 651 143 B2.

[0003] It is desirable to reduce the period of a short-circuit condition due to anomalies as much as possible. In the detection method according to Patent Document 1, semiconductor elements are sometimes damaged because a short-circuit condition is detected after the end of a mirror period. Furthermore, given that a semiconductor element with low short-circuit resistance, such as a wide-band-gap semiconductor element, will continue to be used in the future, it is desirable to detect a short-circuit condition earlier. SUMMARY

[0004] A first aspect of the present invention relates to a short-circuit detector according to claim 1. A second aspect of the present invention relates to a short-circuit detector according to claim 2. A third aspect of the present invention relates to a short-circuit detector according to claim 4. A fourth aspect of the present invention relates to a device according to claim 8. Further aspects of the invention are the subject of the dependent claims, the drawings and the description of embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] They show: Fig. 1 a device according to the present embodiment. Fig. 2 an operation of the device. Fig. 3 an example operating waveform of the device. Fig. 4 shows another example operating waveform of the device. Fig. 5 shows another exemplary operating waveform of the device during a first detection period. Fig. 6 shows another exemplary operating waveform of the device during the first detection period. DESCRIPTION OF EMBODIMENTS

[0006] One or more embodiments of the present invention are described below. The one or more embodiments do not limit the invention as claimed, and any combinations of features described in the one or more embodiments are not necessarily essential to the means provided by the aspects of the invention.

[0007] Fig. Figure 1 shows a device 1 according to the present embodiment. Note that contour arrows represent voltage or current.

[0008] The device 1 is a section as a branch of a power conversion device used, for example, to drive a motor or supply power, and outputs an AC voltage from a power supply output terminal 105 by switching the connection between a power supply line 101 on the positive side, a power supply line 102 on the negative side, and a power supply output terminal 105.

[0009] For example, a DC voltage Ed of 600 to 800 V is applied between the power supply line 101 on the positive side and the power supply line 102 on the negative side. Also, the power supply line 101 on the positive side and the power supply line 102 on the negative side each have the wiring resistances 1011, 1021 depending on their wiring lengths.

[0010] The device 1 includes: a semiconductor element 11 on the positive side and a semiconductor element 12 on the negative side; a gate drive circuit 2, a detector 3, and a shutoff device 4 corresponding to the semiconductor element 11 on the positive side; and a gate drive circuit 5, a detector 6, and a shutoff device 7 corresponding to the semiconductor element 12 on the negative side. Note that since the configurations of each of the gate drive circuit 5, the detector 6, and the shutoff device 7 on the negative side are similar to those of each of the gate drive circuit 2, the detector 3, and the shutoff device 4 on the positive side, the description will not be repeated.

[0011] The first semiconductor element 11 and the second semiconductor element 12 are sequentially connected in series between the power supply line 101 on the positive side and the power supply line 102 on the negative side. The power supply output terminal 105 is connected to the neutral conductor of the first semiconductor element 11 and the second semiconductor element 12.

[0012] The first semiconductor element 11 and the second semiconductor element 12 are switching elements that are turned on and off by the gate drive circuit 2, which will be described later. As an example, the first semiconductor element 11 and the second semiconductor element 12 may be a lower arm and an upper arm of the power conversion device.

[0013] At least one of the first semiconductor element 11 and the second semiconductor element 12 may be a wide-bandgap semiconductor element. The wide-bandgap semiconductor element is a semiconductor element having a larger bandgap than that of a silicon semiconductor element, for example, a semiconductor element including SiC, GaN, diamond, a gallium nitride-based material, a gallium oxide-based material, AlN, AlGaN, ZnO, or the like. The wide-bandgap semiconductor element can improve the switching speed more than the silicon semiconductor element.

[0014] Also, in the present embodiment, the first semiconductor element 11 and the second semiconductor element 12 are MOSFETs having a parasitic diode with its cathode on the positive side of the power supply line 101. Note that the first semiconductor element 11 and the second semiconductor element 12 may also be other types of semiconductor elements, such as an IGBT or a bipolar transistor.

[0015] The gate drive circuit 2 drives a gate of the first semiconductor element 11 based on a turn-on signal and a turn-off signal included in an input signal S0. For example, when the first semiconductor element 11 and the second semiconductor element 12 are alternately switched to an ON state, the gate drive circuit 2 turns on the semiconductor element 11 after turning off the second semiconductor element 12 to be switched to the OFF state. Note that, in the present embodiment, as an example, when the semiconductor element 11 is switched to the ON state, the input signal S0 is set to HIGH, whereas when it is switched to the OFF state, the input signal S0 is set to LOW.

[0016] The gate drive circuit 2 may include an AND circuit 20 and a totem pole circuit 22.

[0017] The AND circuit 20 corrects an input signal S0 by performing a logical AND operation between the input signal S0 for the gate drive circuit 2 and a signal from the shutdown device 4, which will be described later, and outputs it as a gate signal S1 to the gate of the first semiconductor element 11. For example, the AND circuit 20 outputs a HIGH signal (ON signal) as the gate signal S1 when both of them are set to HIGH, whereas it outputs a LOW signal (OFF signal) as the gate signal S1 when at least one of them is set to LOW. The AND circuit 20 supplies the gate signal S1 to the totem pole circuit 22.

[0018] The totem pole circuit 22 can amplify the gate signal S1 from the AND circuit 20. The totem pole circuit 22 supplies the gate signal S1 to the first semiconductor element 11 via a gate resistor 21.

[0019] It should be noted that in the gate drive circuit 2 described above, the gate resistor 21 may not be provided between the totem pole circuit 22 and the detector 3 but between the AND circuit 20 and the totem pole circuit 22.

[0020] The detector 3 detects a short-circuit condition of the semiconductor element 11. For example, the detector 3 detects a short-circuit condition in response to the semiconductor element 11 being turned on when the semiconductor element 12 is in the ON state. The detector 3 also detects a short-circuit condition in response to the semiconductor element 12 being turned on when the semiconductor element 11 is in the ON state. The short-circuit condition of the semiconductor element 11 may, as an example, be a short-circuit condition between the power supply line 101 on the positive side and the power supply line 102 on the negative side. The detector 3 includes a voltage detection circuit 30, a timing unit 31, and a short-circuit detection circuit 32.

[0021] The voltage detection circuit 30 detects a gate voltage input from the gate drive circuit 2 to the semiconductor element 11. For example, the voltage detection circuit 30 may be connected to an output terminal of the gate drive circuit 2 and detect the gate voltage. The voltage detection circuit 30 may supply the detected gate voltage to a comparator 325, described later, in the short-circuit detection circuit 32. Note that, in the present embodiment, as an example, the voltage detection circuit 30 may include a low-pass filter 302. The low-pass filter 302 limits the high-frequency components of the gate voltage of the semiconductor element 11 (in the present embodiment, the voltage on a wiring between the gate drive circuit 2 and the semiconductor element 11 as an example).

[0022] The timing unit 31 sets, as a first detection period, at least a portion of a transition period from the time a turn-on signal is input to the semiconductor element 11 until the time the semiconductor element 11 is turned from OFF to ON. For example, the timing unit 31 may set, as the first detection period, a period in which the gate voltage is equal to or higher than the gate voltage threshold unique to the semiconductor element 11 and until it approaches a voltage value of the mirror period. The timing unit 31 may supply a period setting signal S3 representing whether or not the current timing is within the first detection period to a reference voltage setting unit 323 in the short-circuit detection circuit 32, which will be described later.For example, the timing unit 31 may continuously supply a HIGH signal to the reference voltage setting unit 323 during the first detection period.

[0023] Note that in the present embodiment, a period other than the first detection period is regarded as a second detection period. However, the timing unit 31 may set at least a part of a period after the transition period as the second detection period.

[0024] The short-circuit detection circuit 32 detects a short-circuit condition of the semiconductor element 11 in response to the gate voltage of the semiconductor element 11 becoming equal to or higher than a reference voltage during a detection period. For example, the short-circuit detection circuit 32 may detect a short-circuit condition in response to the gate voltage becoming the first reference voltage Vref1 during the first detection period, and may detect a short-circuit condition in response to the gate voltage becoming equal to or higher than the second reference voltage Vref2 during the second detection period. The first reference voltage Vref1 and the second reference voltage Vref2 may be different.

[0025] The short-circuit detection circuit 32 may include the reference voltage setting unit 323 and the comparator 325.

[0026] The reference voltage setting unit 323 selects one of the first reference voltage Vref1 and the second reference voltage Vref2 in response to the period setting signal S3 from the timing setting unit 31 and supplies it to the comparator 325. The reference voltage setting unit 323 may include two switches 3231, 3232 and two reference voltage sources 3233, 3234.

[0027] Switches 3231, 3232 are set to ON or OFF in response to the setting result of the first detection period by timing unit 31. For example, switch 3231 and switch 3232 may alternatively be set to ON. In the present embodiment, as an example, switch 3231 may be set such that a signal from timing unit 31 is supplied to switch 3231 as it is, and switch 3231 is closed during the first detection period. Also, switch 3232 may be set such that a signal from timing unit 31 is supplied to switch 3232 via a NOT circuit 3230, and switch 3232 is closed during the second detection period.

[0028] Switch 3231 may be connected between reference voltage source 3233 and comparator 325, which will be described later. Switch 3232 may be connected between reference voltage source 3234 and comparator 325, which will be described later.

[0029] The reference voltage sources 3233, 3234 are each connected between the switches 3231, 3232 and ground and supply the first reference voltage Vref1 and the second reference voltage Vref2 to the comparator 325.

[0030] The comparator 325 detects a short-circuit condition by determining whether the reference voltage is higher than the gate voltage or not. For example, when the reference voltage setting unit 323 sets the switch 3231 to ON, the comparator 325 can determine whether the first reference voltage Vref1 is higher than the gate voltage or not. Also, when the reference voltage setting unit 323 sets the switch 3232 to ON, the comparator 325 can determine whether the second reference voltage Vref2 is higher than the gate voltage or not. In the present embodiment, as an example, when the gate voltage is higher than the reference voltage, the comparator 325 can detect a short-circuit condition and output a HIGH signal. Even when the gate voltage is equal to or lower than the reference voltage, the comparator 325 can output a LOW signal without detecting a short-circuit condition.The comparator 325 can supply a determination result, ie, a signal indicating the detection result of a short-circuit condition, to the shutdown device 4.

[0031] The shutdown device 4 shuts off the current flowing through the semiconductor element 11 when a short-circuit condition is detected. The shutdown device 4 includes a hold circuit 41, a NOT circuit 42, and a shutdown circuit 43.

[0032] The latch circuit 41 latches an output signal from the comparator 325 and outputs it as a short-circuit detection signal S2. For example, the latch circuit 41 may be a peak-hold circuit, and when a HIGH signal is output from the comparator 325, the latch circuit 41 may latch it and output a HIGH signal. The latch circuit 41 may supply the short-circuit detection signal S2 to the NOT circuit.

[0033] The NOT circuit 42 inverts the HIGH signals and LOW signals to output them. For example, if a short-circuit condition is detected by the detector 3 and a HIGH signal is output as the short-circuit detection signal S2, the NOT circuit 42 inverts a HIGH signal to a LOW signal. Even if the detector 3 does not detect a short-circuit condition and a LOW signal is output as the short-circuit detection signal S2, the NOT circuit 42 can invert a LOW signal to a HIGH signal.

[0034] The NOT circuit 42 can invert the inverted short-circuit detection signal S2 for the shutdown circuit 43 and the AND circuit 20 in the previously described gate drive circuit 2. Note that by supplying the inverted short-circuit detection signal S2 to the AND circuit 20, a HIGH signal (ON signal) input to the gate drive circuit 2 when a short-circuit condition is detected is corrected to a LOW signal (OFF signal) by the AND circuit 20 and supplied to the gate. On the other hand, when no short-circuit condition is detected, the input signal S0 to the gate drive circuit 2 is supplied to the gate from the AND circuit 20 as it is.

[0035] The shutdown circuit 43 shuts off the current flowing between the positive-side power supply line 101 and the negative-side power supply line 102 in response to a short-circuit condition being detected by the short-circuit detection circuit 32. In the present embodiment, as an example, in response to a short circuit occurring between the positive-side power supply line 101 and the negative-side power supply line 102 and a LOW signal being supplied from the NOT circuit 42, the shutdown circuit 43 causes a short circuit to occur between the gate and source of the semiconductor element 11 to turn off the semiconductor element 11.

[0036] It should be noted that in the device 1 described above, the detectors 3, 6 and / or the shutdown devices 4, 7 may be connected to a substrate on which the semiconductor elements 11, 12 are provided. The device 1 may also be housed entirely in a single housing.

[0037] According to the device 1 described above, during the transition period, a short-circuit condition is detected in response to the gate voltage of the semiconductor element 11 becoming equal to or higher than the first reference voltage Vref1, whereas during the second detection period other than the transition period, a short-circuit condition is detected in response to the gate voltage becoming equal to or higher than the second reference voltage Vref2. Thus, not only a short-circuit condition during the transition period but also a short-circuit condition after the transition period can be detected. For example, the following short-circuit conditions can be separately detected: a short-circuit condition arising due to a failure, etc., of the semiconductor element 12 at the same time as the turn-on of the semiconductor element 11; and a short-circuit condition arising due to faulty control, etc.of the semiconductor element 12 while the semiconductor element 11 is in the permanently ON state. Thus, the short-circuit conditions can be detected earlier, regardless of the time of occurrence of the short-circuit conditions.

[0038] Also, in response to the detection of a short-circuit condition, the current flowing between the power supply line 101 on the positive side and the power supply line 102 on the negative side is cut off, so that damage to the elements by strong current can be prevented.

[0039] Fig. Figure 2 illustrates a process of device 1. Note that this process begins when a turn-on signal for semiconductor element 11 is input to device 1.

[0040] First, the timing unit 31 sets, as the first detection period, at least a portion of a transition period from the time a turn-on signal is input to the semiconductor element 11 to the time the semiconductor element 11 is turned ON (step S1). For example, the timing unit 31 may set, as the first detection period, a period from the time a turn-on signal is input to the semiconductor element 11 to the time a predetermined second period elapses. Also, the timing unit 31 may set, as the first detection period, a period from the time a turn-on signal is input to the semiconductor element 11 and a predetermined first period elapses to the time the predetermined second period elapses.In the present embodiment, the timing unit 31 sets, as an example, as the first detection period, at least a portion of a transition period from the time a power-on signal is input to the time the mirror period begins. Here, the mirror period is a period in which the gate voltage is limited to a constant value (mirror voltage, gate plateau voltage, gate cutoff voltage) due to a mirror effect. The beginning of the transition period may be after the time the drain-source voltage of the semiconductor element 11 begins to decrease.

[0041] Note that a time point at which the semiconductor element 11 is turned ON, i.e., the end of the transition period, may be, for example, a time point after the gate voltage exceeds the gate threshold voltage and the semiconductor element 11 is just turned on. As an example, the end of the transition period may be a time point at which the parasitic diode of the semiconductor element 12 starts to transition to the OFF state due to current flowing between the drain and source of the semiconductor element 11, i.e., a start time point of the mirror period. Also, the end of the transition period may be a time point at which the parasitic diode of the semiconductor element 12 is completely switched to the OFF state, i.e., an end time point of the mirror period. Also, the end of the transition period may be a time point at which the gate-source voltage of the semiconductor element 11 becomes the forward voltage.The forward voltage may be a gate-source voltage determined according to the maximum current that can flow into the semiconductor element 11. Or it may be determined according to the maximum voltage allowed for the gate.

[0042] Then, the detector 3 detects a short-circuit state of the semiconductor element 11 during the first detection period in the transition period (step S3) and determines whether a short-circuit state has been detected (step S5). For example, the detector 3 may detect a short-circuit state in response to the gate voltage of the semiconductor element 11 becoming equal to or higher than the first reference voltage Vref1 during the first detection period.

[0043] If it is determined in step S5 that a short-circuit condition is detected (step S5; Yes), the shutdown device 4 shuts off the current flowing in the semiconductor element 11 (step S11). For example, the shutdown device 4 can shut off the semiconductor element 11 by causing a short circuit to occur between the gate and source of the semiconductor element 11 to lower the gate potential, or it can shut off the semiconductor element 11 by correcting an input signal S0 for the gate drive circuit 2 to a LOW signal (OFF signal). Then, when step S11 is completed, the device 1 terminates the process.

[0044] If it is determined in step S5 that no short-circuit condition is detected (step S5; No), the detector 3 also detects a short-circuit condition of the semiconductor element 11 during the second detection period after the transition period (step S7) and determines whether a short-circuit condition has been detected (step S9). For example, the detector 3 may detect a short-circuit condition in response to the gate voltage of the semiconductor element 11 becoming equal to or higher than the second reference voltage Vref2.

[0045] If it is determined in step S9 that a short circuit condition is detected (step S9; Yes), the device 1 shifts the process to the previously described step S11.

[0046] Even if it is determined in step S9 that no short circuit condition is detected (step S9; No), the device 1 terminates the process.

[0047] According to the above-described process, a short-circuit state of the semiconductor element 11 is detected in response to the gate voltage of the semiconductor element 11 becoming equal to or higher than the first reference voltage Vref1 during a transition period from the time a turn-on signal is input to the semiconductor element 11 to the time the mirror period begins. Thus, since a short-circuit state can be detected before the mirror period, the detection timing can be earlier compared to the case where a short-circuit state is detected after the mirror period.

[0048] Fig. 3 shows an exemplary operating waveform of the device 1. The device 1 detects according to an operating waveform in Fig. 3 detects a short circuit that occurs at the time of turning on the semiconductor element 11 due to a failure, etc., of the semiconductor element 12, and turns off the power. Note that in the figure, a solid waveform under "gate voltage" represents a waveform when a short circuit has occurred between the positive-side power supply line 101 and the negative-side power supply line 102, whereas a dashed waveform represents a waveform when no short circuit has occurred.

[0049] First, an input signal S0, which transitions to HIGH at time t1, is input to device 1 (see the waveform of the input signal S0). The input signal S0 is fed to the AND circuit 20 and the timing unit 31.

[0050] When the input signal S0 is input, the AND circuit 20 supplies the gate signal S1 to the gate of the semiconductor element 11. At this time, no short circuit is detected when the input signal S0 is input and a HIGH signal is input from the shutdown device 4 to the AND circuit 20. Thus, the AND circuit 20 supplies the input signal S0 unchanged as the gate signal S1 to the gate of the semiconductor element 11 (see the waveform of the gate signal S1). As a result, the gate voltage Vgs of the semiconductor element 11 increases and exceeds the gate threshold Vth at time t2 (for example, 5 V), and the semiconductor element 11 is just turned on (see the waveform of the gate voltage).

[0051] On the other hand, when a turn-on signal is input as input signal S0, the timing unit 31 sets the first detection period in the transition period. Here, in the present embodiment, as an example, when the semiconductor element 11 is turned ON according to the input signal S0 without a short circuit occurring between the positive-side power supply line 101 and the negative-side power supply line 102, the gate voltage Vgs is clamped to the mirror voltage Vm during a period from time t4 to time t6 (see the dashed waveform of the gate voltage). Thus, in the present embodiment, as an example, the timing unit 31 sets a period from time t1 to time t5, which is before the end of the mirror period, as the first detection period during the transition period (for example, a period from time t1 to time t6).Then, the timing unit 31 supplies the reference voltage setting unit 323 with the period setting signal S3, which goes HIGH during the first detection period from time t1 to time t5 (see the waveform of the period setting signal S3).

[0052] Then, the reference voltage setting unit 323 supplies the first reference voltage Vref1 to the comparator 325 during the first detection period from time t1 to time t5 based on the period setting signal S3 (see the reference voltage waveform). Here, the first reference voltage Vref1 may be equal to or lower than the forward voltage +Vgs (for example, 15 to 18 V) (see the gate voltage waveform). For example, the first reference voltage Vref1 may be higher than the gate voltage during the first detection period when the semiconductor element 11 is turned on without a short circuit occurring, and may be lower than the gate voltage during the first detection period when the semiconductor element 11 is turned on with a short circuit occurring.

[0053] Then, the comparator 325 detects a short-circuit condition by comparing the gate voltage Vgs with the first reference voltage Vref1 during the first detection period, and the hold circuit 41 holds the detection result and outputs it as the short-circuit detection signal S2. In the present embodiment, as an example, since the gate voltage Vgs exceeds the first reference voltage Vref1 at time t3 because the semiconductor element 12 is switched to the ON state due to a failure, thereby detecting a short-circuit condition, the short-circuit detection signal S2 transitions to HIGH from time t3 onwards (see the waveform of the short-circuit detection signal S2).

[0054] Then, the shutdown device 4 shuts off the current flowing between the positive-side power supply line 101 and the negative-side power supply line 102 in response to detecting a short-circuit condition. For example, the NOT circuit 42 shuts off the semiconductor element 11 by sending an inverted signal of the short-circuit detection signal S2 to the AND circuit 20 and setting the gate signal S1 from the AND circuit 20 to the gate low from time t3 onwards (see the waveform of the gate signal S1).

[0055] Fig. 4 shows another exemplary operating waveform of the device 1. The device 1 detects according to an operating waveform in Fig. 4, a short circuit caused by faulty control, etc., of the semiconductor element 12 during the continuous ON state of the semiconductor element 11, and switches off the current. It should be noted that for the waveforms, the description of processes similar to those in Fig. 3 are not repeated.

[0056] Since no short-circuit condition is detected during the first detection period from time t1 to time t4, the reference voltage setting unit 323 first supplies the second reference voltage Vref2 to the comparator 325 during the second detection period after the first detection period (see the reference voltage waveform). The second reference voltage Vref2 may be higher than the first reference voltage Vref1 or higher than the forward voltage +Vgs (see the gate voltage waveform). The second reference voltage Vref2 may be equal to or higher than the mirror voltage.

[0057] Then, the comparator 325 detects a short-circuit condition by comparing the gate voltage Vgs with the second reference voltage Vref2 during the second detection period, and the hold circuit 41 holds the detection result and outputs it as the short-circuit detection signal S2. In the present embodiment, as an example, after the gate voltage Vgs exceeds the forward voltage +Vgs at time t6 because the semiconductor element 12 was erroneously turned on, the gate voltage Vgs exceeds the second reference voltage Vref2 at time t7, and a short-circuit condition is detected (see the gate voltage waveform). Thus, the short-circuit detection signal S2 transitions to HIGH from time t7 (see the waveform of the short-circuit detection signal S2).It should be noted that an increase in the gate voltage Vgs may occur because the charging current flows through the reaction capacitance Cgd to the gate side as the drain-source voltage Vds of the semiconductor element 11, which increases due to a short circuit.

[0058] Then, the shutdown device 4 shuts off the current flowing between the positive-side power supply line 101 and the negative-side power supply line 102 in response to detecting a short-circuit condition. For example, the NOT circuit 42 can shut off the semiconductor element 11 by supplying an inverted signal of the short-circuit detection signal S2 to the AND circuit 20 and setting the gate signal S1 from the AND circuit 20 to the gate low from time t7 (see the waveform of the gate signal S1).

[0059] Fig. Figure 5 shows another exemplary operating waveform of the device 1 during a first detection period. In this exemplary operation, the semiconductor element 12 is not switched to the ON state, so that no short circuit occurs due to the switching on of the semiconductor element 11. It should be noted that in Fig. 5, the input signal S0, the short-circuit detection signal S2, the gate signal S1 and the like are not shown repeatedly. Also, in Fig. 5 a period shown by Cgs and Cgd represents the charging periods of the capacities Cgs, Cgd. Also, I FWD and V FWD a current value and a voltage value at the parasitic diode of the semiconductor element 11.

[0060] First, by applying the input signal S0 to the gate to turn the semiconductor element 11 ON, the gate voltage Vgs of the semiconductor element 11 begins to increase from time t11, charging the gate-source capacitance Cgs. Thus, the gate current Ig increases. A gate-drain capacitance Cgd is also charged. Note that since the semiconductor element 11 is not turned ON until time t12, which will be described later, the drain-source voltage Vds, the drain current Id, and the parasitic diode current IFWD can remain constant values.

[0061] Then, when the gate-source voltage Vgs becomes the gate threshold voltage Vth at time t12, the semiconductor element 11 is just turned on, and the decrease in the drain-source voltage Vds, the increase in the drain current Id, and the increase in the parasitic diode current IFWD in the negative region begin. Note that during a period from time t12 to time t13, which will be described later, the charging of the gate-source capacitance Cgs and the gate-drain capacitance Cgd can be carried out simultaneously. Also, an internal inductance of the inductance of the wiring 1011 and the semiconductor element 11 can reduce the drain-source voltage Vds by ΔV=L·dI / dt. Also, the voltage V FWD at both ends of the parasitic diode become equal to or higher than zero.

[0062] Then, the gate-source voltage Vgs becomes the mirror voltage Vm (for example, 12 V) at time t13, and the mirror period begins, in which the mirror effect of Cin=Cgs+(1+Av)·Cgd is generated, where Cin is an input capacitance and Av is a gain factor. Also, the current I FWD from time t13 onwards is equal to zero, and the parasitic diode is just switched to the OFF state. Thus, the drain current Id is saturated to be maintained at a constant value, the drain-source voltage Vds decreases sharply, and the voltage V FWD at both ends of the parasitic diode increases sharply. The gate-source voltage Vgs is maintained at the mirror voltage.

[0063] Then, at time t14, the parasitic diode is completely turned off. Also, at time t15, the mirror period ends. Thus, during a period from time t15 to time t16, the capacitance Cgs is charged until the gate-source voltage Vgs becomes the forward voltage. Then, after time t16, the gate-source voltage Vgs is maintained at the forward voltage +Vgs, and the ON state continues. Note that a period length from time t12, when the gate voltage Vgs becomes the gate threshold voltage Vth (for example, 5 V), to time t16, when the gate voltage Vgs becomes the forward voltage (for example, 15 to 18 V), can be several hundred nanoseconds.

[0064] Note that in the above-described process, in response to a turn-on signal being supplied as input signal S0, a period until the mirror period begins (for example, from time t12 to time t12') may be set as the first detection period. Also, the first reference voltage Vref1 may be lower than the mirror voltage Vm. However, since the semiconductor element 12 is not turned ON in this exemplary process, a short circuit is not detected, and the semiconductor element 11 is turned ON.

[0065] Fig. Fig. 6 shows yet another exemplary operation waveform of the device 1 during the first detection period. In this exemplary operation, the semiconductor element 12 is switched to the ON state due to a failure, etc., and thus a short circuit occurs due to the switching on of the semiconductor element 11. It should be noted that for the waveforms, the description of operations similar to those in Fig. 5 are not repeated.

[0066] First, when the gate-source voltage Vgs becomes the gate threshold voltage Vth at time t12, the semiconductor element 11 is just turned ON, and the drain-source voltage Vds begins to decrease and the drain current Id begins to increase. Also, due to an internal inductance of the inductance of the wiring 1011 and the semiconductor element 11, the drain-source voltage Vds decreases by ΔV=L·dl / dt. However, in the present exemplary process, since the semiconductor element 12 is turned ON, the drain current Id is not saturated and continues to increase. The drain-source voltage Vds increases again from time t13 and becomes the DC voltage Ed between the power supply line 101 on the positive side and the power supply line 102 on the negative side, and the semiconductor element 11 then enters a short-circuit state.Also, the gate-source voltage Vgs increases and exceeds the mirror voltage and becomes the forward voltage +Vgs at time t13.

[0067] When the semiconductor element 11 is in a short-circuit state, for example, when a short-circuit state occurs between the power supply line 101 on the positive side and the power supply line 102 on the negative side, the parasitic diode of the semiconductor element 11 is not switched OFF. Since, in comparison with the Fig. 5, no voltage is generated during the turn-off of the parasitic diode, the drain-source voltage Vds is higher during a period from time t12 to time t13. Thus, the gate-drain capacitance Cgd is not charged enough, and the mirror effect of Cin=Cgs+(1+Av)·Cgd is not generated, and the gate-source capacitance Cgs is charged unchanged with Cin≈Cgs. As a result, the gate-source voltage Vgs during a period from time t12 to time t13 is higher than in Fig. 5 shown case higher.

[0068] Thus, in the present exemplary process, in the first detection period (for example, a period from time t12 to time t12' in the present embodiment), a short-circuit condition is detected by comparing the gate voltage Vgs with the first reference voltage Vref1, which is lower than the mirror voltage Vm. For example, 100 ns later than time t12, when the gate voltage Vgs becomes the gate threshold voltage Vth (for example, 5 V), the gate voltage Vgs becomes equal to or higher than the first reference voltage Vref1 (for example, 12 V), and a short-circuit condition can be detected.

[0069] It should be noted that in the previously described embodiment, the device 1 was described as comprising two semiconductor elements 11, 12. However, it may not comprise one of them, or it may comprise another element as an alternative to one of them. It may also be that the device 1 in this case comprises only one of the two gate drive circuits 2, 5, only one of the two detectors 3, 6, and only one of the two shutdown devices 4, 7.

[0070] It has also been described that detector 3 detects a short circuit during the first detection period and the second detection period, but it may detect it only during the first detection period. In this case, detector 3 may include an analog switch to supply the gate voltage to a low-pass filter 302 only during the first detection period, which is set by timing unit 31.

[0071] It has also been described that the detector 3 detects a short circuit during the first detection period and the second detection period by switching the reference voltage input to the comparator 325 for each period, but it may detect a short circuit in other ways. For example, the detector 3 may include a first comparator to which the first reference voltage Vref1 is always input, driving during the first detection period and detecting a short circuit, and further, the detector 3 may include a second comparator to which the second reference voltage is always input, driving during the second detection period and detecting a short circuit. In this case, the second comparator may always be driven without being limited to the second detection period, or may be driven during the entire ON period of the semiconductor element 11.The second reference voltage may be higher than the forward voltage of the semiconductor element 11.

[0072] It has also been described that the detector 3 includes the timing unit 31 for setting at least a portion of the transition period as the detection period, but the detector 3 may not have this. For example, the detector 3 may detect a short-circuit condition through the short-circuit detection circuit 32 during the entire transition period or at least a portion of the transition period.

[0073] It has also been described that the shutdown device 4 holds an output signal from the comparator 325 through the hold circuit 41 and turns off the semiconductor element 11 by causing a short circuit to occur between the gate and the source of the semiconductor element 11 through the shutdown circuit 43, but it may be that the shutdown device 4 is turned off by another mechanism. LIST OF REFERENCE SYMBOLS 1 device; 2 Gate control circuit; 3 detector; 4 shutdown device; 5 Gate control circuit; 6 detector; 7 shutdown device; 11 semiconductor element; 12 semiconductor element; 20 AND circuit; 21 Gate resistor; 22 totem pole circuit; 30 voltage detection circuit; 31 timing unit; 32 short circuit detection circuit; 41 holding circuit; 42 NOT circuit; 43 shutdown circuit; 101 power supply line on the positive side; 102 Power supply line on the negative side; 105 Power supply output terminal; 302 low-pass filter; 323 Unit for setting a reference voltage; 325 comparator; 1011 Inductance of the wiring; 1021 wiring inductance; 3230 NOT circuit; 3231 switches; 3232 switches; 3233 reference voltage source; 3234 Reference voltage source

Claims

[1] Short circuit detector, comprising: a voltage detection circuit (30) for detecting a gate voltage input from a gate drive circuit (2) to a semiconductor element (11, 12); and a short-circuit detection circuit (32) for detecting a short-circuit condition of the semiconductor element (11, 12), only when the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a first reference voltage during a first detection period, wherein the first detection period is at least part of a transition period, which is a period from the time at which a turn-on signal is input to the gate drive circuit until the time at which a mirror period of the semiconductor element begins, or when, during a second detection period, the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a second reference voltage, wherein the second detection period differs from the first detection period and does not overlap with the first detection period, wherein: the first reference voltage is lower than a mirror voltage, and the short-circuit condition is not detected if the gate voltage of the semiconductor element (11, 12) is higher than the first reference voltage and lower than the second reference voltage during the second detection period. [2] Short circuit detector, comprising: a voltage detection circuit (30) for detecting a gate voltage input from a gate drive circuit (2) to a semiconductor element (11, 12); and a short-circuit detection circuit (32) for detecting a short-circuit condition of the semiconductor element (11, 12), only when the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a first reference voltage during a first detection period, wherein the first detection period is at least part of a transition period, which is a period at least from the time at which a turn-on signal is input to the gate drive circuit (2) to the time at which a mirror period of the semiconductor element (11, 12) begins, or when, during a second detection period, the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a second reference voltage, wherein the second detection period differs from the first detection period and does not overlap with the first detection period, wherein the second reference voltage is higher than the first reference voltage, and the short-circuit condition is not detected if the gate voltage of the semiconductor element (11, 12) is higher than the first reference voltage and lower than the second reference voltage during the second detection period. [3] A short circuit detector according to claim 2, wherein the second reference voltage is equal to or higher than a mirror voltage. [4] Short circuit detector comprising: a voltage detection circuit (30) for detecting a gate voltage input from a gate drive circuit (2) to a semiconductor element (11, 12); and a short-circuit detection circuit (32) for detecting a short-circuit condition of the semiconductor element (11, 12), when the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a first reference voltage during a first detection period, wherein the first detection period is at least part of a transition period, which is a period at least from the time at which a turn-on signal is input to the gate drive circuit (2) to the time at which a mirror period of the semiconductor element (11, 12) begins, or when, during a second detection period, the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a second reference voltage, wherein the second detection period differs from the first detection period and does not overlap with the first detection period, wherein the second reference voltage is higher than the second reference voltage during an entire ON period, and the short-circuit condition is not detected if the gate voltage of the semiconductor element (11, 12) is higher than the first reference voltage and lower than the second reference voltage during the second detection period. [5] A short-circuit detector according to claim 4, wherein the second reference voltage is higher than a forward voltage of the semiconductor element (11, 12). [6] A short-circuit detector according to any one of claims 1 to 5, wherein a detection period of a short-circuit state of the semiconductor element (11, 12) during the transition period is a period from the time when the gate voltage of the semiconductor element (11, 12) becomes equal to or higher than a gate threshold voltage to the time when the mirror period starts. [7] A short-circuit detector according to any one of claims 1 to 6, comprising a timing unit for setting, as a detection period of the short-circuit state of the semiconductor element (11, 12) during the transition period, a period from the time at which the turn-on signal is input to the semiconductor element (11, 12) and a predetermined first period elapses to the time at which a predetermined second period elapses. [8] Device (1) comprising: a plurality of semiconductor elements (11, 12) including the semiconductor element connected in series between a positive-side power supply line (101) and a negative-side power supply line (102); and the short-circuit detector according to one of claims 1 to 7. [9] Device (1) according to claim 8, further comprising a further gate drive circuit (2) for driving a gate of at least one of the semiconductor elements (11, 12). [10] The device (1) according to claim 8 or 9, further comprising a shutdown circuit for shutting off current flowing between the positive-side power supply line (101) and the negative-side power supply line (102) in response to the short-circuit condition being detected by the short-circuit detection circuit (32). [11] The device (1) according to any one of claims 8 to 10, further comprising a series circuit, wherein the semiconductor element (11, 12) and another semiconductor element (11, 12) are connected in series between the positive-side power supply line (101) and the negative-side power supply line (102). [12] Device (1) according to claim 11, further comprising another short-circuit detection circuit (32), wherein the short-circuit detection circuit (32) detects the short-circuit condition in response to the semiconductor element (11, 12) being turned on while at least one of the plurality of semiconductor elements (11, 12) is in an ON state, or during a transition period of at least one of the plurality of semiconductor elements (11, 12) from an ON state to an OFF state; and the other short-circuit detection circuit (32) detects the short-circuit condition in response to at least one of the plurality of semiconductor elements (11, 12) being turned on while the semiconductor element (11, 12) is in an ON state, or during a transition period of at least one of the plurality of semiconductor elements (11, 12) from an ON state to an OFF state. [13] The device (1) according to any one of claims 8 to 12, wherein the semiconductor element (11, 12) is a wide band gap semiconductor element.

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