PROCESSING METHOD FOR A WAFER

Abstract

A processing method for a wafer (11) in which a front surface (11a) of the wafer, on which a component (15) is formed in each of the chip areas divided by several intersecting division lines (13) formed in an intersecting relationship on the front surface (11a) of the wafer (11), is sealed with a sealing element (23) containing carbon black of 0.1 to 0.2% by mass percent, and several elevations (25) are individually formed in the chip areas of the sealing element (23), wherein the processing method comprises: an alignment step for capturing an image of a front surface (11a) of the wafer (11) by the sealing element (23) by an image acquisition means (26) for visible light from the front surface (11a) of the wafer (11) to detect alignment marks, and detecting a planned division line (13) to be laser processed among the multiple planned division lines based on the alignment marks; and a division step for irradiating, after the alignment step has been performed, a laser beam (LB) of a wavelength that is absorbed by the wafer (11) and the sealing element (23), along the planned division line (13) from the front surface (11a) of the wafer (11) to divide the wafer by an ablation process into individual component chips (31) that are sealed with the sealing element (23) on their front surface (11a); wherein the alignment step is carried out while light (28) is emitted in an inclined direction onto an area whose image is to be captured by the image-taking means (26) for visible light, using an inclined light source.

Description

Technical area

[0001] The present invention relates to a processing method for a WL-CSP wafer. Description of the state of the art

[0002] A WL-CSP (wafer-level chip size package) wafer is a technology for sealing the wafer after a wiring layer and electrodes (metal pins) have been formed. While the WL-CSP wafer is in a wafer state, its front surface is covered with plastic, and portions of the wafer are cut into components using a cutting blade or similar device. Because the size of the packages obtained by cutting the wafer is equivalent to the size of the semiconductor device chips, the technology is widely adapted for reducing size and weight.

[0003] In the manufacturing process of the WL-CSP wafer, a wiring layer is formed on a component face of a component wafer on which several components are formed, and metal pins connected to electrodes in components are formed through the wiring layer, and then the metal pins and the components are sealed with plastic.

[0004] A sealing element is then made thin so that the metal pins are exposed on the front surface of the sealing element, and external connections, called electrode protrusions, are formed on one end face of the metal pins. The WL-CSP wafer is then cut by a cutting device or similar instrument to divide it into individual CSPs.

[0005] To protect semiconductor devices from impact, moisture, or similar hazards, it is important to seal them with a sealing element. Typically, a sealing material is created by mixing a filler made of silicon carbide (SiC) into an epoxy resin. This ensures that the coefficient of thermal expansion of the sealing element is close to that of the semiconductor chips, thus preventing damage to the packings during heating caused by a difference in their coefficients of thermal expansion.

[0006] A WL-CSP wafer is generally divided into individual CSPs using a cutting device. In this case, because a component used to detect a planned division line within the WL-CSP wafer is covered with plastic, a target pattern of the component cannot be detected from the front surface.

[0007] Therefore, alignment of the planned parting line and the cutting blade must be carried out by indexing the planned parting line, setting the electrode protrusions formed on the plastic of the WL-CSP wafer as a target, or by printing a target for alignment on the top surface of the plastic.

[0008] However, the electrode protrusions or the target printed on the plastic are not formed with the same high accuracy as the components, resulting in a problem where the target has low accuracy for alignment. In cases where a planned parting line is indicated based on electrode protrusions or a printed target, there is a possibility that a cutting point will be offset from the planned parting line, resulting in a component section being cut. Therefore, for example, Japanese patent application JP 2013-74 021 A proposes a method whereby alignment is performed based on a pattern of the component wafer exposed in an external environment of the wafer.

[0009] JP 2016 - 015 438 A concerns an alignment procedure.

[0010] US 2003 / 0 063 278 A1 concerns a wavefront sensor for detecting alignment features.

[0011] US 6 583 032 B1 concerns a processing method for semiconductor chips.

[0012] US 6 271 102 B1 concerns a method and a system for splitting wafers.

[0013] US 2013 / 0 137 218 A1 concerns a manufacturing process for semiconductor chips. PRESENTATION OF THE INVENTION

[0014] However, in general, component accuracy on the outer environment of the wafer is somewhat inaccurate, and if alignment is performed based on a pattern exposed on the outer environment of the wafer, there is a possibility that the wafer will be split at a position offset from a planned parting line, and furthermore, depending on the wafer, a pattern of the component may not be exposed on the outer environment.

[0015] Therefore, an objective of the present invention is to provide a processing method for a wafer by which an alignment step can be carried out by means of a sealing element that covers the front surface of the wafer and contains carbon black.

[0016] In accordance with one aspect of the present invention, a processing method for a wafer is provided, wherein a front surface of the wafer, on which a component is formed in each chip area divided by several planned division lines formed in an intersecting relationship on the front surface of the wafer, is sealed with a sealing element containing carbon black of 0.1 to 0.2% by mass percent, and wherein several raised areas are individually formed in the chip areas of the sealing element, the processing method comprising an alignment step for capturing an image of a front surface of the wafer through the sealing material with a visible light imaging means from the front surface of the wafer to detect alignment marks and a planned division line to be laser-processed.Based on the alignment marks, and a division step for irradiation after the alignment step has been performed, a laser beam of a wavelength absorbed by the sealing element and the wafer is directed along the planned division line from the front surface of the wafer to divide the wafer into individual device chips, each sealed with the sealing element on its front surface, by an ablation process. The alignment step is performed while light is directed at an angle onto an area through an inclined light source, the image of which is to be acquired by the visible light imaging device.

[0017] According to the processing method for the wafer of the present embodiment, since it is possible to detect the alignment marks formed on the wafer through the sealing element by means of an image acquisition means for visible light while light is emitted in an inclined direction through the inclined light source, and to carry out an alignment on the basis of the alignment marks, it is possible to carry out the alignment step without removing the sealing element on an outer circumferential section of the surface of the wafer as in the prior art.

[0018] Therefore, it is possible to irradiate the laser beam of a wavelength that is absorbed by the wafer and the sealing element along a planned division line from the front surface of the wafer in order to divide the wafer into individual component chips by ablation processing.

[0019] The above and other aims, features and advantages of the present invention and the manner of realizing them will be made clearer and the invention itself best understood by studying the following description and the attached claim with reference to the attached figures which show a preferred embodiment of the invention. BRIEF DESCRIPTION OF THE FIGURES Fig. 1A is a perspective exploded view of a WL-CSP wafer; Fig. Figure 1B is a perspective view of the WL-CSP wafer; Fig. Figure 2 is an enlarged cross-sectional view of the WL-CSP wafer; Fig. Figure 3 is a perspective view showing a way in which the WL-CSP wafer is glued onto a slitting tape, the outer circumferential section of which is attached to an annular frame; Fig. Figure 4 is a section view showing an alignment step; Fig. 5A is a sectional view showing a training step for a modified layer; Fig. 5B is an enlarged section view showing the division step. DETAILED DESCRIPTION OF THE PREFERRED VERSION

[0020] In the following, an embodiment of the present invention is described in detail with reference to the figures. Fig. Figure 1A shows a perspective exploded view of a WL-CSP wafer 27. Fig. Figure 1B is a perspective view of the WL-CSP wafer 27. As shown in Fig. As shown in Figure 1A, components 15, such as LSIs (large scale integrations), are formed in areas divided by several planned division lines (roads) 13, which are formed in a grid pattern on a front surface side 11A of the component wafer 11.

[0021] The component wafer (hereinafter sometimes simply referred to as wafer) 11 is pre-ground on a rear surface 11b so that it is thin to a predetermined thickness (approximately 100 to 200 µm). Then, as in Fig. As shown in Figure 2, several metal pins 21, which are electrically coupled to electrodes 17 in the components 15, are formed and then the front surface side 11a of the wafer 11 is sealed with a sealing element 23 so that the metal pins 21 are embedded in it.

[0022] The sealing element 23 has a composition that includes epoxy resin or epoxy resin with phenolic resin at 10.3%, silica filler at 8.53%, carbon black at 0.1 to 0.2%, and some other components at 4.2 to 4.3% by mass. Other components include, for example, metal hydroxide, antimony trioxide, silicon dioxide, or similar substances.

[0023] If the front surface 11a of the wafer 11 is covered and sealed with the sealing element 23, which has a composition as described above, then the sealing element 23 has a black color resulting from the carbon black contained in a very small amount in the sealing material 23, and it is normally difficult to see the front surface 11a of the wafer 11 through the sealing element 23. The reason for the carbon black being mixed into the sealing element 23 is primarily to prevent electrostatic damage to a component 15, and a sealing material that does not contain carbon black is not currently available on the market.

[0024] As another embodiment, after a wiring layer is formed on the front surface 11a of the component wafer 11, metal pins 21, which are electrically coupled to the electrodes 17 in the components 15, can be formed on the wiring layer.

[0025] The sealing element 23 is then thinned using a surface cutting device (a surface planer) having a cutting tool made of a single-crystal diamond, or a grinding device called a grinder. After the sealing element 23 has been thinned, an end face of the metal pin 21 is exposed, for example by plasma etching.

[0026] Then, metal protrusions 25 made of solder or the like are formed on the exposed end faces of the metal pins 21 by a well-known method to complete the WL-CSP wafer 27. In this WL-CSP wafer 27 of the present embodiment, the thickness of the sealing element 23 is approximately 100 µm.

[0027] When the WL-CSP wafer 27 is laser-processed by a laser processing device, the WL-CSP wafer 27 is preferably adhered to a parting strip T as an adhesion-promoting strip, the outer circumferential section of which is attached to an annular frame F, as shown in Fig. Figure 3 shows that the WL-CSP wafer 27 is attached. Consequently, the WL-CSP wafer 27 is positioned in a state where it is supported on the annular frame F by the dividing strip T. However, if the WL-CSP wafer 27 is to be laser-processed by the laser processing device, an embodiment can be used in which an adhesive strip is applied to the rear surface of the WL-CSP wafer 27 without using the annular frame F.

[0028] In the processing method for a wafer of the present invention, an alignment step is performed to capture an image of the front surface 11a of the component wafer 11 by the sealing element 23 from a front surface side of the WL-CSP wafer 27 by means of a visible light imaging means, detecting at least two alignment marks such as target patterns formed on a front surface of the component wafer 11, and then detecting a planned parting line 13 to be processed based on the alignment marks.

[0029] This alignment step will be described in detail with reference to Fig. 4 described. Before the alignment step is carried out, the rear surface 11b of the wafer 11 is glued to a dividing strip, the outer circumferential section of which is attached to an annular frame F.

[0030] In the alignment step, the WL-CSP wafer 27 is inserted by a clamping table 10 of the laser processing device with the dividing belt T in between, suctioned in and held so that the sealing element 23, which seals the front surface 11a of the component wafer 11, is exposed upwards, as shown in Fig. 4 shown. Then the ring-shaped frame 11 is clamped and fixed by a clamp 12.

[0031] During the alignment step, an image of the front surface of the WL-CSP wafer 27 is acquired by an image acquisition element such as a CCD (charge-coupled device) element, specifically a visible light image acquisition unit 26. However, because components such as silica fillers, carbon black, and so on are contained in the sealing element 23, and the surface of the sealing element is uneven, the light from the vertical illumination of the visible light image acquisition unit 26 passes through the sealing element 23. Therefore, even when an image of the front surface 11a of the wafer 11 is acquired with vertical illumination, the image is blurred, and it is difficult to discern alignment marks such as target patterns from the acquired image.

[0032] Therefore, in the alignment step of the present embodiment, in addition to the vertical illumination of the recording unit 26 for visible light, another light is emitted in an inclined direction onto an imaged area by the inclined light source 28 in order to improve the blurred image in order to make it possible to detect the alignment marks.

[0033] The light emitted by the inclined light source is preferably white light, and the angle of incidence of the light on the front surface of the WL-CSP wafer 27 is preferably in the range of 30° to 60°. Preferably, the image acquisition unit 26 for visible light includes an exposure unit that can adjust the exposure time or the like.

[0034] Then the clamping table 10 is rotated by θ degrees so that a straight line connecting the alignment marks is positioned parallel to a machining feed direction and the clamping table 10, which is in Fig. 5A is furthermore moved in a direction orthogonal to the processing feed direction X1 by a distance equal to a distance between the alignment marks and the center of the planned division lines 13 in order to detect the planned division line 13 to be laser processed.

[0035] After the alignment step has been performed, a laser beam LB of a wavelength (for example, 355 nm), which is absorbed by the component wafer 11 and the sealing element 23, is emitted by a laser head (condenser) 16 along the planned parting line 13 on the front surface of the WL-CSP wafer in order to form such a laser-machined groove 29 by ablation processing, as shown in Fig. 5B is shown, and the WL-CSP wafer 27 is divided into individual component chips (CSPs) 31, the front surfaces of which are sealed with the sealing element 23.

[0036] After this division step has been successively carried out along the planned division lines 13, which extend in a first direction, the clamping table 10 is rotated by 90° and then the division step is successively carried out along the planned division lines 13, which extend in a second direction orthogonal to the first direction. As described in Fig. As shown in Figure 5B, the WL-CSP wafer 27 can be divided into individual component chips (CSPs) 31, whose front surface is sealed with the sealing element 23.

[0037] Each component chip (CSP) 31 manufactured in this manner is flipped from top to bottom and can be attached to a mainboard by flip-chip bonding to connect the protrusions 25 to conductive pads on the mainboard.

Claims

[1] A processing method for a wafer (11), in which a front surface (11a) of the wafer, on which a component (15) is formed in each of the chip regions divided by a plurality of intersecting dividing lines (13) formed in an intersecting relationship on the front surface (11a) of the wafer (11), is sealed with a sealing member (23) containing carbon black of 0.1 to 0.2% by mass, and a plurality of protrusions (25) are individually formed in the chip regions of the sealing member (23), the processing method comprising: an alignment step of capturing an image of a front surface side (11a) of the wafer (11) through the sealing member (23) by a visible light image pickup means (26) from the front surface side (11a) of the wafer (11) to detect alignment marks, and detecting a planned dividing line (13) to be laser-machined among the plurality of planned dividing lines based on the alignment marks; and a dividing step of irradiating, after the alignment step has been performed, a laser beam (LB) of a wavelength absorbed by the wafer (11) and the sealing member (23) along the planned dividing line (13) from the front surface side (11a) of the wafer (11) to divide the wafer by ablation processing into individual component chips (31) sealed with the sealing member (23) on their front surface (11a); wherein the alignment step is carried out while irradiating light (28) in an inclined direction onto an area whose image is to be captured by the visible light image capturing means (26) with an inclined illuminating means.

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